Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
060d22b0 | 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
0bfee649 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
0af1713e | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
9b201bb5 | 6 | This file is part of the GNU opcodes library. |
20f0a1fc | 7 | |
9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. | |
20f0a1fc | 12 | |
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
20f0a1fc NC |
17 | |
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
22 | ||
20f0a1fc NC |
23 | |
24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
25 | July 1988 | |
26 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
27 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
29 | ||
30 | /* The main tables describing the instructions is essentially a copy | |
31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
32 | Programmers Manual. Usually, there is a capital letter, followed | |
33 | by a small letter. The capital letter tell the addressing mode, | |
34 | and the small letter tells about the operand size. Refer to | |
35 | the Intel manual for details. */ | |
252b5132 | 36 | |
252b5132 | 37 | #include "sysdep.h" |
dabbade6 | 38 | #include "dis-asm.h" |
252b5132 | 39 | #include "opintl.h" |
0b1cf022 | 40 | #include "opcode/i386.h" |
85f10a01 | 41 | #include "libiberty.h" |
252b5132 RH |
42 | |
43 | #include <setjmp.h> | |
44 | ||
26ca5450 AJ |
45 | static int print_insn (bfd_vma, disassemble_info *); |
46 | static void dofloat (int); | |
47 | static void OP_ST (int, int); | |
48 | static void OP_STi (int, int); | |
49 | static int putop (const char *, int); | |
50 | static void oappend (const char *); | |
51 | static void append_seg (void); | |
52 | static void OP_indirE (int, int); | |
53 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 54 | static void OP_E_register (int, int); |
c1e679ec | 55 | static void OP_E_memory (int, int); |
5d669648 | 56 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
57 | static void OP_E (int, int); |
58 | static void OP_G (int, int); | |
59 | static bfd_vma get64 (void); | |
60 | static bfd_signed_vma get32 (void); | |
61 | static bfd_signed_vma get32s (void); | |
62 | static int get16 (void); | |
63 | static void set_op (bfd_vma, int); | |
b844680a | 64 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
65 | static void OP_REG (int, int); |
66 | static void OP_IMREG (int, int); | |
67 | static void OP_I (int, int); | |
68 | static void OP_I64 (int, int); | |
69 | static void OP_sI (int, int); | |
70 | static void OP_J (int, int); | |
71 | static void OP_SEG (int, int); | |
72 | static void OP_DIR (int, int); | |
73 | static void OP_OFF (int, int); | |
74 | static void OP_OFF64 (int, int); | |
75 | static void ptr_reg (int, int); | |
76 | static void OP_ESreg (int, int); | |
77 | static void OP_DSreg (int, int); | |
78 | static void OP_C (int, int); | |
79 | static void OP_D (int, int); | |
80 | static void OP_T (int, int); | |
6f74c397 | 81 | static void OP_R (int, int); |
26ca5450 AJ |
82 | static void OP_MMX (int, int); |
83 | static void OP_XMM (int, int); | |
84 | static void OP_EM (int, int); | |
85 | static void OP_EX (int, int); | |
4d9567e0 MM |
86 | static void OP_EMC (int,int); |
87 | static void OP_MXC (int,int); | |
26ca5450 AJ |
88 | static void OP_MS (int, int); |
89 | static void OP_XS (int, int); | |
cc0ec051 | 90 | static void OP_M (int, int); |
c0f3af97 L |
91 | static void OP_VEX (int, int); |
92 | static void OP_EX_Vex (int, int); | |
922d8de8 | 93 | static void OP_EX_VexW (int, int); |
c0f3af97 | 94 | static void OP_XMM_Vex (int, int); |
922d8de8 | 95 | static void OP_XMM_VexW (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
46e883c5 L |
104 | static void NOP_Fixup1 (int, int); |
105 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 106 | static void OP_3DNowSuffix (int, int); |
ad19981d | 107 | static void CMP_Fixup (int, int); |
26ca5450 | 108 | static void BadOp (void); |
35c52694 | 109 | static void REP_Fixup (int, int); |
f5804c90 | 110 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 111 | static void XMM_Fixup (int, int); |
381d071f | 112 | static void CRC32_Fixup (int, int); |
eacc9c89 | 113 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
114 | static void OP_LWPCB_E (int, int); |
115 | static void OP_LWP_E (int, int); | |
116 | static void OP_LWP_I (int, int); | |
5dd85c99 SP |
117 | static void OP_Vex_2src_1 (int, int); |
118 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 119 | |
f1f8f695 | 120 | static void MOVBE_Fixup (int, int); |
252b5132 | 121 | |
6608db57 | 122 | struct dis_private { |
252b5132 RH |
123 | /* Points to first byte not fetched. */ |
124 | bfd_byte *max_fetched; | |
0b1cf022 | 125 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 126 | bfd_vma insn_start; |
e396998b | 127 | int orig_sizeflag; |
252b5132 RH |
128 | jmp_buf bailout; |
129 | }; | |
130 | ||
cb712a9e L |
131 | enum address_mode |
132 | { | |
133 | mode_16bit, | |
134 | mode_32bit, | |
135 | mode_64bit | |
136 | }; | |
137 | ||
138 | enum address_mode address_mode; | |
52b15da3 | 139 | |
5076851f ILT |
140 | /* Flags for the prefixes for the current instruction. See below. */ |
141 | static int prefixes; | |
142 | ||
52b15da3 JH |
143 | /* REX prefix the current instruction. See below. */ |
144 | static int rex; | |
145 | /* Bits of REX we've already used. */ | |
146 | static int rex_used; | |
d869730d | 147 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 148 | static int rex_ignored; |
52b15da3 JH |
149 | /* Mark parts used in the REX prefix. When we are testing for |
150 | empty prefix (for 8bit register REX extension), just mask it | |
151 | out. Otherwise test for REX bit is excuse for existence of REX | |
152 | only in case value is nonzero. */ | |
153 | #define USED_REX(value) \ | |
154 | { \ | |
155 | if (value) \ | |
161a04f6 L |
156 | { \ |
157 | if ((rex & value)) \ | |
158 | rex_used |= (value) | REX_OPCODE; \ | |
159 | } \ | |
52b15da3 | 160 | else \ |
161a04f6 | 161 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
162 | } |
163 | ||
7d421014 ILT |
164 | /* Flags for prefixes which we somehow handled when printing the |
165 | current instruction. */ | |
166 | static int used_prefixes; | |
167 | ||
5076851f ILT |
168 | /* Flags stored in PREFIXES. */ |
169 | #define PREFIX_REPZ 1 | |
170 | #define PREFIX_REPNZ 2 | |
171 | #define PREFIX_LOCK 4 | |
172 | #define PREFIX_CS 8 | |
173 | #define PREFIX_SS 0x10 | |
174 | #define PREFIX_DS 0x20 | |
175 | #define PREFIX_ES 0x40 | |
176 | #define PREFIX_FS 0x80 | |
177 | #define PREFIX_GS 0x100 | |
178 | #define PREFIX_DATA 0x200 | |
179 | #define PREFIX_ADDR 0x400 | |
180 | #define PREFIX_FWAIT 0x800 | |
181 | ||
252b5132 RH |
182 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
183 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
184 | on error. */ | |
185 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 186 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
187 | ? 1 : fetch_data ((info), (addr))) |
188 | ||
189 | static int | |
26ca5450 | 190 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
191 | { |
192 | int status; | |
6608db57 | 193 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
194 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
195 | ||
0b1cf022 | 196 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
197 | status = (*info->read_memory_func) (start, |
198 | priv->max_fetched, | |
199 | addr - priv->max_fetched, | |
200 | info); | |
201 | else | |
202 | status = -1; | |
252b5132 RH |
203 | if (status != 0) |
204 | { | |
7d421014 | 205 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
206 | print_insn_i386 will do something sensible. Otherwise, print |
207 | an error. We do that here because this is where we know | |
208 | STATUS. */ | |
7d421014 | 209 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 210 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
211 | longjmp (priv->bailout, 1); |
212 | } | |
213 | else | |
214 | priv->max_fetched = addr; | |
215 | return 1; | |
216 | } | |
217 | ||
ce518a5f | 218 | #define XX { NULL, 0 } |
592d1631 | 219 | #define Bad_Opcode NULL, { { NULL, 0 } } |
ce518a5f L |
220 | |
221 | #define Eb { OP_E, b_mode } | |
b6169b20 | 222 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 223 | #define Ev { OP_E, v_mode } |
b6169b20 | 224 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
225 | #define Ed { OP_E, d_mode } |
226 | #define Edq { OP_E, dq_mode } | |
227 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
228 | #define Edqb { OP_E, dqb_mode } |
229 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 230 | #define Eq { OP_E, q_mode } |
ce518a5f L |
231 | #define indirEv { OP_indirE, stack_v_mode } |
232 | #define indirEp { OP_indirE, f_mode } | |
233 | #define stackEv { OP_E, stack_v_mode } | |
234 | #define Em { OP_E, m_mode } | |
235 | #define Ew { OP_E, w_mode } | |
236 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 237 | #define Ma { OP_M, a_mode } |
b844680a | 238 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 239 | #define Md { OP_M, d_mode } |
f1f8f695 | 240 | #define Mo { OP_M, o_mode } |
ce518a5f L |
241 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
242 | #define Mq { OP_M, q_mode } | |
4ee52178 | 243 | #define Mx { OP_M, x_mode } |
c0f3af97 | 244 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f L |
245 | #define Gb { OP_G, b_mode } |
246 | #define Gv { OP_G, v_mode } | |
247 | #define Gd { OP_G, d_mode } | |
248 | #define Gdq { OP_G, dq_mode } | |
249 | #define Gm { OP_G, m_mode } | |
250 | #define Gw { OP_G, w_mode } | |
6f74c397 L |
251 | #define Rd { OP_R, d_mode } |
252 | #define Rm { OP_R, m_mode } | |
ce518a5f L |
253 | #define Ib { OP_I, b_mode } |
254 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
255 | #define Iv { OP_I, v_mode } | |
256 | #define Iq { OP_I, q_mode } | |
257 | #define Iv64 { OP_I64, v_mode } | |
258 | #define Iw { OP_I, w_mode } | |
259 | #define I1 { OP_I, const_1_mode } | |
260 | #define Jb { OP_J, b_mode } | |
261 | #define Jv { OP_J, v_mode } | |
262 | #define Cm { OP_C, m_mode } | |
263 | #define Dm { OP_D, m_mode } | |
264 | #define Td { OP_T, d_mode } | |
b844680a | 265 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
266 | |
267 | #define RMeAX { OP_REG, eAX_reg } | |
268 | #define RMeBX { OP_REG, eBX_reg } | |
269 | #define RMeCX { OP_REG, eCX_reg } | |
270 | #define RMeDX { OP_REG, eDX_reg } | |
271 | #define RMeSP { OP_REG, eSP_reg } | |
272 | #define RMeBP { OP_REG, eBP_reg } | |
273 | #define RMeSI { OP_REG, eSI_reg } | |
274 | #define RMeDI { OP_REG, eDI_reg } | |
275 | #define RMrAX { OP_REG, rAX_reg } | |
276 | #define RMrBX { OP_REG, rBX_reg } | |
277 | #define RMrCX { OP_REG, rCX_reg } | |
278 | #define RMrDX { OP_REG, rDX_reg } | |
279 | #define RMrSP { OP_REG, rSP_reg } | |
280 | #define RMrBP { OP_REG, rBP_reg } | |
281 | #define RMrSI { OP_REG, rSI_reg } | |
282 | #define RMrDI { OP_REG, rDI_reg } | |
283 | #define RMAL { OP_REG, al_reg } | |
284 | #define RMAL { OP_REG, al_reg } | |
285 | #define RMCL { OP_REG, cl_reg } | |
286 | #define RMDL { OP_REG, dl_reg } | |
287 | #define RMBL { OP_REG, bl_reg } | |
288 | #define RMAH { OP_REG, ah_reg } | |
289 | #define RMCH { OP_REG, ch_reg } | |
290 | #define RMDH { OP_REG, dh_reg } | |
291 | #define RMBH { OP_REG, bh_reg } | |
292 | #define RMAX { OP_REG, ax_reg } | |
293 | #define RMDX { OP_REG, dx_reg } | |
294 | ||
295 | #define eAX { OP_IMREG, eAX_reg } | |
296 | #define eBX { OP_IMREG, eBX_reg } | |
297 | #define eCX { OP_IMREG, eCX_reg } | |
298 | #define eDX { OP_IMREG, eDX_reg } | |
299 | #define eSP { OP_IMREG, eSP_reg } | |
300 | #define eBP { OP_IMREG, eBP_reg } | |
301 | #define eSI { OP_IMREG, eSI_reg } | |
302 | #define eDI { OP_IMREG, eDI_reg } | |
303 | #define AL { OP_IMREG, al_reg } | |
304 | #define CL { OP_IMREG, cl_reg } | |
305 | #define DL { OP_IMREG, dl_reg } | |
306 | #define BL { OP_IMREG, bl_reg } | |
307 | #define AH { OP_IMREG, ah_reg } | |
308 | #define CH { OP_IMREG, ch_reg } | |
309 | #define DH { OP_IMREG, dh_reg } | |
310 | #define BH { OP_IMREG, bh_reg } | |
311 | #define AX { OP_IMREG, ax_reg } | |
312 | #define DX { OP_IMREG, dx_reg } | |
313 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
314 | #define indirDX { OP_IMREG, indir_dx_reg } | |
315 | ||
316 | #define Sw { OP_SEG, w_mode } | |
317 | #define Sv { OP_SEG, v_mode } | |
318 | #define Ap { OP_DIR, 0 } | |
319 | #define Ob { OP_OFF64, b_mode } | |
320 | #define Ov { OP_OFF64, v_mode } | |
321 | #define Xb { OP_DSreg, eSI_reg } | |
322 | #define Xv { OP_DSreg, eSI_reg } | |
323 | #define Xz { OP_DSreg, eSI_reg } | |
324 | #define Yb { OP_ESreg, eDI_reg } | |
325 | #define Yv { OP_ESreg, eDI_reg } | |
326 | #define DSBX { OP_DSreg, eBX_reg } | |
327 | ||
328 | #define es { OP_REG, es_reg } | |
329 | #define ss { OP_REG, ss_reg } | |
330 | #define cs { OP_REG, cs_reg } | |
331 | #define ds { OP_REG, ds_reg } | |
332 | #define fs { OP_REG, fs_reg } | |
333 | #define gs { OP_REG, gs_reg } | |
334 | ||
335 | #define MX { OP_MMX, 0 } | |
336 | #define XM { OP_XMM, 0 } | |
c0f3af97 | 337 | #define XMM { OP_XMM, xmm_mode } |
ce518a5f | 338 | #define EM { OP_EM, v_mode } |
b6169b20 | 339 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 340 | #define EMd { OP_EM, d_mode } |
14051056 | 341 | #define EMx { OP_EM, x_mode } |
8976381e | 342 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 343 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 344 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 345 | #define EXq { OP_EX, q_mode } |
b6169b20 | 346 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 347 | #define EXx { OP_EX, x_mode } |
b6169b20 | 348 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 L |
349 | #define EXxmm { OP_EX, xmm_mode } |
350 | #define EXxmmq { OP_EX, xmmq_mode } | |
351 | #define EXymmq { OP_EX, ymmq_mode } | |
0bfee649 | 352 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
ce518a5f L |
353 | #define MS { OP_MS, v_mode } |
354 | #define XS { OP_XS, v_mode } | |
09335d05 | 355 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 356 | #define MXC { OP_MXC, 0 } |
ce518a5f | 357 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 358 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 359 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 360 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
361 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
362 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 363 | |
c0f3af97 L |
364 | #define Vex { OP_VEX, vex_mode } |
365 | #define Vex128 { OP_VEX, vex128_mode } | |
366 | #define Vex256 { OP_VEX, vex256_mode } | |
922d8de8 | 367 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 368 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 369 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
c0f3af97 | 370 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 371 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
922d8de8 DR |
372 | #define EXVexW { OP_EX_VexW, x_mode } |
373 | #define EXdVexW { OP_EX_VexW, d_mode } | |
374 | #define EXqVexW { OP_EX_VexW, q_mode } | |
c0f3af97 | 375 | #define XMVex { OP_XMM_Vex, 0 } |
922d8de8 | 376 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
377 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
378 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
379 | #define VZERO { VZERO_Fixup, 0 } | |
380 | #define VCMP { VCMP_Fixup, 0 } | |
c0f3af97 | 381 | |
35c52694 | 382 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
383 | #define Xbr { REP_Fixup, eSI_reg } |
384 | #define Xvr { REP_Fixup, eSI_reg } | |
385 | #define Ybr { REP_Fixup, eDI_reg } | |
386 | #define Yvr { REP_Fixup, eDI_reg } | |
387 | #define Yzr { REP_Fixup, eDI_reg } | |
388 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
389 | #define ALr { REP_Fixup, al_reg } | |
390 | #define eAXr { REP_Fixup, eAX_reg } | |
391 | ||
392 | #define cond_jump_flag { NULL, cond_jump_mode } | |
393 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 394 | |
252b5132 | 395 | /* bits in sizeflag */ |
252b5132 | 396 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
397 | #define AFLAG 2 |
398 | #define DFLAG 1 | |
399 | ||
51e7da1b L |
400 | enum |
401 | { | |
402 | /* byte operand */ | |
403 | b_mode = 1, | |
404 | /* byte operand with operand swapped */ | |
3873ba12 | 405 | b_swap_mode, |
51e7da1b | 406 | /* operand size depends on prefixes */ |
3873ba12 | 407 | v_mode, |
51e7da1b | 408 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 409 | v_swap_mode, |
51e7da1b | 410 | /* word operand */ |
3873ba12 | 411 | w_mode, |
51e7da1b | 412 | /* double word operand */ |
3873ba12 | 413 | d_mode, |
51e7da1b | 414 | /* double word operand with operand swapped */ |
3873ba12 | 415 | d_swap_mode, |
51e7da1b | 416 | /* quad word operand */ |
3873ba12 | 417 | q_mode, |
51e7da1b | 418 | /* quad word operand with operand swapped */ |
3873ba12 | 419 | q_swap_mode, |
51e7da1b | 420 | /* ten-byte operand */ |
3873ba12 | 421 | t_mode, |
51e7da1b | 422 | /* 16-byte XMM or 32-byte YMM operand */ |
3873ba12 | 423 | x_mode, |
51e7da1b | 424 | /* 16-byte XMM or 32-byte YMM operand with operand swapped */ |
3873ba12 | 425 | x_swap_mode, |
51e7da1b | 426 | /* 16-byte XMM operand */ |
3873ba12 | 427 | xmm_mode, |
51e7da1b | 428 | /* 16-byte XMM or quad word operand */ |
3873ba12 | 429 | xmmq_mode, |
51e7da1b | 430 | /* 32-byte YMM or quad word operand */ |
3873ba12 | 431 | ymmq_mode, |
51e7da1b | 432 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 433 | m_mode, |
51e7da1b | 434 | /* pair of v_mode operands */ |
3873ba12 L |
435 | a_mode, |
436 | cond_jump_mode, | |
437 | loop_jcxz_mode, | |
51e7da1b | 438 | /* operand size depends on REX prefixes. */ |
3873ba12 | 439 | dq_mode, |
51e7da1b | 440 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 441 | dqw_mode, |
51e7da1b | 442 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
443 | f_mode, |
444 | const_1_mode, | |
51e7da1b | 445 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 446 | stack_v_mode, |
51e7da1b | 447 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 448 | z_mode, |
51e7da1b | 449 | /* 16-byte operand */ |
3873ba12 | 450 | o_mode, |
51e7da1b | 451 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 452 | dqb_mode, |
51e7da1b | 453 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 454 | dqd_mode, |
51e7da1b | 455 | /* normal vex mode */ |
3873ba12 | 456 | vex_mode, |
51e7da1b | 457 | /* 128bit vex mode */ |
3873ba12 | 458 | vex128_mode, |
51e7da1b | 459 | /* 256bit vex mode */ |
3873ba12 | 460 | vex256_mode, |
51e7da1b | 461 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 462 | vex_w_dq_mode, |
d55ee72f | 463 | |
3873ba12 L |
464 | es_reg, |
465 | cs_reg, | |
466 | ss_reg, | |
467 | ds_reg, | |
468 | fs_reg, | |
469 | gs_reg, | |
d55ee72f | 470 | |
3873ba12 L |
471 | eAX_reg, |
472 | eCX_reg, | |
473 | eDX_reg, | |
474 | eBX_reg, | |
475 | eSP_reg, | |
476 | eBP_reg, | |
477 | eSI_reg, | |
478 | eDI_reg, | |
d55ee72f | 479 | |
3873ba12 L |
480 | al_reg, |
481 | cl_reg, | |
482 | dl_reg, | |
483 | bl_reg, | |
484 | ah_reg, | |
485 | ch_reg, | |
486 | dh_reg, | |
487 | bh_reg, | |
d55ee72f | 488 | |
3873ba12 L |
489 | ax_reg, |
490 | cx_reg, | |
491 | dx_reg, | |
492 | bx_reg, | |
493 | sp_reg, | |
494 | bp_reg, | |
495 | si_reg, | |
496 | di_reg, | |
d55ee72f | 497 | |
3873ba12 L |
498 | rAX_reg, |
499 | rCX_reg, | |
500 | rDX_reg, | |
501 | rBX_reg, | |
502 | rSP_reg, | |
503 | rBP_reg, | |
504 | rSI_reg, | |
505 | rDI_reg, | |
d55ee72f | 506 | |
3873ba12 L |
507 | z_mode_ax_reg, |
508 | indir_dx_reg | |
51e7da1b | 509 | }; |
252b5132 | 510 | |
51e7da1b L |
511 | enum |
512 | { | |
513 | FLOATCODE = 1, | |
3873ba12 L |
514 | USE_REG_TABLE, |
515 | USE_MOD_TABLE, | |
516 | USE_RM_TABLE, | |
517 | USE_PREFIX_TABLE, | |
518 | USE_X86_64_TABLE, | |
519 | USE_3BYTE_TABLE, | |
f88c9eb0 | 520 | USE_XOP_8F_TABLE, |
3873ba12 L |
521 | USE_VEX_C4_TABLE, |
522 | USE_VEX_C5_TABLE, | |
9e30b8e0 L |
523 | USE_VEX_LEN_TABLE, |
524 | USE_VEX_W_TABLE | |
51e7da1b | 525 | }; |
6439fc28 | 526 | |
1ceb70f8 | 527 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 528 | |
4e7d34a6 | 529 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
530 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
531 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
532 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
533 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
534 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
535 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
f88c9eb0 | 536 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
537 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
538 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
539 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 540 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
1ceb70f8 | 541 | |
51e7da1b L |
542 | enum |
543 | { | |
544 | REG_80 = 0, | |
3873ba12 L |
545 | REG_81, |
546 | REG_82, | |
547 | REG_8F, | |
548 | REG_C0, | |
549 | REG_C1, | |
550 | REG_C6, | |
551 | REG_C7, | |
552 | REG_D0, | |
553 | REG_D1, | |
554 | REG_D2, | |
555 | REG_D3, | |
556 | REG_F6, | |
557 | REG_F7, | |
558 | REG_FE, | |
559 | REG_FF, | |
560 | REG_0F00, | |
561 | REG_0F01, | |
562 | REG_0F0D, | |
563 | REG_0F18, | |
564 | REG_0F71, | |
565 | REG_0F72, | |
566 | REG_0F73, | |
567 | REG_0FA6, | |
568 | REG_0FA7, | |
569 | REG_0FAE, | |
570 | REG_0FBA, | |
571 | REG_0FC7, | |
572 | REG_VEX_71, | |
573 | REG_VEX_72, | |
574 | REG_VEX_73, | |
f88c9eb0 SP |
575 | REG_VEX_AE, |
576 | REG_XOP_LWPCB, | |
577 | REG_XOP_LWP | |
51e7da1b | 578 | }; |
1ceb70f8 | 579 | |
51e7da1b L |
580 | enum |
581 | { | |
582 | MOD_8D = 0, | |
3873ba12 L |
583 | MOD_0F01_REG_0, |
584 | MOD_0F01_REG_1, | |
585 | MOD_0F01_REG_2, | |
586 | MOD_0F01_REG_3, | |
587 | MOD_0F01_REG_7, | |
588 | MOD_0F12_PREFIX_0, | |
589 | MOD_0F13, | |
590 | MOD_0F16_PREFIX_0, | |
591 | MOD_0F17, | |
592 | MOD_0F18_REG_0, | |
593 | MOD_0F18_REG_1, | |
594 | MOD_0F18_REG_2, | |
595 | MOD_0F18_REG_3, | |
596 | MOD_0F20, | |
597 | MOD_0F21, | |
598 | MOD_0F22, | |
599 | MOD_0F23, | |
600 | MOD_0F24, | |
601 | MOD_0F26, | |
602 | MOD_0F2B_PREFIX_0, | |
603 | MOD_0F2B_PREFIX_1, | |
604 | MOD_0F2B_PREFIX_2, | |
605 | MOD_0F2B_PREFIX_3, | |
606 | MOD_0F51, | |
607 | MOD_0F71_REG_2, | |
608 | MOD_0F71_REG_4, | |
609 | MOD_0F71_REG_6, | |
610 | MOD_0F72_REG_2, | |
611 | MOD_0F72_REG_4, | |
612 | MOD_0F72_REG_6, | |
613 | MOD_0F73_REG_2, | |
614 | MOD_0F73_REG_3, | |
615 | MOD_0F73_REG_6, | |
616 | MOD_0F73_REG_7, | |
617 | MOD_0FAE_REG_0, | |
618 | MOD_0FAE_REG_1, | |
619 | MOD_0FAE_REG_2, | |
620 | MOD_0FAE_REG_3, | |
621 | MOD_0FAE_REG_4, | |
622 | MOD_0FAE_REG_5, | |
623 | MOD_0FAE_REG_6, | |
624 | MOD_0FAE_REG_7, | |
625 | MOD_0FB2, | |
626 | MOD_0FB4, | |
627 | MOD_0FB5, | |
628 | MOD_0FC7_REG_6, | |
629 | MOD_0FC7_REG_7, | |
630 | MOD_0FD7, | |
631 | MOD_0FE7_PREFIX_2, | |
632 | MOD_0FF0_PREFIX_3, | |
633 | MOD_0F382A_PREFIX_2, | |
634 | MOD_62_32BIT, | |
635 | MOD_C4_32BIT, | |
636 | MOD_C5_32BIT, | |
637 | MOD_VEX_12_PREFIX_0, | |
638 | MOD_VEX_13, | |
639 | MOD_VEX_16_PREFIX_0, | |
640 | MOD_VEX_17, | |
641 | MOD_VEX_2B, | |
976f1fde | 642 | MOD_VEX_50, |
3873ba12 L |
643 | MOD_VEX_71_REG_2, |
644 | MOD_VEX_71_REG_4, | |
645 | MOD_VEX_71_REG_6, | |
646 | MOD_VEX_72_REG_2, | |
647 | MOD_VEX_72_REG_4, | |
648 | MOD_VEX_72_REG_6, | |
649 | MOD_VEX_73_REG_2, | |
650 | MOD_VEX_73_REG_3, | |
651 | MOD_VEX_73_REG_6, | |
652 | MOD_VEX_73_REG_7, | |
653 | MOD_VEX_AE_REG_2, | |
654 | MOD_VEX_AE_REG_3, | |
655 | MOD_VEX_D7_PREFIX_2, | |
656 | MOD_VEX_E7_PREFIX_2, | |
657 | MOD_VEX_F0_PREFIX_3, | |
658 | MOD_VEX_3818_PREFIX_2, | |
659 | MOD_VEX_3819_PREFIX_2, | |
660 | MOD_VEX_381A_PREFIX_2, | |
661 | MOD_VEX_382A_PREFIX_2, | |
662 | MOD_VEX_382C_PREFIX_2, | |
663 | MOD_VEX_382D_PREFIX_2, | |
664 | MOD_VEX_382E_PREFIX_2, | |
665 | MOD_VEX_382F_PREFIX_2 | |
51e7da1b | 666 | }; |
1ceb70f8 | 667 | |
51e7da1b L |
668 | enum |
669 | { | |
670 | RM_0F01_REG_0 = 0, | |
3873ba12 L |
671 | RM_0F01_REG_1, |
672 | RM_0F01_REG_2, | |
673 | RM_0F01_REG_3, | |
674 | RM_0F01_REG_7, | |
675 | RM_0FAE_REG_5, | |
676 | RM_0FAE_REG_6, | |
677 | RM_0FAE_REG_7 | |
51e7da1b | 678 | }; |
1ceb70f8 | 679 | |
51e7da1b L |
680 | enum |
681 | { | |
682 | PREFIX_90 = 0, | |
3873ba12 L |
683 | PREFIX_0F10, |
684 | PREFIX_0F11, | |
685 | PREFIX_0F12, | |
686 | PREFIX_0F16, | |
687 | PREFIX_0F2A, | |
688 | PREFIX_0F2B, | |
689 | PREFIX_0F2C, | |
690 | PREFIX_0F2D, | |
691 | PREFIX_0F2E, | |
692 | PREFIX_0F2F, | |
693 | PREFIX_0F51, | |
694 | PREFIX_0F52, | |
695 | PREFIX_0F53, | |
696 | PREFIX_0F58, | |
697 | PREFIX_0F59, | |
698 | PREFIX_0F5A, | |
699 | PREFIX_0F5B, | |
700 | PREFIX_0F5C, | |
701 | PREFIX_0F5D, | |
702 | PREFIX_0F5E, | |
703 | PREFIX_0F5F, | |
704 | PREFIX_0F60, | |
705 | PREFIX_0F61, | |
706 | PREFIX_0F62, | |
707 | PREFIX_0F6C, | |
708 | PREFIX_0F6D, | |
709 | PREFIX_0F6F, | |
710 | PREFIX_0F70, | |
711 | PREFIX_0F73_REG_3, | |
712 | PREFIX_0F73_REG_7, | |
713 | PREFIX_0F78, | |
714 | PREFIX_0F79, | |
715 | PREFIX_0F7C, | |
716 | PREFIX_0F7D, | |
717 | PREFIX_0F7E, | |
718 | PREFIX_0F7F, | |
719 | PREFIX_0FB8, | |
720 | PREFIX_0FBD, | |
721 | PREFIX_0FC2, | |
722 | PREFIX_0FC3, | |
723 | PREFIX_0FC7_REG_6, | |
724 | PREFIX_0FD0, | |
725 | PREFIX_0FD6, | |
726 | PREFIX_0FE6, | |
727 | PREFIX_0FE7, | |
728 | PREFIX_0FF0, | |
729 | PREFIX_0FF7, | |
730 | PREFIX_0F3810, | |
731 | PREFIX_0F3814, | |
732 | PREFIX_0F3815, | |
733 | PREFIX_0F3817, | |
734 | PREFIX_0F3820, | |
735 | PREFIX_0F3821, | |
736 | PREFIX_0F3822, | |
737 | PREFIX_0F3823, | |
738 | PREFIX_0F3824, | |
739 | PREFIX_0F3825, | |
740 | PREFIX_0F3828, | |
741 | PREFIX_0F3829, | |
742 | PREFIX_0F382A, | |
743 | PREFIX_0F382B, | |
744 | PREFIX_0F3830, | |
745 | PREFIX_0F3831, | |
746 | PREFIX_0F3832, | |
747 | PREFIX_0F3833, | |
748 | PREFIX_0F3834, | |
749 | PREFIX_0F3835, | |
750 | PREFIX_0F3837, | |
751 | PREFIX_0F3838, | |
752 | PREFIX_0F3839, | |
753 | PREFIX_0F383A, | |
754 | PREFIX_0F383B, | |
755 | PREFIX_0F383C, | |
756 | PREFIX_0F383D, | |
757 | PREFIX_0F383E, | |
758 | PREFIX_0F383F, | |
759 | PREFIX_0F3840, | |
760 | PREFIX_0F3841, | |
761 | PREFIX_0F3880, | |
762 | PREFIX_0F3881, | |
763 | PREFIX_0F38DB, | |
764 | PREFIX_0F38DC, | |
765 | PREFIX_0F38DD, | |
766 | PREFIX_0F38DE, | |
767 | PREFIX_0F38DF, | |
768 | PREFIX_0F38F0, | |
769 | PREFIX_0F38F1, | |
770 | PREFIX_0F3A08, | |
771 | PREFIX_0F3A09, | |
772 | PREFIX_0F3A0A, | |
773 | PREFIX_0F3A0B, | |
774 | PREFIX_0F3A0C, | |
775 | PREFIX_0F3A0D, | |
776 | PREFIX_0F3A0E, | |
777 | PREFIX_0F3A14, | |
778 | PREFIX_0F3A15, | |
779 | PREFIX_0F3A16, | |
780 | PREFIX_0F3A17, | |
781 | PREFIX_0F3A20, | |
782 | PREFIX_0F3A21, | |
783 | PREFIX_0F3A22, | |
784 | PREFIX_0F3A40, | |
785 | PREFIX_0F3A41, | |
786 | PREFIX_0F3A42, | |
787 | PREFIX_0F3A44, | |
788 | PREFIX_0F3A60, | |
789 | PREFIX_0F3A61, | |
790 | PREFIX_0F3A62, | |
791 | PREFIX_0F3A63, | |
792 | PREFIX_0F3ADF, | |
793 | PREFIX_VEX_10, | |
794 | PREFIX_VEX_11, | |
795 | PREFIX_VEX_12, | |
796 | PREFIX_VEX_16, | |
797 | PREFIX_VEX_2A, | |
798 | PREFIX_VEX_2C, | |
799 | PREFIX_VEX_2D, | |
800 | PREFIX_VEX_2E, | |
801 | PREFIX_VEX_2F, | |
802 | PREFIX_VEX_51, | |
803 | PREFIX_VEX_52, | |
804 | PREFIX_VEX_53, | |
805 | PREFIX_VEX_58, | |
806 | PREFIX_VEX_59, | |
807 | PREFIX_VEX_5A, | |
808 | PREFIX_VEX_5B, | |
809 | PREFIX_VEX_5C, | |
810 | PREFIX_VEX_5D, | |
811 | PREFIX_VEX_5E, | |
812 | PREFIX_VEX_5F, | |
813 | PREFIX_VEX_60, | |
814 | PREFIX_VEX_61, | |
815 | PREFIX_VEX_62, | |
816 | PREFIX_VEX_63, | |
817 | PREFIX_VEX_64, | |
818 | PREFIX_VEX_65, | |
819 | PREFIX_VEX_66, | |
820 | PREFIX_VEX_67, | |
821 | PREFIX_VEX_68, | |
822 | PREFIX_VEX_69, | |
823 | PREFIX_VEX_6A, | |
824 | PREFIX_VEX_6B, | |
825 | PREFIX_VEX_6C, | |
826 | PREFIX_VEX_6D, | |
827 | PREFIX_VEX_6E, | |
828 | PREFIX_VEX_6F, | |
829 | PREFIX_VEX_70, | |
830 | PREFIX_VEX_71_REG_2, | |
831 | PREFIX_VEX_71_REG_4, | |
832 | PREFIX_VEX_71_REG_6, | |
833 | PREFIX_VEX_72_REG_2, | |
834 | PREFIX_VEX_72_REG_4, | |
835 | PREFIX_VEX_72_REG_6, | |
836 | PREFIX_VEX_73_REG_2, | |
837 | PREFIX_VEX_73_REG_3, | |
838 | PREFIX_VEX_73_REG_6, | |
839 | PREFIX_VEX_73_REG_7, | |
840 | PREFIX_VEX_74, | |
841 | PREFIX_VEX_75, | |
842 | PREFIX_VEX_76, | |
843 | PREFIX_VEX_77, | |
844 | PREFIX_VEX_7C, | |
845 | PREFIX_VEX_7D, | |
846 | PREFIX_VEX_7E, | |
847 | PREFIX_VEX_7F, | |
848 | PREFIX_VEX_C2, | |
849 | PREFIX_VEX_C4, | |
850 | PREFIX_VEX_C5, | |
851 | PREFIX_VEX_D0, | |
852 | PREFIX_VEX_D1, | |
853 | PREFIX_VEX_D2, | |
854 | PREFIX_VEX_D3, | |
855 | PREFIX_VEX_D4, | |
856 | PREFIX_VEX_D5, | |
857 | PREFIX_VEX_D6, | |
858 | PREFIX_VEX_D7, | |
859 | PREFIX_VEX_D8, | |
860 | PREFIX_VEX_D9, | |
861 | PREFIX_VEX_DA, | |
862 | PREFIX_VEX_DB, | |
863 | PREFIX_VEX_DC, | |
864 | PREFIX_VEX_DD, | |
865 | PREFIX_VEX_DE, | |
866 | PREFIX_VEX_DF, | |
867 | PREFIX_VEX_E0, | |
868 | PREFIX_VEX_E1, | |
869 | PREFIX_VEX_E2, | |
870 | PREFIX_VEX_E3, | |
871 | PREFIX_VEX_E4, | |
872 | PREFIX_VEX_E5, | |
873 | PREFIX_VEX_E6, | |
874 | PREFIX_VEX_E7, | |
875 | PREFIX_VEX_E8, | |
876 | PREFIX_VEX_E9, | |
877 | PREFIX_VEX_EA, | |
878 | PREFIX_VEX_EB, | |
879 | PREFIX_VEX_EC, | |
880 | PREFIX_VEX_ED, | |
881 | PREFIX_VEX_EE, | |
882 | PREFIX_VEX_EF, | |
883 | PREFIX_VEX_F0, | |
884 | PREFIX_VEX_F1, | |
885 | PREFIX_VEX_F2, | |
886 | PREFIX_VEX_F3, | |
887 | PREFIX_VEX_F4, | |
888 | PREFIX_VEX_F5, | |
889 | PREFIX_VEX_F6, | |
890 | PREFIX_VEX_F7, | |
891 | PREFIX_VEX_F8, | |
892 | PREFIX_VEX_F9, | |
893 | PREFIX_VEX_FA, | |
894 | PREFIX_VEX_FB, | |
895 | PREFIX_VEX_FC, | |
896 | PREFIX_VEX_FD, | |
897 | PREFIX_VEX_FE, | |
898 | PREFIX_VEX_3800, | |
899 | PREFIX_VEX_3801, | |
900 | PREFIX_VEX_3802, | |
901 | PREFIX_VEX_3803, | |
902 | PREFIX_VEX_3804, | |
903 | PREFIX_VEX_3805, | |
904 | PREFIX_VEX_3806, | |
905 | PREFIX_VEX_3807, | |
906 | PREFIX_VEX_3808, | |
907 | PREFIX_VEX_3809, | |
908 | PREFIX_VEX_380A, | |
909 | PREFIX_VEX_380B, | |
910 | PREFIX_VEX_380C, | |
911 | PREFIX_VEX_380D, | |
912 | PREFIX_VEX_380E, | |
913 | PREFIX_VEX_380F, | |
914 | PREFIX_VEX_3817, | |
915 | PREFIX_VEX_3818, | |
916 | PREFIX_VEX_3819, | |
917 | PREFIX_VEX_381A, | |
918 | PREFIX_VEX_381C, | |
919 | PREFIX_VEX_381D, | |
920 | PREFIX_VEX_381E, | |
921 | PREFIX_VEX_3820, | |
922 | PREFIX_VEX_3821, | |
923 | PREFIX_VEX_3822, | |
924 | PREFIX_VEX_3823, | |
925 | PREFIX_VEX_3824, | |
926 | PREFIX_VEX_3825, | |
927 | PREFIX_VEX_3828, | |
928 | PREFIX_VEX_3829, | |
929 | PREFIX_VEX_382A, | |
930 | PREFIX_VEX_382B, | |
931 | PREFIX_VEX_382C, | |
932 | PREFIX_VEX_382D, | |
933 | PREFIX_VEX_382E, | |
934 | PREFIX_VEX_382F, | |
935 | PREFIX_VEX_3830, | |
936 | PREFIX_VEX_3831, | |
937 | PREFIX_VEX_3832, | |
938 | PREFIX_VEX_3833, | |
939 | PREFIX_VEX_3834, | |
940 | PREFIX_VEX_3835, | |
941 | PREFIX_VEX_3837, | |
942 | PREFIX_VEX_3838, | |
943 | PREFIX_VEX_3839, | |
944 | PREFIX_VEX_383A, | |
945 | PREFIX_VEX_383B, | |
946 | PREFIX_VEX_383C, | |
947 | PREFIX_VEX_383D, | |
948 | PREFIX_VEX_383E, | |
949 | PREFIX_VEX_383F, | |
950 | PREFIX_VEX_3840, | |
951 | PREFIX_VEX_3841, | |
952 | PREFIX_VEX_3896, | |
953 | PREFIX_VEX_3897, | |
954 | PREFIX_VEX_3898, | |
955 | PREFIX_VEX_3899, | |
956 | PREFIX_VEX_389A, | |
957 | PREFIX_VEX_389B, | |
958 | PREFIX_VEX_389C, | |
959 | PREFIX_VEX_389D, | |
960 | PREFIX_VEX_389E, | |
961 | PREFIX_VEX_389F, | |
962 | PREFIX_VEX_38A6, | |
963 | PREFIX_VEX_38A7, | |
964 | PREFIX_VEX_38A8, | |
965 | PREFIX_VEX_38A9, | |
966 | PREFIX_VEX_38AA, | |
967 | PREFIX_VEX_38AB, | |
968 | PREFIX_VEX_38AC, | |
969 | PREFIX_VEX_38AD, | |
970 | PREFIX_VEX_38AE, | |
971 | PREFIX_VEX_38AF, | |
972 | PREFIX_VEX_38B6, | |
973 | PREFIX_VEX_38B7, | |
974 | PREFIX_VEX_38B8, | |
975 | PREFIX_VEX_38B9, | |
976 | PREFIX_VEX_38BA, | |
977 | PREFIX_VEX_38BB, | |
978 | PREFIX_VEX_38BC, | |
979 | PREFIX_VEX_38BD, | |
980 | PREFIX_VEX_38BE, | |
981 | PREFIX_VEX_38BF, | |
982 | PREFIX_VEX_38DB, | |
983 | PREFIX_VEX_38DC, | |
984 | PREFIX_VEX_38DD, | |
985 | PREFIX_VEX_38DE, | |
986 | PREFIX_VEX_38DF, | |
987 | PREFIX_VEX_3A04, | |
988 | PREFIX_VEX_3A05, | |
989 | PREFIX_VEX_3A06, | |
990 | PREFIX_VEX_3A08, | |
991 | PREFIX_VEX_3A09, | |
992 | PREFIX_VEX_3A0A, | |
993 | PREFIX_VEX_3A0B, | |
994 | PREFIX_VEX_3A0C, | |
995 | PREFIX_VEX_3A0D, | |
996 | PREFIX_VEX_3A0E, | |
997 | PREFIX_VEX_3A0F, | |
998 | PREFIX_VEX_3A14, | |
999 | PREFIX_VEX_3A15, | |
1000 | PREFIX_VEX_3A16, | |
1001 | PREFIX_VEX_3A17, | |
1002 | PREFIX_VEX_3A18, | |
1003 | PREFIX_VEX_3A19, | |
1004 | PREFIX_VEX_3A20, | |
1005 | PREFIX_VEX_3A21, | |
1006 | PREFIX_VEX_3A22, | |
1007 | PREFIX_VEX_3A40, | |
1008 | PREFIX_VEX_3A41, | |
1009 | PREFIX_VEX_3A42, | |
1010 | PREFIX_VEX_3A44, | |
1011 | PREFIX_VEX_3A4A, | |
1012 | PREFIX_VEX_3A4B, | |
1013 | PREFIX_VEX_3A4C, | |
1014 | PREFIX_VEX_3A5C, | |
1015 | PREFIX_VEX_3A5D, | |
1016 | PREFIX_VEX_3A5E, | |
1017 | PREFIX_VEX_3A5F, | |
1018 | PREFIX_VEX_3A60, | |
1019 | PREFIX_VEX_3A61, | |
1020 | PREFIX_VEX_3A62, | |
1021 | PREFIX_VEX_3A63, | |
1022 | PREFIX_VEX_3A68, | |
1023 | PREFIX_VEX_3A69, | |
1024 | PREFIX_VEX_3A6A, | |
1025 | PREFIX_VEX_3A6B, | |
1026 | PREFIX_VEX_3A6C, | |
1027 | PREFIX_VEX_3A6D, | |
1028 | PREFIX_VEX_3A6E, | |
1029 | PREFIX_VEX_3A6F, | |
1030 | PREFIX_VEX_3A78, | |
1031 | PREFIX_VEX_3A79, | |
1032 | PREFIX_VEX_3A7A, | |
1033 | PREFIX_VEX_3A7B, | |
1034 | PREFIX_VEX_3A7C, | |
1035 | PREFIX_VEX_3A7D, | |
1036 | PREFIX_VEX_3A7E, | |
1037 | PREFIX_VEX_3A7F, | |
1038 | PREFIX_VEX_3ADF | |
51e7da1b | 1039 | }; |
4e7d34a6 | 1040 | |
51e7da1b L |
1041 | enum |
1042 | { | |
1043 | X86_64_06 = 0, | |
3873ba12 L |
1044 | X86_64_07, |
1045 | X86_64_0D, | |
1046 | X86_64_16, | |
1047 | X86_64_17, | |
1048 | X86_64_1E, | |
1049 | X86_64_1F, | |
1050 | X86_64_27, | |
1051 | X86_64_2F, | |
1052 | X86_64_37, | |
1053 | X86_64_3F, | |
1054 | X86_64_60, | |
1055 | X86_64_61, | |
1056 | X86_64_62, | |
1057 | X86_64_63, | |
1058 | X86_64_6D, | |
1059 | X86_64_6F, | |
1060 | X86_64_9A, | |
1061 | X86_64_C4, | |
1062 | X86_64_C5, | |
1063 | X86_64_CE, | |
1064 | X86_64_D4, | |
1065 | X86_64_D5, | |
1066 | X86_64_EA, | |
1067 | X86_64_0F01_REG_0, | |
1068 | X86_64_0F01_REG_1, | |
1069 | X86_64_0F01_REG_2, | |
1070 | X86_64_0F01_REG_3 | |
51e7da1b | 1071 | }; |
4e7d34a6 | 1072 | |
51e7da1b L |
1073 | enum |
1074 | { | |
1075 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1076 | THREE_BYTE_0F3A, |
1077 | THREE_BYTE_0F7A | |
51e7da1b | 1078 | }; |
4e7d34a6 | 1079 | |
f88c9eb0 SP |
1080 | enum |
1081 | { | |
5dd85c99 SP |
1082 | XOP_08 = 0, |
1083 | XOP_09, | |
f88c9eb0 SP |
1084 | XOP_0A |
1085 | }; | |
1086 | ||
51e7da1b L |
1087 | enum |
1088 | { | |
1089 | VEX_0F = 0, | |
3873ba12 L |
1090 | VEX_0F38, |
1091 | VEX_0F3A | |
51e7da1b | 1092 | }; |
c0f3af97 | 1093 | |
51e7da1b L |
1094 | enum |
1095 | { | |
1096 | VEX_LEN_10_P_1 = 0, | |
3873ba12 L |
1097 | VEX_LEN_10_P_3, |
1098 | VEX_LEN_11_P_1, | |
1099 | VEX_LEN_11_P_3, | |
1100 | VEX_LEN_12_P_0_M_0, | |
1101 | VEX_LEN_12_P_0_M_1, | |
1102 | VEX_LEN_12_P_2, | |
1103 | VEX_LEN_13_M_0, | |
1104 | VEX_LEN_16_P_0_M_0, | |
1105 | VEX_LEN_16_P_0_M_1, | |
1106 | VEX_LEN_16_P_2, | |
1107 | VEX_LEN_17_M_0, | |
1108 | VEX_LEN_2A_P_1, | |
1109 | VEX_LEN_2A_P_3, | |
1110 | VEX_LEN_2C_P_1, | |
1111 | VEX_LEN_2C_P_3, | |
1112 | VEX_LEN_2D_P_1, | |
1113 | VEX_LEN_2D_P_3, | |
1114 | VEX_LEN_2E_P_0, | |
1115 | VEX_LEN_2E_P_2, | |
1116 | VEX_LEN_2F_P_0, | |
1117 | VEX_LEN_2F_P_2, | |
1118 | VEX_LEN_51_P_1, | |
1119 | VEX_LEN_51_P_3, | |
1120 | VEX_LEN_52_P_1, | |
1121 | VEX_LEN_53_P_1, | |
1122 | VEX_LEN_58_P_1, | |
1123 | VEX_LEN_58_P_3, | |
1124 | VEX_LEN_59_P_1, | |
1125 | VEX_LEN_59_P_3, | |
1126 | VEX_LEN_5A_P_1, | |
1127 | VEX_LEN_5A_P_3, | |
1128 | VEX_LEN_5C_P_1, | |
1129 | VEX_LEN_5C_P_3, | |
1130 | VEX_LEN_5D_P_1, | |
1131 | VEX_LEN_5D_P_3, | |
1132 | VEX_LEN_5E_P_1, | |
1133 | VEX_LEN_5E_P_3, | |
1134 | VEX_LEN_5F_P_1, | |
1135 | VEX_LEN_5F_P_3, | |
1136 | VEX_LEN_60_P_2, | |
1137 | VEX_LEN_61_P_2, | |
1138 | VEX_LEN_62_P_2, | |
1139 | VEX_LEN_63_P_2, | |
1140 | VEX_LEN_64_P_2, | |
1141 | VEX_LEN_65_P_2, | |
1142 | VEX_LEN_66_P_2, | |
1143 | VEX_LEN_67_P_2, | |
1144 | VEX_LEN_68_P_2, | |
1145 | VEX_LEN_69_P_2, | |
1146 | VEX_LEN_6A_P_2, | |
1147 | VEX_LEN_6B_P_2, | |
1148 | VEX_LEN_6C_P_2, | |
1149 | VEX_LEN_6D_P_2, | |
1150 | VEX_LEN_6E_P_2, | |
1151 | VEX_LEN_70_P_1, | |
1152 | VEX_LEN_70_P_2, | |
1153 | VEX_LEN_70_P_3, | |
1154 | VEX_LEN_71_R_2_P_2, | |
1155 | VEX_LEN_71_R_4_P_2, | |
1156 | VEX_LEN_71_R_6_P_2, | |
1157 | VEX_LEN_72_R_2_P_2, | |
1158 | VEX_LEN_72_R_4_P_2, | |
1159 | VEX_LEN_72_R_6_P_2, | |
1160 | VEX_LEN_73_R_2_P_2, | |
1161 | VEX_LEN_73_R_3_P_2, | |
1162 | VEX_LEN_73_R_6_P_2, | |
1163 | VEX_LEN_73_R_7_P_2, | |
1164 | VEX_LEN_74_P_2, | |
1165 | VEX_LEN_75_P_2, | |
1166 | VEX_LEN_76_P_2, | |
1167 | VEX_LEN_7E_P_1, | |
1168 | VEX_LEN_7E_P_2, | |
1169 | VEX_LEN_AE_R_2_M_0, | |
1170 | VEX_LEN_AE_R_3_M_0, | |
1171 | VEX_LEN_C2_P_1, | |
1172 | VEX_LEN_C2_P_3, | |
1173 | VEX_LEN_C4_P_2, | |
1174 | VEX_LEN_C5_P_2, | |
1175 | VEX_LEN_D1_P_2, | |
1176 | VEX_LEN_D2_P_2, | |
1177 | VEX_LEN_D3_P_2, | |
1178 | VEX_LEN_D4_P_2, | |
1179 | VEX_LEN_D5_P_2, | |
1180 | VEX_LEN_D6_P_2, | |
1181 | VEX_LEN_D7_P_2_M_1, | |
1182 | VEX_LEN_D8_P_2, | |
1183 | VEX_LEN_D9_P_2, | |
1184 | VEX_LEN_DA_P_2, | |
1185 | VEX_LEN_DB_P_2, | |
1186 | VEX_LEN_DC_P_2, | |
1187 | VEX_LEN_DD_P_2, | |
1188 | VEX_LEN_DE_P_2, | |
1189 | VEX_LEN_DF_P_2, | |
1190 | VEX_LEN_E0_P_2, | |
1191 | VEX_LEN_E1_P_2, | |
1192 | VEX_LEN_E2_P_2, | |
1193 | VEX_LEN_E3_P_2, | |
1194 | VEX_LEN_E4_P_2, | |
1195 | VEX_LEN_E5_P_2, | |
1196 | VEX_LEN_E8_P_2, | |
1197 | VEX_LEN_E9_P_2, | |
1198 | VEX_LEN_EA_P_2, | |
1199 | VEX_LEN_EB_P_2, | |
1200 | VEX_LEN_EC_P_2, | |
1201 | VEX_LEN_ED_P_2, | |
1202 | VEX_LEN_EE_P_2, | |
1203 | VEX_LEN_EF_P_2, | |
1204 | VEX_LEN_F1_P_2, | |
1205 | VEX_LEN_F2_P_2, | |
1206 | VEX_LEN_F3_P_2, | |
1207 | VEX_LEN_F4_P_2, | |
1208 | VEX_LEN_F5_P_2, | |
1209 | VEX_LEN_F6_P_2, | |
1210 | VEX_LEN_F7_P_2, | |
1211 | VEX_LEN_F8_P_2, | |
1212 | VEX_LEN_F9_P_2, | |
1213 | VEX_LEN_FA_P_2, | |
1214 | VEX_LEN_FB_P_2, | |
1215 | VEX_LEN_FC_P_2, | |
1216 | VEX_LEN_FD_P_2, | |
1217 | VEX_LEN_FE_P_2, | |
1218 | VEX_LEN_3800_P_2, | |
1219 | VEX_LEN_3801_P_2, | |
1220 | VEX_LEN_3802_P_2, | |
1221 | VEX_LEN_3803_P_2, | |
1222 | VEX_LEN_3804_P_2, | |
1223 | VEX_LEN_3805_P_2, | |
1224 | VEX_LEN_3806_P_2, | |
1225 | VEX_LEN_3807_P_2, | |
1226 | VEX_LEN_3808_P_2, | |
1227 | VEX_LEN_3809_P_2, | |
1228 | VEX_LEN_380A_P_2, | |
1229 | VEX_LEN_380B_P_2, | |
1230 | VEX_LEN_3819_P_2_M_0, | |
1231 | VEX_LEN_381A_P_2_M_0, | |
1232 | VEX_LEN_381C_P_2, | |
1233 | VEX_LEN_381D_P_2, | |
1234 | VEX_LEN_381E_P_2, | |
1235 | VEX_LEN_3820_P_2, | |
1236 | VEX_LEN_3821_P_2, | |
1237 | VEX_LEN_3822_P_2, | |
1238 | VEX_LEN_3823_P_2, | |
1239 | VEX_LEN_3824_P_2, | |
1240 | VEX_LEN_3825_P_2, | |
1241 | VEX_LEN_3828_P_2, | |
1242 | VEX_LEN_3829_P_2, | |
1243 | VEX_LEN_382A_P_2_M_0, | |
1244 | VEX_LEN_382B_P_2, | |
1245 | VEX_LEN_3830_P_2, | |
1246 | VEX_LEN_3831_P_2, | |
1247 | VEX_LEN_3832_P_2, | |
1248 | VEX_LEN_3833_P_2, | |
1249 | VEX_LEN_3834_P_2, | |
1250 | VEX_LEN_3835_P_2, | |
1251 | VEX_LEN_3837_P_2, | |
1252 | VEX_LEN_3838_P_2, | |
1253 | VEX_LEN_3839_P_2, | |
1254 | VEX_LEN_383A_P_2, | |
1255 | VEX_LEN_383B_P_2, | |
1256 | VEX_LEN_383C_P_2, | |
1257 | VEX_LEN_383D_P_2, | |
1258 | VEX_LEN_383E_P_2, | |
1259 | VEX_LEN_383F_P_2, | |
1260 | VEX_LEN_3840_P_2, | |
1261 | VEX_LEN_3841_P_2, | |
1262 | VEX_LEN_38DB_P_2, | |
1263 | VEX_LEN_38DC_P_2, | |
1264 | VEX_LEN_38DD_P_2, | |
1265 | VEX_LEN_38DE_P_2, | |
1266 | VEX_LEN_38DF_P_2, | |
1267 | VEX_LEN_3A06_P_2, | |
1268 | VEX_LEN_3A0A_P_2, | |
1269 | VEX_LEN_3A0B_P_2, | |
1270 | VEX_LEN_3A0E_P_2, | |
1271 | VEX_LEN_3A0F_P_2, | |
1272 | VEX_LEN_3A14_P_2, | |
1273 | VEX_LEN_3A15_P_2, | |
1274 | VEX_LEN_3A16_P_2, | |
1275 | VEX_LEN_3A17_P_2, | |
1276 | VEX_LEN_3A18_P_2, | |
1277 | VEX_LEN_3A19_P_2, | |
1278 | VEX_LEN_3A20_P_2, | |
1279 | VEX_LEN_3A21_P_2, | |
1280 | VEX_LEN_3A22_P_2, | |
1281 | VEX_LEN_3A41_P_2, | |
1282 | VEX_LEN_3A42_P_2, | |
1283 | VEX_LEN_3A44_P_2, | |
1284 | VEX_LEN_3A4C_P_2, | |
1285 | VEX_LEN_3A60_P_2, | |
1286 | VEX_LEN_3A61_P_2, | |
1287 | VEX_LEN_3A62_P_2, | |
1288 | VEX_LEN_3A63_P_2, | |
1289 | VEX_LEN_3A6A_P_2, | |
1290 | VEX_LEN_3A6B_P_2, | |
1291 | VEX_LEN_3A6E_P_2, | |
1292 | VEX_LEN_3A6F_P_2, | |
1293 | VEX_LEN_3A7A_P_2, | |
1294 | VEX_LEN_3A7B_P_2, | |
1295 | VEX_LEN_3A7E_P_2, | |
1296 | VEX_LEN_3A7F_P_2, | |
5dd85c99 | 1297 | VEX_LEN_3ADF_P_2, |
5dd85c99 SP |
1298 | VEX_LEN_XOP_09_80, |
1299 | VEX_LEN_XOP_09_81 | |
51e7da1b | 1300 | }; |
c0f3af97 | 1301 | |
9e30b8e0 L |
1302 | enum |
1303 | { | |
1304 | VEX_W_10_P_0 = 0, | |
1305 | VEX_W_10_P_1, | |
1306 | VEX_W_10_P_2, | |
1307 | VEX_W_10_P_3, | |
1308 | VEX_W_11_P_0, | |
1309 | VEX_W_11_P_1, | |
1310 | VEX_W_11_P_2, | |
1311 | VEX_W_11_P_3, | |
1312 | VEX_W_12_P_0_M_0, | |
1313 | VEX_W_12_P_0_M_1, | |
1314 | VEX_W_12_P_1, | |
1315 | VEX_W_12_P_2, | |
1316 | VEX_W_12_P_3, | |
1317 | VEX_W_13_M_0, | |
1318 | VEX_W_14, | |
1319 | VEX_W_15, | |
1320 | VEX_W_16_P_0_M_0, | |
1321 | VEX_W_16_P_0_M_1, | |
1322 | VEX_W_16_P_1, | |
1323 | VEX_W_16_P_2, | |
1324 | VEX_W_17_M_0, | |
1325 | VEX_W_28, | |
1326 | VEX_W_29, | |
1327 | VEX_W_2B_M_0, | |
1328 | VEX_W_2E_P_0, | |
1329 | VEX_W_2E_P_2, | |
1330 | VEX_W_2F_P_0, | |
1331 | VEX_W_2F_P_2, | |
1332 | VEX_W_50_M_0, | |
1333 | VEX_W_51_P_0, | |
1334 | VEX_W_51_P_1, | |
1335 | VEX_W_51_P_2, | |
1336 | VEX_W_51_P_3, | |
1337 | VEX_W_52_P_0, | |
1338 | VEX_W_52_P_1, | |
1339 | VEX_W_53_P_0, | |
1340 | VEX_W_53_P_1, | |
1341 | VEX_W_58_P_0, | |
1342 | VEX_W_58_P_1, | |
1343 | VEX_W_58_P_2, | |
1344 | VEX_W_58_P_3, | |
1345 | VEX_W_59_P_0, | |
1346 | VEX_W_59_P_1, | |
1347 | VEX_W_59_P_2, | |
1348 | VEX_W_59_P_3, | |
1349 | VEX_W_5A_P_0, | |
1350 | VEX_W_5A_P_1, | |
1351 | VEX_W_5A_P_3, | |
1352 | VEX_W_5B_P_0, | |
1353 | VEX_W_5B_P_1, | |
1354 | VEX_W_5B_P_2, | |
1355 | VEX_W_5C_P_0, | |
1356 | VEX_W_5C_P_1, | |
1357 | VEX_W_5C_P_2, | |
1358 | VEX_W_5C_P_3, | |
1359 | VEX_W_5D_P_0, | |
1360 | VEX_W_5D_P_1, | |
1361 | VEX_W_5D_P_2, | |
1362 | VEX_W_5D_P_3, | |
1363 | VEX_W_5E_P_0, | |
1364 | VEX_W_5E_P_1, | |
1365 | VEX_W_5E_P_2, | |
1366 | VEX_W_5E_P_3, | |
1367 | VEX_W_5F_P_0, | |
1368 | VEX_W_5F_P_1, | |
1369 | VEX_W_5F_P_2, | |
1370 | VEX_W_5F_P_3, | |
1371 | VEX_W_60_P_2, | |
1372 | VEX_W_61_P_2, | |
1373 | VEX_W_62_P_2, | |
1374 | VEX_W_63_P_2, | |
1375 | VEX_W_64_P_2, | |
1376 | VEX_W_65_P_2, | |
1377 | VEX_W_66_P_2, | |
1378 | VEX_W_67_P_2, | |
1379 | VEX_W_68_P_2, | |
1380 | VEX_W_69_P_2, | |
1381 | VEX_W_6A_P_2, | |
1382 | VEX_W_6B_P_2, | |
1383 | VEX_W_6C_P_2, | |
1384 | VEX_W_6D_P_2, | |
1385 | VEX_W_6F_P_1, | |
1386 | VEX_W_6F_P_2, | |
1387 | VEX_W_70_P_1, | |
1388 | VEX_W_70_P_2, | |
1389 | VEX_W_70_P_3, | |
1390 | VEX_W_71_R_2_P_2, | |
1391 | VEX_W_71_R_4_P_2, | |
1392 | VEX_W_71_R_6_P_2, | |
1393 | VEX_W_72_R_2_P_2, | |
1394 | VEX_W_72_R_4_P_2, | |
1395 | VEX_W_72_R_6_P_2, | |
1396 | VEX_W_73_R_2_P_2, | |
1397 | VEX_W_73_R_3_P_2, | |
1398 | VEX_W_73_R_6_P_2, | |
1399 | VEX_W_73_R_7_P_2, | |
1400 | VEX_W_74_P_2, | |
1401 | VEX_W_75_P_2, | |
1402 | VEX_W_76_P_2, | |
1403 | VEX_W_77_P_0, | |
1404 | VEX_W_7C_P_2, | |
1405 | VEX_W_7C_P_3, | |
1406 | VEX_W_7D_P_2, | |
1407 | VEX_W_7D_P_3, | |
1408 | VEX_W_7E_P_1, | |
1409 | VEX_W_7F_P_1, | |
1410 | VEX_W_7F_P_2, | |
1411 | VEX_W_AE_R_2_M_0, | |
1412 | VEX_W_AE_R_3_M_0, | |
1413 | VEX_W_C2_P_0, | |
1414 | VEX_W_C2_P_1, | |
1415 | VEX_W_C2_P_2, | |
1416 | VEX_W_C2_P_3, | |
1417 | VEX_W_C4_P_2, | |
1418 | VEX_W_C5_P_2, | |
1419 | VEX_W_D0_P_2, | |
1420 | VEX_W_D0_P_3, | |
1421 | VEX_W_D1_P_2, | |
1422 | VEX_W_D2_P_2, | |
1423 | VEX_W_D3_P_2, | |
1424 | VEX_W_D4_P_2, | |
1425 | VEX_W_D5_P_2, | |
1426 | VEX_W_D6_P_2, | |
1427 | VEX_W_D7_P_2_M_1, | |
1428 | VEX_W_D8_P_2, | |
1429 | VEX_W_D9_P_2, | |
1430 | VEX_W_DA_P_2, | |
1431 | VEX_W_DB_P_2, | |
1432 | VEX_W_DC_P_2, | |
1433 | VEX_W_DD_P_2, | |
1434 | VEX_W_DE_P_2, | |
1435 | VEX_W_DF_P_2, | |
1436 | VEX_W_E0_P_2, | |
1437 | VEX_W_E1_P_2, | |
1438 | VEX_W_E2_P_2, | |
1439 | VEX_W_E3_P_2, | |
1440 | VEX_W_E4_P_2, | |
1441 | VEX_W_E5_P_2, | |
1442 | VEX_W_E6_P_1, | |
1443 | VEX_W_E6_P_2, | |
1444 | VEX_W_E6_P_3, | |
1445 | VEX_W_E7_P_2_M_0, | |
1446 | VEX_W_E8_P_2, | |
1447 | VEX_W_E9_P_2, | |
1448 | VEX_W_EA_P_2, | |
1449 | VEX_W_EB_P_2, | |
1450 | VEX_W_EC_P_2, | |
1451 | VEX_W_ED_P_2, | |
1452 | VEX_W_EE_P_2, | |
1453 | VEX_W_EF_P_2, | |
1454 | VEX_W_F0_P_3_M_0, | |
1455 | VEX_W_F1_P_2, | |
1456 | VEX_W_F2_P_2, | |
1457 | VEX_W_F3_P_2, | |
1458 | VEX_W_F4_P_2, | |
1459 | VEX_W_F5_P_2, | |
1460 | VEX_W_F6_P_2, | |
1461 | VEX_W_F7_P_2, | |
1462 | VEX_W_F8_P_2, | |
1463 | VEX_W_F9_P_2, | |
1464 | VEX_W_FA_P_2, | |
1465 | VEX_W_FB_P_2, | |
1466 | VEX_W_FC_P_2, | |
1467 | VEX_W_FD_P_2, | |
1468 | VEX_W_FE_P_2, | |
1469 | VEX_W_3800_P_2, | |
1470 | VEX_W_3801_P_2, | |
1471 | VEX_W_3802_P_2, | |
1472 | VEX_W_3803_P_2, | |
1473 | VEX_W_3804_P_2, | |
1474 | VEX_W_3805_P_2, | |
1475 | VEX_W_3806_P_2, | |
1476 | VEX_W_3807_P_2, | |
1477 | VEX_W_3808_P_2, | |
1478 | VEX_W_3809_P_2, | |
1479 | VEX_W_380A_P_2, | |
1480 | VEX_W_380B_P_2, | |
1481 | VEX_W_380C_P_2, | |
1482 | VEX_W_380D_P_2, | |
1483 | VEX_W_380E_P_2, | |
1484 | VEX_W_380F_P_2, | |
1485 | VEX_W_3817_P_2, | |
bcf2684f | 1486 | VEX_W_3818_P_2_M_0, |
9e30b8e0 L |
1487 | VEX_W_3819_P_2_M_0, |
1488 | VEX_W_381A_P_2_M_0, | |
1489 | VEX_W_381C_P_2, | |
1490 | VEX_W_381D_P_2, | |
1491 | VEX_W_381E_P_2, | |
1492 | VEX_W_3820_P_2, | |
1493 | VEX_W_3821_P_2, | |
1494 | VEX_W_3822_P_2, | |
1495 | VEX_W_3823_P_2, | |
1496 | VEX_W_3824_P_2, | |
1497 | VEX_W_3825_P_2, | |
1498 | VEX_W_3828_P_2, | |
1499 | VEX_W_3829_P_2, | |
1500 | VEX_W_382A_P_2_M_0, | |
1501 | VEX_W_382B_P_2, | |
53aa04a0 L |
1502 | VEX_W_382C_P_2_M_0, |
1503 | VEX_W_382D_P_2_M_0, | |
1504 | VEX_W_382E_P_2_M_0, | |
1505 | VEX_W_382F_P_2_M_0, | |
9e30b8e0 L |
1506 | VEX_W_3830_P_2, |
1507 | VEX_W_3831_P_2, | |
1508 | VEX_W_3832_P_2, | |
1509 | VEX_W_3833_P_2, | |
1510 | VEX_W_3834_P_2, | |
1511 | VEX_W_3835_P_2, | |
1512 | VEX_W_3837_P_2, | |
1513 | VEX_W_3838_P_2, | |
1514 | VEX_W_3839_P_2, | |
1515 | VEX_W_383A_P_2, | |
1516 | VEX_W_383B_P_2, | |
1517 | VEX_W_383C_P_2, | |
1518 | VEX_W_383D_P_2, | |
1519 | VEX_W_383E_P_2, | |
1520 | VEX_W_383F_P_2, | |
1521 | VEX_W_3840_P_2, | |
1522 | VEX_W_3841_P_2, | |
1523 | VEX_W_38DB_P_2, | |
1524 | VEX_W_38DC_P_2, | |
1525 | VEX_W_38DD_P_2, | |
1526 | VEX_W_38DE_P_2, | |
1527 | VEX_W_38DF_P_2, | |
1528 | VEX_W_3A04_P_2, | |
1529 | VEX_W_3A05_P_2, | |
1530 | VEX_W_3A06_P_2, | |
1531 | VEX_W_3A08_P_2, | |
1532 | VEX_W_3A09_P_2, | |
1533 | VEX_W_3A0A_P_2, | |
1534 | VEX_W_3A0B_P_2, | |
1535 | VEX_W_3A0C_P_2, | |
1536 | VEX_W_3A0D_P_2, | |
1537 | VEX_W_3A0E_P_2, | |
1538 | VEX_W_3A0F_P_2, | |
1539 | VEX_W_3A14_P_2, | |
1540 | VEX_W_3A15_P_2, | |
1541 | VEX_W_3A18_P_2, | |
1542 | VEX_W_3A19_P_2, | |
1543 | VEX_W_3A20_P_2, | |
1544 | VEX_W_3A21_P_2, | |
1545 | VEX_W_3A40_P_2, | |
1546 | VEX_W_3A41_P_2, | |
1547 | VEX_W_3A42_P_2, | |
1548 | VEX_W_3A44_P_2, | |
1549 | VEX_W_3A4A_P_2, | |
1550 | VEX_W_3A4B_P_2, | |
1551 | VEX_W_3A4C_P_2, | |
1552 | VEX_W_3A60_P_2, | |
1553 | VEX_W_3A61_P_2, | |
1554 | VEX_W_3A62_P_2, | |
1555 | VEX_W_3A63_P_2, | |
1556 | VEX_W_3ADF_P_2 | |
1557 | }; | |
1558 | ||
26ca5450 | 1559 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1560 | |
1561 | struct dis386 { | |
2da11e11 | 1562 | const char *name; |
ce518a5f L |
1563 | struct |
1564 | { | |
1565 | op_rtn rtn; | |
1566 | int bytemode; | |
1567 | } op[MAX_OPERANDS]; | |
252b5132 RH |
1568 | }; |
1569 | ||
1570 | /* Upper case letters in the instruction names here are macros. | |
1571 | 'A' => print 'b' if no register operands or suffix_always is true | |
1572 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1573 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1574 | size prefix |
ed7841b3 | 1575 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1576 | suffix_always is true |
252b5132 | 1577 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1578 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1579 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1580 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 1581 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 1582 | for some of the macro letters) |
9306ca4a | 1583 | 'J' => print 'l' |
42903f7f | 1584 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 1585 | 'L' => print 'l' if suffix_always is true |
9d141669 | 1586 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1587 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1588 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 1589 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
1590 | or suffix_always is true. print 'q' if rex prefix is present. |
1591 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
1592 | is true | |
a35ca55a | 1593 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1594 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
1595 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
1596 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 1597 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 1598 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1599 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
1600 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
1601 | suffix_always is true. | |
6dd5059a | 1602 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 1603 | '!' => change condition from true to false or from false to true. |
98b528ac L |
1604 | '%' => add 1 upper case letter to the macro. |
1605 | ||
1606 | 2 upper case letter macros: | |
c0f3af97 L |
1607 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
1608 | is true. | |
4b06377f L |
1609 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
1610 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 1611 | or suffix_always is true |
4b06377f L |
1612 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
1613 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
1614 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
52b15da3 | 1615 | |
6439fc28 AM |
1616 | Many of the above letters print nothing in Intel mode. See "putop" |
1617 | for the details. | |
52b15da3 | 1618 | |
6439fc28 | 1619 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1620 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1621 | |
6439fc28 | 1622 | static const struct dis386 dis386[] = { |
252b5132 | 1623 | /* 00 */ |
ce518a5f L |
1624 | { "addB", { Eb, Gb } }, |
1625 | { "addS", { Ev, Gv } }, | |
c7532693 L |
1626 | { "addB", { Gb, EbS } }, |
1627 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
1628 | { "addB", { AL, Ib } }, |
1629 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
1630 | { X86_64_TABLE (X86_64_06) }, |
1631 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1632 | /* 08 */ |
ce518a5f L |
1633 | { "orB", { Eb, Gb } }, |
1634 | { "orS", { Ev, Gv } }, | |
c7532693 L |
1635 | { "orB", { Gb, EbS } }, |
1636 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
1637 | { "orB", { AL, Ib } }, |
1638 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 1639 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 1640 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 1641 | /* 10 */ |
ce518a5f L |
1642 | { "adcB", { Eb, Gb } }, |
1643 | { "adcS", { Ev, Gv } }, | |
c7532693 L |
1644 | { "adcB", { Gb, EbS } }, |
1645 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
1646 | { "adcB", { AL, Ib } }, |
1647 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
1648 | { X86_64_TABLE (X86_64_16) }, |
1649 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1650 | /* 18 */ |
ce518a5f L |
1651 | { "sbbB", { Eb, Gb } }, |
1652 | { "sbbS", { Ev, Gv } }, | |
c7532693 L |
1653 | { "sbbB", { Gb, EbS } }, |
1654 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
1655 | { "sbbB", { AL, Ib } }, |
1656 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
1657 | { X86_64_TABLE (X86_64_1E) }, |
1658 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1659 | /* 20 */ |
ce518a5f L |
1660 | { "andB", { Eb, Gb } }, |
1661 | { "andS", { Ev, Gv } }, | |
c7532693 L |
1662 | { "andB", { Gb, EbS } }, |
1663 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
1664 | { "andB", { AL, Ib } }, |
1665 | { "andS", { eAX, Iv } }, | |
592d1631 | 1666 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 1667 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1668 | /* 28 */ |
ce518a5f L |
1669 | { "subB", { Eb, Gb } }, |
1670 | { "subS", { Ev, Gv } }, | |
c7532693 L |
1671 | { "subB", { Gb, EbS } }, |
1672 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
1673 | { "subB", { AL, Ib } }, |
1674 | { "subS", { eAX, Iv } }, | |
592d1631 | 1675 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 1676 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1677 | /* 30 */ |
ce518a5f L |
1678 | { "xorB", { Eb, Gb } }, |
1679 | { "xorS", { Ev, Gv } }, | |
c7532693 L |
1680 | { "xorB", { Gb, EbS } }, |
1681 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
1682 | { "xorB", { AL, Ib } }, |
1683 | { "xorS", { eAX, Iv } }, | |
592d1631 | 1684 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 1685 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1686 | /* 38 */ |
ce518a5f L |
1687 | { "cmpB", { Eb, Gb } }, |
1688 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
1689 | { "cmpB", { Gb, EbS } }, |
1690 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
1691 | { "cmpB", { AL, Ib } }, |
1692 | { "cmpS", { eAX, Iv } }, | |
592d1631 | 1693 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 1694 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1695 | /* 40 */ |
ce518a5f L |
1696 | { "inc{S|}", { RMeAX } }, |
1697 | { "inc{S|}", { RMeCX } }, | |
1698 | { "inc{S|}", { RMeDX } }, | |
1699 | { "inc{S|}", { RMeBX } }, | |
1700 | { "inc{S|}", { RMeSP } }, | |
1701 | { "inc{S|}", { RMeBP } }, | |
1702 | { "inc{S|}", { RMeSI } }, | |
1703 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 1704 | /* 48 */ |
ce518a5f L |
1705 | { "dec{S|}", { RMeAX } }, |
1706 | { "dec{S|}", { RMeCX } }, | |
1707 | { "dec{S|}", { RMeDX } }, | |
1708 | { "dec{S|}", { RMeBX } }, | |
1709 | { "dec{S|}", { RMeSP } }, | |
1710 | { "dec{S|}", { RMeBP } }, | |
1711 | { "dec{S|}", { RMeSI } }, | |
1712 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 1713 | /* 50 */ |
ce518a5f L |
1714 | { "pushV", { RMrAX } }, |
1715 | { "pushV", { RMrCX } }, | |
1716 | { "pushV", { RMrDX } }, | |
1717 | { "pushV", { RMrBX } }, | |
1718 | { "pushV", { RMrSP } }, | |
1719 | { "pushV", { RMrBP } }, | |
1720 | { "pushV", { RMrSI } }, | |
1721 | { "pushV", { RMrDI } }, | |
252b5132 | 1722 | /* 58 */ |
ce518a5f L |
1723 | { "popV", { RMrAX } }, |
1724 | { "popV", { RMrCX } }, | |
1725 | { "popV", { RMrDX } }, | |
1726 | { "popV", { RMrBX } }, | |
1727 | { "popV", { RMrSP } }, | |
1728 | { "popV", { RMrBP } }, | |
1729 | { "popV", { RMrSI } }, | |
1730 | { "popV", { RMrDI } }, | |
252b5132 | 1731 | /* 60 */ |
4e7d34a6 L |
1732 | { X86_64_TABLE (X86_64_60) }, |
1733 | { X86_64_TABLE (X86_64_61) }, | |
1734 | { X86_64_TABLE (X86_64_62) }, | |
1735 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
1736 | { Bad_Opcode }, /* seg fs */ |
1737 | { Bad_Opcode }, /* seg gs */ | |
1738 | { Bad_Opcode }, /* op size prefix */ | |
1739 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 1740 | /* 68 */ |
ce518a5f L |
1741 | { "pushT", { Iq } }, |
1742 | { "imulS", { Gv, Ev, Iv } }, | |
1743 | { "pushT", { sIb } }, | |
1744 | { "imulS", { Gv, Ev, sIb } }, | |
7c52e0e8 | 1745 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 1746 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 1747 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 1748 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1749 | /* 70 */ |
ce518a5f L |
1750 | { "joH", { Jb, XX, cond_jump_flag } }, |
1751 | { "jnoH", { Jb, XX, cond_jump_flag } }, | |
1752 | { "jbH", { Jb, XX, cond_jump_flag } }, | |
1753 | { "jaeH", { Jb, XX, cond_jump_flag } }, | |
1754 | { "jeH", { Jb, XX, cond_jump_flag } }, | |
1755 | { "jneH", { Jb, XX, cond_jump_flag } }, | |
1756 | { "jbeH", { Jb, XX, cond_jump_flag } }, | |
1757 | { "jaH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1758 | /* 78 */ |
ce518a5f L |
1759 | { "jsH", { Jb, XX, cond_jump_flag } }, |
1760 | { "jnsH", { Jb, XX, cond_jump_flag } }, | |
1761 | { "jpH", { Jb, XX, cond_jump_flag } }, | |
1762 | { "jnpH", { Jb, XX, cond_jump_flag } }, | |
1763 | { "jlH", { Jb, XX, cond_jump_flag } }, | |
1764 | { "jgeH", { Jb, XX, cond_jump_flag } }, | |
1765 | { "jleH", { Jb, XX, cond_jump_flag } }, | |
1766 | { "jgH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1767 | /* 80 */ |
1ceb70f8 L |
1768 | { REG_TABLE (REG_80) }, |
1769 | { REG_TABLE (REG_81) }, | |
592d1631 | 1770 | { Bad_Opcode }, |
1ceb70f8 | 1771 | { REG_TABLE (REG_82) }, |
ce518a5f L |
1772 | { "testB", { Eb, Gb } }, |
1773 | { "testS", { Ev, Gv } }, | |
1774 | { "xchgB", { Eb, Gb } }, | |
1775 | { "xchgS", { Ev, Gv } }, | |
252b5132 | 1776 | /* 88 */ |
ce518a5f L |
1777 | { "movB", { Eb, Gb } }, |
1778 | { "movS", { Ev, Gv } }, | |
b6169b20 L |
1779 | { "movB", { Gb, EbS } }, |
1780 | { "movS", { Gv, EvS } }, | |
ce518a5f | 1781 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 1782 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 1783 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 1784 | { REG_TABLE (REG_8F) }, |
252b5132 | 1785 | /* 90 */ |
1ceb70f8 | 1786 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
1787 | { "xchgS", { RMeCX, eAX } }, |
1788 | { "xchgS", { RMeDX, eAX } }, | |
1789 | { "xchgS", { RMeBX, eAX } }, | |
1790 | { "xchgS", { RMeSP, eAX } }, | |
1791 | { "xchgS", { RMeBP, eAX } }, | |
1792 | { "xchgS", { RMeSI, eAX } }, | |
1793 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 1794 | /* 98 */ |
7c52e0e8 L |
1795 | { "cW{t|}R", { XX } }, |
1796 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 1797 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 1798 | { Bad_Opcode }, /* fwait */ |
ce518a5f L |
1799 | { "pushfT", { XX } }, |
1800 | { "popfT", { XX } }, | |
7c52e0e8 L |
1801 | { "sahf", { XX } }, |
1802 | { "lahf", { XX } }, | |
252b5132 | 1803 | /* a0 */ |
4b06377f L |
1804 | { "mov%LB", { AL, Ob } }, |
1805 | { "mov%LS", { eAX, Ov } }, | |
1806 | { "mov%LB", { Ob, AL } }, | |
1807 | { "mov%LS", { Ov, eAX } }, | |
7c52e0e8 L |
1808 | { "movs{b|}", { Ybr, Xb } }, |
1809 | { "movs{R|}", { Yvr, Xv } }, | |
1810 | { "cmps{b|}", { Xb, Yb } }, | |
1811 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 1812 | /* a8 */ |
ce518a5f L |
1813 | { "testB", { AL, Ib } }, |
1814 | { "testS", { eAX, Iv } }, | |
1815 | { "stosB", { Ybr, AL } }, | |
1816 | { "stosS", { Yvr, eAX } }, | |
1817 | { "lodsB", { ALr, Xb } }, | |
1818 | { "lodsS", { eAXr, Xv } }, | |
1819 | { "scasB", { AL, Yb } }, | |
1820 | { "scasS", { eAX, Yv } }, | |
252b5132 | 1821 | /* b0 */ |
ce518a5f L |
1822 | { "movB", { RMAL, Ib } }, |
1823 | { "movB", { RMCL, Ib } }, | |
1824 | { "movB", { RMDL, Ib } }, | |
1825 | { "movB", { RMBL, Ib } }, | |
1826 | { "movB", { RMAH, Ib } }, | |
1827 | { "movB", { RMCH, Ib } }, | |
1828 | { "movB", { RMDH, Ib } }, | |
1829 | { "movB", { RMBH, Ib } }, | |
252b5132 | 1830 | /* b8 */ |
4b06377f L |
1831 | { "mov%LV", { RMeAX, Iv64 } }, |
1832 | { "mov%LV", { RMeCX, Iv64 } }, | |
1833 | { "mov%LV", { RMeDX, Iv64 } }, | |
1834 | { "mov%LV", { RMeBX, Iv64 } }, | |
1835 | { "mov%LV", { RMeSP, Iv64 } }, | |
1836 | { "mov%LV", { RMeBP, Iv64 } }, | |
1837 | { "mov%LV", { RMeSI, Iv64 } }, | |
1838 | { "mov%LV", { RMeDI, Iv64 } }, | |
252b5132 | 1839 | /* c0 */ |
1ceb70f8 L |
1840 | { REG_TABLE (REG_C0) }, |
1841 | { REG_TABLE (REG_C1) }, | |
ce518a5f L |
1842 | { "retT", { Iw } }, |
1843 | { "retT", { XX } }, | |
4e7d34a6 L |
1844 | { X86_64_TABLE (X86_64_C4) }, |
1845 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
1846 | { REG_TABLE (REG_C6) }, |
1847 | { REG_TABLE (REG_C7) }, | |
252b5132 | 1848 | /* c8 */ |
ce518a5f L |
1849 | { "enterT", { Iw, Ib } }, |
1850 | { "leaveT", { XX } }, | |
ddab3d59 JB |
1851 | { "Jret{|f}P", { Iw } }, |
1852 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
1853 | { "int3", { XX } }, |
1854 | { "int", { Ib } }, | |
4e7d34a6 | 1855 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 1856 | { "iretP", { XX } }, |
252b5132 | 1857 | /* d0 */ |
1ceb70f8 L |
1858 | { REG_TABLE (REG_D0) }, |
1859 | { REG_TABLE (REG_D1) }, | |
1860 | { REG_TABLE (REG_D2) }, | |
1861 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
1862 | { X86_64_TABLE (X86_64_D4) }, |
1863 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 1864 | { Bad_Opcode }, |
ce518a5f | 1865 | { "xlat", { DSBX } }, |
252b5132 RH |
1866 | /* d8 */ |
1867 | { FLOAT }, | |
1868 | { FLOAT }, | |
1869 | { FLOAT }, | |
1870 | { FLOAT }, | |
1871 | { FLOAT }, | |
1872 | { FLOAT }, | |
1873 | { FLOAT }, | |
1874 | { FLOAT }, | |
1875 | /* e0 */ | |
ce518a5f L |
1876 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
1877 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
1878 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
1879 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
1880 | { "inB", { AL, Ib } }, | |
1881 | { "inG", { zAX, Ib } }, | |
1882 | { "outB", { Ib, AL } }, | |
1883 | { "outG", { Ib, zAX } }, | |
252b5132 | 1884 | /* e8 */ |
ce518a5f L |
1885 | { "callT", { Jv } }, |
1886 | { "jmpT", { Jv } }, | |
4e7d34a6 | 1887 | { X86_64_TABLE (X86_64_EA) }, |
ce518a5f L |
1888 | { "jmp", { Jb } }, |
1889 | { "inB", { AL, indirDX } }, | |
1890 | { "inG", { zAX, indirDX } }, | |
1891 | { "outB", { indirDX, AL } }, | |
1892 | { "outG", { indirDX, zAX } }, | |
252b5132 | 1893 | /* f0 */ |
592d1631 | 1894 | { Bad_Opcode }, /* lock prefix */ |
ce518a5f | 1895 | { "icebp", { XX } }, |
592d1631 L |
1896 | { Bad_Opcode }, /* repne */ |
1897 | { Bad_Opcode }, /* repz */ | |
ce518a5f L |
1898 | { "hlt", { XX } }, |
1899 | { "cmc", { XX } }, | |
1ceb70f8 L |
1900 | { REG_TABLE (REG_F6) }, |
1901 | { REG_TABLE (REG_F7) }, | |
252b5132 | 1902 | /* f8 */ |
ce518a5f L |
1903 | { "clc", { XX } }, |
1904 | { "stc", { XX } }, | |
1905 | { "cli", { XX } }, | |
1906 | { "sti", { XX } }, | |
1907 | { "cld", { XX } }, | |
1908 | { "std", { XX } }, | |
1ceb70f8 L |
1909 | { REG_TABLE (REG_FE) }, |
1910 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
1911 | }; |
1912 | ||
6439fc28 | 1913 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 1914 | /* 00 */ |
1ceb70f8 L |
1915 | { REG_TABLE (REG_0F00 ) }, |
1916 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
1917 | { "larS", { Gv, Ew } }, |
1918 | { "lslS", { Gv, Ew } }, | |
592d1631 | 1919 | { Bad_Opcode }, |
ce518a5f L |
1920 | { "syscall", { XX } }, |
1921 | { "clts", { XX } }, | |
1922 | { "sysretP", { XX } }, | |
252b5132 | 1923 | /* 08 */ |
ce518a5f L |
1924 | { "invd", { XX } }, |
1925 | { "wbinvd", { XX } }, | |
592d1631 | 1926 | { Bad_Opcode }, |
ce518a5f | 1927 | { "ud2a", { XX } }, |
592d1631 | 1928 | { Bad_Opcode }, |
b5b1fc4f | 1929 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
1930 | { "femms", { XX } }, |
1931 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 1932 | /* 10 */ |
1ceb70f8 L |
1933 | { PREFIX_TABLE (PREFIX_0F10) }, |
1934 | { PREFIX_TABLE (PREFIX_0F11) }, | |
1935 | { PREFIX_TABLE (PREFIX_0F12) }, | |
1936 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
1937 | { "unpcklpX", { XM, EXx } }, |
1938 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
1939 | { PREFIX_TABLE (PREFIX_0F16) }, |
1940 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 1941 | /* 18 */ |
1ceb70f8 | 1942 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f L |
1943 | { "nopQ", { Ev } }, |
1944 | { "nopQ", { Ev } }, | |
1945 | { "nopQ", { Ev } }, | |
1946 | { "nopQ", { Ev } }, | |
1947 | { "nopQ", { Ev } }, | |
1948 | { "nopQ", { Ev } }, | |
ce518a5f | 1949 | { "nopQ", { Ev } }, |
252b5132 | 1950 | /* 20 */ |
1ceb70f8 L |
1951 | { MOD_TABLE (MOD_0F20) }, |
1952 | { MOD_TABLE (MOD_0F21) }, | |
1953 | { MOD_TABLE (MOD_0F22) }, | |
1954 | { MOD_TABLE (MOD_0F23) }, | |
1955 | { MOD_TABLE (MOD_0F24) }, | |
592d1631 | 1956 | { Bad_Opcode }, |
1ceb70f8 | 1957 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 1958 | { Bad_Opcode }, |
252b5132 | 1959 | /* 28 */ |
09a2c6cf | 1960 | { "movapX", { XM, EXx } }, |
b6169b20 | 1961 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
1962 | { PREFIX_TABLE (PREFIX_0F2A) }, |
1963 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
1964 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
1965 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
1966 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
1967 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 1968 | /* 30 */ |
ce518a5f L |
1969 | { "wrmsr", { XX } }, |
1970 | { "rdtsc", { XX } }, | |
1971 | { "rdmsr", { XX } }, | |
1972 | { "rdpmc", { XX } }, | |
1973 | { "sysenter", { XX } }, | |
1974 | { "sysexit", { XX } }, | |
592d1631 | 1975 | { Bad_Opcode }, |
47dd174c | 1976 | { "getsec", { XX } }, |
252b5132 | 1977 | /* 38 */ |
4e7d34a6 | 1978 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
592d1631 | 1979 | { Bad_Opcode }, |
4e7d34a6 | 1980 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
592d1631 L |
1981 | { Bad_Opcode }, |
1982 | { Bad_Opcode }, | |
1983 | { Bad_Opcode }, | |
1984 | { Bad_Opcode }, | |
1985 | { Bad_Opcode }, | |
252b5132 | 1986 | /* 40 */ |
b19d5385 JB |
1987 | { "cmovoS", { Gv, Ev } }, |
1988 | { "cmovnoS", { Gv, Ev } }, | |
1989 | { "cmovbS", { Gv, Ev } }, | |
1990 | { "cmovaeS", { Gv, Ev } }, | |
1991 | { "cmoveS", { Gv, Ev } }, | |
1992 | { "cmovneS", { Gv, Ev } }, | |
1993 | { "cmovbeS", { Gv, Ev } }, | |
1994 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 1995 | /* 48 */ |
b19d5385 JB |
1996 | { "cmovsS", { Gv, Ev } }, |
1997 | { "cmovnsS", { Gv, Ev } }, | |
1998 | { "cmovpS", { Gv, Ev } }, | |
1999 | { "cmovnpS", { Gv, Ev } }, | |
2000 | { "cmovlS", { Gv, Ev } }, | |
2001 | { "cmovgeS", { Gv, Ev } }, | |
2002 | { "cmovleS", { Gv, Ev } }, | |
2003 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 2004 | /* 50 */ |
75c135a8 | 2005 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2006 | { PREFIX_TABLE (PREFIX_0F51) }, |
2007 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2008 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
2009 | { "andpX", { XM, EXx } }, |
2010 | { "andnpX", { XM, EXx } }, | |
2011 | { "orpX", { XM, EXx } }, | |
2012 | { "xorpX", { XM, EXx } }, | |
252b5132 | 2013 | /* 58 */ |
1ceb70f8 L |
2014 | { PREFIX_TABLE (PREFIX_0F58) }, |
2015 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2016 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2017 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2018 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2019 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2020 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2021 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2022 | /* 60 */ |
1ceb70f8 L |
2023 | { PREFIX_TABLE (PREFIX_0F60) }, |
2024 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2025 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
2026 | { "packsswb", { MX, EM } }, |
2027 | { "pcmpgtb", { MX, EM } }, | |
2028 | { "pcmpgtw", { MX, EM } }, | |
2029 | { "pcmpgtd", { MX, EM } }, | |
2030 | { "packuswb", { MX, EM } }, | |
252b5132 | 2031 | /* 68 */ |
ce518a5f L |
2032 | { "punpckhbw", { MX, EM } }, |
2033 | { "punpckhwd", { MX, EM } }, | |
2034 | { "punpckhdq", { MX, EM } }, | |
2035 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
2036 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2037 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 2038 | { "movK", { MX, Edq } }, |
1ceb70f8 | 2039 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2040 | /* 70 */ |
1ceb70f8 L |
2041 | { PREFIX_TABLE (PREFIX_0F70) }, |
2042 | { REG_TABLE (REG_0F71) }, | |
2043 | { REG_TABLE (REG_0F72) }, | |
2044 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
2045 | { "pcmpeqb", { MX, EM } }, |
2046 | { "pcmpeqw", { MX, EM } }, | |
2047 | { "pcmpeqd", { MX, EM } }, | |
2048 | { "emms", { XX } }, | |
252b5132 | 2049 | /* 78 */ |
1ceb70f8 L |
2050 | { PREFIX_TABLE (PREFIX_0F78) }, |
2051 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2052 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2053 | { Bad_Opcode }, |
1ceb70f8 L |
2054 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2055 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2056 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2057 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2058 | /* 80 */ |
ce518a5f L |
2059 | { "joH", { Jv, XX, cond_jump_flag } }, |
2060 | { "jnoH", { Jv, XX, cond_jump_flag } }, | |
2061 | { "jbH", { Jv, XX, cond_jump_flag } }, | |
2062 | { "jaeH", { Jv, XX, cond_jump_flag } }, | |
2063 | { "jeH", { Jv, XX, cond_jump_flag } }, | |
2064 | { "jneH", { Jv, XX, cond_jump_flag } }, | |
2065 | { "jbeH", { Jv, XX, cond_jump_flag } }, | |
2066 | { "jaH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 2067 | /* 88 */ |
ce518a5f L |
2068 | { "jsH", { Jv, XX, cond_jump_flag } }, |
2069 | { "jnsH", { Jv, XX, cond_jump_flag } }, | |
2070 | { "jpH", { Jv, XX, cond_jump_flag } }, | |
2071 | { "jnpH", { Jv, XX, cond_jump_flag } }, | |
2072 | { "jlH", { Jv, XX, cond_jump_flag } }, | |
2073 | { "jgeH", { Jv, XX, cond_jump_flag } }, | |
2074 | { "jleH", { Jv, XX, cond_jump_flag } }, | |
2075 | { "jgH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 2076 | /* 90 */ |
ce518a5f L |
2077 | { "seto", { Eb } }, |
2078 | { "setno", { Eb } }, | |
2079 | { "setb", { Eb } }, | |
2080 | { "setae", { Eb } }, | |
2081 | { "sete", { Eb } }, | |
2082 | { "setne", { Eb } }, | |
2083 | { "setbe", { Eb } }, | |
2084 | { "seta", { Eb } }, | |
252b5132 | 2085 | /* 98 */ |
ce518a5f L |
2086 | { "sets", { Eb } }, |
2087 | { "setns", { Eb } }, | |
2088 | { "setp", { Eb } }, | |
2089 | { "setnp", { Eb } }, | |
2090 | { "setl", { Eb } }, | |
2091 | { "setge", { Eb } }, | |
2092 | { "setle", { Eb } }, | |
2093 | { "setg", { Eb } }, | |
252b5132 | 2094 | /* a0 */ |
ce518a5f L |
2095 | { "pushT", { fs } }, |
2096 | { "popT", { fs } }, | |
2097 | { "cpuid", { XX } }, | |
2098 | { "btS", { Ev, Gv } }, | |
2099 | { "shldS", { Ev, Gv, Ib } }, | |
2100 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
2101 | { REG_TABLE (REG_0FA6) }, |
2102 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2103 | /* a8 */ |
ce518a5f L |
2104 | { "pushT", { gs } }, |
2105 | { "popT", { gs } }, | |
2106 | { "rsm", { XX } }, | |
2107 | { "btsS", { Ev, Gv } }, | |
2108 | { "shrdS", { Ev, Gv, Ib } }, | |
2109 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 2110 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 2111 | { "imulS", { Gv, Ev } }, |
252b5132 | 2112 | /* b0 */ |
ce518a5f L |
2113 | { "cmpxchgB", { Eb, Gb } }, |
2114 | { "cmpxchgS", { Ev, Gv } }, | |
1ceb70f8 | 2115 | { MOD_TABLE (MOD_0FB2) }, |
ce518a5f | 2116 | { "btrS", { Ev, Gv } }, |
1ceb70f8 L |
2117 | { MOD_TABLE (MOD_0FB4) }, |
2118 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
2119 | { "movz{bR|x}", { Gv, Eb } }, |
2120 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 2121 | /* b8 */ |
1ceb70f8 | 2122 | { PREFIX_TABLE (PREFIX_0FB8) }, |
ce518a5f | 2123 | { "ud2b", { XX } }, |
1ceb70f8 | 2124 | { REG_TABLE (REG_0FBA) }, |
ce518a5f L |
2125 | { "btcS", { Ev, Gv } }, |
2126 | { "bsfS", { Gv, Ev } }, | |
1ceb70f8 | 2127 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
2128 | { "movs{bR|x}", { Gv, Eb } }, |
2129 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 2130 | /* c0 */ |
ce518a5f L |
2131 | { "xaddB", { Eb, Gb } }, |
2132 | { "xaddS", { Ev, Gv } }, | |
1ceb70f8 | 2133 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 2134 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
2135 | { "pinsrw", { MX, Edqw, Ib } }, |
2136 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 2137 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 2138 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2139 | /* c8 */ |
ce518a5f L |
2140 | { "bswap", { RMeAX } }, |
2141 | { "bswap", { RMeCX } }, | |
2142 | { "bswap", { RMeDX } }, | |
2143 | { "bswap", { RMeBX } }, | |
2144 | { "bswap", { RMeSP } }, | |
2145 | { "bswap", { RMeBP } }, | |
2146 | { "bswap", { RMeSI } }, | |
2147 | { "bswap", { RMeDI } }, | |
252b5132 | 2148 | /* d0 */ |
1ceb70f8 | 2149 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
2150 | { "psrlw", { MX, EM } }, |
2151 | { "psrld", { MX, EM } }, | |
2152 | { "psrlq", { MX, EM } }, | |
2153 | { "paddq", { MX, EM } }, | |
2154 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 2155 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2156 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2157 | /* d8 */ |
ce518a5f L |
2158 | { "psubusb", { MX, EM } }, |
2159 | { "psubusw", { MX, EM } }, | |
2160 | { "pminub", { MX, EM } }, | |
2161 | { "pand", { MX, EM } }, | |
2162 | { "paddusb", { MX, EM } }, | |
2163 | { "paddusw", { MX, EM } }, | |
2164 | { "pmaxub", { MX, EM } }, | |
2165 | { "pandn", { MX, EM } }, | |
252b5132 | 2166 | /* e0 */ |
ce518a5f L |
2167 | { "pavgb", { MX, EM } }, |
2168 | { "psraw", { MX, EM } }, | |
2169 | { "psrad", { MX, EM } }, | |
2170 | { "pavgw", { MX, EM } }, | |
2171 | { "pmulhuw", { MX, EM } }, | |
2172 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
2173 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2174 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2175 | /* e8 */ |
ce518a5f L |
2176 | { "psubsb", { MX, EM } }, |
2177 | { "psubsw", { MX, EM } }, | |
2178 | { "pminsw", { MX, EM } }, | |
2179 | { "por", { MX, EM } }, | |
2180 | { "paddsb", { MX, EM } }, | |
2181 | { "paddsw", { MX, EM } }, | |
2182 | { "pmaxsw", { MX, EM } }, | |
2183 | { "pxor", { MX, EM } }, | |
252b5132 | 2184 | /* f0 */ |
1ceb70f8 | 2185 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
2186 | { "psllw", { MX, EM } }, |
2187 | { "pslld", { MX, EM } }, | |
2188 | { "psllq", { MX, EM } }, | |
2189 | { "pmuludq", { MX, EM } }, | |
2190 | { "pmaddwd", { MX, EM } }, | |
2191 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 2192 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2193 | /* f8 */ |
ce518a5f L |
2194 | { "psubb", { MX, EM } }, |
2195 | { "psubw", { MX, EM } }, | |
2196 | { "psubd", { MX, EM } }, | |
2197 | { "psubq", { MX, EM } }, | |
2198 | { "paddb", { MX, EM } }, | |
2199 | { "paddw", { MX, EM } }, | |
2200 | { "paddd", { MX, EM } }, | |
592d1631 | 2201 | { Bad_Opcode }, |
252b5132 RH |
2202 | }; |
2203 | ||
2204 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2205 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2206 | /* ------------------------------- */ | |
2207 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2208 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2209 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2210 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2211 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2212 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2213 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2214 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2215 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2216 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2217 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2218 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2219 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2220 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2221 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2222 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2223 | /* ------------------------------- */ | |
2224 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2225 | }; |
2226 | ||
2227 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2228 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2229 | /* ------------------------------- */ | |
252b5132 | 2230 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2231 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2232 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2233 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2234 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2235 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2236 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2237 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2238 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2239 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2240 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 2241 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 2242 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2243 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2244 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 2245 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
2246 | /* ------------------------------- */ |
2247 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2248 | }; | |
2249 | ||
252b5132 RH |
2250 | static char obuf[100]; |
2251 | static char *obufp; | |
ea397f5b | 2252 | static char *mnemonicendp; |
252b5132 RH |
2253 | static char scratchbuf[100]; |
2254 | static unsigned char *start_codep; | |
2255 | static unsigned char *insn_codep; | |
2256 | static unsigned char *codep; | |
f16cd0d5 L |
2257 | static int last_lock_prefix; |
2258 | static int last_repz_prefix; | |
2259 | static int last_repnz_prefix; | |
2260 | static int last_data_prefix; | |
2261 | static int last_addr_prefix; | |
2262 | static int last_rex_prefix; | |
2263 | static int last_seg_prefix; | |
2264 | #define MAX_CODE_LENGTH 15 | |
2265 | /* We can up to 14 prefixes since the maximum instruction length is | |
2266 | 15bytes. */ | |
2267 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2268 | static disassemble_info *the_info; |
7967e09e L |
2269 | static struct |
2270 | { | |
2271 | int mod; | |
7967e09e | 2272 | int reg; |
484c222e | 2273 | int rm; |
7967e09e L |
2274 | } |
2275 | modrm; | |
4bba6815 | 2276 | static unsigned char need_modrm; |
c0f3af97 L |
2277 | static struct |
2278 | { | |
2279 | int register_specifier; | |
2280 | int length; | |
2281 | int prefix; | |
2282 | int w; | |
2283 | } | |
2284 | vex; | |
2285 | static unsigned char need_vex; | |
2286 | static unsigned char need_vex_reg; | |
dae39acc | 2287 | static unsigned char vex_w_done; |
252b5132 | 2288 | |
ea397f5b L |
2289 | struct op |
2290 | { | |
2291 | const char *name; | |
2292 | unsigned int len; | |
2293 | }; | |
2294 | ||
4bba6815 AM |
2295 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2296 | values are stale. Hitting this abort likely indicates that you | |
2297 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2298 | #define MODRM_CHECK if (!need_modrm) abort () | |
2299 | ||
d708bcba AM |
2300 | static const char **names64; |
2301 | static const char **names32; | |
2302 | static const char **names16; | |
2303 | static const char **names8; | |
2304 | static const char **names8rex; | |
2305 | static const char **names_seg; | |
db51cc60 L |
2306 | static const char *index64; |
2307 | static const char *index32; | |
d708bcba AM |
2308 | static const char **index16; |
2309 | ||
2310 | static const char *intel_names64[] = { | |
2311 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2312 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2313 | }; | |
2314 | static const char *intel_names32[] = { | |
2315 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2316 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2317 | }; | |
2318 | static const char *intel_names16[] = { | |
2319 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2320 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2321 | }; | |
2322 | static const char *intel_names8[] = { | |
2323 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2324 | }; | |
2325 | static const char *intel_names8rex[] = { | |
2326 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2327 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2328 | }; | |
2329 | static const char *intel_names_seg[] = { | |
2330 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2331 | }; | |
db51cc60 L |
2332 | static const char *intel_index64 = "riz"; |
2333 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2334 | static const char *intel_index16[] = { |
2335 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2336 | }; | |
2337 | ||
2338 | static const char *att_names64[] = { | |
2339 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2340 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2341 | }; | |
d708bcba AM |
2342 | static const char *att_names32[] = { |
2343 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2344 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2345 | }; |
d708bcba AM |
2346 | static const char *att_names16[] = { |
2347 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2348 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2349 | }; |
d708bcba AM |
2350 | static const char *att_names8[] = { |
2351 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2352 | }; |
d708bcba AM |
2353 | static const char *att_names8rex[] = { |
2354 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2355 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2356 | }; | |
d708bcba AM |
2357 | static const char *att_names_seg[] = { |
2358 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2359 | }; |
db51cc60 L |
2360 | static const char *att_index64 = "%riz"; |
2361 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2362 | static const char *att_index16[] = { |
2363 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2364 | }; |
2365 | ||
b9733481 L |
2366 | static const char **names_mm; |
2367 | static const char *intel_names_mm[] = { | |
2368 | "mm0", "mm1", "mm2", "mm3", | |
2369 | "mm4", "mm5", "mm6", "mm7" | |
2370 | }; | |
2371 | static const char *att_names_mm[] = { | |
2372 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2373 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2374 | }; | |
2375 | ||
2376 | static const char **names_xmm; | |
2377 | static const char *intel_names_xmm[] = { | |
2378 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2379 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2380 | "xmm8", "xmm9", "xmm10", "xmm11", | |
2381 | "xmm12", "xmm13", "xmm14", "xmm15" | |
2382 | }; | |
2383 | static const char *att_names_xmm[] = { | |
2384 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
2385 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2386 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
2387 | "%xmm12", "%xmm13", "%xmm14", "%xmm15" | |
2388 | }; | |
2389 | ||
2390 | static const char **names_ymm; | |
2391 | static const char *intel_names_ymm[] = { | |
2392 | "ymm0", "ymm1", "ymm2", "ymm3", | |
2393 | "ymm4", "ymm5", "ymm6", "ymm7", | |
2394 | "ymm8", "ymm9", "ymm10", "ymm11", | |
2395 | "ymm12", "ymm13", "ymm14", "ymm15" | |
2396 | }; | |
2397 | static const char *att_names_ymm[] = { | |
2398 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
2399 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
2400 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
2401 | "%ymm12", "%ymm13", "%ymm14", "%ymm15" | |
2402 | }; | |
2403 | ||
1ceb70f8 L |
2404 | static const struct dis386 reg_table[][8] = { |
2405 | /* REG_80 */ | |
252b5132 | 2406 | { |
ce518a5f L |
2407 | { "addA", { Eb, Ib } }, |
2408 | { "orA", { Eb, Ib } }, | |
2409 | { "adcA", { Eb, Ib } }, | |
2410 | { "sbbA", { Eb, Ib } }, | |
2411 | { "andA", { Eb, Ib } }, | |
2412 | { "subA", { Eb, Ib } }, | |
2413 | { "xorA", { Eb, Ib } }, | |
2414 | { "cmpA", { Eb, Ib } }, | |
252b5132 | 2415 | }, |
1ceb70f8 | 2416 | /* REG_81 */ |
252b5132 | 2417 | { |
ce518a5f L |
2418 | { "addQ", { Ev, Iv } }, |
2419 | { "orQ", { Ev, Iv } }, | |
2420 | { "adcQ", { Ev, Iv } }, | |
2421 | { "sbbQ", { Ev, Iv } }, | |
2422 | { "andQ", { Ev, Iv } }, | |
2423 | { "subQ", { Ev, Iv } }, | |
2424 | { "xorQ", { Ev, Iv } }, | |
2425 | { "cmpQ", { Ev, Iv } }, | |
252b5132 | 2426 | }, |
1ceb70f8 | 2427 | /* REG_82 */ |
252b5132 | 2428 | { |
ce518a5f L |
2429 | { "addQ", { Ev, sIb } }, |
2430 | { "orQ", { Ev, sIb } }, | |
2431 | { "adcQ", { Ev, sIb } }, | |
2432 | { "sbbQ", { Ev, sIb } }, | |
2433 | { "andQ", { Ev, sIb } }, | |
2434 | { "subQ", { Ev, sIb } }, | |
2435 | { "xorQ", { Ev, sIb } }, | |
2436 | { "cmpQ", { Ev, sIb } }, | |
252b5132 | 2437 | }, |
1ceb70f8 | 2438 | /* REG_8F */ |
4e7d34a6 L |
2439 | { |
2440 | { "popU", { stackEv } }, | |
c48244a5 | 2441 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
2442 | { Bad_Opcode }, |
2443 | { Bad_Opcode }, | |
2444 | { Bad_Opcode }, | |
f88c9eb0 | 2445 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 2446 | }, |
1ceb70f8 | 2447 | /* REG_C0 */ |
252b5132 | 2448 | { |
ce518a5f L |
2449 | { "rolA", { Eb, Ib } }, |
2450 | { "rorA", { Eb, Ib } }, | |
2451 | { "rclA", { Eb, Ib } }, | |
2452 | { "rcrA", { Eb, Ib } }, | |
2453 | { "shlA", { Eb, Ib } }, | |
2454 | { "shrA", { Eb, Ib } }, | |
592d1631 | 2455 | { Bad_Opcode }, |
ce518a5f | 2456 | { "sarA", { Eb, Ib } }, |
252b5132 | 2457 | }, |
1ceb70f8 | 2458 | /* REG_C1 */ |
252b5132 | 2459 | { |
ce518a5f L |
2460 | { "rolQ", { Ev, Ib } }, |
2461 | { "rorQ", { Ev, Ib } }, | |
2462 | { "rclQ", { Ev, Ib } }, | |
2463 | { "rcrQ", { Ev, Ib } }, | |
2464 | { "shlQ", { Ev, Ib } }, | |
2465 | { "shrQ", { Ev, Ib } }, | |
592d1631 | 2466 | { Bad_Opcode }, |
ce518a5f | 2467 | { "sarQ", { Ev, Ib } }, |
252b5132 | 2468 | }, |
1ceb70f8 | 2469 | /* REG_C6 */ |
4e7d34a6 L |
2470 | { |
2471 | { "movA", { Eb, Ib } }, | |
4e7d34a6 | 2472 | }, |
1ceb70f8 | 2473 | /* REG_C7 */ |
4e7d34a6 L |
2474 | { |
2475 | { "movQ", { Ev, Iv } }, | |
4e7d34a6 | 2476 | }, |
1ceb70f8 | 2477 | /* REG_D0 */ |
252b5132 | 2478 | { |
ce518a5f L |
2479 | { "rolA", { Eb, I1 } }, |
2480 | { "rorA", { Eb, I1 } }, | |
2481 | { "rclA", { Eb, I1 } }, | |
2482 | { "rcrA", { Eb, I1 } }, | |
2483 | { "shlA", { Eb, I1 } }, | |
2484 | { "shrA", { Eb, I1 } }, | |
592d1631 | 2485 | { Bad_Opcode }, |
ce518a5f | 2486 | { "sarA", { Eb, I1 } }, |
252b5132 | 2487 | }, |
1ceb70f8 | 2488 | /* REG_D1 */ |
252b5132 | 2489 | { |
ce518a5f L |
2490 | { "rolQ", { Ev, I1 } }, |
2491 | { "rorQ", { Ev, I1 } }, | |
2492 | { "rclQ", { Ev, I1 } }, | |
2493 | { "rcrQ", { Ev, I1 } }, | |
2494 | { "shlQ", { Ev, I1 } }, | |
2495 | { "shrQ", { Ev, I1 } }, | |
592d1631 | 2496 | { Bad_Opcode }, |
ce518a5f | 2497 | { "sarQ", { Ev, I1 } }, |
252b5132 | 2498 | }, |
1ceb70f8 | 2499 | /* REG_D2 */ |
252b5132 | 2500 | { |
ce518a5f L |
2501 | { "rolA", { Eb, CL } }, |
2502 | { "rorA", { Eb, CL } }, | |
2503 | { "rclA", { Eb, CL } }, | |
2504 | { "rcrA", { Eb, CL } }, | |
2505 | { "shlA", { Eb, CL } }, | |
2506 | { "shrA", { Eb, CL } }, | |
592d1631 | 2507 | { Bad_Opcode }, |
ce518a5f | 2508 | { "sarA", { Eb, CL } }, |
252b5132 | 2509 | }, |
1ceb70f8 | 2510 | /* REG_D3 */ |
252b5132 | 2511 | { |
ce518a5f L |
2512 | { "rolQ", { Ev, CL } }, |
2513 | { "rorQ", { Ev, CL } }, | |
2514 | { "rclQ", { Ev, CL } }, | |
2515 | { "rcrQ", { Ev, CL } }, | |
2516 | { "shlQ", { Ev, CL } }, | |
2517 | { "shrQ", { Ev, CL } }, | |
592d1631 | 2518 | { Bad_Opcode }, |
ce518a5f | 2519 | { "sarQ", { Ev, CL } }, |
252b5132 | 2520 | }, |
1ceb70f8 | 2521 | /* REG_F6 */ |
252b5132 | 2522 | { |
ce518a5f | 2523 | { "testA", { Eb, Ib } }, |
592d1631 | 2524 | { Bad_Opcode }, |
ce518a5f L |
2525 | { "notA", { Eb } }, |
2526 | { "negA", { Eb } }, | |
2527 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ | |
2528 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
2529 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
2530 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 2531 | }, |
1ceb70f8 | 2532 | /* REG_F7 */ |
252b5132 | 2533 | { |
ce518a5f | 2534 | { "testQ", { Ev, Iv } }, |
592d1631 | 2535 | { Bad_Opcode }, |
ce518a5f L |
2536 | { "notQ", { Ev } }, |
2537 | { "negQ", { Ev } }, | |
2538 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ | |
2539 | { "imulQ", { Ev } }, | |
2540 | { "divQ", { Ev } }, | |
2541 | { "idivQ", { Ev } }, | |
252b5132 | 2542 | }, |
1ceb70f8 | 2543 | /* REG_FE */ |
252b5132 | 2544 | { |
ce518a5f L |
2545 | { "incA", { Eb } }, |
2546 | { "decA", { Eb } }, | |
252b5132 | 2547 | }, |
1ceb70f8 | 2548 | /* REG_FF */ |
252b5132 | 2549 | { |
ce518a5f L |
2550 | { "incQ", { Ev } }, |
2551 | { "decQ", { Ev } }, | |
2552 | { "callT", { indirEv } }, | |
2553 | { "JcallT", { indirEp } }, | |
2554 | { "jmpT", { indirEv } }, | |
2555 | { "JjmpT", { indirEp } }, | |
2556 | { "pushU", { stackEv } }, | |
592d1631 | 2557 | { Bad_Opcode }, |
252b5132 | 2558 | }, |
1ceb70f8 | 2559 | /* REG_0F00 */ |
252b5132 | 2560 | { |
ce518a5f L |
2561 | { "sldtD", { Sv } }, |
2562 | { "strD", { Sv } }, | |
2563 | { "lldt", { Ew } }, | |
2564 | { "ltr", { Ew } }, | |
2565 | { "verr", { Ew } }, | |
2566 | { "verw", { Ew } }, | |
592d1631 L |
2567 | { Bad_Opcode }, |
2568 | { Bad_Opcode }, | |
252b5132 | 2569 | }, |
1ceb70f8 | 2570 | /* REG_0F01 */ |
252b5132 | 2571 | { |
1ceb70f8 L |
2572 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2573 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2574 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2575 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f | 2576 | { "smswD", { Sv } }, |
592d1631 | 2577 | { Bad_Opcode }, |
ce518a5f | 2578 | { "lmsw", { Ew } }, |
1ceb70f8 | 2579 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2580 | }, |
b5b1fc4f | 2581 | /* REG_0F0D */ |
252b5132 | 2582 | { |
4e7d34a6 L |
2583 | { "prefetch", { Eb } }, |
2584 | { "prefetchw", { Eb } }, | |
252b5132 | 2585 | }, |
1ceb70f8 | 2586 | /* REG_0F18 */ |
252b5132 | 2587 | { |
1ceb70f8 L |
2588 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2589 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2590 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2591 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
252b5132 | 2592 | }, |
1ceb70f8 | 2593 | /* REG_0F71 */ |
a6bd098c | 2594 | { |
592d1631 L |
2595 | { Bad_Opcode }, |
2596 | { Bad_Opcode }, | |
1ceb70f8 | 2597 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 2598 | { Bad_Opcode }, |
1ceb70f8 | 2599 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 2600 | { Bad_Opcode }, |
1ceb70f8 | 2601 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 2602 | }, |
1ceb70f8 | 2603 | /* REG_0F72 */ |
a6bd098c | 2604 | { |
592d1631 L |
2605 | { Bad_Opcode }, |
2606 | { Bad_Opcode }, | |
1ceb70f8 | 2607 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 2608 | { Bad_Opcode }, |
1ceb70f8 | 2609 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 2610 | { Bad_Opcode }, |
1ceb70f8 | 2611 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 2612 | }, |
1ceb70f8 | 2613 | /* REG_0F73 */ |
252b5132 | 2614 | { |
592d1631 L |
2615 | { Bad_Opcode }, |
2616 | { Bad_Opcode }, | |
1ceb70f8 L |
2617 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2618 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
2619 | { Bad_Opcode }, |
2620 | { Bad_Opcode }, | |
1ceb70f8 L |
2621 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2622 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2623 | }, |
1ceb70f8 | 2624 | /* REG_0FA6 */ |
252b5132 | 2625 | { |
4e7d34a6 L |
2626 | { "montmul", { { OP_0f07, 0 } } }, |
2627 | { "xsha1", { { OP_0f07, 0 } } }, | |
2628 | { "xsha256", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 2629 | }, |
1ceb70f8 | 2630 | /* REG_0FA7 */ |
4e7d34a6 L |
2631 | { |
2632 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
2633 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
2634 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
2635 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
2636 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
2637 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 2638 | }, |
1ceb70f8 | 2639 | /* REG_0FAE */ |
4e7d34a6 | 2640 | { |
1ceb70f8 L |
2641 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2642 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2643 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2644 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2645 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2646 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2647 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2648 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2649 | }, |
1ceb70f8 | 2650 | /* REG_0FBA */ |
252b5132 | 2651 | { |
592d1631 L |
2652 | { Bad_Opcode }, |
2653 | { Bad_Opcode }, | |
2654 | { Bad_Opcode }, | |
2655 | { Bad_Opcode }, | |
4e7d34a6 L |
2656 | { "btQ", { Ev, Ib } }, |
2657 | { "btsQ", { Ev, Ib } }, | |
2658 | { "btrQ", { Ev, Ib } }, | |
2659 | { "btcQ", { Ev, Ib } }, | |
c608c12e | 2660 | }, |
1ceb70f8 | 2661 | /* REG_0FC7 */ |
c608c12e | 2662 | { |
592d1631 | 2663 | { Bad_Opcode }, |
4e7d34a6 | 2664 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
592d1631 L |
2665 | { Bad_Opcode }, |
2666 | { Bad_Opcode }, | |
2667 | { Bad_Opcode }, | |
2668 | { Bad_Opcode }, | |
1ceb70f8 L |
2669 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
2670 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 2671 | }, |
c0f3af97 L |
2672 | /* REG_VEX_71 */ |
2673 | { | |
592d1631 L |
2674 | { Bad_Opcode }, |
2675 | { Bad_Opcode }, | |
c0f3af97 | 2676 | { MOD_TABLE (MOD_VEX_71_REG_2) }, |
592d1631 | 2677 | { Bad_Opcode }, |
c0f3af97 | 2678 | { MOD_TABLE (MOD_VEX_71_REG_4) }, |
592d1631 | 2679 | { Bad_Opcode }, |
c0f3af97 | 2680 | { MOD_TABLE (MOD_VEX_71_REG_6) }, |
c0f3af97 L |
2681 | }, |
2682 | /* REG_VEX_72 */ | |
2683 | { | |
592d1631 L |
2684 | { Bad_Opcode }, |
2685 | { Bad_Opcode }, | |
c0f3af97 | 2686 | { MOD_TABLE (MOD_VEX_72_REG_2) }, |
592d1631 | 2687 | { Bad_Opcode }, |
c0f3af97 | 2688 | { MOD_TABLE (MOD_VEX_72_REG_4) }, |
592d1631 | 2689 | { Bad_Opcode }, |
c0f3af97 | 2690 | { MOD_TABLE (MOD_VEX_72_REG_6) }, |
c0f3af97 L |
2691 | }, |
2692 | /* REG_VEX_73 */ | |
2693 | { | |
592d1631 L |
2694 | { Bad_Opcode }, |
2695 | { Bad_Opcode }, | |
c0f3af97 L |
2696 | { MOD_TABLE (MOD_VEX_73_REG_2) }, |
2697 | { MOD_TABLE (MOD_VEX_73_REG_3) }, | |
592d1631 L |
2698 | { Bad_Opcode }, |
2699 | { Bad_Opcode }, | |
c0f3af97 L |
2700 | { MOD_TABLE (MOD_VEX_73_REG_6) }, |
2701 | { MOD_TABLE (MOD_VEX_73_REG_7) }, | |
2702 | }, | |
2703 | /* REG_VEX_AE */ | |
2704 | { | |
592d1631 L |
2705 | { Bad_Opcode }, |
2706 | { Bad_Opcode }, | |
c0f3af97 L |
2707 | { MOD_TABLE (MOD_VEX_AE_REG_2) }, |
2708 | { MOD_TABLE (MOD_VEX_AE_REG_3) }, | |
c0f3af97 | 2709 | }, |
f88c9eb0 SP |
2710 | /* REG_XOP_LWPCB */ |
2711 | { | |
2712 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, | |
2713 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, | |
f88c9eb0 SP |
2714 | }, |
2715 | /* REG_XOP_LWP */ | |
2716 | { | |
2717 | { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } }, | |
2718 | { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } }, | |
f88c9eb0 | 2719 | }, |
4e7d34a6 L |
2720 | }; |
2721 | ||
1ceb70f8 L |
2722 | static const struct dis386 prefix_table[][4] = { |
2723 | /* PREFIX_90 */ | |
252b5132 | 2724 | { |
4e7d34a6 L |
2725 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
2726 | { "pause", { XX } }, | |
2727 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
0f10071e | 2728 | }, |
4e7d34a6 | 2729 | |
1ceb70f8 | 2730 | /* PREFIX_0F10 */ |
cc0ec051 | 2731 | { |
4e7d34a6 L |
2732 | { "movups", { XM, EXx } }, |
2733 | { "movss", { XM, EXd } }, | |
2734 | { "movupd", { XM, EXx } }, | |
2735 | { "movsd", { XM, EXq } }, | |
30d1c836 | 2736 | }, |
4e7d34a6 | 2737 | |
1ceb70f8 | 2738 | /* PREFIX_0F11 */ |
30d1c836 | 2739 | { |
b6169b20 | 2740 | { "movups", { EXxS, XM } }, |
fa99fab2 | 2741 | { "movss", { EXdS, XM } }, |
b6169b20 | 2742 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 2743 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 2744 | }, |
252b5132 | 2745 | |
1ceb70f8 | 2746 | /* PREFIX_0F12 */ |
c608c12e | 2747 | { |
1ceb70f8 | 2748 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
2749 | { "movsldup", { XM, EXx } }, |
2750 | { "movlpd", { XM, EXq } }, | |
2751 | { "movddup", { XM, EXq } }, | |
c608c12e | 2752 | }, |
4e7d34a6 | 2753 | |
1ceb70f8 | 2754 | /* PREFIX_0F16 */ |
c608c12e | 2755 | { |
1ceb70f8 | 2756 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
2757 | { "movshdup", { XM, EXx } }, |
2758 | { "movhpd", { XM, EXq } }, | |
c608c12e | 2759 | }, |
4e7d34a6 | 2760 | |
1ceb70f8 | 2761 | /* PREFIX_0F2A */ |
c608c12e | 2762 | { |
09335d05 | 2763 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 2764 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 2765 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 2766 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 2767 | }, |
4e7d34a6 | 2768 | |
1ceb70f8 | 2769 | /* PREFIX_0F2B */ |
c608c12e | 2770 | { |
75c135a8 L |
2771 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
2772 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
2773 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
2774 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 2775 | }, |
4e7d34a6 | 2776 | |
1ceb70f8 | 2777 | /* PREFIX_0F2C */ |
c608c12e | 2778 | { |
09335d05 L |
2779 | { "cvttps2pi", { MXC, EXq } }, |
2780 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 2781 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 2782 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 2783 | }, |
4e7d34a6 | 2784 | |
1ceb70f8 | 2785 | /* PREFIX_0F2D */ |
c608c12e | 2786 | { |
4e7d34a6 L |
2787 | { "cvtps2pi", { MXC, EXq } }, |
2788 | { "cvtss2siY", { Gv, EXd } }, | |
2789 | { "cvtpd2pi", { MXC, EXx } }, | |
2790 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 2791 | }, |
4e7d34a6 | 2792 | |
1ceb70f8 | 2793 | /* PREFIX_0F2E */ |
c608c12e | 2794 | { |
4e7d34a6 | 2795 | { "ucomiss",{ XM, EXd } }, |
592d1631 | 2796 | { Bad_Opcode }, |
4e7d34a6 | 2797 | { "ucomisd",{ XM, EXq } }, |
c608c12e | 2798 | }, |
4e7d34a6 | 2799 | |
1ceb70f8 | 2800 | /* PREFIX_0F2F */ |
c608c12e | 2801 | { |
4e7d34a6 | 2802 | { "comiss", { XM, EXd } }, |
592d1631 | 2803 | { Bad_Opcode }, |
4e7d34a6 | 2804 | { "comisd", { XM, EXq } }, |
c608c12e | 2805 | }, |
4e7d34a6 | 2806 | |
1ceb70f8 | 2807 | /* PREFIX_0F51 */ |
c608c12e | 2808 | { |
4e7d34a6 L |
2809 | { "sqrtps", { XM, EXx } }, |
2810 | { "sqrtss", { XM, EXd } }, | |
2811 | { "sqrtpd", { XM, EXx } }, | |
2812 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 2813 | }, |
4e7d34a6 | 2814 | |
1ceb70f8 | 2815 | /* PREFIX_0F52 */ |
c608c12e | 2816 | { |
4e7d34a6 L |
2817 | { "rsqrtps",{ XM, EXx } }, |
2818 | { "rsqrtss",{ XM, EXd } }, | |
c608c12e | 2819 | }, |
4e7d34a6 | 2820 | |
1ceb70f8 | 2821 | /* PREFIX_0F53 */ |
c608c12e | 2822 | { |
4e7d34a6 L |
2823 | { "rcpps", { XM, EXx } }, |
2824 | { "rcpss", { XM, EXd } }, | |
c608c12e | 2825 | }, |
4e7d34a6 | 2826 | |
1ceb70f8 | 2827 | /* PREFIX_0F58 */ |
c608c12e | 2828 | { |
4e7d34a6 L |
2829 | { "addps", { XM, EXx } }, |
2830 | { "addss", { XM, EXd } }, | |
2831 | { "addpd", { XM, EXx } }, | |
2832 | { "addsd", { XM, EXq } }, | |
c608c12e | 2833 | }, |
4e7d34a6 | 2834 | |
1ceb70f8 | 2835 | /* PREFIX_0F59 */ |
c608c12e | 2836 | { |
4e7d34a6 L |
2837 | { "mulps", { XM, EXx } }, |
2838 | { "mulss", { XM, EXd } }, | |
2839 | { "mulpd", { XM, EXx } }, | |
2840 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 2841 | }, |
4e7d34a6 | 2842 | |
1ceb70f8 | 2843 | /* PREFIX_0F5A */ |
041bd2e0 | 2844 | { |
4e7d34a6 L |
2845 | { "cvtps2pd", { XM, EXq } }, |
2846 | { "cvtss2sd", { XM, EXd } }, | |
2847 | { "cvtpd2ps", { XM, EXx } }, | |
2848 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 2849 | }, |
4e7d34a6 | 2850 | |
1ceb70f8 | 2851 | /* PREFIX_0F5B */ |
041bd2e0 | 2852 | { |
09a2c6cf L |
2853 | { "cvtdq2ps", { XM, EXx } }, |
2854 | { "cvttps2dq", { XM, EXx } }, | |
2855 | { "cvtps2dq", { XM, EXx } }, | |
041bd2e0 | 2856 | }, |
4e7d34a6 | 2857 | |
1ceb70f8 | 2858 | /* PREFIX_0F5C */ |
041bd2e0 | 2859 | { |
4e7d34a6 L |
2860 | { "subps", { XM, EXx } }, |
2861 | { "subss", { XM, EXd } }, | |
2862 | { "subpd", { XM, EXx } }, | |
2863 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 2864 | }, |
4e7d34a6 | 2865 | |
1ceb70f8 | 2866 | /* PREFIX_0F5D */ |
041bd2e0 | 2867 | { |
4e7d34a6 L |
2868 | { "minps", { XM, EXx } }, |
2869 | { "minss", { XM, EXd } }, | |
2870 | { "minpd", { XM, EXx } }, | |
2871 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 2872 | }, |
4e7d34a6 | 2873 | |
1ceb70f8 | 2874 | /* PREFIX_0F5E */ |
041bd2e0 | 2875 | { |
4e7d34a6 L |
2876 | { "divps", { XM, EXx } }, |
2877 | { "divss", { XM, EXd } }, | |
2878 | { "divpd", { XM, EXx } }, | |
2879 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 2880 | }, |
4e7d34a6 | 2881 | |
1ceb70f8 | 2882 | /* PREFIX_0F5F */ |
041bd2e0 | 2883 | { |
4e7d34a6 L |
2884 | { "maxps", { XM, EXx } }, |
2885 | { "maxss", { XM, EXd } }, | |
2886 | { "maxpd", { XM, EXx } }, | |
2887 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 2888 | }, |
4e7d34a6 | 2889 | |
1ceb70f8 | 2890 | /* PREFIX_0F60 */ |
041bd2e0 | 2891 | { |
4e7d34a6 | 2892 | { "punpcklbw",{ MX, EMd } }, |
592d1631 | 2893 | { Bad_Opcode }, |
4e7d34a6 | 2894 | { "punpcklbw",{ MX, EMx } }, |
041bd2e0 | 2895 | }, |
4e7d34a6 | 2896 | |
1ceb70f8 | 2897 | /* PREFIX_0F61 */ |
041bd2e0 | 2898 | { |
4e7d34a6 | 2899 | { "punpcklwd",{ MX, EMd } }, |
592d1631 | 2900 | { Bad_Opcode }, |
4e7d34a6 | 2901 | { "punpcklwd",{ MX, EMx } }, |
041bd2e0 | 2902 | }, |
4e7d34a6 | 2903 | |
1ceb70f8 | 2904 | /* PREFIX_0F62 */ |
041bd2e0 | 2905 | { |
4e7d34a6 | 2906 | { "punpckldq",{ MX, EMd } }, |
592d1631 | 2907 | { Bad_Opcode }, |
4e7d34a6 | 2908 | { "punpckldq",{ MX, EMx } }, |
041bd2e0 | 2909 | }, |
4e7d34a6 | 2910 | |
1ceb70f8 | 2911 | /* PREFIX_0F6C */ |
041bd2e0 | 2912 | { |
592d1631 L |
2913 | { Bad_Opcode }, |
2914 | { Bad_Opcode }, | |
4e7d34a6 | 2915 | { "punpcklqdq", { XM, EXx } }, |
0f17484f | 2916 | }, |
4e7d34a6 | 2917 | |
1ceb70f8 | 2918 | /* PREFIX_0F6D */ |
0f17484f | 2919 | { |
592d1631 L |
2920 | { Bad_Opcode }, |
2921 | { Bad_Opcode }, | |
4e7d34a6 | 2922 | { "punpckhqdq", { XM, EXx } }, |
041bd2e0 | 2923 | }, |
4e7d34a6 | 2924 | |
1ceb70f8 | 2925 | /* PREFIX_0F6F */ |
ca164297 | 2926 | { |
4e7d34a6 L |
2927 | { "movq", { MX, EM } }, |
2928 | { "movdqu", { XM, EXx } }, | |
2929 | { "movdqa", { XM, EXx } }, | |
ca164297 | 2930 | }, |
4e7d34a6 | 2931 | |
1ceb70f8 | 2932 | /* PREFIX_0F70 */ |
4e7d34a6 L |
2933 | { |
2934 | { "pshufw", { MX, EM, Ib } }, | |
2935 | { "pshufhw",{ XM, EXx, Ib } }, | |
2936 | { "pshufd", { XM, EXx, Ib } }, | |
2937 | { "pshuflw",{ XM, EXx, Ib } }, | |
2938 | }, | |
2939 | ||
92fddf8e L |
2940 | /* PREFIX_0F73_REG_3 */ |
2941 | { | |
592d1631 L |
2942 | { Bad_Opcode }, |
2943 | { Bad_Opcode }, | |
92fddf8e | 2944 | { "psrldq", { XS, Ib } }, |
92fddf8e L |
2945 | }, |
2946 | ||
2947 | /* PREFIX_0F73_REG_7 */ | |
2948 | { | |
592d1631 L |
2949 | { Bad_Opcode }, |
2950 | { Bad_Opcode }, | |
92fddf8e | 2951 | { "pslldq", { XS, Ib } }, |
92fddf8e L |
2952 | }, |
2953 | ||
1ceb70f8 | 2954 | /* PREFIX_0F78 */ |
4e7d34a6 L |
2955 | { |
2956 | {"vmread", { Em, Gm } }, | |
592d1631 | 2957 | { Bad_Opcode }, |
4e7d34a6 L |
2958 | {"extrq", { XS, Ib, Ib } }, |
2959 | {"insertq", { XM, XS, Ib, Ib } }, | |
2960 | }, | |
2961 | ||
1ceb70f8 | 2962 | /* PREFIX_0F79 */ |
4e7d34a6 L |
2963 | { |
2964 | {"vmwrite", { Gm, Em } }, | |
592d1631 | 2965 | { Bad_Opcode }, |
4e7d34a6 L |
2966 | {"extrq", { XM, XS } }, |
2967 | {"insertq", { XM, XS } }, | |
2968 | }, | |
2969 | ||
1ceb70f8 | 2970 | /* PREFIX_0F7C */ |
ca164297 | 2971 | { |
592d1631 L |
2972 | { Bad_Opcode }, |
2973 | { Bad_Opcode }, | |
09a2c6cf L |
2974 | { "haddpd", { XM, EXx } }, |
2975 | { "haddps", { XM, EXx } }, | |
ca164297 | 2976 | }, |
4e7d34a6 | 2977 | |
1ceb70f8 | 2978 | /* PREFIX_0F7D */ |
ca164297 | 2979 | { |
592d1631 L |
2980 | { Bad_Opcode }, |
2981 | { Bad_Opcode }, | |
09a2c6cf L |
2982 | { "hsubpd", { XM, EXx } }, |
2983 | { "hsubps", { XM, EXx } }, | |
ca164297 | 2984 | }, |
4e7d34a6 | 2985 | |
1ceb70f8 | 2986 | /* PREFIX_0F7E */ |
ca164297 | 2987 | { |
4e7d34a6 L |
2988 | { "movK", { Edq, MX } }, |
2989 | { "movq", { XM, EXq } }, | |
2990 | { "movK", { Edq, XM } }, | |
ca164297 | 2991 | }, |
4e7d34a6 | 2992 | |
1ceb70f8 | 2993 | /* PREFIX_0F7F */ |
ca164297 | 2994 | { |
b6169b20 L |
2995 | { "movq", { EMS, MX } }, |
2996 | { "movdqu", { EXxS, XM } }, | |
2997 | { "movdqa", { EXxS, XM } }, | |
ca164297 | 2998 | }, |
4e7d34a6 | 2999 | |
1ceb70f8 | 3000 | /* PREFIX_0FB8 */ |
ca164297 | 3001 | { |
592d1631 | 3002 | { Bad_Opcode }, |
4e7d34a6 | 3003 | { "popcntS", { Gv, Ev } }, |
ca164297 | 3004 | }, |
4e7d34a6 | 3005 | |
1ceb70f8 | 3006 | /* PREFIX_0FBD */ |
050dfa73 | 3007 | { |
4e7d34a6 L |
3008 | { "bsrS", { Gv, Ev } }, |
3009 | { "lzcntS", { Gv, Ev } }, | |
3010 | { "bsrS", { Gv, Ev } }, | |
050dfa73 MM |
3011 | }, |
3012 | ||
1ceb70f8 | 3013 | /* PREFIX_0FC2 */ |
050dfa73 | 3014 | { |
ad19981d L |
3015 | { "cmpps", { XM, EXx, CMP } }, |
3016 | { "cmpss", { XM, EXd, CMP } }, | |
3017 | { "cmppd", { XM, EXx, CMP } }, | |
3018 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 3019 | }, |
246c51aa | 3020 | |
4ee52178 L |
3021 | /* PREFIX_0FC3 */ |
3022 | { | |
3023 | { "movntiS", { Ma, Gv } }, | |
4ee52178 L |
3024 | }, |
3025 | ||
92fddf8e L |
3026 | /* PREFIX_0FC7_REG_6 */ |
3027 | { | |
3028 | { "vmptrld",{ Mq } }, | |
3029 | { "vmxon", { Mq } }, | |
3030 | { "vmclear",{ Mq } }, | |
92fddf8e L |
3031 | }, |
3032 | ||
1ceb70f8 | 3033 | /* PREFIX_0FD0 */ |
050dfa73 | 3034 | { |
592d1631 L |
3035 | { Bad_Opcode }, |
3036 | { Bad_Opcode }, | |
4e7d34a6 L |
3037 | { "addsubpd", { XM, EXx } }, |
3038 | { "addsubps", { XM, EXx } }, | |
246c51aa | 3039 | }, |
050dfa73 | 3040 | |
1ceb70f8 | 3041 | /* PREFIX_0FD6 */ |
050dfa73 | 3042 | { |
592d1631 | 3043 | { Bad_Opcode }, |
4e7d34a6 | 3044 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 3045 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 3046 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
3047 | }, |
3048 | ||
1ceb70f8 | 3049 | /* PREFIX_0FE6 */ |
7918206c | 3050 | { |
592d1631 | 3051 | { Bad_Opcode }, |
4e7d34a6 L |
3052 | { "cvtdq2pd", { XM, EXq } }, |
3053 | { "cvttpd2dq", { XM, EXx } }, | |
3054 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 3055 | }, |
8b38ad71 | 3056 | |
1ceb70f8 | 3057 | /* PREFIX_0FE7 */ |
8b38ad71 | 3058 | { |
4ee52178 | 3059 | { "movntq", { Mq, MX } }, |
592d1631 | 3060 | { Bad_Opcode }, |
75c135a8 | 3061 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3062 | }, |
3063 | ||
1ceb70f8 | 3064 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3065 | { |
592d1631 L |
3066 | { Bad_Opcode }, |
3067 | { Bad_Opcode }, | |
3068 | { Bad_Opcode }, | |
1ceb70f8 | 3069 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3070 | }, |
3071 | ||
1ceb70f8 | 3072 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
3073 | { |
3074 | { "maskmovq", { MX, MS } }, | |
592d1631 | 3075 | { Bad_Opcode }, |
4e7d34a6 | 3076 | { "maskmovdqu", { XM, XS } }, |
8b38ad71 | 3077 | }, |
42903f7f | 3078 | |
1ceb70f8 | 3079 | /* PREFIX_0F3810 */ |
42903f7f | 3080 | { |
592d1631 L |
3081 | { Bad_Opcode }, |
3082 | { Bad_Opcode }, | |
88a94849 | 3083 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
3084 | }, |
3085 | ||
1ceb70f8 | 3086 | /* PREFIX_0F3814 */ |
42903f7f | 3087 | { |
592d1631 L |
3088 | { Bad_Opcode }, |
3089 | { Bad_Opcode }, | |
88a94849 | 3090 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
3091 | }, |
3092 | ||
1ceb70f8 | 3093 | /* PREFIX_0F3815 */ |
42903f7f | 3094 | { |
592d1631 L |
3095 | { Bad_Opcode }, |
3096 | { Bad_Opcode }, | |
09a2c6cf | 3097 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
3098 | }, |
3099 | ||
1ceb70f8 | 3100 | /* PREFIX_0F3817 */ |
42903f7f | 3101 | { |
592d1631 L |
3102 | { Bad_Opcode }, |
3103 | { Bad_Opcode }, | |
09a2c6cf | 3104 | { "ptest", { XM, EXx } }, |
42903f7f L |
3105 | }, |
3106 | ||
1ceb70f8 | 3107 | /* PREFIX_0F3820 */ |
42903f7f | 3108 | { |
592d1631 L |
3109 | { Bad_Opcode }, |
3110 | { Bad_Opcode }, | |
8976381e | 3111 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
3112 | }, |
3113 | ||
1ceb70f8 | 3114 | /* PREFIX_0F3821 */ |
42903f7f | 3115 | { |
592d1631 L |
3116 | { Bad_Opcode }, |
3117 | { Bad_Opcode }, | |
8976381e | 3118 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
3119 | }, |
3120 | ||
1ceb70f8 | 3121 | /* PREFIX_0F3822 */ |
42903f7f | 3122 | { |
592d1631 L |
3123 | { Bad_Opcode }, |
3124 | { Bad_Opcode }, | |
8976381e | 3125 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
3126 | }, |
3127 | ||
1ceb70f8 | 3128 | /* PREFIX_0F3823 */ |
42903f7f | 3129 | { |
592d1631 L |
3130 | { Bad_Opcode }, |
3131 | { Bad_Opcode }, | |
8976381e | 3132 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
3133 | }, |
3134 | ||
1ceb70f8 | 3135 | /* PREFIX_0F3824 */ |
42903f7f | 3136 | { |
592d1631 L |
3137 | { Bad_Opcode }, |
3138 | { Bad_Opcode }, | |
8976381e | 3139 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
3140 | }, |
3141 | ||
1ceb70f8 | 3142 | /* PREFIX_0F3825 */ |
42903f7f | 3143 | { |
592d1631 L |
3144 | { Bad_Opcode }, |
3145 | { Bad_Opcode }, | |
8976381e | 3146 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
3147 | }, |
3148 | ||
1ceb70f8 | 3149 | /* PREFIX_0F3828 */ |
42903f7f | 3150 | { |
592d1631 L |
3151 | { Bad_Opcode }, |
3152 | { Bad_Opcode }, | |
09a2c6cf | 3153 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
3154 | }, |
3155 | ||
1ceb70f8 | 3156 | /* PREFIX_0F3829 */ |
42903f7f | 3157 | { |
592d1631 L |
3158 | { Bad_Opcode }, |
3159 | { Bad_Opcode }, | |
09a2c6cf | 3160 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
3161 | }, |
3162 | ||
1ceb70f8 | 3163 | /* PREFIX_0F382A */ |
42903f7f | 3164 | { |
592d1631 L |
3165 | { Bad_Opcode }, |
3166 | { Bad_Opcode }, | |
75c135a8 | 3167 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
3168 | }, |
3169 | ||
1ceb70f8 | 3170 | /* PREFIX_0F382B */ |
42903f7f | 3171 | { |
592d1631 L |
3172 | { Bad_Opcode }, |
3173 | { Bad_Opcode }, | |
09a2c6cf | 3174 | { "packusdw", { XM, EXx } }, |
42903f7f L |
3175 | }, |
3176 | ||
1ceb70f8 | 3177 | /* PREFIX_0F3830 */ |
42903f7f | 3178 | { |
592d1631 L |
3179 | { Bad_Opcode }, |
3180 | { Bad_Opcode }, | |
8976381e | 3181 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
3182 | }, |
3183 | ||
1ceb70f8 | 3184 | /* PREFIX_0F3831 */ |
42903f7f | 3185 | { |
592d1631 L |
3186 | { Bad_Opcode }, |
3187 | { Bad_Opcode }, | |
8976381e | 3188 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
3189 | }, |
3190 | ||
1ceb70f8 | 3191 | /* PREFIX_0F3832 */ |
42903f7f | 3192 | { |
592d1631 L |
3193 | { Bad_Opcode }, |
3194 | { Bad_Opcode }, | |
8976381e | 3195 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
3196 | }, |
3197 | ||
1ceb70f8 | 3198 | /* PREFIX_0F3833 */ |
42903f7f | 3199 | { |
592d1631 L |
3200 | { Bad_Opcode }, |
3201 | { Bad_Opcode }, | |
8976381e | 3202 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
3203 | }, |
3204 | ||
1ceb70f8 | 3205 | /* PREFIX_0F3834 */ |
42903f7f | 3206 | { |
592d1631 L |
3207 | { Bad_Opcode }, |
3208 | { Bad_Opcode }, | |
8976381e | 3209 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
3210 | }, |
3211 | ||
1ceb70f8 | 3212 | /* PREFIX_0F3835 */ |
42903f7f | 3213 | { |
592d1631 L |
3214 | { Bad_Opcode }, |
3215 | { Bad_Opcode }, | |
8976381e | 3216 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
3217 | }, |
3218 | ||
1ceb70f8 | 3219 | /* PREFIX_0F3837 */ |
4e7d34a6 | 3220 | { |
592d1631 L |
3221 | { Bad_Opcode }, |
3222 | { Bad_Opcode }, | |
4e7d34a6 | 3223 | { "pcmpgtq", { XM, EXx } }, |
4e7d34a6 L |
3224 | }, |
3225 | ||
1ceb70f8 | 3226 | /* PREFIX_0F3838 */ |
42903f7f | 3227 | { |
592d1631 L |
3228 | { Bad_Opcode }, |
3229 | { Bad_Opcode }, | |
09a2c6cf | 3230 | { "pminsb", { XM, EXx } }, |
42903f7f L |
3231 | }, |
3232 | ||
1ceb70f8 | 3233 | /* PREFIX_0F3839 */ |
42903f7f | 3234 | { |
592d1631 L |
3235 | { Bad_Opcode }, |
3236 | { Bad_Opcode }, | |
09a2c6cf | 3237 | { "pminsd", { XM, EXx } }, |
42903f7f L |
3238 | }, |
3239 | ||
1ceb70f8 | 3240 | /* PREFIX_0F383A */ |
42903f7f | 3241 | { |
592d1631 L |
3242 | { Bad_Opcode }, |
3243 | { Bad_Opcode }, | |
09a2c6cf | 3244 | { "pminuw", { XM, EXx } }, |
42903f7f L |
3245 | }, |
3246 | ||
1ceb70f8 | 3247 | /* PREFIX_0F383B */ |
42903f7f | 3248 | { |
592d1631 L |
3249 | { Bad_Opcode }, |
3250 | { Bad_Opcode }, | |
09a2c6cf | 3251 | { "pminud", { XM, EXx } }, |
42903f7f L |
3252 | }, |
3253 | ||
1ceb70f8 | 3254 | /* PREFIX_0F383C */ |
42903f7f | 3255 | { |
592d1631 L |
3256 | { Bad_Opcode }, |
3257 | { Bad_Opcode }, | |
09a2c6cf | 3258 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
3259 | }, |
3260 | ||
1ceb70f8 | 3261 | /* PREFIX_0F383D */ |
42903f7f | 3262 | { |
592d1631 L |
3263 | { Bad_Opcode }, |
3264 | { Bad_Opcode }, | |
09a2c6cf | 3265 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
3266 | }, |
3267 | ||
1ceb70f8 | 3268 | /* PREFIX_0F383E */ |
42903f7f | 3269 | { |
592d1631 L |
3270 | { Bad_Opcode }, |
3271 | { Bad_Opcode }, | |
09a2c6cf | 3272 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
3273 | }, |
3274 | ||
1ceb70f8 | 3275 | /* PREFIX_0F383F */ |
42903f7f | 3276 | { |
592d1631 L |
3277 | { Bad_Opcode }, |
3278 | { Bad_Opcode }, | |
09a2c6cf | 3279 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
3280 | }, |
3281 | ||
1ceb70f8 | 3282 | /* PREFIX_0F3840 */ |
42903f7f | 3283 | { |
592d1631 L |
3284 | { Bad_Opcode }, |
3285 | { Bad_Opcode }, | |
09a2c6cf | 3286 | { "pmulld", { XM, EXx } }, |
42903f7f L |
3287 | }, |
3288 | ||
1ceb70f8 | 3289 | /* PREFIX_0F3841 */ |
42903f7f | 3290 | { |
592d1631 L |
3291 | { Bad_Opcode }, |
3292 | { Bad_Opcode }, | |
09a2c6cf | 3293 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
3294 | }, |
3295 | ||
f1f8f695 L |
3296 | /* PREFIX_0F3880 */ |
3297 | { | |
592d1631 L |
3298 | { Bad_Opcode }, |
3299 | { Bad_Opcode }, | |
f1f8f695 | 3300 | { "invept", { Gm, Mo } }, |
f1f8f695 L |
3301 | }, |
3302 | ||
3303 | /* PREFIX_0F3881 */ | |
3304 | { | |
592d1631 L |
3305 | { Bad_Opcode }, |
3306 | { Bad_Opcode }, | |
f1f8f695 | 3307 | { "invvpid", { Gm, Mo } }, |
f1f8f695 L |
3308 | }, |
3309 | ||
c0f3af97 L |
3310 | /* PREFIX_0F38DB */ |
3311 | { | |
592d1631 L |
3312 | { Bad_Opcode }, |
3313 | { Bad_Opcode }, | |
c0f3af97 | 3314 | { "aesimc", { XM, EXx } }, |
c0f3af97 L |
3315 | }, |
3316 | ||
3317 | /* PREFIX_0F38DC */ | |
3318 | { | |
592d1631 L |
3319 | { Bad_Opcode }, |
3320 | { Bad_Opcode }, | |
c0f3af97 | 3321 | { "aesenc", { XM, EXx } }, |
c0f3af97 L |
3322 | }, |
3323 | ||
3324 | /* PREFIX_0F38DD */ | |
3325 | { | |
592d1631 L |
3326 | { Bad_Opcode }, |
3327 | { Bad_Opcode }, | |
c0f3af97 | 3328 | { "aesenclast", { XM, EXx } }, |
c0f3af97 L |
3329 | }, |
3330 | ||
3331 | /* PREFIX_0F38DE */ | |
3332 | { | |
592d1631 L |
3333 | { Bad_Opcode }, |
3334 | { Bad_Opcode }, | |
c0f3af97 | 3335 | { "aesdec", { XM, EXx } }, |
c0f3af97 L |
3336 | }, |
3337 | ||
3338 | /* PREFIX_0F38DF */ | |
3339 | { | |
592d1631 L |
3340 | { Bad_Opcode }, |
3341 | { Bad_Opcode }, | |
c0f3af97 | 3342 | { "aesdeclast", { XM, EXx } }, |
c0f3af97 L |
3343 | }, |
3344 | ||
1ceb70f8 | 3345 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3346 | { |
f1f8f695 | 3347 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
592d1631 | 3348 | { Bad_Opcode }, |
f1f8f695 | 3349 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4e7d34a6 L |
3350 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
3351 | }, | |
3352 | ||
1ceb70f8 | 3353 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3354 | { |
f1f8f695 | 3355 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
592d1631 | 3356 | { Bad_Opcode }, |
f1f8f695 | 3357 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4e7d34a6 L |
3358 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
3359 | }, | |
3360 | ||
1ceb70f8 | 3361 | /* PREFIX_0F3A08 */ |
42903f7f | 3362 | { |
592d1631 L |
3363 | { Bad_Opcode }, |
3364 | { Bad_Opcode }, | |
09a2c6cf | 3365 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
3366 | }, |
3367 | ||
1ceb70f8 | 3368 | /* PREFIX_0F3A09 */ |
42903f7f | 3369 | { |
592d1631 L |
3370 | { Bad_Opcode }, |
3371 | { Bad_Opcode }, | |
09a2c6cf | 3372 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
3373 | }, |
3374 | ||
1ceb70f8 | 3375 | /* PREFIX_0F3A0A */ |
42903f7f | 3376 | { |
592d1631 L |
3377 | { Bad_Opcode }, |
3378 | { Bad_Opcode }, | |
09335d05 | 3379 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
3380 | }, |
3381 | ||
1ceb70f8 | 3382 | /* PREFIX_0F3A0B */ |
42903f7f | 3383 | { |
592d1631 L |
3384 | { Bad_Opcode }, |
3385 | { Bad_Opcode }, | |
09335d05 | 3386 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
3387 | }, |
3388 | ||
1ceb70f8 | 3389 | /* PREFIX_0F3A0C */ |
42903f7f | 3390 | { |
592d1631 L |
3391 | { Bad_Opcode }, |
3392 | { Bad_Opcode }, | |
09a2c6cf | 3393 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
3394 | }, |
3395 | ||
1ceb70f8 | 3396 | /* PREFIX_0F3A0D */ |
42903f7f | 3397 | { |
592d1631 L |
3398 | { Bad_Opcode }, |
3399 | { Bad_Opcode }, | |
09a2c6cf | 3400 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
3401 | }, |
3402 | ||
1ceb70f8 | 3403 | /* PREFIX_0F3A0E */ |
42903f7f | 3404 | { |
592d1631 L |
3405 | { Bad_Opcode }, |
3406 | { Bad_Opcode }, | |
09a2c6cf | 3407 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
3408 | }, |
3409 | ||
1ceb70f8 | 3410 | /* PREFIX_0F3A14 */ |
42903f7f | 3411 | { |
592d1631 L |
3412 | { Bad_Opcode }, |
3413 | { Bad_Opcode }, | |
42903f7f | 3414 | { "pextrb", { Edqb, XM, Ib } }, |
42903f7f L |
3415 | }, |
3416 | ||
1ceb70f8 | 3417 | /* PREFIX_0F3A15 */ |
42903f7f | 3418 | { |
592d1631 L |
3419 | { Bad_Opcode }, |
3420 | { Bad_Opcode }, | |
42903f7f | 3421 | { "pextrw", { Edqw, XM, Ib } }, |
42903f7f L |
3422 | }, |
3423 | ||
1ceb70f8 | 3424 | /* PREFIX_0F3A16 */ |
42903f7f | 3425 | { |
592d1631 L |
3426 | { Bad_Opcode }, |
3427 | { Bad_Opcode }, | |
42903f7f | 3428 | { "pextrK", { Edq, XM, Ib } }, |
42903f7f L |
3429 | }, |
3430 | ||
1ceb70f8 | 3431 | /* PREFIX_0F3A17 */ |
42903f7f | 3432 | { |
592d1631 L |
3433 | { Bad_Opcode }, |
3434 | { Bad_Opcode }, | |
42903f7f | 3435 | { "extractps", { Edqd, XM, Ib } }, |
42903f7f L |
3436 | }, |
3437 | ||
1ceb70f8 | 3438 | /* PREFIX_0F3A20 */ |
42903f7f | 3439 | { |
592d1631 L |
3440 | { Bad_Opcode }, |
3441 | { Bad_Opcode }, | |
42903f7f | 3442 | { "pinsrb", { XM, Edqb, Ib } }, |
42903f7f L |
3443 | }, |
3444 | ||
1ceb70f8 | 3445 | /* PREFIX_0F3A21 */ |
42903f7f | 3446 | { |
592d1631 L |
3447 | { Bad_Opcode }, |
3448 | { Bad_Opcode }, | |
8976381e | 3449 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
3450 | }, |
3451 | ||
1ceb70f8 | 3452 | /* PREFIX_0F3A22 */ |
42903f7f | 3453 | { |
592d1631 L |
3454 | { Bad_Opcode }, |
3455 | { Bad_Opcode }, | |
42903f7f | 3456 | { "pinsrK", { XM, Edq, Ib } }, |
42903f7f L |
3457 | }, |
3458 | ||
1ceb70f8 | 3459 | /* PREFIX_0F3A40 */ |
42903f7f | 3460 | { |
592d1631 L |
3461 | { Bad_Opcode }, |
3462 | { Bad_Opcode }, | |
09a2c6cf | 3463 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
3464 | }, |
3465 | ||
1ceb70f8 | 3466 | /* PREFIX_0F3A41 */ |
42903f7f | 3467 | { |
592d1631 L |
3468 | { Bad_Opcode }, |
3469 | { Bad_Opcode }, | |
09a2c6cf | 3470 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
3471 | }, |
3472 | ||
1ceb70f8 | 3473 | /* PREFIX_0F3A42 */ |
42903f7f | 3474 | { |
592d1631 L |
3475 | { Bad_Opcode }, |
3476 | { Bad_Opcode }, | |
09a2c6cf | 3477 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f | 3478 | }, |
381d071f | 3479 | |
c0f3af97 L |
3480 | /* PREFIX_0F3A44 */ |
3481 | { | |
592d1631 L |
3482 | { Bad_Opcode }, |
3483 | { Bad_Opcode }, | |
c0f3af97 | 3484 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
c0f3af97 L |
3485 | }, |
3486 | ||
1ceb70f8 | 3487 | /* PREFIX_0F3A60 */ |
381d071f | 3488 | { |
592d1631 L |
3489 | { Bad_Opcode }, |
3490 | { Bad_Opcode }, | |
4e7d34a6 | 3491 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
3492 | }, |
3493 | ||
1ceb70f8 | 3494 | /* PREFIX_0F3A61 */ |
381d071f | 3495 | { |
592d1631 L |
3496 | { Bad_Opcode }, |
3497 | { Bad_Opcode }, | |
4e7d34a6 | 3498 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f L |
3499 | }, |
3500 | ||
1ceb70f8 | 3501 | /* PREFIX_0F3A62 */ |
381d071f | 3502 | { |
592d1631 L |
3503 | { Bad_Opcode }, |
3504 | { Bad_Opcode }, | |
4e7d34a6 | 3505 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f L |
3506 | }, |
3507 | ||
1ceb70f8 | 3508 | /* PREFIX_0F3A63 */ |
381d071f | 3509 | { |
592d1631 L |
3510 | { Bad_Opcode }, |
3511 | { Bad_Opcode }, | |
4e7d34a6 | 3512 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f | 3513 | }, |
09a2c6cf | 3514 | |
c0f3af97 | 3515 | /* PREFIX_0F3ADF */ |
09a2c6cf | 3516 | { |
592d1631 L |
3517 | { Bad_Opcode }, |
3518 | { Bad_Opcode }, | |
c0f3af97 | 3519 | { "aeskeygenassist", { XM, EXx, Ib } }, |
09a2c6cf L |
3520 | }, |
3521 | ||
c0f3af97 | 3522 | /* PREFIX_VEX_10 */ |
09a2c6cf | 3523 | { |
9e30b8e0 | 3524 | { VEX_W_TABLE (VEX_W_10_P_0) }, |
c0f3af97 | 3525 | { VEX_LEN_TABLE (VEX_LEN_10_P_1) }, |
9e30b8e0 | 3526 | { VEX_W_TABLE (VEX_W_10_P_2) }, |
c0f3af97 | 3527 | { VEX_LEN_TABLE (VEX_LEN_10_P_3) }, |
09a2c6cf L |
3528 | }, |
3529 | ||
c0f3af97 | 3530 | /* PREFIX_VEX_11 */ |
09a2c6cf | 3531 | { |
9e30b8e0 | 3532 | { VEX_W_TABLE (VEX_W_11_P_0) }, |
c0f3af97 | 3533 | { VEX_LEN_TABLE (VEX_LEN_11_P_1) }, |
9e30b8e0 | 3534 | { VEX_W_TABLE (VEX_W_11_P_2) }, |
c0f3af97 | 3535 | { VEX_LEN_TABLE (VEX_LEN_11_P_3) }, |
09a2c6cf L |
3536 | }, |
3537 | ||
c0f3af97 | 3538 | /* PREFIX_VEX_12 */ |
09a2c6cf | 3539 | { |
c0f3af97 | 3540 | { MOD_TABLE (MOD_VEX_12_PREFIX_0) }, |
9e30b8e0 | 3541 | { VEX_W_TABLE (VEX_W_12_P_1) }, |
c0f3af97 | 3542 | { VEX_LEN_TABLE (VEX_LEN_12_P_2) }, |
9e30b8e0 | 3543 | { VEX_W_TABLE (VEX_W_12_P_3) }, |
09a2c6cf L |
3544 | }, |
3545 | ||
c0f3af97 | 3546 | /* PREFIX_VEX_16 */ |
09a2c6cf | 3547 | { |
c0f3af97 | 3548 | { MOD_TABLE (MOD_VEX_16_PREFIX_0) }, |
9e30b8e0 | 3549 | { VEX_W_TABLE (VEX_W_16_P_1) }, |
c0f3af97 | 3550 | { VEX_LEN_TABLE (VEX_LEN_16_P_2) }, |
5f754f58 | 3551 | }, |
7c52e0e8 | 3552 | |
c0f3af97 | 3553 | /* PREFIX_VEX_2A */ |
5f754f58 | 3554 | { |
592d1631 | 3555 | { Bad_Opcode }, |
c0f3af97 | 3556 | { VEX_LEN_TABLE (VEX_LEN_2A_P_1) }, |
592d1631 | 3557 | { Bad_Opcode }, |
c0f3af97 | 3558 | { VEX_LEN_TABLE (VEX_LEN_2A_P_3) }, |
5f754f58 | 3559 | }, |
7c52e0e8 | 3560 | |
c0f3af97 | 3561 | /* PREFIX_VEX_2C */ |
5f754f58 | 3562 | { |
592d1631 | 3563 | { Bad_Opcode }, |
c0f3af97 | 3564 | { VEX_LEN_TABLE (VEX_LEN_2C_P_1) }, |
592d1631 | 3565 | { Bad_Opcode }, |
c0f3af97 | 3566 | { VEX_LEN_TABLE (VEX_LEN_2C_P_3) }, |
5f754f58 | 3567 | }, |
7c52e0e8 | 3568 | |
c0f3af97 | 3569 | /* PREFIX_VEX_2D */ |
7c52e0e8 | 3570 | { |
592d1631 | 3571 | { Bad_Opcode }, |
c0f3af97 | 3572 | { VEX_LEN_TABLE (VEX_LEN_2D_P_1) }, |
592d1631 | 3573 | { Bad_Opcode }, |
c0f3af97 | 3574 | { VEX_LEN_TABLE (VEX_LEN_2D_P_3) }, |
7c52e0e8 L |
3575 | }, |
3576 | ||
c0f3af97 | 3577 | /* PREFIX_VEX_2E */ |
7c52e0e8 | 3578 | { |
c0f3af97 | 3579 | { VEX_LEN_TABLE (VEX_LEN_2E_P_0) }, |
592d1631 | 3580 | { Bad_Opcode }, |
c0f3af97 | 3581 | { VEX_LEN_TABLE (VEX_LEN_2E_P_2) }, |
7c52e0e8 L |
3582 | }, |
3583 | ||
c0f3af97 | 3584 | /* PREFIX_VEX_2F */ |
7c52e0e8 | 3585 | { |
c0f3af97 | 3586 | { VEX_LEN_TABLE (VEX_LEN_2F_P_0) }, |
592d1631 | 3587 | { Bad_Opcode }, |
c0f3af97 | 3588 | { VEX_LEN_TABLE (VEX_LEN_2F_P_2) }, |
7c52e0e8 L |
3589 | }, |
3590 | ||
c0f3af97 | 3591 | /* PREFIX_VEX_51 */ |
7c52e0e8 | 3592 | { |
9e30b8e0 | 3593 | { VEX_W_TABLE (VEX_W_51_P_0) }, |
c0f3af97 | 3594 | { VEX_LEN_TABLE (VEX_LEN_51_P_1) }, |
9e30b8e0 | 3595 | { VEX_W_TABLE (VEX_W_51_P_2) }, |
c0f3af97 | 3596 | { VEX_LEN_TABLE (VEX_LEN_51_P_3) }, |
7c52e0e8 L |
3597 | }, |
3598 | ||
c0f3af97 | 3599 | /* PREFIX_VEX_52 */ |
7c52e0e8 | 3600 | { |
9e30b8e0 | 3601 | { VEX_W_TABLE (VEX_W_52_P_0) }, |
c0f3af97 | 3602 | { VEX_LEN_TABLE (VEX_LEN_52_P_1) }, |
7c52e0e8 L |
3603 | }, |
3604 | ||
c0f3af97 | 3605 | /* PREFIX_VEX_53 */ |
7c52e0e8 | 3606 | { |
9e30b8e0 | 3607 | { VEX_W_TABLE (VEX_W_53_P_0) }, |
c0f3af97 | 3608 | { VEX_LEN_TABLE (VEX_LEN_53_P_1) }, |
7c52e0e8 L |
3609 | }, |
3610 | ||
c0f3af97 | 3611 | /* PREFIX_VEX_58 */ |
7c52e0e8 | 3612 | { |
9e30b8e0 | 3613 | { VEX_W_TABLE (VEX_W_58_P_0) }, |
c0f3af97 | 3614 | { VEX_LEN_TABLE (VEX_LEN_58_P_1) }, |
9e30b8e0 | 3615 | { VEX_W_TABLE (VEX_W_58_P_2) }, |
c0f3af97 | 3616 | { VEX_LEN_TABLE (VEX_LEN_58_P_3) }, |
7c52e0e8 L |
3617 | }, |
3618 | ||
c0f3af97 | 3619 | /* PREFIX_VEX_59 */ |
7c52e0e8 | 3620 | { |
9e30b8e0 | 3621 | { VEX_W_TABLE (VEX_W_59_P_0) }, |
c0f3af97 | 3622 | { VEX_LEN_TABLE (VEX_LEN_59_P_1) }, |
9e30b8e0 | 3623 | { VEX_W_TABLE (VEX_W_59_P_2) }, |
c0f3af97 | 3624 | { VEX_LEN_TABLE (VEX_LEN_59_P_3) }, |
7c52e0e8 L |
3625 | }, |
3626 | ||
c0f3af97 | 3627 | /* PREFIX_VEX_5A */ |
7c52e0e8 | 3628 | { |
9e30b8e0 | 3629 | { VEX_W_TABLE (VEX_W_5A_P_0) }, |
c0f3af97 L |
3630 | { VEX_LEN_TABLE (VEX_LEN_5A_P_1) }, |
3631 | { "vcvtpd2ps%XY", { XMM, EXx } }, | |
3632 | { VEX_LEN_TABLE (VEX_LEN_5A_P_3) }, | |
7c52e0e8 L |
3633 | }, |
3634 | ||
c0f3af97 | 3635 | /* PREFIX_VEX_5B */ |
7c52e0e8 | 3636 | { |
9e30b8e0 L |
3637 | { VEX_W_TABLE (VEX_W_5B_P_0) }, |
3638 | { VEX_W_TABLE (VEX_W_5B_P_1) }, | |
3639 | { VEX_W_TABLE (VEX_W_5B_P_2) }, | |
7c52e0e8 L |
3640 | }, |
3641 | ||
c0f3af97 | 3642 | /* PREFIX_VEX_5C */ |
7c52e0e8 | 3643 | { |
9e30b8e0 | 3644 | { VEX_W_TABLE (VEX_W_5C_P_0) }, |
c0f3af97 | 3645 | { VEX_LEN_TABLE (VEX_LEN_5C_P_1) }, |
9e30b8e0 | 3646 | { VEX_W_TABLE (VEX_W_5C_P_2) }, |
c0f3af97 | 3647 | { VEX_LEN_TABLE (VEX_LEN_5C_P_3) }, |
7c52e0e8 L |
3648 | }, |
3649 | ||
c0f3af97 | 3650 | /* PREFIX_VEX_5D */ |
7c52e0e8 | 3651 | { |
9e30b8e0 | 3652 | { VEX_W_TABLE (VEX_W_5D_P_0) }, |
c0f3af97 | 3653 | { VEX_LEN_TABLE (VEX_LEN_5D_P_1) }, |
9e30b8e0 | 3654 | { VEX_W_TABLE (VEX_W_5D_P_2) }, |
c0f3af97 | 3655 | { VEX_LEN_TABLE (VEX_LEN_5D_P_3) }, |
7c52e0e8 L |
3656 | }, |
3657 | ||
c0f3af97 | 3658 | /* PREFIX_VEX_5E */ |
7c52e0e8 | 3659 | { |
9e30b8e0 | 3660 | { VEX_W_TABLE (VEX_W_5E_P_0) }, |
c0f3af97 | 3661 | { VEX_LEN_TABLE (VEX_LEN_5E_P_1) }, |
9e30b8e0 | 3662 | { VEX_W_TABLE (VEX_W_5E_P_2) }, |
c0f3af97 | 3663 | { VEX_LEN_TABLE (VEX_LEN_5E_P_3) }, |
7c52e0e8 L |
3664 | }, |
3665 | ||
c0f3af97 | 3666 | /* PREFIX_VEX_5F */ |
7c52e0e8 | 3667 | { |
9e30b8e0 | 3668 | { VEX_W_TABLE (VEX_W_5F_P_0) }, |
c0f3af97 | 3669 | { VEX_LEN_TABLE (VEX_LEN_5F_P_1) }, |
9e30b8e0 | 3670 | { VEX_W_TABLE (VEX_W_5F_P_2) }, |
c0f3af97 | 3671 | { VEX_LEN_TABLE (VEX_LEN_5F_P_3) }, |
7c52e0e8 L |
3672 | }, |
3673 | ||
c0f3af97 | 3674 | /* PREFIX_VEX_60 */ |
7c52e0e8 | 3675 | { |
592d1631 L |
3676 | { Bad_Opcode }, |
3677 | { Bad_Opcode }, | |
c0f3af97 | 3678 | { VEX_LEN_TABLE (VEX_LEN_60_P_2) }, |
7c52e0e8 L |
3679 | }, |
3680 | ||
c0f3af97 | 3681 | /* PREFIX_VEX_61 */ |
7c52e0e8 | 3682 | { |
592d1631 L |
3683 | { Bad_Opcode }, |
3684 | { Bad_Opcode }, | |
c0f3af97 | 3685 | { VEX_LEN_TABLE (VEX_LEN_61_P_2) }, |
7c52e0e8 L |
3686 | }, |
3687 | ||
c0f3af97 | 3688 | /* PREFIX_VEX_62 */ |
7c52e0e8 | 3689 | { |
592d1631 L |
3690 | { Bad_Opcode }, |
3691 | { Bad_Opcode }, | |
c0f3af97 | 3692 | { VEX_LEN_TABLE (VEX_LEN_62_P_2) }, |
7c52e0e8 L |
3693 | }, |
3694 | ||
c0f3af97 | 3695 | /* PREFIX_VEX_63 */ |
7c52e0e8 | 3696 | { |
592d1631 L |
3697 | { Bad_Opcode }, |
3698 | { Bad_Opcode }, | |
c0f3af97 | 3699 | { VEX_LEN_TABLE (VEX_LEN_63_P_2) }, |
7c52e0e8 L |
3700 | }, |
3701 | ||
c0f3af97 | 3702 | /* PREFIX_VEX_64 */ |
7c52e0e8 | 3703 | { |
592d1631 L |
3704 | { Bad_Opcode }, |
3705 | { Bad_Opcode }, | |
c0f3af97 | 3706 | { VEX_LEN_TABLE (VEX_LEN_64_P_2) }, |
7c52e0e8 L |
3707 | }, |
3708 | ||
c0f3af97 | 3709 | /* PREFIX_VEX_65 */ |
7c52e0e8 | 3710 | { |
592d1631 L |
3711 | { Bad_Opcode }, |
3712 | { Bad_Opcode }, | |
c0f3af97 | 3713 | { VEX_LEN_TABLE (VEX_LEN_65_P_2) }, |
7c52e0e8 L |
3714 | }, |
3715 | ||
c0f3af97 | 3716 | /* PREFIX_VEX_66 */ |
7c52e0e8 | 3717 | { |
592d1631 L |
3718 | { Bad_Opcode }, |
3719 | { Bad_Opcode }, | |
c0f3af97 | 3720 | { VEX_LEN_TABLE (VEX_LEN_66_P_2) }, |
7c52e0e8 | 3721 | }, |
6439fc28 | 3722 | |
c0f3af97 | 3723 | /* PREFIX_VEX_67 */ |
331d2d0d | 3724 | { |
592d1631 L |
3725 | { Bad_Opcode }, |
3726 | { Bad_Opcode }, | |
c0f3af97 | 3727 | { VEX_LEN_TABLE (VEX_LEN_67_P_2) }, |
c0f3af97 L |
3728 | }, |
3729 | ||
3730 | /* PREFIX_VEX_68 */ | |
3731 | { | |
592d1631 L |
3732 | { Bad_Opcode }, |
3733 | { Bad_Opcode }, | |
c0f3af97 | 3734 | { VEX_LEN_TABLE (VEX_LEN_68_P_2) }, |
c0f3af97 L |
3735 | }, |
3736 | ||
3737 | /* PREFIX_VEX_69 */ | |
3738 | { | |
592d1631 L |
3739 | { Bad_Opcode }, |
3740 | { Bad_Opcode }, | |
c0f3af97 | 3741 | { VEX_LEN_TABLE (VEX_LEN_69_P_2) }, |
c0f3af97 L |
3742 | }, |
3743 | ||
3744 | /* PREFIX_VEX_6A */ | |
3745 | { | |
592d1631 L |
3746 | { Bad_Opcode }, |
3747 | { Bad_Opcode }, | |
c0f3af97 | 3748 | { VEX_LEN_TABLE (VEX_LEN_6A_P_2) }, |
c0f3af97 L |
3749 | }, |
3750 | ||
3751 | /* PREFIX_VEX_6B */ | |
3752 | { | |
592d1631 L |
3753 | { Bad_Opcode }, |
3754 | { Bad_Opcode }, | |
c0f3af97 | 3755 | { VEX_LEN_TABLE (VEX_LEN_6B_P_2) }, |
c0f3af97 L |
3756 | }, |
3757 | ||
3758 | /* PREFIX_VEX_6C */ | |
3759 | { | |
592d1631 L |
3760 | { Bad_Opcode }, |
3761 | { Bad_Opcode }, | |
c0f3af97 | 3762 | { VEX_LEN_TABLE (VEX_LEN_6C_P_2) }, |
c0f3af97 L |
3763 | }, |
3764 | ||
3765 | /* PREFIX_VEX_6D */ | |
3766 | { | |
592d1631 L |
3767 | { Bad_Opcode }, |
3768 | { Bad_Opcode }, | |
c0f3af97 | 3769 | { VEX_LEN_TABLE (VEX_LEN_6D_P_2) }, |
c0f3af97 L |
3770 | }, |
3771 | ||
3772 | /* PREFIX_VEX_6E */ | |
3773 | { | |
592d1631 L |
3774 | { Bad_Opcode }, |
3775 | { Bad_Opcode }, | |
c0f3af97 | 3776 | { VEX_LEN_TABLE (VEX_LEN_6E_P_2) }, |
c0f3af97 L |
3777 | }, |
3778 | ||
3779 | /* PREFIX_VEX_6F */ | |
3780 | { | |
592d1631 | 3781 | { Bad_Opcode }, |
9e30b8e0 L |
3782 | { VEX_W_TABLE (VEX_W_6F_P_1) }, |
3783 | { VEX_W_TABLE (VEX_W_6F_P_2) }, | |
c0f3af97 L |
3784 | }, |
3785 | ||
3786 | /* PREFIX_VEX_70 */ | |
3787 | { | |
592d1631 | 3788 | { Bad_Opcode }, |
c0f3af97 L |
3789 | { VEX_LEN_TABLE (VEX_LEN_70_P_1) }, |
3790 | { VEX_LEN_TABLE (VEX_LEN_70_P_2) }, | |
3791 | { VEX_LEN_TABLE (VEX_LEN_70_P_3) }, | |
3792 | }, | |
3793 | ||
3794 | /* PREFIX_VEX_71_REG_2 */ | |
3795 | { | |
592d1631 L |
3796 | { Bad_Opcode }, |
3797 | { Bad_Opcode }, | |
c0f3af97 | 3798 | { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) }, |
c0f3af97 L |
3799 | }, |
3800 | ||
3801 | /* PREFIX_VEX_71_REG_4 */ | |
3802 | { | |
592d1631 L |
3803 | { Bad_Opcode }, |
3804 | { Bad_Opcode }, | |
c0f3af97 | 3805 | { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) }, |
c0f3af97 L |
3806 | }, |
3807 | ||
3808 | /* PREFIX_VEX_71_REG_6 */ | |
3809 | { | |
592d1631 L |
3810 | { Bad_Opcode }, |
3811 | { Bad_Opcode }, | |
c0f3af97 | 3812 | { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) }, |
c0f3af97 L |
3813 | }, |
3814 | ||
3815 | /* PREFIX_VEX_72_REG_2 */ | |
3816 | { | |
592d1631 L |
3817 | { Bad_Opcode }, |
3818 | { Bad_Opcode }, | |
c0f3af97 | 3819 | { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) }, |
c0f3af97 L |
3820 | }, |
3821 | ||
3822 | /* PREFIX_VEX_72_REG_4 */ | |
3823 | { | |
592d1631 L |
3824 | { Bad_Opcode }, |
3825 | { Bad_Opcode }, | |
c0f3af97 | 3826 | { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) }, |
c0f3af97 L |
3827 | }, |
3828 | ||
3829 | /* PREFIX_VEX_72_REG_6 */ | |
3830 | { | |
592d1631 L |
3831 | { Bad_Opcode }, |
3832 | { Bad_Opcode }, | |
c0f3af97 | 3833 | { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) }, |
c0f3af97 L |
3834 | }, |
3835 | ||
3836 | /* PREFIX_VEX_73_REG_2 */ | |
3837 | { | |
592d1631 L |
3838 | { Bad_Opcode }, |
3839 | { Bad_Opcode }, | |
c0f3af97 | 3840 | { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) }, |
c0f3af97 L |
3841 | }, |
3842 | ||
3843 | /* PREFIX_VEX_73_REG_3 */ | |
3844 | { | |
592d1631 L |
3845 | { Bad_Opcode }, |
3846 | { Bad_Opcode }, | |
c0f3af97 | 3847 | { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) }, |
c0f3af97 L |
3848 | }, |
3849 | ||
3850 | /* PREFIX_VEX_73_REG_6 */ | |
3851 | { | |
592d1631 L |
3852 | { Bad_Opcode }, |
3853 | { Bad_Opcode }, | |
c0f3af97 | 3854 | { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) }, |
c0f3af97 L |
3855 | }, |
3856 | ||
3857 | /* PREFIX_VEX_73_REG_7 */ | |
3858 | { | |
592d1631 L |
3859 | { Bad_Opcode }, |
3860 | { Bad_Opcode }, | |
c0f3af97 | 3861 | { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) }, |
c0f3af97 L |
3862 | }, |
3863 | ||
3864 | /* PREFIX_VEX_74 */ | |
3865 | { | |
592d1631 L |
3866 | { Bad_Opcode }, |
3867 | { Bad_Opcode }, | |
c0f3af97 | 3868 | { VEX_LEN_TABLE (VEX_LEN_74_P_2) }, |
c0f3af97 L |
3869 | }, |
3870 | ||
3871 | /* PREFIX_VEX_75 */ | |
3872 | { | |
592d1631 L |
3873 | { Bad_Opcode }, |
3874 | { Bad_Opcode }, | |
c0f3af97 | 3875 | { VEX_LEN_TABLE (VEX_LEN_75_P_2) }, |
c0f3af97 L |
3876 | }, |
3877 | ||
3878 | /* PREFIX_VEX_76 */ | |
3879 | { | |
592d1631 L |
3880 | { Bad_Opcode }, |
3881 | { Bad_Opcode }, | |
c0f3af97 | 3882 | { VEX_LEN_TABLE (VEX_LEN_76_P_2) }, |
c0f3af97 L |
3883 | }, |
3884 | ||
3885 | /* PREFIX_VEX_77 */ | |
3886 | { | |
9e30b8e0 | 3887 | { VEX_W_TABLE (VEX_W_77_P_0) }, |
c0f3af97 L |
3888 | }, |
3889 | ||
3890 | /* PREFIX_VEX_7C */ | |
3891 | { | |
592d1631 L |
3892 | { Bad_Opcode }, |
3893 | { Bad_Opcode }, | |
9e30b8e0 L |
3894 | { VEX_W_TABLE (VEX_W_7C_P_2) }, |
3895 | { VEX_W_TABLE (VEX_W_7C_P_3) }, | |
c0f3af97 L |
3896 | }, |
3897 | ||
3898 | /* PREFIX_VEX_7D */ | |
3899 | { | |
592d1631 L |
3900 | { Bad_Opcode }, |
3901 | { Bad_Opcode }, | |
9e30b8e0 L |
3902 | { VEX_W_TABLE (VEX_W_7D_P_2) }, |
3903 | { VEX_W_TABLE (VEX_W_7D_P_3) }, | |
c0f3af97 L |
3904 | }, |
3905 | ||
3906 | /* PREFIX_VEX_7E */ | |
3907 | { | |
592d1631 | 3908 | { Bad_Opcode }, |
c0f3af97 L |
3909 | { VEX_LEN_TABLE (VEX_LEN_7E_P_1) }, |
3910 | { VEX_LEN_TABLE (VEX_LEN_7E_P_2) }, | |
c0f3af97 L |
3911 | }, |
3912 | ||
3913 | /* PREFIX_VEX_7F */ | |
3914 | { | |
592d1631 | 3915 | { Bad_Opcode }, |
9e30b8e0 L |
3916 | { VEX_W_TABLE (VEX_W_7F_P_1) }, |
3917 | { VEX_W_TABLE (VEX_W_7F_P_2) }, | |
c0f3af97 L |
3918 | }, |
3919 | ||
3920 | /* PREFIX_VEX_C2 */ | |
3921 | { | |
9e30b8e0 | 3922 | { VEX_W_TABLE (VEX_W_C2_P_0) }, |
c0f3af97 | 3923 | { VEX_LEN_TABLE (VEX_LEN_C2_P_1) }, |
9e30b8e0 | 3924 | { VEX_W_TABLE (VEX_W_C2_P_2) }, |
c0f3af97 L |
3925 | { VEX_LEN_TABLE (VEX_LEN_C2_P_3) }, |
3926 | }, | |
3927 | ||
3928 | /* PREFIX_VEX_C4 */ | |
3929 | { | |
592d1631 L |
3930 | { Bad_Opcode }, |
3931 | { Bad_Opcode }, | |
c0f3af97 | 3932 | { VEX_LEN_TABLE (VEX_LEN_C4_P_2) }, |
c0f3af97 L |
3933 | }, |
3934 | ||
3935 | /* PREFIX_VEX_C5 */ | |
3936 | { | |
592d1631 L |
3937 | { Bad_Opcode }, |
3938 | { Bad_Opcode }, | |
c0f3af97 | 3939 | { VEX_LEN_TABLE (VEX_LEN_C5_P_2) }, |
c0f3af97 L |
3940 | }, |
3941 | ||
3942 | /* PREFIX_VEX_D0 */ | |
3943 | { | |
592d1631 L |
3944 | { Bad_Opcode }, |
3945 | { Bad_Opcode }, | |
9e30b8e0 L |
3946 | { VEX_W_TABLE (VEX_W_D0_P_2) }, |
3947 | { VEX_W_TABLE (VEX_W_D0_P_3) }, | |
c0f3af97 L |
3948 | }, |
3949 | ||
3950 | /* PREFIX_VEX_D1 */ | |
3951 | { | |
592d1631 L |
3952 | { Bad_Opcode }, |
3953 | { Bad_Opcode }, | |
c0f3af97 | 3954 | { VEX_LEN_TABLE (VEX_LEN_D1_P_2) }, |
c0f3af97 L |
3955 | }, |
3956 | ||
3957 | /* PREFIX_VEX_D2 */ | |
3958 | { | |
592d1631 L |
3959 | { Bad_Opcode }, |
3960 | { Bad_Opcode }, | |
c0f3af97 | 3961 | { VEX_LEN_TABLE (VEX_LEN_D2_P_2) }, |
c0f3af97 L |
3962 | }, |
3963 | ||
3964 | /* PREFIX_VEX_D3 */ | |
3965 | { | |
592d1631 L |
3966 | { Bad_Opcode }, |
3967 | { Bad_Opcode }, | |
c0f3af97 | 3968 | { VEX_LEN_TABLE (VEX_LEN_D3_P_2) }, |
c0f3af97 L |
3969 | }, |
3970 | ||
3971 | /* PREFIX_VEX_D4 */ | |
3972 | { | |
592d1631 L |
3973 | { Bad_Opcode }, |
3974 | { Bad_Opcode }, | |
c0f3af97 | 3975 | { VEX_LEN_TABLE (VEX_LEN_D4_P_2) }, |
c0f3af97 L |
3976 | }, |
3977 | ||
3978 | /* PREFIX_VEX_D5 */ | |
3979 | { | |
592d1631 L |
3980 | { Bad_Opcode }, |
3981 | { Bad_Opcode }, | |
c0f3af97 | 3982 | { VEX_LEN_TABLE (VEX_LEN_D5_P_2) }, |
c0f3af97 L |
3983 | }, |
3984 | ||
3985 | /* PREFIX_VEX_D6 */ | |
3986 | { | |
592d1631 L |
3987 | { Bad_Opcode }, |
3988 | { Bad_Opcode }, | |
c0f3af97 | 3989 | { VEX_LEN_TABLE (VEX_LEN_D6_P_2) }, |
c0f3af97 L |
3990 | }, |
3991 | ||
3992 | /* PREFIX_VEX_D7 */ | |
3993 | { | |
592d1631 L |
3994 | { Bad_Opcode }, |
3995 | { Bad_Opcode }, | |
c0f3af97 | 3996 | { MOD_TABLE (MOD_VEX_D7_PREFIX_2) }, |
c0f3af97 L |
3997 | }, |
3998 | ||
3999 | /* PREFIX_VEX_D8 */ | |
4000 | { | |
592d1631 L |
4001 | { Bad_Opcode }, |
4002 | { Bad_Opcode }, | |
c0f3af97 | 4003 | { VEX_LEN_TABLE (VEX_LEN_D8_P_2) }, |
c0f3af97 L |
4004 | }, |
4005 | ||
4006 | /* PREFIX_VEX_D9 */ | |
4007 | { | |
592d1631 L |
4008 | { Bad_Opcode }, |
4009 | { Bad_Opcode }, | |
c0f3af97 | 4010 | { VEX_LEN_TABLE (VEX_LEN_D9_P_2) }, |
c0f3af97 L |
4011 | }, |
4012 | ||
4013 | /* PREFIX_VEX_DA */ | |
4014 | { | |
592d1631 L |
4015 | { Bad_Opcode }, |
4016 | { Bad_Opcode }, | |
c0f3af97 | 4017 | { VEX_LEN_TABLE (VEX_LEN_DA_P_2) }, |
c0f3af97 L |
4018 | }, |
4019 | ||
4020 | /* PREFIX_VEX_DB */ | |
4021 | { | |
592d1631 L |
4022 | { Bad_Opcode }, |
4023 | { Bad_Opcode }, | |
c0f3af97 | 4024 | { VEX_LEN_TABLE (VEX_LEN_DB_P_2) }, |
c0f3af97 L |
4025 | }, |
4026 | ||
4027 | /* PREFIX_VEX_DC */ | |
4028 | { | |
592d1631 L |
4029 | { Bad_Opcode }, |
4030 | { Bad_Opcode }, | |
c0f3af97 | 4031 | { VEX_LEN_TABLE (VEX_LEN_DC_P_2) }, |
c0f3af97 L |
4032 | }, |
4033 | ||
4034 | /* PREFIX_VEX_DD */ | |
4035 | { | |
592d1631 L |
4036 | { Bad_Opcode }, |
4037 | { Bad_Opcode }, | |
c0f3af97 | 4038 | { VEX_LEN_TABLE (VEX_LEN_DD_P_2) }, |
c0f3af97 L |
4039 | }, |
4040 | ||
4041 | /* PREFIX_VEX_DE */ | |
4042 | { | |
592d1631 L |
4043 | { Bad_Opcode }, |
4044 | { Bad_Opcode }, | |
c0f3af97 | 4045 | { VEX_LEN_TABLE (VEX_LEN_DE_P_2) }, |
c0f3af97 L |
4046 | }, |
4047 | ||
4048 | /* PREFIX_VEX_DF */ | |
4049 | { | |
592d1631 L |
4050 | { Bad_Opcode }, |
4051 | { Bad_Opcode }, | |
c0f3af97 | 4052 | { VEX_LEN_TABLE (VEX_LEN_DF_P_2) }, |
c0f3af97 L |
4053 | }, |
4054 | ||
4055 | /* PREFIX_VEX_E0 */ | |
4056 | { | |
592d1631 L |
4057 | { Bad_Opcode }, |
4058 | { Bad_Opcode }, | |
c0f3af97 | 4059 | { VEX_LEN_TABLE (VEX_LEN_E0_P_2) }, |
c0f3af97 L |
4060 | }, |
4061 | ||
4062 | /* PREFIX_VEX_E1 */ | |
4063 | { | |
592d1631 L |
4064 | { Bad_Opcode }, |
4065 | { Bad_Opcode }, | |
c0f3af97 | 4066 | { VEX_LEN_TABLE (VEX_LEN_E1_P_2) }, |
c0f3af97 L |
4067 | }, |
4068 | ||
4069 | /* PREFIX_VEX_E2 */ | |
4070 | { | |
592d1631 L |
4071 | { Bad_Opcode }, |
4072 | { Bad_Opcode }, | |
c0f3af97 | 4073 | { VEX_LEN_TABLE (VEX_LEN_E2_P_2) }, |
c0f3af97 L |
4074 | }, |
4075 | ||
4076 | /* PREFIX_VEX_E3 */ | |
4077 | { | |
592d1631 L |
4078 | { Bad_Opcode }, |
4079 | { Bad_Opcode }, | |
c0f3af97 | 4080 | { VEX_LEN_TABLE (VEX_LEN_E3_P_2) }, |
c0f3af97 L |
4081 | }, |
4082 | ||
4083 | /* PREFIX_VEX_E4 */ | |
4084 | { | |
592d1631 L |
4085 | { Bad_Opcode }, |
4086 | { Bad_Opcode }, | |
c0f3af97 | 4087 | { VEX_LEN_TABLE (VEX_LEN_E4_P_2) }, |
c0f3af97 L |
4088 | }, |
4089 | ||
4090 | /* PREFIX_VEX_E5 */ | |
4091 | { | |
592d1631 L |
4092 | { Bad_Opcode }, |
4093 | { Bad_Opcode }, | |
c0f3af97 | 4094 | { VEX_LEN_TABLE (VEX_LEN_E5_P_2) }, |
c0f3af97 L |
4095 | }, |
4096 | ||
4097 | /* PREFIX_VEX_E6 */ | |
4098 | { | |
592d1631 | 4099 | { Bad_Opcode }, |
9e30b8e0 L |
4100 | { VEX_W_TABLE (VEX_W_E6_P_1) }, |
4101 | { VEX_W_TABLE (VEX_W_E6_P_2) }, | |
4102 | { VEX_W_TABLE (VEX_W_E6_P_3) }, | |
c0f3af97 L |
4103 | }, |
4104 | ||
4105 | /* PREFIX_VEX_E7 */ | |
4106 | { | |
592d1631 L |
4107 | { Bad_Opcode }, |
4108 | { Bad_Opcode }, | |
c0f3af97 | 4109 | { MOD_TABLE (MOD_VEX_E7_PREFIX_2) }, |
c0f3af97 L |
4110 | }, |
4111 | ||
4112 | /* PREFIX_VEX_E8 */ | |
4113 | { | |
592d1631 L |
4114 | { Bad_Opcode }, |
4115 | { Bad_Opcode }, | |
c0f3af97 | 4116 | { VEX_LEN_TABLE (VEX_LEN_E8_P_2) }, |
c0f3af97 L |
4117 | }, |
4118 | ||
4119 | /* PREFIX_VEX_E9 */ | |
4120 | { | |
592d1631 L |
4121 | { Bad_Opcode }, |
4122 | { Bad_Opcode }, | |
c0f3af97 | 4123 | { VEX_LEN_TABLE (VEX_LEN_E9_P_2) }, |
c0f3af97 L |
4124 | }, |
4125 | ||
4126 | /* PREFIX_VEX_EA */ | |
4127 | { | |
592d1631 L |
4128 | { Bad_Opcode }, |
4129 | { Bad_Opcode }, | |
c0f3af97 | 4130 | { VEX_LEN_TABLE (VEX_LEN_EA_P_2) }, |
c0f3af97 L |
4131 | }, |
4132 | ||
4133 | /* PREFIX_VEX_EB */ | |
4134 | { | |
592d1631 L |
4135 | { Bad_Opcode }, |
4136 | { Bad_Opcode }, | |
c0f3af97 | 4137 | { VEX_LEN_TABLE (VEX_LEN_EB_P_2) }, |
c0f3af97 L |
4138 | }, |
4139 | ||
4140 | /* PREFIX_VEX_EC */ | |
4141 | { | |
592d1631 L |
4142 | { Bad_Opcode }, |
4143 | { Bad_Opcode }, | |
c0f3af97 | 4144 | { VEX_LEN_TABLE (VEX_LEN_EC_P_2) }, |
c0f3af97 L |
4145 | }, |
4146 | ||
4147 | /* PREFIX_VEX_ED */ | |
4148 | { | |
592d1631 L |
4149 | { Bad_Opcode }, |
4150 | { Bad_Opcode }, | |
c0f3af97 | 4151 | { VEX_LEN_TABLE (VEX_LEN_ED_P_2) }, |
c0f3af97 L |
4152 | }, |
4153 | ||
4154 | /* PREFIX_VEX_EE */ | |
4155 | { | |
592d1631 L |
4156 | { Bad_Opcode }, |
4157 | { Bad_Opcode }, | |
c0f3af97 | 4158 | { VEX_LEN_TABLE (VEX_LEN_EE_P_2) }, |
c0f3af97 L |
4159 | }, |
4160 | ||
4161 | /* PREFIX_VEX_EF */ | |
4162 | { | |
592d1631 L |
4163 | { Bad_Opcode }, |
4164 | { Bad_Opcode }, | |
c0f3af97 | 4165 | { VEX_LEN_TABLE (VEX_LEN_EF_P_2) }, |
c0f3af97 L |
4166 | }, |
4167 | ||
4168 | /* PREFIX_VEX_F0 */ | |
4169 | { | |
592d1631 L |
4170 | { Bad_Opcode }, |
4171 | { Bad_Opcode }, | |
4172 | { Bad_Opcode }, | |
c0f3af97 L |
4173 | { MOD_TABLE (MOD_VEX_F0_PREFIX_3) }, |
4174 | }, | |
4175 | ||
4176 | /* PREFIX_VEX_F1 */ | |
4177 | { | |
592d1631 L |
4178 | { Bad_Opcode }, |
4179 | { Bad_Opcode }, | |
c0f3af97 | 4180 | { VEX_LEN_TABLE (VEX_LEN_F1_P_2) }, |
c0f3af97 L |
4181 | }, |
4182 | ||
4183 | /* PREFIX_VEX_F2 */ | |
4184 | { | |
592d1631 L |
4185 | { Bad_Opcode }, |
4186 | { Bad_Opcode }, | |
c0f3af97 | 4187 | { VEX_LEN_TABLE (VEX_LEN_F2_P_2) }, |
c0f3af97 L |
4188 | }, |
4189 | ||
4190 | /* PREFIX_VEX_F3 */ | |
4191 | { | |
592d1631 L |
4192 | { Bad_Opcode }, |
4193 | { Bad_Opcode }, | |
c0f3af97 | 4194 | { VEX_LEN_TABLE (VEX_LEN_F3_P_2) }, |
c0f3af97 L |
4195 | }, |
4196 | ||
4197 | /* PREFIX_VEX_F4 */ | |
4198 | { | |
592d1631 L |
4199 | { Bad_Opcode }, |
4200 | { Bad_Opcode }, | |
c0f3af97 | 4201 | { VEX_LEN_TABLE (VEX_LEN_F4_P_2) }, |
c0f3af97 L |
4202 | }, |
4203 | ||
4204 | /* PREFIX_VEX_F5 */ | |
4205 | { | |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
c0f3af97 | 4208 | { VEX_LEN_TABLE (VEX_LEN_F5_P_2) }, |
c0f3af97 L |
4209 | }, |
4210 | ||
4211 | /* PREFIX_VEX_F6 */ | |
4212 | { | |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
c0f3af97 | 4215 | { VEX_LEN_TABLE (VEX_LEN_F6_P_2) }, |
c0f3af97 L |
4216 | }, |
4217 | ||
4218 | /* PREFIX_VEX_F7 */ | |
4219 | { | |
592d1631 L |
4220 | { Bad_Opcode }, |
4221 | { Bad_Opcode }, | |
c0f3af97 | 4222 | { VEX_LEN_TABLE (VEX_LEN_F7_P_2) }, |
c0f3af97 L |
4223 | }, |
4224 | ||
4225 | /* PREFIX_VEX_F8 */ | |
4226 | { | |
592d1631 L |
4227 | { Bad_Opcode }, |
4228 | { Bad_Opcode }, | |
c0f3af97 | 4229 | { VEX_LEN_TABLE (VEX_LEN_F8_P_2) }, |
c0f3af97 L |
4230 | }, |
4231 | ||
4232 | /* PREFIX_VEX_F9 */ | |
4233 | { | |
592d1631 L |
4234 | { Bad_Opcode }, |
4235 | { Bad_Opcode }, | |
c0f3af97 | 4236 | { VEX_LEN_TABLE (VEX_LEN_F9_P_2) }, |
c0f3af97 L |
4237 | }, |
4238 | ||
4239 | /* PREFIX_VEX_FA */ | |
4240 | { | |
592d1631 L |
4241 | { Bad_Opcode }, |
4242 | { Bad_Opcode }, | |
c0f3af97 | 4243 | { VEX_LEN_TABLE (VEX_LEN_FA_P_2) }, |
c0f3af97 L |
4244 | }, |
4245 | ||
4246 | /* PREFIX_VEX_FB */ | |
4247 | { | |
592d1631 L |
4248 | { Bad_Opcode }, |
4249 | { Bad_Opcode }, | |
c0f3af97 | 4250 | { VEX_LEN_TABLE (VEX_LEN_FB_P_2) }, |
c0f3af97 L |
4251 | }, |
4252 | ||
4253 | /* PREFIX_VEX_FC */ | |
4254 | { | |
592d1631 L |
4255 | { Bad_Opcode }, |
4256 | { Bad_Opcode }, | |
c0f3af97 | 4257 | { VEX_LEN_TABLE (VEX_LEN_FC_P_2) }, |
c0f3af97 L |
4258 | }, |
4259 | ||
4260 | /* PREFIX_VEX_FD */ | |
4261 | { | |
592d1631 L |
4262 | { Bad_Opcode }, |
4263 | { Bad_Opcode }, | |
c0f3af97 | 4264 | { VEX_LEN_TABLE (VEX_LEN_FD_P_2) }, |
c0f3af97 L |
4265 | }, |
4266 | ||
4267 | /* PREFIX_VEX_FE */ | |
4268 | { | |
592d1631 L |
4269 | { Bad_Opcode }, |
4270 | { Bad_Opcode }, | |
c0f3af97 | 4271 | { VEX_LEN_TABLE (VEX_LEN_FE_P_2) }, |
c0f3af97 L |
4272 | }, |
4273 | ||
4274 | /* PREFIX_VEX_3800 */ | |
4275 | { | |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
c0f3af97 | 4278 | { VEX_LEN_TABLE (VEX_LEN_3800_P_2) }, |
c0f3af97 L |
4279 | }, |
4280 | ||
4281 | /* PREFIX_VEX_3801 */ | |
4282 | { | |
592d1631 L |
4283 | { Bad_Opcode }, |
4284 | { Bad_Opcode }, | |
c0f3af97 | 4285 | { VEX_LEN_TABLE (VEX_LEN_3801_P_2) }, |
c0f3af97 L |
4286 | }, |
4287 | ||
4288 | /* PREFIX_VEX_3802 */ | |
4289 | { | |
592d1631 L |
4290 | { Bad_Opcode }, |
4291 | { Bad_Opcode }, | |
c0f3af97 | 4292 | { VEX_LEN_TABLE (VEX_LEN_3802_P_2) }, |
c0f3af97 L |
4293 | }, |
4294 | ||
4295 | /* PREFIX_VEX_3803 */ | |
4296 | { | |
592d1631 L |
4297 | { Bad_Opcode }, |
4298 | { Bad_Opcode }, | |
c0f3af97 | 4299 | { VEX_LEN_TABLE (VEX_LEN_3803_P_2) }, |
c0f3af97 L |
4300 | }, |
4301 | ||
4302 | /* PREFIX_VEX_3804 */ | |
4303 | { | |
592d1631 L |
4304 | { Bad_Opcode }, |
4305 | { Bad_Opcode }, | |
c0f3af97 | 4306 | { VEX_LEN_TABLE (VEX_LEN_3804_P_2) }, |
c0f3af97 L |
4307 | }, |
4308 | ||
4309 | /* PREFIX_VEX_3805 */ | |
4310 | { | |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
c0f3af97 | 4313 | { VEX_LEN_TABLE (VEX_LEN_3805_P_2) }, |
c0f3af97 L |
4314 | }, |
4315 | ||
4316 | /* PREFIX_VEX_3806 */ | |
4317 | { | |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
c0f3af97 | 4320 | { VEX_LEN_TABLE (VEX_LEN_3806_P_2) }, |
c0f3af97 L |
4321 | }, |
4322 | ||
4323 | /* PREFIX_VEX_3807 */ | |
4324 | { | |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
c0f3af97 | 4327 | { VEX_LEN_TABLE (VEX_LEN_3807_P_2) }, |
c0f3af97 L |
4328 | }, |
4329 | ||
4330 | /* PREFIX_VEX_3808 */ | |
4331 | { | |
592d1631 L |
4332 | { Bad_Opcode }, |
4333 | { Bad_Opcode }, | |
c0f3af97 | 4334 | { VEX_LEN_TABLE (VEX_LEN_3808_P_2) }, |
c0f3af97 L |
4335 | }, |
4336 | ||
4337 | /* PREFIX_VEX_3809 */ | |
4338 | { | |
592d1631 L |
4339 | { Bad_Opcode }, |
4340 | { Bad_Opcode }, | |
c0f3af97 | 4341 | { VEX_LEN_TABLE (VEX_LEN_3809_P_2) }, |
c0f3af97 L |
4342 | }, |
4343 | ||
4344 | /* PREFIX_VEX_380A */ | |
4345 | { | |
592d1631 L |
4346 | { Bad_Opcode }, |
4347 | { Bad_Opcode }, | |
c0f3af97 | 4348 | { VEX_LEN_TABLE (VEX_LEN_380A_P_2) }, |
c0f3af97 L |
4349 | }, |
4350 | ||
4351 | /* PREFIX_VEX_380B */ | |
4352 | { | |
592d1631 L |
4353 | { Bad_Opcode }, |
4354 | { Bad_Opcode }, | |
c0f3af97 | 4355 | { VEX_LEN_TABLE (VEX_LEN_380B_P_2) }, |
c0f3af97 L |
4356 | }, |
4357 | ||
4358 | /* PREFIX_VEX_380C */ | |
4359 | { | |
592d1631 L |
4360 | { Bad_Opcode }, |
4361 | { Bad_Opcode }, | |
9e30b8e0 | 4362 | { VEX_W_TABLE (VEX_W_380C_P_2) }, |
c0f3af97 L |
4363 | }, |
4364 | ||
4365 | /* PREFIX_VEX_380D */ | |
4366 | { | |
592d1631 L |
4367 | { Bad_Opcode }, |
4368 | { Bad_Opcode }, | |
9e30b8e0 | 4369 | { VEX_W_TABLE (VEX_W_380D_P_2) }, |
c0f3af97 L |
4370 | }, |
4371 | ||
4372 | /* PREFIX_VEX_380E */ | |
4373 | { | |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
9e30b8e0 | 4376 | { VEX_W_TABLE (VEX_W_380E_P_2) }, |
c0f3af97 L |
4377 | }, |
4378 | ||
4379 | /* PREFIX_VEX_380F */ | |
4380 | { | |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
9e30b8e0 | 4383 | { VEX_W_TABLE (VEX_W_380F_P_2) }, |
c0f3af97 L |
4384 | }, |
4385 | ||
4386 | /* PREFIX_VEX_3817 */ | |
4387 | { | |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
9e30b8e0 | 4390 | { VEX_W_TABLE (VEX_W_3817_P_2) }, |
c0f3af97 L |
4391 | }, |
4392 | ||
4393 | /* PREFIX_VEX_3818 */ | |
4394 | { | |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
c0f3af97 | 4397 | { MOD_TABLE (MOD_VEX_3818_PREFIX_2) }, |
c0f3af97 L |
4398 | }, |
4399 | ||
4400 | /* PREFIX_VEX_3819 */ | |
4401 | { | |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
c0f3af97 | 4404 | { MOD_TABLE (MOD_VEX_3819_PREFIX_2) }, |
c0f3af97 L |
4405 | }, |
4406 | ||
4407 | /* PREFIX_VEX_381A */ | |
4408 | { | |
592d1631 L |
4409 | { Bad_Opcode }, |
4410 | { Bad_Opcode }, | |
c0f3af97 | 4411 | { MOD_TABLE (MOD_VEX_381A_PREFIX_2) }, |
c0f3af97 L |
4412 | }, |
4413 | ||
4414 | /* PREFIX_VEX_381C */ | |
4415 | { | |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
c0f3af97 | 4418 | { VEX_LEN_TABLE (VEX_LEN_381C_P_2) }, |
c0f3af97 L |
4419 | }, |
4420 | ||
4421 | /* PREFIX_VEX_381D */ | |
4422 | { | |
592d1631 L |
4423 | { Bad_Opcode }, |
4424 | { Bad_Opcode }, | |
c0f3af97 | 4425 | { VEX_LEN_TABLE (VEX_LEN_381D_P_2) }, |
c0f3af97 L |
4426 | }, |
4427 | ||
4428 | /* PREFIX_VEX_381E */ | |
4429 | { | |
592d1631 L |
4430 | { Bad_Opcode }, |
4431 | { Bad_Opcode }, | |
c0f3af97 | 4432 | { VEX_LEN_TABLE (VEX_LEN_381E_P_2) }, |
c0f3af97 L |
4433 | }, |
4434 | ||
4435 | /* PREFIX_VEX_3820 */ | |
4436 | { | |
592d1631 L |
4437 | { Bad_Opcode }, |
4438 | { Bad_Opcode }, | |
c0f3af97 | 4439 | { VEX_LEN_TABLE (VEX_LEN_3820_P_2) }, |
c0f3af97 L |
4440 | }, |
4441 | ||
4442 | /* PREFIX_VEX_3821 */ | |
4443 | { | |
592d1631 L |
4444 | { Bad_Opcode }, |
4445 | { Bad_Opcode }, | |
c0f3af97 | 4446 | { VEX_LEN_TABLE (VEX_LEN_3821_P_2) }, |
c0f3af97 L |
4447 | }, |
4448 | ||
4449 | /* PREFIX_VEX_3822 */ | |
4450 | { | |
592d1631 L |
4451 | { Bad_Opcode }, |
4452 | { Bad_Opcode }, | |
c0f3af97 | 4453 | { VEX_LEN_TABLE (VEX_LEN_3822_P_2) }, |
c0f3af97 L |
4454 | }, |
4455 | ||
4456 | /* PREFIX_VEX_3823 */ | |
4457 | { | |
592d1631 L |
4458 | { Bad_Opcode }, |
4459 | { Bad_Opcode }, | |
c0f3af97 | 4460 | { VEX_LEN_TABLE (VEX_LEN_3823_P_2) }, |
c0f3af97 L |
4461 | }, |
4462 | ||
4463 | /* PREFIX_VEX_3824 */ | |
4464 | { | |
592d1631 L |
4465 | { Bad_Opcode }, |
4466 | { Bad_Opcode }, | |
c0f3af97 | 4467 | { VEX_LEN_TABLE (VEX_LEN_3824_P_2) }, |
c0f3af97 L |
4468 | }, |
4469 | ||
4470 | /* PREFIX_VEX_3825 */ | |
4471 | { | |
592d1631 L |
4472 | { Bad_Opcode }, |
4473 | { Bad_Opcode }, | |
c0f3af97 | 4474 | { VEX_LEN_TABLE (VEX_LEN_3825_P_2) }, |
c0f3af97 L |
4475 | }, |
4476 | ||
4477 | /* PREFIX_VEX_3828 */ | |
4478 | { | |
592d1631 L |
4479 | { Bad_Opcode }, |
4480 | { Bad_Opcode }, | |
c0f3af97 | 4481 | { VEX_LEN_TABLE (VEX_LEN_3828_P_2) }, |
c0f3af97 L |
4482 | }, |
4483 | ||
4484 | /* PREFIX_VEX_3829 */ | |
4485 | { | |
592d1631 L |
4486 | { Bad_Opcode }, |
4487 | { Bad_Opcode }, | |
c0f3af97 | 4488 | { VEX_LEN_TABLE (VEX_LEN_3829_P_2) }, |
c0f3af97 L |
4489 | }, |
4490 | ||
4491 | /* PREFIX_VEX_382A */ | |
4492 | { | |
592d1631 L |
4493 | { Bad_Opcode }, |
4494 | { Bad_Opcode }, | |
c0f3af97 | 4495 | { MOD_TABLE (MOD_VEX_382A_PREFIX_2) }, |
c0f3af97 L |
4496 | }, |
4497 | ||
4498 | /* PREFIX_VEX_382B */ | |
4499 | { | |
592d1631 L |
4500 | { Bad_Opcode }, |
4501 | { Bad_Opcode }, | |
c0f3af97 | 4502 | { VEX_LEN_TABLE (VEX_LEN_382B_P_2) }, |
c0f3af97 L |
4503 | }, |
4504 | ||
4505 | /* PREFIX_VEX_382C */ | |
4506 | { | |
592d1631 L |
4507 | { Bad_Opcode }, |
4508 | { Bad_Opcode }, | |
c0f3af97 | 4509 | { MOD_TABLE (MOD_VEX_382C_PREFIX_2) }, |
c0f3af97 L |
4510 | }, |
4511 | ||
4512 | /* PREFIX_VEX_382D */ | |
4513 | { | |
592d1631 L |
4514 | { Bad_Opcode }, |
4515 | { Bad_Opcode }, | |
c0f3af97 | 4516 | { MOD_TABLE (MOD_VEX_382D_PREFIX_2) }, |
c0f3af97 L |
4517 | }, |
4518 | ||
4519 | /* PREFIX_VEX_382E */ | |
4520 | { | |
592d1631 L |
4521 | { Bad_Opcode }, |
4522 | { Bad_Opcode }, | |
c0f3af97 | 4523 | { MOD_TABLE (MOD_VEX_382E_PREFIX_2) }, |
c0f3af97 L |
4524 | }, |
4525 | ||
4526 | /* PREFIX_VEX_382F */ | |
4527 | { | |
592d1631 L |
4528 | { Bad_Opcode }, |
4529 | { Bad_Opcode }, | |
c0f3af97 | 4530 | { MOD_TABLE (MOD_VEX_382F_PREFIX_2) }, |
c0f3af97 L |
4531 | }, |
4532 | ||
4533 | /* PREFIX_VEX_3830 */ | |
4534 | { | |
592d1631 L |
4535 | { Bad_Opcode }, |
4536 | { Bad_Opcode }, | |
c0f3af97 | 4537 | { VEX_LEN_TABLE (VEX_LEN_3830_P_2) }, |
c0f3af97 L |
4538 | }, |
4539 | ||
4540 | /* PREFIX_VEX_3831 */ | |
4541 | { | |
592d1631 L |
4542 | { Bad_Opcode }, |
4543 | { Bad_Opcode }, | |
c0f3af97 | 4544 | { VEX_LEN_TABLE (VEX_LEN_3831_P_2) }, |
c0f3af97 L |
4545 | }, |
4546 | ||
4547 | /* PREFIX_VEX_3832 */ | |
4548 | { | |
592d1631 L |
4549 | { Bad_Opcode }, |
4550 | { Bad_Opcode }, | |
c0f3af97 | 4551 | { VEX_LEN_TABLE (VEX_LEN_3832_P_2) }, |
c0f3af97 L |
4552 | }, |
4553 | ||
4554 | /* PREFIX_VEX_3833 */ | |
4555 | { | |
592d1631 L |
4556 | { Bad_Opcode }, |
4557 | { Bad_Opcode }, | |
c0f3af97 | 4558 | { VEX_LEN_TABLE (VEX_LEN_3833_P_2) }, |
c0f3af97 L |
4559 | }, |
4560 | ||
4561 | /* PREFIX_VEX_3834 */ | |
4562 | { | |
592d1631 L |
4563 | { Bad_Opcode }, |
4564 | { Bad_Opcode }, | |
c0f3af97 | 4565 | { VEX_LEN_TABLE (VEX_LEN_3834_P_2) }, |
c0f3af97 L |
4566 | }, |
4567 | ||
4568 | /* PREFIX_VEX_3835 */ | |
4569 | { | |
592d1631 L |
4570 | { Bad_Opcode }, |
4571 | { Bad_Opcode }, | |
c0f3af97 | 4572 | { VEX_LEN_TABLE (VEX_LEN_3835_P_2) }, |
c0f3af97 L |
4573 | }, |
4574 | ||
4575 | /* PREFIX_VEX_3837 */ | |
4576 | { | |
592d1631 L |
4577 | { Bad_Opcode }, |
4578 | { Bad_Opcode }, | |
c0f3af97 | 4579 | { VEX_LEN_TABLE (VEX_LEN_3837_P_2) }, |
c0f3af97 L |
4580 | }, |
4581 | ||
4582 | /* PREFIX_VEX_3838 */ | |
4583 | { | |
592d1631 L |
4584 | { Bad_Opcode }, |
4585 | { Bad_Opcode }, | |
c0f3af97 | 4586 | { VEX_LEN_TABLE (VEX_LEN_3838_P_2) }, |
c0f3af97 L |
4587 | }, |
4588 | ||
4589 | /* PREFIX_VEX_3839 */ | |
4590 | { | |
592d1631 L |
4591 | { Bad_Opcode }, |
4592 | { Bad_Opcode }, | |
c0f3af97 | 4593 | { VEX_LEN_TABLE (VEX_LEN_3839_P_2) }, |
c0f3af97 L |
4594 | }, |
4595 | ||
4596 | /* PREFIX_VEX_383A */ | |
4597 | { | |
592d1631 L |
4598 | { Bad_Opcode }, |
4599 | { Bad_Opcode }, | |
c0f3af97 | 4600 | { VEX_LEN_TABLE (VEX_LEN_383A_P_2) }, |
c0f3af97 L |
4601 | }, |
4602 | ||
4603 | /* PREFIX_VEX_383B */ | |
4604 | { | |
592d1631 L |
4605 | { Bad_Opcode }, |
4606 | { Bad_Opcode }, | |
c0f3af97 | 4607 | { VEX_LEN_TABLE (VEX_LEN_383B_P_2) }, |
c0f3af97 L |
4608 | }, |
4609 | ||
4610 | /* PREFIX_VEX_383C */ | |
4611 | { | |
592d1631 L |
4612 | { Bad_Opcode }, |
4613 | { Bad_Opcode }, | |
c0f3af97 | 4614 | { VEX_LEN_TABLE (VEX_LEN_383C_P_2) }, |
c0f3af97 L |
4615 | }, |
4616 | ||
4617 | /* PREFIX_VEX_383D */ | |
4618 | { | |
592d1631 L |
4619 | { Bad_Opcode }, |
4620 | { Bad_Opcode }, | |
c0f3af97 | 4621 | { VEX_LEN_TABLE (VEX_LEN_383D_P_2) }, |
c0f3af97 L |
4622 | }, |
4623 | ||
4624 | /* PREFIX_VEX_383E */ | |
4625 | { | |
592d1631 L |
4626 | { Bad_Opcode }, |
4627 | { Bad_Opcode }, | |
c0f3af97 | 4628 | { VEX_LEN_TABLE (VEX_LEN_383E_P_2) }, |
c0f3af97 L |
4629 | }, |
4630 | ||
4631 | /* PREFIX_VEX_383F */ | |
4632 | { | |
592d1631 L |
4633 | { Bad_Opcode }, |
4634 | { Bad_Opcode }, | |
c0f3af97 | 4635 | { VEX_LEN_TABLE (VEX_LEN_383F_P_2) }, |
c0f3af97 L |
4636 | }, |
4637 | ||
4638 | /* PREFIX_VEX_3840 */ | |
4639 | { | |
592d1631 L |
4640 | { Bad_Opcode }, |
4641 | { Bad_Opcode }, | |
c0f3af97 | 4642 | { VEX_LEN_TABLE (VEX_LEN_3840_P_2) }, |
c0f3af97 L |
4643 | }, |
4644 | ||
4645 | /* PREFIX_VEX_3841 */ | |
4646 | { | |
592d1631 L |
4647 | { Bad_Opcode }, |
4648 | { Bad_Opcode }, | |
c0f3af97 | 4649 | { VEX_LEN_TABLE (VEX_LEN_3841_P_2) }, |
c0f3af97 L |
4650 | }, |
4651 | ||
0bfee649 | 4652 | /* PREFIX_VEX_3896 */ |
a5ff0eb2 | 4653 | { |
592d1631 L |
4654 | { Bad_Opcode }, |
4655 | { Bad_Opcode }, | |
0bfee649 | 4656 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4657 | }, |
4658 | ||
0bfee649 | 4659 | /* PREFIX_VEX_3897 */ |
a5ff0eb2 | 4660 | { |
592d1631 L |
4661 | { Bad_Opcode }, |
4662 | { Bad_Opcode }, | |
0bfee649 | 4663 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4664 | }, |
4665 | ||
0bfee649 | 4666 | /* PREFIX_VEX_3898 */ |
a5ff0eb2 | 4667 | { |
592d1631 L |
4668 | { Bad_Opcode }, |
4669 | { Bad_Opcode }, | |
0bfee649 | 4670 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4671 | }, |
4672 | ||
0bfee649 | 4673 | /* PREFIX_VEX_3899 */ |
a5ff0eb2 | 4674 | { |
592d1631 L |
4675 | { Bad_Opcode }, |
4676 | { Bad_Opcode }, | |
0bfee649 | 4677 | { "vfmadd132s%XW", { XM, Vex, EXVexWdq } }, |
a5ff0eb2 L |
4678 | }, |
4679 | ||
0bfee649 | 4680 | /* PREFIX_VEX_389A */ |
a5ff0eb2 | 4681 | { |
592d1631 L |
4682 | { Bad_Opcode }, |
4683 | { Bad_Opcode }, | |
0bfee649 | 4684 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4685 | }, |
4686 | ||
0bfee649 | 4687 | /* PREFIX_VEX_389B */ |
c0f3af97 | 4688 | { |
592d1631 L |
4689 | { Bad_Opcode }, |
4690 | { Bad_Opcode }, | |
0bfee649 | 4691 | { "vfmsub132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4692 | }, |
4693 | ||
0bfee649 | 4694 | /* PREFIX_VEX_389C */ |
c0f3af97 | 4695 | { |
592d1631 L |
4696 | { Bad_Opcode }, |
4697 | { Bad_Opcode }, | |
0bfee649 | 4698 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4699 | }, |
4700 | ||
0bfee649 | 4701 | /* PREFIX_VEX_389D */ |
c0f3af97 | 4702 | { |
592d1631 L |
4703 | { Bad_Opcode }, |
4704 | { Bad_Opcode }, | |
0bfee649 | 4705 | { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4706 | }, |
4707 | ||
0bfee649 | 4708 | /* PREFIX_VEX_389E */ |
c0f3af97 | 4709 | { |
592d1631 L |
4710 | { Bad_Opcode }, |
4711 | { Bad_Opcode }, | |
0bfee649 | 4712 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4713 | }, |
4714 | ||
0bfee649 | 4715 | /* PREFIX_VEX_389F */ |
c0f3af97 | 4716 | { |
592d1631 L |
4717 | { Bad_Opcode }, |
4718 | { Bad_Opcode }, | |
0bfee649 | 4719 | { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4720 | }, |
4721 | ||
0bfee649 | 4722 | /* PREFIX_VEX_38A6 */ |
c0f3af97 | 4723 | { |
592d1631 L |
4724 | { Bad_Opcode }, |
4725 | { Bad_Opcode }, | |
0bfee649 | 4726 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
592d1631 | 4727 | { Bad_Opcode }, |
c0f3af97 L |
4728 | }, |
4729 | ||
0bfee649 | 4730 | /* PREFIX_VEX_38A7 */ |
c0f3af97 | 4731 | { |
592d1631 L |
4732 | { Bad_Opcode }, |
4733 | { Bad_Opcode }, | |
0bfee649 | 4734 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4735 | }, |
4736 | ||
0bfee649 | 4737 | /* PREFIX_VEX_38A8 */ |
c0f3af97 | 4738 | { |
592d1631 L |
4739 | { Bad_Opcode }, |
4740 | { Bad_Opcode }, | |
0bfee649 | 4741 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4742 | }, |
4743 | ||
0bfee649 | 4744 | /* PREFIX_VEX_38A9 */ |
c0f3af97 | 4745 | { |
592d1631 L |
4746 | { Bad_Opcode }, |
4747 | { Bad_Opcode }, | |
0bfee649 | 4748 | { "vfmadd213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4749 | }, |
4750 | ||
0bfee649 | 4751 | /* PREFIX_VEX_38AA */ |
c0f3af97 | 4752 | { |
592d1631 L |
4753 | { Bad_Opcode }, |
4754 | { Bad_Opcode }, | |
0bfee649 | 4755 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4756 | }, |
4757 | ||
0bfee649 | 4758 | /* PREFIX_VEX_38AB */ |
c0f3af97 | 4759 | { |
592d1631 L |
4760 | { Bad_Opcode }, |
4761 | { Bad_Opcode }, | |
0bfee649 | 4762 | { "vfmsub213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4763 | }, |
4764 | ||
0bfee649 | 4765 | /* PREFIX_VEX_38AC */ |
c0f3af97 | 4766 | { |
592d1631 L |
4767 | { Bad_Opcode }, |
4768 | { Bad_Opcode }, | |
0bfee649 | 4769 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4770 | }, |
4771 | ||
0bfee649 | 4772 | /* PREFIX_VEX_38AD */ |
c0f3af97 | 4773 | { |
592d1631 L |
4774 | { Bad_Opcode }, |
4775 | { Bad_Opcode }, | |
0bfee649 | 4776 | { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4777 | }, |
4778 | ||
0bfee649 | 4779 | /* PREFIX_VEX_38AE */ |
c0f3af97 | 4780 | { |
592d1631 L |
4781 | { Bad_Opcode }, |
4782 | { Bad_Opcode }, | |
0bfee649 | 4783 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4784 | }, |
4785 | ||
0bfee649 | 4786 | /* PREFIX_VEX_38AF */ |
c0f3af97 | 4787 | { |
592d1631 L |
4788 | { Bad_Opcode }, |
4789 | { Bad_Opcode }, | |
0bfee649 | 4790 | { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4791 | }, |
4792 | ||
0bfee649 | 4793 | /* PREFIX_VEX_38B6 */ |
c0f3af97 | 4794 | { |
592d1631 L |
4795 | { Bad_Opcode }, |
4796 | { Bad_Opcode }, | |
0bfee649 | 4797 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4798 | }, |
4799 | ||
0bfee649 | 4800 | /* PREFIX_VEX_38B7 */ |
c0f3af97 | 4801 | { |
592d1631 L |
4802 | { Bad_Opcode }, |
4803 | { Bad_Opcode }, | |
0bfee649 | 4804 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4805 | }, |
4806 | ||
0bfee649 | 4807 | /* PREFIX_VEX_38B8 */ |
c0f3af97 | 4808 | { |
592d1631 L |
4809 | { Bad_Opcode }, |
4810 | { Bad_Opcode }, | |
0bfee649 | 4811 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4812 | }, |
4813 | ||
0bfee649 | 4814 | /* PREFIX_VEX_38B9 */ |
c0f3af97 | 4815 | { |
592d1631 L |
4816 | { Bad_Opcode }, |
4817 | { Bad_Opcode }, | |
0bfee649 | 4818 | { "vfmadd231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4819 | }, |
4820 | ||
0bfee649 | 4821 | /* PREFIX_VEX_38BA */ |
c0f3af97 | 4822 | { |
592d1631 L |
4823 | { Bad_Opcode }, |
4824 | { Bad_Opcode }, | |
0bfee649 | 4825 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4826 | }, |
4827 | ||
0bfee649 | 4828 | /* PREFIX_VEX_38BB */ |
c0f3af97 | 4829 | { |
592d1631 L |
4830 | { Bad_Opcode }, |
4831 | { Bad_Opcode }, | |
0bfee649 | 4832 | { "vfmsub231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4833 | }, |
4834 | ||
0bfee649 | 4835 | /* PREFIX_VEX_38BC */ |
c0f3af97 | 4836 | { |
592d1631 L |
4837 | { Bad_Opcode }, |
4838 | { Bad_Opcode }, | |
0bfee649 | 4839 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4840 | }, |
4841 | ||
0bfee649 | 4842 | /* PREFIX_VEX_38BD */ |
c0f3af97 | 4843 | { |
592d1631 L |
4844 | { Bad_Opcode }, |
4845 | { Bad_Opcode }, | |
0bfee649 | 4846 | { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4847 | }, |
4848 | ||
0bfee649 | 4849 | /* PREFIX_VEX_38BE */ |
c0f3af97 | 4850 | { |
592d1631 L |
4851 | { Bad_Opcode }, |
4852 | { Bad_Opcode }, | |
0bfee649 | 4853 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4854 | }, |
4855 | ||
0bfee649 | 4856 | /* PREFIX_VEX_38BF */ |
c0f3af97 | 4857 | { |
592d1631 L |
4858 | { Bad_Opcode }, |
4859 | { Bad_Opcode }, | |
0bfee649 | 4860 | { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4861 | }, |
4862 | ||
0bfee649 | 4863 | /* PREFIX_VEX_38DB */ |
c0f3af97 | 4864 | { |
592d1631 L |
4865 | { Bad_Opcode }, |
4866 | { Bad_Opcode }, | |
0bfee649 | 4867 | { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) }, |
c0f3af97 L |
4868 | }, |
4869 | ||
0bfee649 | 4870 | /* PREFIX_VEX_38DC */ |
c0f3af97 | 4871 | { |
592d1631 L |
4872 | { Bad_Opcode }, |
4873 | { Bad_Opcode }, | |
0bfee649 | 4874 | { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) }, |
c0f3af97 L |
4875 | }, |
4876 | ||
0bfee649 | 4877 | /* PREFIX_VEX_38DD */ |
c0f3af97 | 4878 | { |
592d1631 L |
4879 | { Bad_Opcode }, |
4880 | { Bad_Opcode }, | |
0bfee649 | 4881 | { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) }, |
c0f3af97 L |
4882 | }, |
4883 | ||
0bfee649 | 4884 | /* PREFIX_VEX_38DE */ |
c0f3af97 | 4885 | { |
592d1631 L |
4886 | { Bad_Opcode }, |
4887 | { Bad_Opcode }, | |
0bfee649 | 4888 | { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) }, |
c0f3af97 L |
4889 | }, |
4890 | ||
0bfee649 | 4891 | /* PREFIX_VEX_38DF */ |
c0f3af97 | 4892 | { |
592d1631 L |
4893 | { Bad_Opcode }, |
4894 | { Bad_Opcode }, | |
0bfee649 | 4895 | { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) }, |
c0f3af97 L |
4896 | }, |
4897 | ||
0bfee649 | 4898 | /* PREFIX_VEX_3A04 */ |
c0f3af97 | 4899 | { |
592d1631 L |
4900 | { Bad_Opcode }, |
4901 | { Bad_Opcode }, | |
9e30b8e0 | 4902 | { VEX_W_TABLE (VEX_W_3A04_P_2) }, |
c0f3af97 L |
4903 | }, |
4904 | ||
0bfee649 | 4905 | /* PREFIX_VEX_3A05 */ |
c0f3af97 | 4906 | { |
592d1631 L |
4907 | { Bad_Opcode }, |
4908 | { Bad_Opcode }, | |
9e30b8e0 | 4909 | { VEX_W_TABLE (VEX_W_3A05_P_2) }, |
c0f3af97 L |
4910 | }, |
4911 | ||
0bfee649 | 4912 | /* PREFIX_VEX_3A06 */ |
c0f3af97 | 4913 | { |
592d1631 L |
4914 | { Bad_Opcode }, |
4915 | { Bad_Opcode }, | |
0bfee649 | 4916 | { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) }, |
c0f3af97 L |
4917 | }, |
4918 | ||
0bfee649 | 4919 | /* PREFIX_VEX_3A08 */ |
c0f3af97 | 4920 | { |
592d1631 L |
4921 | { Bad_Opcode }, |
4922 | { Bad_Opcode }, | |
9e30b8e0 | 4923 | { VEX_W_TABLE (VEX_W_3A08_P_2) }, |
c0f3af97 L |
4924 | }, |
4925 | ||
0bfee649 | 4926 | /* PREFIX_VEX_3A09 */ |
c0f3af97 | 4927 | { |
592d1631 L |
4928 | { Bad_Opcode }, |
4929 | { Bad_Opcode }, | |
9e30b8e0 | 4930 | { VEX_W_TABLE (VEX_W_3A09_P_2) }, |
c0f3af97 L |
4931 | }, |
4932 | ||
0bfee649 | 4933 | /* PREFIX_VEX_3A0A */ |
c0f3af97 | 4934 | { |
592d1631 L |
4935 | { Bad_Opcode }, |
4936 | { Bad_Opcode }, | |
0bfee649 | 4937 | { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) }, |
0bfee649 L |
4938 | }, |
4939 | ||
4940 | /* PREFIX_VEX_3A0B */ | |
4941 | { | |
592d1631 L |
4942 | { Bad_Opcode }, |
4943 | { Bad_Opcode }, | |
0bfee649 | 4944 | { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) }, |
0bfee649 L |
4945 | }, |
4946 | ||
4947 | /* PREFIX_VEX_3A0C */ | |
4948 | { | |
592d1631 L |
4949 | { Bad_Opcode }, |
4950 | { Bad_Opcode }, | |
9e30b8e0 | 4951 | { VEX_W_TABLE (VEX_W_3A0C_P_2) }, |
0bfee649 L |
4952 | }, |
4953 | ||
4954 | /* PREFIX_VEX_3A0D */ | |
4955 | { | |
592d1631 L |
4956 | { Bad_Opcode }, |
4957 | { Bad_Opcode }, | |
9e30b8e0 | 4958 | { VEX_W_TABLE (VEX_W_3A0D_P_2) }, |
c0f3af97 L |
4959 | }, |
4960 | ||
0bfee649 L |
4961 | /* PREFIX_VEX_3A0E */ |
4962 | { | |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
0bfee649 | 4965 | { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) }, |
0bfee649 L |
4966 | }, |
4967 | ||
4968 | /* PREFIX_VEX_3A0F */ | |
4969 | { | |
592d1631 L |
4970 | { Bad_Opcode }, |
4971 | { Bad_Opcode }, | |
0bfee649 | 4972 | { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) }, |
0bfee649 L |
4973 | }, |
4974 | ||
4975 | /* PREFIX_VEX_3A14 */ | |
4976 | { | |
592d1631 L |
4977 | { Bad_Opcode }, |
4978 | { Bad_Opcode }, | |
0bfee649 | 4979 | { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) }, |
0bfee649 L |
4980 | }, |
4981 | ||
4982 | /* PREFIX_VEX_3A15 */ | |
4983 | { | |
592d1631 L |
4984 | { Bad_Opcode }, |
4985 | { Bad_Opcode }, | |
0bfee649 | 4986 | { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) }, |
0bfee649 L |
4987 | }, |
4988 | ||
4989 | /* PREFIX_VEX_3A16 */ | |
c0f3af97 | 4990 | { |
592d1631 L |
4991 | { Bad_Opcode }, |
4992 | { Bad_Opcode }, | |
0bfee649 | 4993 | { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) }, |
c0f3af97 L |
4994 | }, |
4995 | ||
0bfee649 | 4996 | /* PREFIX_VEX_3A17 */ |
c0f3af97 | 4997 | { |
592d1631 L |
4998 | { Bad_Opcode }, |
4999 | { Bad_Opcode }, | |
0bfee649 | 5000 | { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) }, |
c0f3af97 L |
5001 | }, |
5002 | ||
0bfee649 | 5003 | /* PREFIX_VEX_3A18 */ |
c0f3af97 | 5004 | { |
592d1631 L |
5005 | { Bad_Opcode }, |
5006 | { Bad_Opcode }, | |
0bfee649 | 5007 | { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) }, |
c0f3af97 L |
5008 | }, |
5009 | ||
0bfee649 | 5010 | /* PREFIX_VEX_3A19 */ |
c0f3af97 | 5011 | { |
592d1631 L |
5012 | { Bad_Opcode }, |
5013 | { Bad_Opcode }, | |
0bfee649 | 5014 | { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) }, |
c0f3af97 L |
5015 | }, |
5016 | ||
0bfee649 | 5017 | /* PREFIX_VEX_3A20 */ |
c0f3af97 | 5018 | { |
592d1631 L |
5019 | { Bad_Opcode }, |
5020 | { Bad_Opcode }, | |
0bfee649 | 5021 | { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) }, |
c0f3af97 L |
5022 | }, |
5023 | ||
0bfee649 | 5024 | /* PREFIX_VEX_3A21 */ |
c0f3af97 | 5025 | { |
592d1631 L |
5026 | { Bad_Opcode }, |
5027 | { Bad_Opcode }, | |
0bfee649 | 5028 | { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) }, |
c0f3af97 L |
5029 | }, |
5030 | ||
0bfee649 L |
5031 | /* PREFIX_VEX_3A22 */ |
5032 | { | |
592d1631 L |
5033 | { Bad_Opcode }, |
5034 | { Bad_Opcode }, | |
0bfee649 | 5035 | { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) }, |
0bfee649 L |
5036 | }, |
5037 | ||
5038 | /* PREFIX_VEX_3A40 */ | |
c0f3af97 | 5039 | { |
592d1631 L |
5040 | { Bad_Opcode }, |
5041 | { Bad_Opcode }, | |
9e30b8e0 | 5042 | { VEX_W_TABLE (VEX_W_3A40_P_2) }, |
c0f3af97 L |
5043 | }, |
5044 | ||
0bfee649 | 5045 | /* PREFIX_VEX_3A41 */ |
c0f3af97 | 5046 | { |
592d1631 L |
5047 | { Bad_Opcode }, |
5048 | { Bad_Opcode }, | |
0bfee649 | 5049 | { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) }, |
c0f3af97 L |
5050 | }, |
5051 | ||
0bfee649 | 5052 | /* PREFIX_VEX_3A42 */ |
c0f3af97 | 5053 | { |
592d1631 L |
5054 | { Bad_Opcode }, |
5055 | { Bad_Opcode }, | |
0bfee649 | 5056 | { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) }, |
c0f3af97 L |
5057 | }, |
5058 | ||
ce2f5b3c L |
5059 | /* PREFIX_VEX_3A44 */ |
5060 | { | |
592d1631 L |
5061 | { Bad_Opcode }, |
5062 | { Bad_Opcode }, | |
ce2f5b3c | 5063 | { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) }, |
ce2f5b3c L |
5064 | }, |
5065 | ||
0bfee649 | 5066 | /* PREFIX_VEX_3A4A */ |
c0f3af97 | 5067 | { |
592d1631 L |
5068 | { Bad_Opcode }, |
5069 | { Bad_Opcode }, | |
9e30b8e0 | 5070 | { VEX_W_TABLE (VEX_W_3A4A_P_2) }, |
c0f3af97 L |
5071 | }, |
5072 | ||
0bfee649 | 5073 | /* PREFIX_VEX_3A4B */ |
c0f3af97 | 5074 | { |
592d1631 L |
5075 | { Bad_Opcode }, |
5076 | { Bad_Opcode }, | |
9e30b8e0 | 5077 | { VEX_W_TABLE (VEX_W_3A4B_P_2) }, |
c0f3af97 L |
5078 | }, |
5079 | ||
0bfee649 | 5080 | /* PREFIX_VEX_3A4C */ |
c0f3af97 | 5081 | { |
592d1631 L |
5082 | { Bad_Opcode }, |
5083 | { Bad_Opcode }, | |
0bfee649 | 5084 | { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) }, |
c0f3af97 L |
5085 | }, |
5086 | ||
922d8de8 DR |
5087 | /* PREFIX_VEX_3A5C */ |
5088 | { | |
592d1631 L |
5089 | { Bad_Opcode }, |
5090 | { Bad_Opcode }, | |
206c2556 | 5091 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5092 | }, |
5093 | ||
5094 | /* PREFIX_VEX_3A5D */ | |
5095 | { | |
592d1631 L |
5096 | { Bad_Opcode }, |
5097 | { Bad_Opcode }, | |
206c2556 | 5098 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5099 | }, |
5100 | ||
5101 | /* PREFIX_VEX_3A5E */ | |
5102 | { | |
592d1631 L |
5103 | { Bad_Opcode }, |
5104 | { Bad_Opcode }, | |
206c2556 | 5105 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5106 | }, |
5107 | ||
5108 | /* PREFIX_VEX_3A5F */ | |
5109 | { | |
592d1631 L |
5110 | { Bad_Opcode }, |
5111 | { Bad_Opcode }, | |
206c2556 | 5112 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5113 | }, |
5114 | ||
0bfee649 | 5115 | /* PREFIX_VEX_3A60 */ |
c0f3af97 | 5116 | { |
592d1631 L |
5117 | { Bad_Opcode }, |
5118 | { Bad_Opcode }, | |
0bfee649 | 5119 | { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) }, |
592d1631 | 5120 | { Bad_Opcode }, |
c0f3af97 L |
5121 | }, |
5122 | ||
0bfee649 | 5123 | /* PREFIX_VEX_3A61 */ |
c0f3af97 | 5124 | { |
592d1631 L |
5125 | { Bad_Opcode }, |
5126 | { Bad_Opcode }, | |
0bfee649 | 5127 | { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) }, |
c0f3af97 L |
5128 | }, |
5129 | ||
0bfee649 | 5130 | /* PREFIX_VEX_3A62 */ |
c0f3af97 | 5131 | { |
592d1631 L |
5132 | { Bad_Opcode }, |
5133 | { Bad_Opcode }, | |
0bfee649 | 5134 | { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) }, |
c0f3af97 L |
5135 | }, |
5136 | ||
0bfee649 | 5137 | /* PREFIX_VEX_3A63 */ |
c0f3af97 | 5138 | { |
592d1631 L |
5139 | { Bad_Opcode }, |
5140 | { Bad_Opcode }, | |
0bfee649 | 5141 | { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) }, |
c0f3af97 | 5142 | }, |
a5ff0eb2 | 5143 | |
922d8de8 DR |
5144 | /* PREFIX_VEX_3A68 */ |
5145 | { | |
592d1631 L |
5146 | { Bad_Opcode }, |
5147 | { Bad_Opcode }, | |
206c2556 | 5148 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5149 | }, |
5150 | ||
5151 | /* PREFIX_VEX_3A69 */ | |
5152 | { | |
592d1631 L |
5153 | { Bad_Opcode }, |
5154 | { Bad_Opcode }, | |
206c2556 | 5155 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5156 | }, |
5157 | ||
5158 | /* PREFIX_VEX_3A6A */ | |
5159 | { | |
592d1631 L |
5160 | { Bad_Opcode }, |
5161 | { Bad_Opcode }, | |
922d8de8 | 5162 | { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) }, |
922d8de8 DR |
5163 | }, |
5164 | ||
5165 | /* PREFIX_VEX_3A6B */ | |
5166 | { | |
592d1631 L |
5167 | { Bad_Opcode }, |
5168 | { Bad_Opcode }, | |
922d8de8 | 5169 | { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) }, |
922d8de8 DR |
5170 | }, |
5171 | ||
5172 | /* PREFIX_VEX_3A6C */ | |
5173 | { | |
592d1631 L |
5174 | { Bad_Opcode }, |
5175 | { Bad_Opcode }, | |
206c2556 | 5176 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5177 | }, |
5178 | ||
5179 | /* PREFIX_VEX_3A6D */ | |
5180 | { | |
592d1631 L |
5181 | { Bad_Opcode }, |
5182 | { Bad_Opcode }, | |
206c2556 | 5183 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5184 | }, |
5185 | ||
5186 | /* PREFIX_VEX_3A6E */ | |
5187 | { | |
592d1631 L |
5188 | { Bad_Opcode }, |
5189 | { Bad_Opcode }, | |
922d8de8 | 5190 | { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) }, |
922d8de8 DR |
5191 | }, |
5192 | ||
5193 | /* PREFIX_VEX_3A6F */ | |
5194 | { | |
592d1631 L |
5195 | { Bad_Opcode }, |
5196 | { Bad_Opcode }, | |
922d8de8 | 5197 | { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) }, |
922d8de8 DR |
5198 | }, |
5199 | ||
5200 | /* PREFIX_VEX_3A78 */ | |
5201 | { | |
592d1631 L |
5202 | { Bad_Opcode }, |
5203 | { Bad_Opcode }, | |
206c2556 | 5204 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5205 | }, |
5206 | ||
5207 | /* PREFIX_VEX_3A79 */ | |
5208 | { | |
592d1631 L |
5209 | { Bad_Opcode }, |
5210 | { Bad_Opcode }, | |
206c2556 | 5211 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5212 | }, |
5213 | ||
5214 | /* PREFIX_VEX_3A7A */ | |
5215 | { | |
592d1631 L |
5216 | { Bad_Opcode }, |
5217 | { Bad_Opcode }, | |
922d8de8 | 5218 | { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) }, |
922d8de8 DR |
5219 | }, |
5220 | ||
5221 | /* PREFIX_VEX_3A7B */ | |
5222 | { | |
592d1631 L |
5223 | { Bad_Opcode }, |
5224 | { Bad_Opcode }, | |
922d8de8 | 5225 | { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) }, |
922d8de8 DR |
5226 | }, |
5227 | ||
5228 | /* PREFIX_VEX_3A7C */ | |
5229 | { | |
592d1631 L |
5230 | { Bad_Opcode }, |
5231 | { Bad_Opcode }, | |
206c2556 | 5232 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 5233 | { Bad_Opcode }, |
922d8de8 DR |
5234 | }, |
5235 | ||
5236 | /* PREFIX_VEX_3A7D */ | |
5237 | { | |
592d1631 L |
5238 | { Bad_Opcode }, |
5239 | { Bad_Opcode }, | |
206c2556 | 5240 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5241 | }, |
5242 | ||
5243 | /* PREFIX_VEX_3A7E */ | |
5244 | { | |
592d1631 L |
5245 | { Bad_Opcode }, |
5246 | { Bad_Opcode }, | |
922d8de8 | 5247 | { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) }, |
922d8de8 DR |
5248 | }, |
5249 | ||
5250 | /* PREFIX_VEX_3A7F */ | |
5251 | { | |
592d1631 L |
5252 | { Bad_Opcode }, |
5253 | { Bad_Opcode }, | |
922d8de8 | 5254 | { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) }, |
922d8de8 DR |
5255 | }, |
5256 | ||
a5ff0eb2 L |
5257 | /* PREFIX_VEX_3ADF */ |
5258 | { | |
592d1631 L |
5259 | { Bad_Opcode }, |
5260 | { Bad_Opcode }, | |
a5ff0eb2 | 5261 | { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) }, |
a5ff0eb2 | 5262 | }, |
c0f3af97 L |
5263 | }; |
5264 | ||
5265 | static const struct dis386 x86_64_table[][2] = { | |
5266 | /* X86_64_06 */ | |
5267 | { | |
5268 | { "push{T|}", { es } }, | |
c0f3af97 L |
5269 | }, |
5270 | ||
5271 | /* X86_64_07 */ | |
5272 | { | |
5273 | { "pop{T|}", { es } }, | |
c0f3af97 L |
5274 | }, |
5275 | ||
5276 | /* X86_64_0D */ | |
5277 | { | |
5278 | { "push{T|}", { cs } }, | |
c0f3af97 L |
5279 | }, |
5280 | ||
5281 | /* X86_64_16 */ | |
5282 | { | |
5283 | { "push{T|}", { ss } }, | |
c0f3af97 L |
5284 | }, |
5285 | ||
5286 | /* X86_64_17 */ | |
5287 | { | |
5288 | { "pop{T|}", { ss } }, | |
c0f3af97 L |
5289 | }, |
5290 | ||
5291 | /* X86_64_1E */ | |
5292 | { | |
5293 | { "push{T|}", { ds } }, | |
c0f3af97 L |
5294 | }, |
5295 | ||
5296 | /* X86_64_1F */ | |
5297 | { | |
5298 | { "pop{T|}", { ds } }, | |
c0f3af97 L |
5299 | }, |
5300 | ||
5301 | /* X86_64_27 */ | |
5302 | { | |
5303 | { "daa", { XX } }, | |
c0f3af97 L |
5304 | }, |
5305 | ||
5306 | /* X86_64_2F */ | |
5307 | { | |
5308 | { "das", { XX } }, | |
c0f3af97 L |
5309 | }, |
5310 | ||
5311 | /* X86_64_37 */ | |
5312 | { | |
5313 | { "aaa", { XX } }, | |
c0f3af97 L |
5314 | }, |
5315 | ||
5316 | /* X86_64_3F */ | |
5317 | { | |
5318 | { "aas", { XX } }, | |
c0f3af97 L |
5319 | }, |
5320 | ||
5321 | /* X86_64_60 */ | |
5322 | { | |
5323 | { "pusha{P|}", { XX } }, | |
c0f3af97 L |
5324 | }, |
5325 | ||
5326 | /* X86_64_61 */ | |
5327 | { | |
5328 | { "popa{P|}", { XX } }, | |
c0f3af97 L |
5329 | }, |
5330 | ||
5331 | /* X86_64_62 */ | |
5332 | { | |
5333 | { MOD_TABLE (MOD_62_32BIT) }, | |
c0f3af97 L |
5334 | }, |
5335 | ||
5336 | /* X86_64_63 */ | |
5337 | { | |
5338 | { "arpl", { Ew, Gw } }, | |
5339 | { "movs{lq|xd}", { Gv, Ed } }, | |
5340 | }, | |
5341 | ||
5342 | /* X86_64_6D */ | |
5343 | { | |
5344 | { "ins{R|}", { Yzr, indirDX } }, | |
5345 | { "ins{G|}", { Yzr, indirDX } }, | |
5346 | }, | |
5347 | ||
5348 | /* X86_64_6F */ | |
5349 | { | |
5350 | { "outs{R|}", { indirDXr, Xz } }, | |
5351 | { "outs{G|}", { indirDXr, Xz } }, | |
5352 | }, | |
5353 | ||
5354 | /* X86_64_9A */ | |
5355 | { | |
5356 | { "Jcall{T|}", { Ap } }, | |
c0f3af97 L |
5357 | }, |
5358 | ||
5359 | /* X86_64_C4 */ | |
5360 | { | |
5361 | { MOD_TABLE (MOD_C4_32BIT) }, | |
5362 | { VEX_C4_TABLE (VEX_0F) }, | |
5363 | }, | |
5364 | ||
5365 | /* X86_64_C5 */ | |
5366 | { | |
5367 | { MOD_TABLE (MOD_C5_32BIT) }, | |
5368 | { VEX_C5_TABLE (VEX_0F) }, | |
5369 | }, | |
5370 | ||
5371 | /* X86_64_CE */ | |
5372 | { | |
5373 | { "into", { XX } }, | |
c0f3af97 L |
5374 | }, |
5375 | ||
5376 | /* X86_64_D4 */ | |
5377 | { | |
5378 | { "aam", { sIb } }, | |
c0f3af97 L |
5379 | }, |
5380 | ||
5381 | /* X86_64_D5 */ | |
5382 | { | |
5383 | { "aad", { sIb } }, | |
c0f3af97 L |
5384 | }, |
5385 | ||
5386 | /* X86_64_EA */ | |
5387 | { | |
5388 | { "Jjmp{T|}", { Ap } }, | |
c0f3af97 L |
5389 | }, |
5390 | ||
5391 | /* X86_64_0F01_REG_0 */ | |
5392 | { | |
5393 | { "sgdt{Q|IQ}", { M } }, | |
5394 | { "sgdt", { M } }, | |
5395 | }, | |
5396 | ||
5397 | /* X86_64_0F01_REG_1 */ | |
5398 | { | |
5399 | { "sidt{Q|IQ}", { M } }, | |
5400 | { "sidt", { M } }, | |
5401 | }, | |
5402 | ||
5403 | /* X86_64_0F01_REG_2 */ | |
5404 | { | |
5405 | { "lgdt{Q|Q}", { M } }, | |
5406 | { "lgdt", { M } }, | |
5407 | }, | |
5408 | ||
5409 | /* X86_64_0F01_REG_3 */ | |
5410 | { | |
5411 | { "lidt{Q|Q}", { M } }, | |
5412 | { "lidt", { M } }, | |
5413 | }, | |
5414 | }; | |
5415 | ||
5416 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
5417 | |
5418 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
5419 | { |
5420 | /* 00 */ | |
c1e679ec DR |
5421 | { "pshufb", { MX, EM } }, |
5422 | { "phaddw", { MX, EM } }, | |
5423 | { "phaddd", { MX, EM } }, | |
5424 | { "phaddsw", { MX, EM } }, | |
5425 | { "pmaddubsw", { MX, EM } }, | |
5426 | { "phsubw", { MX, EM } }, | |
5427 | { "phsubd", { MX, EM } }, | |
5428 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 5429 | /* 08 */ |
c1e679ec DR |
5430 | { "psignb", { MX, EM } }, |
5431 | { "psignw", { MX, EM } }, | |
5432 | { "psignd", { MX, EM } }, | |
5433 | { "pmulhrsw", { MX, EM } }, | |
592d1631 L |
5434 | { Bad_Opcode }, |
5435 | { Bad_Opcode }, | |
5436 | { Bad_Opcode }, | |
5437 | { Bad_Opcode }, | |
f88c9eb0 SP |
5438 | /* 10 */ |
5439 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
5440 | { Bad_Opcode }, |
5441 | { Bad_Opcode }, | |
5442 | { Bad_Opcode }, | |
f88c9eb0 SP |
5443 | { PREFIX_TABLE (PREFIX_0F3814) }, |
5444 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 5445 | { Bad_Opcode }, |
f88c9eb0 SP |
5446 | { PREFIX_TABLE (PREFIX_0F3817) }, |
5447 | /* 18 */ | |
592d1631 L |
5448 | { Bad_Opcode }, |
5449 | { Bad_Opcode }, | |
5450 | { Bad_Opcode }, | |
5451 | { Bad_Opcode }, | |
f88c9eb0 SP |
5452 | { "pabsb", { MX, EM } }, |
5453 | { "pabsw", { MX, EM } }, | |
5454 | { "pabsd", { MX, EM } }, | |
592d1631 | 5455 | { Bad_Opcode }, |
f88c9eb0 SP |
5456 | /* 20 */ |
5457 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
5458 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
5459 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
5460 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
5461 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
5462 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
5463 | { Bad_Opcode }, |
5464 | { Bad_Opcode }, | |
f88c9eb0 SP |
5465 | /* 28 */ |
5466 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
5467 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
5468 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
5469 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
5470 | { Bad_Opcode }, |
5471 | { Bad_Opcode }, | |
5472 | { Bad_Opcode }, | |
5473 | { Bad_Opcode }, | |
f88c9eb0 SP |
5474 | /* 30 */ |
5475 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
5476 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
5477 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
5478 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
5479 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
5480 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 5481 | { Bad_Opcode }, |
f88c9eb0 SP |
5482 | { PREFIX_TABLE (PREFIX_0F3837) }, |
5483 | /* 38 */ | |
5484 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
5485 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
5486 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
5487 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
5488 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
5489 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
5490 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
5491 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
5492 | /* 40 */ | |
5493 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
5494 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
5495 | { Bad_Opcode }, |
5496 | { Bad_Opcode }, | |
5497 | { Bad_Opcode }, | |
5498 | { Bad_Opcode }, | |
5499 | { Bad_Opcode }, | |
5500 | { Bad_Opcode }, | |
f88c9eb0 | 5501 | /* 48 */ |
592d1631 L |
5502 | { Bad_Opcode }, |
5503 | { Bad_Opcode }, | |
5504 | { Bad_Opcode }, | |
5505 | { Bad_Opcode }, | |
5506 | { Bad_Opcode }, | |
5507 | { Bad_Opcode }, | |
5508 | { Bad_Opcode }, | |
5509 | { Bad_Opcode }, | |
f88c9eb0 | 5510 | /* 50 */ |
592d1631 L |
5511 | { Bad_Opcode }, |
5512 | { Bad_Opcode }, | |
5513 | { Bad_Opcode }, | |
5514 | { Bad_Opcode }, | |
5515 | { Bad_Opcode }, | |
5516 | { Bad_Opcode }, | |
5517 | { Bad_Opcode }, | |
5518 | { Bad_Opcode }, | |
f88c9eb0 | 5519 | /* 58 */ |
592d1631 L |
5520 | { Bad_Opcode }, |
5521 | { Bad_Opcode }, | |
5522 | { Bad_Opcode }, | |
5523 | { Bad_Opcode }, | |
5524 | { Bad_Opcode }, | |
5525 | { Bad_Opcode }, | |
5526 | { Bad_Opcode }, | |
5527 | { Bad_Opcode }, | |
f88c9eb0 | 5528 | /* 60 */ |
592d1631 L |
5529 | { Bad_Opcode }, |
5530 | { Bad_Opcode }, | |
5531 | { Bad_Opcode }, | |
5532 | { Bad_Opcode }, | |
5533 | { Bad_Opcode }, | |
5534 | { Bad_Opcode }, | |
5535 | { Bad_Opcode }, | |
5536 | { Bad_Opcode }, | |
f88c9eb0 | 5537 | /* 68 */ |
592d1631 L |
5538 | { Bad_Opcode }, |
5539 | { Bad_Opcode }, | |
5540 | { Bad_Opcode }, | |
5541 | { Bad_Opcode }, | |
5542 | { Bad_Opcode }, | |
5543 | { Bad_Opcode }, | |
5544 | { Bad_Opcode }, | |
5545 | { Bad_Opcode }, | |
f88c9eb0 | 5546 | /* 70 */ |
592d1631 L |
5547 | { Bad_Opcode }, |
5548 | { Bad_Opcode }, | |
5549 | { Bad_Opcode }, | |
5550 | { Bad_Opcode }, | |
5551 | { Bad_Opcode }, | |
5552 | { Bad_Opcode }, | |
5553 | { Bad_Opcode }, | |
5554 | { Bad_Opcode }, | |
f88c9eb0 | 5555 | /* 78 */ |
592d1631 L |
5556 | { Bad_Opcode }, |
5557 | { Bad_Opcode }, | |
5558 | { Bad_Opcode }, | |
5559 | { Bad_Opcode }, | |
5560 | { Bad_Opcode }, | |
5561 | { Bad_Opcode }, | |
5562 | { Bad_Opcode }, | |
5563 | { Bad_Opcode }, | |
f88c9eb0 SP |
5564 | /* 80 */ |
5565 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
5566 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
592d1631 L |
5567 | { Bad_Opcode }, |
5568 | { Bad_Opcode }, | |
5569 | { Bad_Opcode }, | |
5570 | { Bad_Opcode }, | |
5571 | { Bad_Opcode }, | |
5572 | { Bad_Opcode }, | |
f88c9eb0 | 5573 | /* 88 */ |
592d1631 L |
5574 | { Bad_Opcode }, |
5575 | { Bad_Opcode }, | |
5576 | { Bad_Opcode }, | |
5577 | { Bad_Opcode }, | |
5578 | { Bad_Opcode }, | |
5579 | { Bad_Opcode }, | |
5580 | { Bad_Opcode }, | |
5581 | { Bad_Opcode }, | |
f88c9eb0 | 5582 | /* 90 */ |
592d1631 L |
5583 | { Bad_Opcode }, |
5584 | { Bad_Opcode }, | |
5585 | { Bad_Opcode }, | |
5586 | { Bad_Opcode }, | |
5587 | { Bad_Opcode }, | |
5588 | { Bad_Opcode }, | |
5589 | { Bad_Opcode }, | |
5590 | { Bad_Opcode }, | |
f88c9eb0 | 5591 | /* 98 */ |
592d1631 L |
5592 | { Bad_Opcode }, |
5593 | { Bad_Opcode }, | |
5594 | { Bad_Opcode }, | |
5595 | { Bad_Opcode }, | |
5596 | { Bad_Opcode }, | |
5597 | { Bad_Opcode }, | |
5598 | { Bad_Opcode }, | |
5599 | { Bad_Opcode }, | |
f88c9eb0 | 5600 | /* a0 */ |
592d1631 L |
5601 | { Bad_Opcode }, |
5602 | { Bad_Opcode }, | |
5603 | { Bad_Opcode }, | |
5604 | { Bad_Opcode }, | |
5605 | { Bad_Opcode }, | |
5606 | { Bad_Opcode }, | |
5607 | { Bad_Opcode }, | |
5608 | { Bad_Opcode }, | |
f88c9eb0 | 5609 | /* a8 */ |
592d1631 L |
5610 | { Bad_Opcode }, |
5611 | { Bad_Opcode }, | |
5612 | { Bad_Opcode }, | |
5613 | { Bad_Opcode }, | |
5614 | { Bad_Opcode }, | |
5615 | { Bad_Opcode }, | |
5616 | { Bad_Opcode }, | |
5617 | { Bad_Opcode }, | |
f88c9eb0 | 5618 | /* b0 */ |
592d1631 L |
5619 | { Bad_Opcode }, |
5620 | { Bad_Opcode }, | |
5621 | { Bad_Opcode }, | |
5622 | { Bad_Opcode }, | |
5623 | { Bad_Opcode }, | |
5624 | { Bad_Opcode }, | |
5625 | { Bad_Opcode }, | |
5626 | { Bad_Opcode }, | |
f88c9eb0 | 5627 | /* b8 */ |
592d1631 L |
5628 | { Bad_Opcode }, |
5629 | { Bad_Opcode }, | |
5630 | { Bad_Opcode }, | |
5631 | { Bad_Opcode }, | |
5632 | { Bad_Opcode }, | |
5633 | { Bad_Opcode }, | |
5634 | { Bad_Opcode }, | |
5635 | { Bad_Opcode }, | |
f88c9eb0 | 5636 | /* c0 */ |
592d1631 L |
5637 | { Bad_Opcode }, |
5638 | { Bad_Opcode }, | |
5639 | { Bad_Opcode }, | |
5640 | { Bad_Opcode }, | |
5641 | { Bad_Opcode }, | |
5642 | { Bad_Opcode }, | |
5643 | { Bad_Opcode }, | |
5644 | { Bad_Opcode }, | |
f88c9eb0 | 5645 | /* c8 */ |
592d1631 L |
5646 | { Bad_Opcode }, |
5647 | { Bad_Opcode }, | |
5648 | { Bad_Opcode }, | |
5649 | { Bad_Opcode }, | |
5650 | { Bad_Opcode }, | |
5651 | { Bad_Opcode }, | |
5652 | { Bad_Opcode }, | |
5653 | { Bad_Opcode }, | |
f88c9eb0 | 5654 | /* d0 */ |
592d1631 L |
5655 | { Bad_Opcode }, |
5656 | { Bad_Opcode }, | |
5657 | { Bad_Opcode }, | |
5658 | { Bad_Opcode }, | |
5659 | { Bad_Opcode }, | |
5660 | { Bad_Opcode }, | |
5661 | { Bad_Opcode }, | |
5662 | { Bad_Opcode }, | |
f88c9eb0 | 5663 | /* d8 */ |
592d1631 L |
5664 | { Bad_Opcode }, |
5665 | { Bad_Opcode }, | |
5666 | { Bad_Opcode }, | |
f88c9eb0 SP |
5667 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
5668 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
5669 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
5670 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
5671 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
5672 | /* e0 */ | |
592d1631 L |
5673 | { Bad_Opcode }, |
5674 | { Bad_Opcode }, | |
5675 | { Bad_Opcode }, | |
5676 | { Bad_Opcode }, | |
5677 | { Bad_Opcode }, | |
5678 | { Bad_Opcode }, | |
5679 | { Bad_Opcode }, | |
5680 | { Bad_Opcode }, | |
f88c9eb0 | 5681 | /* e8 */ |
592d1631 L |
5682 | { Bad_Opcode }, |
5683 | { Bad_Opcode }, | |
5684 | { Bad_Opcode }, | |
5685 | { Bad_Opcode }, | |
5686 | { Bad_Opcode }, | |
5687 | { Bad_Opcode }, | |
5688 | { Bad_Opcode }, | |
5689 | { Bad_Opcode }, | |
f88c9eb0 SP |
5690 | /* f0 */ |
5691 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
5692 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
5693 | { Bad_Opcode }, |
5694 | { Bad_Opcode }, | |
5695 | { Bad_Opcode }, | |
5696 | { Bad_Opcode }, | |
5697 | { Bad_Opcode }, | |
5698 | { Bad_Opcode }, | |
f88c9eb0 | 5699 | /* f8 */ |
592d1631 L |
5700 | { Bad_Opcode }, |
5701 | { Bad_Opcode }, | |
5702 | { Bad_Opcode }, | |
5703 | { Bad_Opcode }, | |
5704 | { Bad_Opcode }, | |
5705 | { Bad_Opcode }, | |
5706 | { Bad_Opcode }, | |
5707 | { Bad_Opcode }, | |
f88c9eb0 SP |
5708 | }, |
5709 | /* THREE_BYTE_0F3A */ | |
5710 | { | |
5711 | /* 00 */ | |
592d1631 L |
5712 | { Bad_Opcode }, |
5713 | { Bad_Opcode }, | |
5714 | { Bad_Opcode }, | |
5715 | { Bad_Opcode }, | |
5716 | { Bad_Opcode }, | |
5717 | { Bad_Opcode }, | |
5718 | { Bad_Opcode }, | |
5719 | { Bad_Opcode }, | |
f88c9eb0 SP |
5720 | /* 08 */ |
5721 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
5722 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
5723 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
5724 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
5725 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
5726 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
5727 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
5728 | { "palignr", { MX, EM, Ib } }, | |
5729 | /* 10 */ | |
592d1631 L |
5730 | { Bad_Opcode }, |
5731 | { Bad_Opcode }, | |
5732 | { Bad_Opcode }, | |
5733 | { Bad_Opcode }, | |
f88c9eb0 SP |
5734 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
5735 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
5736 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
5737 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
5738 | /* 18 */ | |
592d1631 L |
5739 | { Bad_Opcode }, |
5740 | { Bad_Opcode }, | |
5741 | { Bad_Opcode }, | |
5742 | { Bad_Opcode }, | |
5743 | { Bad_Opcode }, | |
5744 | { Bad_Opcode }, | |
5745 | { Bad_Opcode }, | |
5746 | { Bad_Opcode }, | |
f88c9eb0 SP |
5747 | /* 20 */ |
5748 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
5749 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
5750 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
5751 | { Bad_Opcode }, |
5752 | { Bad_Opcode }, | |
5753 | { Bad_Opcode }, | |
5754 | { Bad_Opcode }, | |
5755 | { Bad_Opcode }, | |
f88c9eb0 | 5756 | /* 28 */ |
592d1631 L |
5757 | { Bad_Opcode }, |
5758 | { Bad_Opcode }, | |
5759 | { Bad_Opcode }, | |
5760 | { Bad_Opcode }, | |
5761 | { Bad_Opcode }, | |
5762 | { Bad_Opcode }, | |
5763 | { Bad_Opcode }, | |
5764 | { Bad_Opcode }, | |
f88c9eb0 | 5765 | /* 30 */ |
592d1631 L |
5766 | { Bad_Opcode }, |
5767 | { Bad_Opcode }, | |
5768 | { Bad_Opcode }, | |
5769 | { Bad_Opcode }, | |
5770 | { Bad_Opcode }, | |
5771 | { Bad_Opcode }, | |
5772 | { Bad_Opcode }, | |
5773 | { Bad_Opcode }, | |
f88c9eb0 | 5774 | /* 38 */ |
592d1631 L |
5775 | { Bad_Opcode }, |
5776 | { Bad_Opcode }, | |
5777 | { Bad_Opcode }, | |
5778 | { Bad_Opcode }, | |
5779 | { Bad_Opcode }, | |
5780 | { Bad_Opcode }, | |
5781 | { Bad_Opcode }, | |
5782 | { Bad_Opcode }, | |
f88c9eb0 SP |
5783 | /* 40 */ |
5784 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
5785 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
5786 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 5787 | { Bad_Opcode }, |
f88c9eb0 | 5788 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
5789 | { Bad_Opcode }, |
5790 | { Bad_Opcode }, | |
5791 | { Bad_Opcode }, | |
f88c9eb0 | 5792 | /* 48 */ |
592d1631 L |
5793 | { Bad_Opcode }, |
5794 | { Bad_Opcode }, | |
5795 | { Bad_Opcode }, | |
5796 | { Bad_Opcode }, | |
5797 | { Bad_Opcode }, | |
5798 | { Bad_Opcode }, | |
5799 | { Bad_Opcode }, | |
5800 | { Bad_Opcode }, | |
f88c9eb0 | 5801 | /* 50 */ |
592d1631 L |
5802 | { Bad_Opcode }, |
5803 | { Bad_Opcode }, | |
5804 | { Bad_Opcode }, | |
5805 | { Bad_Opcode }, | |
5806 | { Bad_Opcode }, | |
5807 | { Bad_Opcode }, | |
5808 | { Bad_Opcode }, | |
5809 | { Bad_Opcode }, | |
f88c9eb0 | 5810 | /* 58 */ |
592d1631 L |
5811 | { Bad_Opcode }, |
5812 | { Bad_Opcode }, | |
5813 | { Bad_Opcode }, | |
5814 | { Bad_Opcode }, | |
5815 | { Bad_Opcode }, | |
5816 | { Bad_Opcode }, | |
5817 | { Bad_Opcode }, | |
5818 | { Bad_Opcode }, | |
f88c9eb0 SP |
5819 | /* 60 */ |
5820 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
5821 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
5822 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
5823 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
5824 | { Bad_Opcode }, |
5825 | { Bad_Opcode }, | |
5826 | { Bad_Opcode }, | |
5827 | { Bad_Opcode }, | |
f88c9eb0 | 5828 | /* 68 */ |
592d1631 L |
5829 | { Bad_Opcode }, |
5830 | { Bad_Opcode }, | |
5831 | { Bad_Opcode }, | |
5832 | { Bad_Opcode }, | |
5833 | { Bad_Opcode }, | |
5834 | { Bad_Opcode }, | |
5835 | { Bad_Opcode }, | |
5836 | { Bad_Opcode }, | |
f88c9eb0 | 5837 | /* 70 */ |
592d1631 L |
5838 | { Bad_Opcode }, |
5839 | { Bad_Opcode }, | |
5840 | { Bad_Opcode }, | |
5841 | { Bad_Opcode }, | |
5842 | { Bad_Opcode }, | |
5843 | { Bad_Opcode }, | |
5844 | { Bad_Opcode }, | |
5845 | { Bad_Opcode }, | |
f88c9eb0 | 5846 | /* 78 */ |
592d1631 L |
5847 | { Bad_Opcode }, |
5848 | { Bad_Opcode }, | |
5849 | { Bad_Opcode }, | |
5850 | { Bad_Opcode }, | |
5851 | { Bad_Opcode }, | |
5852 | { Bad_Opcode }, | |
5853 | { Bad_Opcode }, | |
5854 | { Bad_Opcode }, | |
f88c9eb0 | 5855 | /* 80 */ |
592d1631 L |
5856 | { Bad_Opcode }, |
5857 | { Bad_Opcode }, | |
5858 | { Bad_Opcode }, | |
5859 | { Bad_Opcode }, | |
5860 | { Bad_Opcode }, | |
5861 | { Bad_Opcode }, | |
5862 | { Bad_Opcode }, | |
5863 | { Bad_Opcode }, | |
f88c9eb0 | 5864 | /* 88 */ |
592d1631 L |
5865 | { Bad_Opcode }, |
5866 | { Bad_Opcode }, | |
5867 | { Bad_Opcode }, | |
5868 | { Bad_Opcode }, | |
5869 | { Bad_Opcode }, | |
5870 | { Bad_Opcode }, | |
5871 | { Bad_Opcode }, | |
5872 | { Bad_Opcode }, | |
f88c9eb0 | 5873 | /* 90 */ |
592d1631 L |
5874 | { Bad_Opcode }, |
5875 | { Bad_Opcode }, | |
5876 | { Bad_Opcode }, | |
5877 | { Bad_Opcode }, | |
5878 | { Bad_Opcode }, | |
5879 | { Bad_Opcode }, | |
5880 | { Bad_Opcode }, | |
5881 | { Bad_Opcode }, | |
f88c9eb0 | 5882 | /* 98 */ |
592d1631 L |
5883 | { Bad_Opcode }, |
5884 | { Bad_Opcode }, | |
5885 | { Bad_Opcode }, | |
5886 | { Bad_Opcode }, | |
5887 | { Bad_Opcode }, | |
5888 | { Bad_Opcode }, | |
5889 | { Bad_Opcode }, | |
5890 | { Bad_Opcode }, | |
f88c9eb0 | 5891 | /* a0 */ |
592d1631 L |
5892 | { Bad_Opcode }, |
5893 | { Bad_Opcode }, | |
5894 | { Bad_Opcode }, | |
5895 | { Bad_Opcode }, | |
5896 | { Bad_Opcode }, | |
5897 | { Bad_Opcode }, | |
5898 | { Bad_Opcode }, | |
5899 | { Bad_Opcode }, | |
f88c9eb0 | 5900 | /* a8 */ |
592d1631 L |
5901 | { Bad_Opcode }, |
5902 | { Bad_Opcode }, | |
5903 | { Bad_Opcode }, | |
5904 | { Bad_Opcode }, | |
5905 | { Bad_Opcode }, | |
5906 | { Bad_Opcode }, | |
5907 | { Bad_Opcode }, | |
5908 | { Bad_Opcode }, | |
f88c9eb0 | 5909 | /* b0 */ |
592d1631 L |
5910 | { Bad_Opcode }, |
5911 | { Bad_Opcode }, | |
5912 | { Bad_Opcode }, | |
5913 | { Bad_Opcode }, | |
5914 | { Bad_Opcode }, | |
5915 | { Bad_Opcode }, | |
5916 | { Bad_Opcode }, | |
5917 | { Bad_Opcode }, | |
f88c9eb0 | 5918 | /* b8 */ |
592d1631 L |
5919 | { Bad_Opcode }, |
5920 | { Bad_Opcode }, | |
5921 | { Bad_Opcode }, | |
5922 | { Bad_Opcode }, | |
5923 | { Bad_Opcode }, | |
5924 | { Bad_Opcode }, | |
5925 | { Bad_Opcode }, | |
5926 | { Bad_Opcode }, | |
f88c9eb0 | 5927 | /* c0 */ |
592d1631 L |
5928 | { Bad_Opcode }, |
5929 | { Bad_Opcode }, | |
5930 | { Bad_Opcode }, | |
5931 | { Bad_Opcode }, | |
5932 | { Bad_Opcode }, | |
5933 | { Bad_Opcode }, | |
5934 | { Bad_Opcode }, | |
5935 | { Bad_Opcode }, | |
f88c9eb0 | 5936 | /* c8 */ |
592d1631 L |
5937 | { Bad_Opcode }, |
5938 | { Bad_Opcode }, | |
5939 | { Bad_Opcode }, | |
5940 | { Bad_Opcode }, | |
5941 | { Bad_Opcode }, | |
5942 | { Bad_Opcode }, | |
5943 | { Bad_Opcode }, | |
5944 | { Bad_Opcode }, | |
f88c9eb0 | 5945 | /* d0 */ |
592d1631 L |
5946 | { Bad_Opcode }, |
5947 | { Bad_Opcode }, | |
5948 | { Bad_Opcode }, | |
5949 | { Bad_Opcode }, | |
5950 | { Bad_Opcode }, | |
5951 | { Bad_Opcode }, | |
5952 | { Bad_Opcode }, | |
5953 | { Bad_Opcode }, | |
f88c9eb0 | 5954 | /* d8 */ |
592d1631 L |
5955 | { Bad_Opcode }, |
5956 | { Bad_Opcode }, | |
5957 | { Bad_Opcode }, | |
5958 | { Bad_Opcode }, | |
5959 | { Bad_Opcode }, | |
5960 | { Bad_Opcode }, | |
5961 | { Bad_Opcode }, | |
f88c9eb0 SP |
5962 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
5963 | /* e0 */ | |
592d1631 L |
5964 | { Bad_Opcode }, |
5965 | { Bad_Opcode }, | |
5966 | { Bad_Opcode }, | |
5967 | { Bad_Opcode }, | |
5968 | { Bad_Opcode }, | |
5969 | { Bad_Opcode }, | |
5970 | { Bad_Opcode }, | |
5971 | { Bad_Opcode }, | |
f88c9eb0 | 5972 | /* e8 */ |
592d1631 L |
5973 | { Bad_Opcode }, |
5974 | { Bad_Opcode }, | |
5975 | { Bad_Opcode }, | |
5976 | { Bad_Opcode }, | |
5977 | { Bad_Opcode }, | |
5978 | { Bad_Opcode }, | |
5979 | { Bad_Opcode }, | |
5980 | { Bad_Opcode }, | |
f88c9eb0 | 5981 | /* f0 */ |
592d1631 L |
5982 | { Bad_Opcode }, |
5983 | { Bad_Opcode }, | |
5984 | { Bad_Opcode }, | |
5985 | { Bad_Opcode }, | |
5986 | { Bad_Opcode }, | |
5987 | { Bad_Opcode }, | |
5988 | { Bad_Opcode }, | |
5989 | { Bad_Opcode }, | |
f88c9eb0 | 5990 | /* f8 */ |
592d1631 L |
5991 | { Bad_Opcode }, |
5992 | { Bad_Opcode }, | |
5993 | { Bad_Opcode }, | |
5994 | { Bad_Opcode }, | |
5995 | { Bad_Opcode }, | |
5996 | { Bad_Opcode }, | |
5997 | { Bad_Opcode }, | |
5998 | { Bad_Opcode }, | |
f88c9eb0 SP |
5999 | }, |
6000 | ||
6001 | /* THREE_BYTE_0F7A */ | |
6002 | { | |
6003 | /* 00 */ | |
592d1631 L |
6004 | { Bad_Opcode }, |
6005 | { Bad_Opcode }, | |
6006 | { Bad_Opcode }, | |
6007 | { Bad_Opcode }, | |
6008 | { Bad_Opcode }, | |
6009 | { Bad_Opcode }, | |
6010 | { Bad_Opcode }, | |
6011 | { Bad_Opcode }, | |
f88c9eb0 | 6012 | /* 08 */ |
592d1631 L |
6013 | { Bad_Opcode }, |
6014 | { Bad_Opcode }, | |
6015 | { Bad_Opcode }, | |
6016 | { Bad_Opcode }, | |
6017 | { Bad_Opcode }, | |
6018 | { Bad_Opcode }, | |
6019 | { Bad_Opcode }, | |
6020 | { Bad_Opcode }, | |
f88c9eb0 | 6021 | /* 10 */ |
592d1631 L |
6022 | { Bad_Opcode }, |
6023 | { Bad_Opcode }, | |
6024 | { Bad_Opcode }, | |
6025 | { Bad_Opcode }, | |
6026 | { Bad_Opcode }, | |
6027 | { Bad_Opcode }, | |
6028 | { Bad_Opcode }, | |
6029 | { Bad_Opcode }, | |
f88c9eb0 | 6030 | /* 18 */ |
592d1631 L |
6031 | { Bad_Opcode }, |
6032 | { Bad_Opcode }, | |
6033 | { Bad_Opcode }, | |
6034 | { Bad_Opcode }, | |
6035 | { Bad_Opcode }, | |
6036 | { Bad_Opcode }, | |
6037 | { Bad_Opcode }, | |
6038 | { Bad_Opcode }, | |
f88c9eb0 SP |
6039 | /* 20 */ |
6040 | { "ptest", { XX } }, | |
592d1631 L |
6041 | { Bad_Opcode }, |
6042 | { Bad_Opcode }, | |
6043 | { Bad_Opcode }, | |
6044 | { Bad_Opcode }, | |
6045 | { Bad_Opcode }, | |
6046 | { Bad_Opcode }, | |
6047 | { Bad_Opcode }, | |
f88c9eb0 | 6048 | /* 28 */ |
592d1631 L |
6049 | { Bad_Opcode }, |
6050 | { Bad_Opcode }, | |
6051 | { Bad_Opcode }, | |
6052 | { Bad_Opcode }, | |
6053 | { Bad_Opcode }, | |
6054 | { Bad_Opcode }, | |
6055 | { Bad_Opcode }, | |
6056 | { Bad_Opcode }, | |
f88c9eb0 | 6057 | /* 30 */ |
592d1631 L |
6058 | { Bad_Opcode }, |
6059 | { Bad_Opcode }, | |
6060 | { Bad_Opcode }, | |
6061 | { Bad_Opcode }, | |
6062 | { Bad_Opcode }, | |
6063 | { Bad_Opcode }, | |
6064 | { Bad_Opcode }, | |
6065 | { Bad_Opcode }, | |
f88c9eb0 | 6066 | /* 38 */ |
592d1631 L |
6067 | { Bad_Opcode }, |
6068 | { Bad_Opcode }, | |
6069 | { Bad_Opcode }, | |
6070 | { Bad_Opcode }, | |
6071 | { Bad_Opcode }, | |
6072 | { Bad_Opcode }, | |
6073 | { Bad_Opcode }, | |
6074 | { Bad_Opcode }, | |
f88c9eb0 | 6075 | /* 40 */ |
592d1631 | 6076 | { Bad_Opcode }, |
f88c9eb0 SP |
6077 | { "phaddbw", { XM, EXq } }, |
6078 | { "phaddbd", { XM, EXq } }, | |
6079 | { "phaddbq", { XM, EXq } }, | |
592d1631 L |
6080 | { Bad_Opcode }, |
6081 | { Bad_Opcode }, | |
f88c9eb0 SP |
6082 | { "phaddwd", { XM, EXq } }, |
6083 | { "phaddwq", { XM, EXq } }, | |
6084 | /* 48 */ | |
592d1631 L |
6085 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, | |
6087 | { Bad_Opcode }, | |
f88c9eb0 | 6088 | { "phadddq", { XM, EXq } }, |
592d1631 L |
6089 | { Bad_Opcode }, |
6090 | { Bad_Opcode }, | |
6091 | { Bad_Opcode }, | |
6092 | { Bad_Opcode }, | |
f88c9eb0 | 6093 | /* 50 */ |
592d1631 | 6094 | { Bad_Opcode }, |
f88c9eb0 SP |
6095 | { "phaddubw", { XM, EXq } }, |
6096 | { "phaddubd", { XM, EXq } }, | |
6097 | { "phaddubq", { XM, EXq } }, | |
592d1631 L |
6098 | { Bad_Opcode }, |
6099 | { Bad_Opcode }, | |
f88c9eb0 SP |
6100 | { "phadduwd", { XM, EXq } }, |
6101 | { "phadduwq", { XM, EXq } }, | |
6102 | /* 58 */ | |
592d1631 L |
6103 | { Bad_Opcode }, |
6104 | { Bad_Opcode }, | |
6105 | { Bad_Opcode }, | |
f88c9eb0 | 6106 | { "phaddudq", { XM, EXq } }, |
592d1631 L |
6107 | { Bad_Opcode }, |
6108 | { Bad_Opcode }, | |
6109 | { Bad_Opcode }, | |
6110 | { Bad_Opcode }, | |
f88c9eb0 | 6111 | /* 60 */ |
592d1631 | 6112 | { Bad_Opcode }, |
f88c9eb0 SP |
6113 | { "phsubbw", { XM, EXq } }, |
6114 | { "phsubbd", { XM, EXq } }, | |
6115 | { "phsubbq", { XM, EXq } }, | |
592d1631 L |
6116 | { Bad_Opcode }, |
6117 | { Bad_Opcode }, | |
6118 | { Bad_Opcode }, | |
6119 | { Bad_Opcode }, | |
4e7d34a6 | 6120 | /* 68 */ |
592d1631 L |
6121 | { Bad_Opcode }, |
6122 | { Bad_Opcode }, | |
6123 | { Bad_Opcode }, | |
6124 | { Bad_Opcode }, | |
6125 | { Bad_Opcode }, | |
6126 | { Bad_Opcode }, | |
6127 | { Bad_Opcode }, | |
6128 | { Bad_Opcode }, | |
85f10a01 | 6129 | /* 70 */ |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
6132 | { Bad_Opcode }, | |
6133 | { Bad_Opcode }, | |
6134 | { Bad_Opcode }, | |
6135 | { Bad_Opcode }, | |
6136 | { Bad_Opcode }, | |
6137 | { Bad_Opcode }, | |
85f10a01 | 6138 | /* 78 */ |
592d1631 L |
6139 | { Bad_Opcode }, |
6140 | { Bad_Opcode }, | |
6141 | { Bad_Opcode }, | |
6142 | { Bad_Opcode }, | |
6143 | { Bad_Opcode }, | |
6144 | { Bad_Opcode }, | |
6145 | { Bad_Opcode }, | |
6146 | { Bad_Opcode }, | |
85f10a01 | 6147 | /* 80 */ |
592d1631 L |
6148 | { Bad_Opcode }, |
6149 | { Bad_Opcode }, | |
6150 | { Bad_Opcode }, | |
6151 | { Bad_Opcode }, | |
6152 | { Bad_Opcode }, | |
6153 | { Bad_Opcode }, | |
6154 | { Bad_Opcode }, | |
6155 | { Bad_Opcode }, | |
85f10a01 | 6156 | /* 88 */ |
592d1631 L |
6157 | { Bad_Opcode }, |
6158 | { Bad_Opcode }, | |
6159 | { Bad_Opcode }, | |
6160 | { Bad_Opcode }, | |
6161 | { Bad_Opcode }, | |
6162 | { Bad_Opcode }, | |
6163 | { Bad_Opcode }, | |
6164 | { Bad_Opcode }, | |
85f10a01 | 6165 | /* 90 */ |
592d1631 L |
6166 | { Bad_Opcode }, |
6167 | { Bad_Opcode }, | |
6168 | { Bad_Opcode }, | |
6169 | { Bad_Opcode }, | |
6170 | { Bad_Opcode }, | |
6171 | { Bad_Opcode }, | |
6172 | { Bad_Opcode }, | |
6173 | { Bad_Opcode }, | |
85f10a01 | 6174 | /* 98 */ |
592d1631 L |
6175 | { Bad_Opcode }, |
6176 | { Bad_Opcode }, | |
6177 | { Bad_Opcode }, | |
6178 | { Bad_Opcode }, | |
6179 | { Bad_Opcode }, | |
6180 | { Bad_Opcode }, | |
6181 | { Bad_Opcode }, | |
6182 | { Bad_Opcode }, | |
85f10a01 | 6183 | /* a0 */ |
592d1631 L |
6184 | { Bad_Opcode }, |
6185 | { Bad_Opcode }, | |
6186 | { Bad_Opcode }, | |
6187 | { Bad_Opcode }, | |
6188 | { Bad_Opcode }, | |
6189 | { Bad_Opcode }, | |
6190 | { Bad_Opcode }, | |
6191 | { Bad_Opcode }, | |
85f10a01 | 6192 | /* a8 */ |
592d1631 L |
6193 | { Bad_Opcode }, |
6194 | { Bad_Opcode }, | |
6195 | { Bad_Opcode }, | |
6196 | { Bad_Opcode }, | |
6197 | { Bad_Opcode }, | |
6198 | { Bad_Opcode }, | |
6199 | { Bad_Opcode }, | |
6200 | { Bad_Opcode }, | |
85f10a01 | 6201 | /* b0 */ |
592d1631 L |
6202 | { Bad_Opcode }, |
6203 | { Bad_Opcode }, | |
6204 | { Bad_Opcode }, | |
6205 | { Bad_Opcode }, | |
6206 | { Bad_Opcode }, | |
6207 | { Bad_Opcode }, | |
6208 | { Bad_Opcode }, | |
6209 | { Bad_Opcode }, | |
85f10a01 | 6210 | /* b8 */ |
592d1631 L |
6211 | { Bad_Opcode }, |
6212 | { Bad_Opcode }, | |
6213 | { Bad_Opcode }, | |
6214 | { Bad_Opcode }, | |
6215 | { Bad_Opcode }, | |
6216 | { Bad_Opcode }, | |
6217 | { Bad_Opcode }, | |
6218 | { Bad_Opcode }, | |
85f10a01 | 6219 | /* c0 */ |
592d1631 L |
6220 | { Bad_Opcode }, |
6221 | { Bad_Opcode }, | |
6222 | { Bad_Opcode }, | |
6223 | { Bad_Opcode }, | |
6224 | { Bad_Opcode }, | |
6225 | { Bad_Opcode }, | |
6226 | { Bad_Opcode }, | |
6227 | { Bad_Opcode }, | |
85f10a01 | 6228 | /* c8 */ |
592d1631 L |
6229 | { Bad_Opcode }, |
6230 | { Bad_Opcode }, | |
6231 | { Bad_Opcode }, | |
6232 | { Bad_Opcode }, | |
6233 | { Bad_Opcode }, | |
6234 | { Bad_Opcode }, | |
6235 | { Bad_Opcode }, | |
6236 | { Bad_Opcode }, | |
85f10a01 | 6237 | /* d0 */ |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
6240 | { Bad_Opcode }, | |
6241 | { Bad_Opcode }, | |
6242 | { Bad_Opcode }, | |
6243 | { Bad_Opcode }, | |
6244 | { Bad_Opcode }, | |
6245 | { Bad_Opcode }, | |
85f10a01 | 6246 | /* d8 */ |
592d1631 L |
6247 | { Bad_Opcode }, |
6248 | { Bad_Opcode }, | |
6249 | { Bad_Opcode }, | |
6250 | { Bad_Opcode }, | |
6251 | { Bad_Opcode }, | |
6252 | { Bad_Opcode }, | |
6253 | { Bad_Opcode }, | |
6254 | { Bad_Opcode }, | |
85f10a01 | 6255 | /* e0 */ |
592d1631 L |
6256 | { Bad_Opcode }, |
6257 | { Bad_Opcode }, | |
6258 | { Bad_Opcode }, | |
6259 | { Bad_Opcode }, | |
6260 | { Bad_Opcode }, | |
6261 | { Bad_Opcode }, | |
6262 | { Bad_Opcode }, | |
6263 | { Bad_Opcode }, | |
85f10a01 | 6264 | /* e8 */ |
592d1631 L |
6265 | { Bad_Opcode }, |
6266 | { Bad_Opcode }, | |
6267 | { Bad_Opcode }, | |
6268 | { Bad_Opcode }, | |
6269 | { Bad_Opcode }, | |
6270 | { Bad_Opcode }, | |
6271 | { Bad_Opcode }, | |
6272 | { Bad_Opcode }, | |
85f10a01 | 6273 | /* f0 */ |
592d1631 L |
6274 | { Bad_Opcode }, |
6275 | { Bad_Opcode }, | |
6276 | { Bad_Opcode }, | |
6277 | { Bad_Opcode }, | |
6278 | { Bad_Opcode }, | |
6279 | { Bad_Opcode }, | |
6280 | { Bad_Opcode }, | |
6281 | { Bad_Opcode }, | |
85f10a01 | 6282 | /* f8 */ |
592d1631 L |
6283 | { Bad_Opcode }, |
6284 | { Bad_Opcode }, | |
6285 | { Bad_Opcode }, | |
6286 | { Bad_Opcode }, | |
6287 | { Bad_Opcode }, | |
6288 | { Bad_Opcode }, | |
6289 | { Bad_Opcode }, | |
6290 | { Bad_Opcode }, | |
85f10a01 | 6291 | }, |
f88c9eb0 SP |
6292 | }; |
6293 | ||
6294 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 6295 | /* XOP_08 */ |
85f10a01 MM |
6296 | { |
6297 | /* 00 */ | |
592d1631 L |
6298 | { Bad_Opcode }, |
6299 | { Bad_Opcode }, | |
6300 | { Bad_Opcode }, | |
6301 | { Bad_Opcode }, | |
6302 | { Bad_Opcode }, | |
6303 | { Bad_Opcode }, | |
6304 | { Bad_Opcode }, | |
6305 | { Bad_Opcode }, | |
85f10a01 | 6306 | /* 08 */ |
592d1631 L |
6307 | { Bad_Opcode }, |
6308 | { Bad_Opcode }, | |
6309 | { Bad_Opcode }, | |
6310 | { Bad_Opcode }, | |
6311 | { Bad_Opcode }, | |
6312 | { Bad_Opcode }, | |
6313 | { Bad_Opcode }, | |
6314 | { Bad_Opcode }, | |
85f10a01 | 6315 | /* 10 */ |
592d1631 L |
6316 | { Bad_Opcode }, |
6317 | { Bad_Opcode }, | |
6318 | { Bad_Opcode }, | |
6319 | { Bad_Opcode }, | |
6320 | { Bad_Opcode }, | |
6321 | { Bad_Opcode }, | |
6322 | { Bad_Opcode }, | |
6323 | { Bad_Opcode }, | |
85f10a01 | 6324 | /* 18 */ |
592d1631 L |
6325 | { Bad_Opcode }, |
6326 | { Bad_Opcode }, | |
6327 | { Bad_Opcode }, | |
6328 | { Bad_Opcode }, | |
6329 | { Bad_Opcode }, | |
6330 | { Bad_Opcode }, | |
6331 | { Bad_Opcode }, | |
6332 | { Bad_Opcode }, | |
85f10a01 | 6333 | /* 20 */ |
592d1631 L |
6334 | { Bad_Opcode }, |
6335 | { Bad_Opcode }, | |
6336 | { Bad_Opcode }, | |
6337 | { Bad_Opcode }, | |
6338 | { Bad_Opcode }, | |
6339 | { Bad_Opcode }, | |
6340 | { Bad_Opcode }, | |
6341 | { Bad_Opcode }, | |
85f10a01 | 6342 | /* 28 */ |
592d1631 L |
6343 | { Bad_Opcode }, |
6344 | { Bad_Opcode }, | |
6345 | { Bad_Opcode }, | |
6346 | { Bad_Opcode }, | |
6347 | { Bad_Opcode }, | |
6348 | { Bad_Opcode }, | |
6349 | { Bad_Opcode }, | |
6350 | { Bad_Opcode }, | |
c0f3af97 | 6351 | /* 30 */ |
592d1631 L |
6352 | { Bad_Opcode }, |
6353 | { Bad_Opcode }, | |
6354 | { Bad_Opcode }, | |
6355 | { Bad_Opcode }, | |
6356 | { Bad_Opcode }, | |
6357 | { Bad_Opcode }, | |
6358 | { Bad_Opcode }, | |
6359 | { Bad_Opcode }, | |
c0f3af97 | 6360 | /* 38 */ |
592d1631 L |
6361 | { Bad_Opcode }, |
6362 | { Bad_Opcode }, | |
6363 | { Bad_Opcode }, | |
6364 | { Bad_Opcode }, | |
6365 | { Bad_Opcode }, | |
6366 | { Bad_Opcode }, | |
6367 | { Bad_Opcode }, | |
6368 | { Bad_Opcode }, | |
c0f3af97 | 6369 | /* 40 */ |
592d1631 L |
6370 | { Bad_Opcode }, |
6371 | { Bad_Opcode }, | |
6372 | { Bad_Opcode }, | |
6373 | { Bad_Opcode }, | |
6374 | { Bad_Opcode }, | |
6375 | { Bad_Opcode }, | |
6376 | { Bad_Opcode }, | |
6377 | { Bad_Opcode }, | |
85f10a01 | 6378 | /* 48 */ |
592d1631 L |
6379 | { Bad_Opcode }, |
6380 | { Bad_Opcode }, | |
6381 | { Bad_Opcode }, | |
6382 | { Bad_Opcode }, | |
6383 | { Bad_Opcode }, | |
6384 | { Bad_Opcode }, | |
6385 | { Bad_Opcode }, | |
6386 | { Bad_Opcode }, | |
c0f3af97 | 6387 | /* 50 */ |
592d1631 L |
6388 | { Bad_Opcode }, |
6389 | { Bad_Opcode }, | |
6390 | { Bad_Opcode }, | |
6391 | { Bad_Opcode }, | |
6392 | { Bad_Opcode }, | |
6393 | { Bad_Opcode }, | |
6394 | { Bad_Opcode }, | |
6395 | { Bad_Opcode }, | |
85f10a01 | 6396 | /* 58 */ |
592d1631 L |
6397 | { Bad_Opcode }, |
6398 | { Bad_Opcode }, | |
6399 | { Bad_Opcode }, | |
6400 | { Bad_Opcode }, | |
6401 | { Bad_Opcode }, | |
6402 | { Bad_Opcode }, | |
6403 | { Bad_Opcode }, | |
6404 | { Bad_Opcode }, | |
c1e679ec | 6405 | /* 60 */ |
592d1631 L |
6406 | { Bad_Opcode }, |
6407 | { Bad_Opcode }, | |
6408 | { Bad_Opcode }, | |
6409 | { Bad_Opcode }, | |
6410 | { Bad_Opcode }, | |
6411 | { Bad_Opcode }, | |
6412 | { Bad_Opcode }, | |
6413 | { Bad_Opcode }, | |
c0f3af97 | 6414 | /* 68 */ |
592d1631 L |
6415 | { Bad_Opcode }, |
6416 | { Bad_Opcode }, | |
6417 | { Bad_Opcode }, | |
6418 | { Bad_Opcode }, | |
6419 | { Bad_Opcode }, | |
6420 | { Bad_Opcode }, | |
6421 | { Bad_Opcode }, | |
6422 | { Bad_Opcode }, | |
85f10a01 | 6423 | /* 70 */ |
592d1631 L |
6424 | { Bad_Opcode }, |
6425 | { Bad_Opcode }, | |
6426 | { Bad_Opcode }, | |
6427 | { Bad_Opcode }, | |
6428 | { Bad_Opcode }, | |
6429 | { Bad_Opcode }, | |
6430 | { Bad_Opcode }, | |
6431 | { Bad_Opcode }, | |
85f10a01 | 6432 | /* 78 */ |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
6435 | { Bad_Opcode }, | |
6436 | { Bad_Opcode }, | |
6437 | { Bad_Opcode }, | |
6438 | { Bad_Opcode }, | |
6439 | { Bad_Opcode }, | |
6440 | { Bad_Opcode }, | |
85f10a01 | 6441 | /* 80 */ |
592d1631 L |
6442 | { Bad_Opcode }, |
6443 | { Bad_Opcode }, | |
6444 | { Bad_Opcode }, | |
6445 | { Bad_Opcode }, | |
6446 | { Bad_Opcode }, | |
5dd85c99 SP |
6447 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6448 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6449 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6450 | /* 88 */ | |
592d1631 L |
6451 | { Bad_Opcode }, |
6452 | { Bad_Opcode }, | |
6453 | { Bad_Opcode }, | |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { Bad_Opcode }, | |
5dd85c99 SP |
6457 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6458 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6459 | /* 90 */ | |
592d1631 L |
6460 | { Bad_Opcode }, |
6461 | { Bad_Opcode }, | |
6462 | { Bad_Opcode }, | |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
5dd85c99 SP |
6465 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6466 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6467 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6468 | /* 98 */ | |
592d1631 L |
6469 | { Bad_Opcode }, |
6470 | { Bad_Opcode }, | |
6471 | { Bad_Opcode }, | |
6472 | { Bad_Opcode }, | |
6473 | { Bad_Opcode }, | |
6474 | { Bad_Opcode }, | |
5dd85c99 SP |
6475 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6476 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6477 | /* a0 */ | |
592d1631 L |
6478 | { Bad_Opcode }, |
6479 | { Bad_Opcode }, | |
5dd85c99 SP |
6480 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6481 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
592d1631 L |
6482 | { Bad_Opcode }, |
6483 | { Bad_Opcode }, | |
5dd85c99 | 6484 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6485 | { Bad_Opcode }, |
5dd85c99 | 6486 | /* a8 */ |
592d1631 L |
6487 | { Bad_Opcode }, |
6488 | { Bad_Opcode }, | |
6489 | { Bad_Opcode }, | |
6490 | { Bad_Opcode }, | |
6491 | { Bad_Opcode }, | |
6492 | { Bad_Opcode }, | |
6493 | { Bad_Opcode }, | |
6494 | { Bad_Opcode }, | |
5dd85c99 | 6495 | /* b0 */ |
592d1631 L |
6496 | { Bad_Opcode }, |
6497 | { Bad_Opcode }, | |
6498 | { Bad_Opcode }, | |
6499 | { Bad_Opcode }, | |
6500 | { Bad_Opcode }, | |
6501 | { Bad_Opcode }, | |
5dd85c99 | 6502 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6503 | { Bad_Opcode }, |
5dd85c99 | 6504 | /* b8 */ |
592d1631 L |
6505 | { Bad_Opcode }, |
6506 | { Bad_Opcode }, | |
6507 | { Bad_Opcode }, | |
6508 | { Bad_Opcode }, | |
6509 | { Bad_Opcode }, | |
6510 | { Bad_Opcode }, | |
6511 | { Bad_Opcode }, | |
6512 | { Bad_Opcode }, | |
5dd85c99 SP |
6513 | /* c0 */ |
6514 | { "vprotb", { XM, Vex_2src_1, Ib } }, | |
6515 | { "vprotw", { XM, Vex_2src_1, Ib } }, | |
6516 | { "vprotd", { XM, Vex_2src_1, Ib } }, | |
6517 | { "vprotq", { XM, Vex_2src_1, Ib } }, | |
592d1631 L |
6518 | { Bad_Opcode }, |
6519 | { Bad_Opcode }, | |
6520 | { Bad_Opcode }, | |
6521 | { Bad_Opcode }, | |
5dd85c99 | 6522 | /* c8 */ |
592d1631 L |
6523 | { Bad_Opcode }, |
6524 | { Bad_Opcode }, | |
6525 | { Bad_Opcode }, | |
6526 | { Bad_Opcode }, | |
5dd85c99 SP |
6527 | { "vpcomb", { XM, Vex128, EXx, Ib } }, |
6528 | { "vpcomw", { XM, Vex128, EXx, Ib } }, | |
6529 | { "vpcomd", { XM, Vex128, EXx, Ib } }, | |
6530 | { "vpcomq", { XM, Vex128, EXx, Ib } }, | |
6531 | /* d0 */ | |
592d1631 L |
6532 | { Bad_Opcode }, |
6533 | { Bad_Opcode }, | |
6534 | { Bad_Opcode }, | |
6535 | { Bad_Opcode }, | |
6536 | { Bad_Opcode }, | |
6537 | { Bad_Opcode }, | |
6538 | { Bad_Opcode }, | |
6539 | { Bad_Opcode }, | |
5dd85c99 | 6540 | /* d8 */ |
592d1631 L |
6541 | { Bad_Opcode }, |
6542 | { Bad_Opcode }, | |
6543 | { Bad_Opcode }, | |
6544 | { Bad_Opcode }, | |
6545 | { Bad_Opcode }, | |
6546 | { Bad_Opcode }, | |
6547 | { Bad_Opcode }, | |
6548 | { Bad_Opcode }, | |
5dd85c99 | 6549 | /* e0 */ |
592d1631 L |
6550 | { Bad_Opcode }, |
6551 | { Bad_Opcode }, | |
6552 | { Bad_Opcode }, | |
6553 | { Bad_Opcode }, | |
6554 | { Bad_Opcode }, | |
6555 | { Bad_Opcode }, | |
6556 | { Bad_Opcode }, | |
6557 | { Bad_Opcode }, | |
5dd85c99 | 6558 | /* e8 */ |
592d1631 L |
6559 | { Bad_Opcode }, |
6560 | { Bad_Opcode }, | |
6561 | { Bad_Opcode }, | |
6562 | { Bad_Opcode }, | |
5dd85c99 SP |
6563 | { "vpcomub", { XM, Vex128, EXx, Ib } }, |
6564 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, | |
6565 | { "vpcomud", { XM, Vex128, EXx, Ib } }, | |
6566 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, | |
6567 | /* f0 */ | |
592d1631 L |
6568 | { Bad_Opcode }, |
6569 | { Bad_Opcode }, | |
6570 | { Bad_Opcode }, | |
6571 | { Bad_Opcode }, | |
6572 | { Bad_Opcode }, | |
6573 | { Bad_Opcode }, | |
6574 | { Bad_Opcode }, | |
6575 | { Bad_Opcode }, | |
5dd85c99 | 6576 | /* f8 */ |
592d1631 L |
6577 | { Bad_Opcode }, |
6578 | { Bad_Opcode }, | |
6579 | { Bad_Opcode }, | |
6580 | { Bad_Opcode }, | |
6581 | { Bad_Opcode }, | |
6582 | { Bad_Opcode }, | |
6583 | { Bad_Opcode }, | |
6584 | { Bad_Opcode }, | |
5dd85c99 SP |
6585 | }, |
6586 | /* XOP_09 */ | |
6587 | { | |
6588 | /* 00 */ | |
592d1631 L |
6589 | { Bad_Opcode }, |
6590 | { Bad_Opcode }, | |
6591 | { Bad_Opcode }, | |
6592 | { Bad_Opcode }, | |
6593 | { Bad_Opcode }, | |
6594 | { Bad_Opcode }, | |
6595 | { Bad_Opcode }, | |
6596 | { Bad_Opcode }, | |
5dd85c99 | 6597 | /* 08 */ |
592d1631 L |
6598 | { Bad_Opcode }, |
6599 | { Bad_Opcode }, | |
6600 | { Bad_Opcode }, | |
6601 | { Bad_Opcode }, | |
6602 | { Bad_Opcode }, | |
6603 | { Bad_Opcode }, | |
6604 | { Bad_Opcode }, | |
6605 | { Bad_Opcode }, | |
5dd85c99 | 6606 | /* 10 */ |
592d1631 L |
6607 | { Bad_Opcode }, |
6608 | { Bad_Opcode }, | |
5dd85c99 | 6609 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
6610 | { Bad_Opcode }, |
6611 | { Bad_Opcode }, | |
6612 | { Bad_Opcode }, | |
6613 | { Bad_Opcode }, | |
6614 | { Bad_Opcode }, | |
5dd85c99 | 6615 | /* 18 */ |
592d1631 L |
6616 | { Bad_Opcode }, |
6617 | { Bad_Opcode }, | |
6618 | { Bad_Opcode }, | |
6619 | { Bad_Opcode }, | |
6620 | { Bad_Opcode }, | |
6621 | { Bad_Opcode }, | |
6622 | { Bad_Opcode }, | |
6623 | { Bad_Opcode }, | |
5dd85c99 | 6624 | /* 20 */ |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
6627 | { Bad_Opcode }, | |
6628 | { Bad_Opcode }, | |
6629 | { Bad_Opcode }, | |
6630 | { Bad_Opcode }, | |
6631 | { Bad_Opcode }, | |
6632 | { Bad_Opcode }, | |
5dd85c99 | 6633 | /* 28 */ |
592d1631 L |
6634 | { Bad_Opcode }, |
6635 | { Bad_Opcode }, | |
6636 | { Bad_Opcode }, | |
6637 | { Bad_Opcode }, | |
6638 | { Bad_Opcode }, | |
6639 | { Bad_Opcode }, | |
6640 | { Bad_Opcode }, | |
6641 | { Bad_Opcode }, | |
5dd85c99 | 6642 | /* 30 */ |
592d1631 L |
6643 | { Bad_Opcode }, |
6644 | { Bad_Opcode }, | |
6645 | { Bad_Opcode }, | |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
6648 | { Bad_Opcode }, | |
6649 | { Bad_Opcode }, | |
6650 | { Bad_Opcode }, | |
5dd85c99 | 6651 | /* 38 */ |
592d1631 L |
6652 | { Bad_Opcode }, |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { Bad_Opcode }, | |
6656 | { Bad_Opcode }, | |
6657 | { Bad_Opcode }, | |
6658 | { Bad_Opcode }, | |
6659 | { Bad_Opcode }, | |
5dd85c99 | 6660 | /* 40 */ |
592d1631 L |
6661 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, | |
6663 | { Bad_Opcode }, | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { Bad_Opcode }, | |
6667 | { Bad_Opcode }, | |
6668 | { Bad_Opcode }, | |
5dd85c99 | 6669 | /* 48 */ |
592d1631 L |
6670 | { Bad_Opcode }, |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
6673 | { Bad_Opcode }, | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
6676 | { Bad_Opcode }, | |
6677 | { Bad_Opcode }, | |
5dd85c99 | 6678 | /* 50 */ |
592d1631 L |
6679 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
6683 | { Bad_Opcode }, | |
6684 | { Bad_Opcode }, | |
6685 | { Bad_Opcode }, | |
6686 | { Bad_Opcode }, | |
5dd85c99 | 6687 | /* 58 */ |
592d1631 L |
6688 | { Bad_Opcode }, |
6689 | { Bad_Opcode }, | |
6690 | { Bad_Opcode }, | |
6691 | { Bad_Opcode }, | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
6694 | { Bad_Opcode }, | |
6695 | { Bad_Opcode }, | |
5dd85c99 | 6696 | /* 60 */ |
592d1631 L |
6697 | { Bad_Opcode }, |
6698 | { Bad_Opcode }, | |
6699 | { Bad_Opcode }, | |
6700 | { Bad_Opcode }, | |
6701 | { Bad_Opcode }, | |
6702 | { Bad_Opcode }, | |
6703 | { Bad_Opcode }, | |
6704 | { Bad_Opcode }, | |
5dd85c99 | 6705 | /* 68 */ |
592d1631 L |
6706 | { Bad_Opcode }, |
6707 | { Bad_Opcode }, | |
6708 | { Bad_Opcode }, | |
6709 | { Bad_Opcode }, | |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
6712 | { Bad_Opcode }, | |
6713 | { Bad_Opcode }, | |
5dd85c99 | 6714 | /* 70 */ |
592d1631 L |
6715 | { Bad_Opcode }, |
6716 | { Bad_Opcode }, | |
6717 | { Bad_Opcode }, | |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
6721 | { Bad_Opcode }, | |
6722 | { Bad_Opcode }, | |
5dd85c99 | 6723 | /* 78 */ |
592d1631 L |
6724 | { Bad_Opcode }, |
6725 | { Bad_Opcode }, | |
6726 | { Bad_Opcode }, | |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
6729 | { Bad_Opcode }, | |
6730 | { Bad_Opcode }, | |
6731 | { Bad_Opcode }, | |
5dd85c99 SP |
6732 | /* 80 */ |
6733 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) }, | |
6734 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) }, | |
6735 | { "vfrczss", { XM, EXd } }, | |
6736 | { "vfrczsd", { XM, EXq } }, | |
592d1631 L |
6737 | { Bad_Opcode }, |
6738 | { Bad_Opcode }, | |
6739 | { Bad_Opcode }, | |
6740 | { Bad_Opcode }, | |
5dd85c99 | 6741 | /* 88 */ |
592d1631 L |
6742 | { Bad_Opcode }, |
6743 | { Bad_Opcode }, | |
6744 | { Bad_Opcode }, | |
6745 | { Bad_Opcode }, | |
6746 | { Bad_Opcode }, | |
6747 | { Bad_Opcode }, | |
6748 | { Bad_Opcode }, | |
6749 | { Bad_Opcode }, | |
5dd85c99 SP |
6750 | /* 90 */ |
6751 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6752 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6753 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6754 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6755 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6756 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6757 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6758 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6759 | /* 98 */ | |
6760 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6761 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6762 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, | |
6763 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
592d1631 L |
6764 | { Bad_Opcode }, |
6765 | { Bad_Opcode }, | |
6766 | { Bad_Opcode }, | |
6767 | { Bad_Opcode }, | |
5dd85c99 | 6768 | /* a0 */ |
592d1631 L |
6769 | { Bad_Opcode }, |
6770 | { Bad_Opcode }, | |
6771 | { Bad_Opcode }, | |
6772 | { Bad_Opcode }, | |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
6775 | { Bad_Opcode }, | |
6776 | { Bad_Opcode }, | |
5dd85c99 | 6777 | /* a8 */ |
592d1631 L |
6778 | { Bad_Opcode }, |
6779 | { Bad_Opcode }, | |
6780 | { Bad_Opcode }, | |
6781 | { Bad_Opcode }, | |
6782 | { Bad_Opcode }, | |
6783 | { Bad_Opcode }, | |
6784 | { Bad_Opcode }, | |
6785 | { Bad_Opcode }, | |
5dd85c99 | 6786 | /* b0 */ |
592d1631 L |
6787 | { Bad_Opcode }, |
6788 | { Bad_Opcode }, | |
6789 | { Bad_Opcode }, | |
6790 | { Bad_Opcode }, | |
6791 | { Bad_Opcode }, | |
6792 | { Bad_Opcode }, | |
6793 | { Bad_Opcode }, | |
6794 | { Bad_Opcode }, | |
5dd85c99 | 6795 | /* b8 */ |
592d1631 L |
6796 | { Bad_Opcode }, |
6797 | { Bad_Opcode }, | |
6798 | { Bad_Opcode }, | |
6799 | { Bad_Opcode }, | |
6800 | { Bad_Opcode }, | |
6801 | { Bad_Opcode }, | |
6802 | { Bad_Opcode }, | |
6803 | { Bad_Opcode }, | |
5dd85c99 | 6804 | /* c0 */ |
592d1631 | 6805 | { Bad_Opcode }, |
5dd85c99 SP |
6806 | { "vphaddbw", { XM, EXxmm } }, |
6807 | { "vphaddbd", { XM, EXxmm } }, | |
6808 | { "vphaddbq", { XM, EXxmm } }, | |
592d1631 L |
6809 | { Bad_Opcode }, |
6810 | { Bad_Opcode }, | |
5dd85c99 SP |
6811 | { "vphaddwd", { XM, EXxmm } }, |
6812 | { "vphaddwq", { XM, EXxmm } }, | |
6813 | /* c8 */ | |
592d1631 L |
6814 | { Bad_Opcode }, |
6815 | { Bad_Opcode }, | |
6816 | { Bad_Opcode }, | |
5dd85c99 | 6817 | { "vphadddq", { XM, EXxmm } }, |
592d1631 L |
6818 | { Bad_Opcode }, |
6819 | { Bad_Opcode }, | |
6820 | { Bad_Opcode }, | |
6821 | { Bad_Opcode }, | |
5dd85c99 | 6822 | /* d0 */ |
592d1631 | 6823 | { Bad_Opcode }, |
5dd85c99 SP |
6824 | { "vphaddubw", { XM, EXxmm } }, |
6825 | { "vphaddubd", { XM, EXxmm } }, | |
6826 | { "vphaddubq", { XM, EXxmm } }, | |
592d1631 L |
6827 | { Bad_Opcode }, |
6828 | { Bad_Opcode }, | |
5dd85c99 SP |
6829 | { "vphadduwd", { XM, EXxmm } }, |
6830 | { "vphadduwq", { XM, EXxmm } }, | |
6831 | /* d8 */ | |
592d1631 L |
6832 | { Bad_Opcode }, |
6833 | { Bad_Opcode }, | |
6834 | { Bad_Opcode }, | |
5dd85c99 | 6835 | { "vphaddudq", { XM, EXxmm } }, |
592d1631 L |
6836 | { Bad_Opcode }, |
6837 | { Bad_Opcode }, | |
6838 | { Bad_Opcode }, | |
6839 | { Bad_Opcode }, | |
5dd85c99 | 6840 | /* e0 */ |
592d1631 | 6841 | { Bad_Opcode }, |
5dd85c99 SP |
6842 | { "vphsubbw", { XM, EXxmm } }, |
6843 | { "vphsubwd", { XM, EXxmm } }, | |
6844 | { "vphsubdq", { XM, EXxmm } }, | |
592d1631 L |
6845 | { Bad_Opcode }, |
6846 | { Bad_Opcode }, | |
6847 | { Bad_Opcode }, | |
6848 | { Bad_Opcode }, | |
4e7d34a6 | 6849 | /* e8 */ |
592d1631 L |
6850 | { Bad_Opcode }, |
6851 | { Bad_Opcode }, | |
6852 | { Bad_Opcode }, | |
6853 | { Bad_Opcode }, | |
6854 | { Bad_Opcode }, | |
6855 | { Bad_Opcode }, | |
6856 | { Bad_Opcode }, | |
6857 | { Bad_Opcode }, | |
4e7d34a6 | 6858 | /* f0 */ |
592d1631 L |
6859 | { Bad_Opcode }, |
6860 | { Bad_Opcode }, | |
6861 | { Bad_Opcode }, | |
6862 | { Bad_Opcode }, | |
6863 | { Bad_Opcode }, | |
6864 | { Bad_Opcode }, | |
6865 | { Bad_Opcode }, | |
6866 | { Bad_Opcode }, | |
4e7d34a6 | 6867 | /* f8 */ |
592d1631 L |
6868 | { Bad_Opcode }, |
6869 | { Bad_Opcode }, | |
6870 | { Bad_Opcode }, | |
6871 | { Bad_Opcode }, | |
6872 | { Bad_Opcode }, | |
6873 | { Bad_Opcode }, | |
6874 | { Bad_Opcode }, | |
6875 | { Bad_Opcode }, | |
4e7d34a6 | 6876 | }, |
f88c9eb0 | 6877 | /* XOP_0A */ |
4e7d34a6 L |
6878 | { |
6879 | /* 00 */ | |
592d1631 L |
6880 | { Bad_Opcode }, |
6881 | { Bad_Opcode }, | |
6882 | { Bad_Opcode }, | |
6883 | { Bad_Opcode }, | |
6884 | { Bad_Opcode }, | |
6885 | { Bad_Opcode }, | |
6886 | { Bad_Opcode }, | |
6887 | { Bad_Opcode }, | |
4e7d34a6 | 6888 | /* 08 */ |
592d1631 L |
6889 | { Bad_Opcode }, |
6890 | { Bad_Opcode }, | |
6891 | { Bad_Opcode }, | |
6892 | { Bad_Opcode }, | |
6893 | { Bad_Opcode }, | |
6894 | { Bad_Opcode }, | |
6895 | { Bad_Opcode }, | |
6896 | { Bad_Opcode }, | |
4e7d34a6 | 6897 | /* 10 */ |
592d1631 L |
6898 | { Bad_Opcode }, |
6899 | { Bad_Opcode }, | |
f88c9eb0 | 6900 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
6901 | { Bad_Opcode }, |
6902 | { Bad_Opcode }, | |
6903 | { Bad_Opcode }, | |
6904 | { Bad_Opcode }, | |
6905 | { Bad_Opcode }, | |
4e7d34a6 | 6906 | /* 18 */ |
592d1631 L |
6907 | { Bad_Opcode }, |
6908 | { Bad_Opcode }, | |
6909 | { Bad_Opcode }, | |
6910 | { Bad_Opcode }, | |
6911 | { Bad_Opcode }, | |
6912 | { Bad_Opcode }, | |
6913 | { Bad_Opcode }, | |
6914 | { Bad_Opcode }, | |
4e7d34a6 | 6915 | /* 20 */ |
592d1631 L |
6916 | { Bad_Opcode }, |
6917 | { Bad_Opcode }, | |
6918 | { Bad_Opcode }, | |
6919 | { Bad_Opcode }, | |
6920 | { Bad_Opcode }, | |
6921 | { Bad_Opcode }, | |
6922 | { Bad_Opcode }, | |
6923 | { Bad_Opcode }, | |
4e7d34a6 | 6924 | /* 28 */ |
592d1631 L |
6925 | { Bad_Opcode }, |
6926 | { Bad_Opcode }, | |
6927 | { Bad_Opcode }, | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { Bad_Opcode }, | |
6931 | { Bad_Opcode }, | |
6932 | { Bad_Opcode }, | |
4e7d34a6 | 6933 | /* 30 */ |
592d1631 L |
6934 | { Bad_Opcode }, |
6935 | { Bad_Opcode }, | |
6936 | { Bad_Opcode }, | |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
6941 | { Bad_Opcode }, | |
c0f3af97 | 6942 | /* 38 */ |
592d1631 L |
6943 | { Bad_Opcode }, |
6944 | { Bad_Opcode }, | |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
6949 | { Bad_Opcode }, | |
6950 | { Bad_Opcode }, | |
c0f3af97 | 6951 | /* 40 */ |
592d1631 L |
6952 | { Bad_Opcode }, |
6953 | { Bad_Opcode }, | |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
6957 | { Bad_Opcode }, | |
6958 | { Bad_Opcode }, | |
6959 | { Bad_Opcode }, | |
c1e679ec | 6960 | /* 48 */ |
592d1631 L |
6961 | { Bad_Opcode }, |
6962 | { Bad_Opcode }, | |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
6968 | { Bad_Opcode }, | |
c1e679ec | 6969 | /* 50 */ |
592d1631 L |
6970 | { Bad_Opcode }, |
6971 | { Bad_Opcode }, | |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
4e7d34a6 | 6978 | /* 58 */ |
592d1631 L |
6979 | { Bad_Opcode }, |
6980 | { Bad_Opcode }, | |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
6984 | { Bad_Opcode }, | |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
4e7d34a6 | 6987 | /* 60 */ |
592d1631 L |
6988 | { Bad_Opcode }, |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
4e7d34a6 | 6996 | /* 68 */ |
592d1631 L |
6997 | { Bad_Opcode }, |
6998 | { Bad_Opcode }, | |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
4e7d34a6 | 7005 | /* 70 */ |
592d1631 L |
7006 | { Bad_Opcode }, |
7007 | { Bad_Opcode }, | |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
4e7d34a6 | 7014 | /* 78 */ |
592d1631 L |
7015 | { Bad_Opcode }, |
7016 | { Bad_Opcode }, | |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
4e7d34a6 | 7023 | /* 80 */ |
592d1631 L |
7024 | { Bad_Opcode }, |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
4e7d34a6 | 7032 | /* 88 */ |
592d1631 L |
7033 | { Bad_Opcode }, |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
4e7d34a6 | 7041 | /* 90 */ |
592d1631 L |
7042 | { Bad_Opcode }, |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
4e7d34a6 | 7050 | /* 98 */ |
592d1631 L |
7051 | { Bad_Opcode }, |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
4e7d34a6 | 7059 | /* a0 */ |
592d1631 L |
7060 | { Bad_Opcode }, |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
4e7d34a6 | 7068 | /* a8 */ |
592d1631 L |
7069 | { Bad_Opcode }, |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
d5d7db8e | 7077 | /* b0 */ |
592d1631 L |
7078 | { Bad_Opcode }, |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
85f10a01 | 7086 | /* b8 */ |
592d1631 L |
7087 | { Bad_Opcode }, |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
85f10a01 | 7095 | /* c0 */ |
592d1631 L |
7096 | { Bad_Opcode }, |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
85f10a01 | 7104 | /* c8 */ |
592d1631 L |
7105 | { Bad_Opcode }, |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
85f10a01 | 7113 | /* d0 */ |
592d1631 L |
7114 | { Bad_Opcode }, |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
85f10a01 | 7122 | /* d8 */ |
592d1631 L |
7123 | { Bad_Opcode }, |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
85f10a01 | 7131 | /* e0 */ |
592d1631 L |
7132 | { Bad_Opcode }, |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
85f10a01 | 7140 | /* e8 */ |
592d1631 L |
7141 | { Bad_Opcode }, |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
85f10a01 | 7149 | /* f0 */ |
592d1631 L |
7150 | { Bad_Opcode }, |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
85f10a01 | 7158 | /* f8 */ |
592d1631 L |
7159 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
85f10a01 | 7167 | }, |
c0f3af97 L |
7168 | }; |
7169 | ||
7170 | static const struct dis386 vex_table[][256] = { | |
7171 | /* VEX_0F */ | |
85f10a01 MM |
7172 | { |
7173 | /* 00 */ | |
592d1631 L |
7174 | { Bad_Opcode }, |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
85f10a01 | 7182 | /* 08 */ |
592d1631 L |
7183 | { Bad_Opcode }, |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
c0f3af97 L |
7191 | /* 10 */ |
7192 | { PREFIX_TABLE (PREFIX_VEX_10) }, | |
7193 | { PREFIX_TABLE (PREFIX_VEX_11) }, | |
7194 | { PREFIX_TABLE (PREFIX_VEX_12) }, | |
7195 | { MOD_TABLE (MOD_VEX_13) }, | |
9e30b8e0 L |
7196 | { VEX_W_TABLE (VEX_W_14) }, |
7197 | { VEX_W_TABLE (VEX_W_15) }, | |
c0f3af97 L |
7198 | { PREFIX_TABLE (PREFIX_VEX_16) }, |
7199 | { MOD_TABLE (MOD_VEX_17) }, | |
7200 | /* 18 */ | |
592d1631 L |
7201 | { Bad_Opcode }, |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
c0f3af97 | 7209 | /* 20 */ |
592d1631 L |
7210 | { Bad_Opcode }, |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
c0f3af97 | 7218 | /* 28 */ |
9e30b8e0 L |
7219 | { VEX_W_TABLE (VEX_W_28) }, |
7220 | { VEX_W_TABLE (VEX_W_29) }, | |
c0f3af97 L |
7221 | { PREFIX_TABLE (PREFIX_VEX_2A) }, |
7222 | { MOD_TABLE (MOD_VEX_2B) }, | |
7223 | { PREFIX_TABLE (PREFIX_VEX_2C) }, | |
7224 | { PREFIX_TABLE (PREFIX_VEX_2D) }, | |
7225 | { PREFIX_TABLE (PREFIX_VEX_2E) }, | |
7226 | { PREFIX_TABLE (PREFIX_VEX_2F) }, | |
85f10a01 | 7227 | /* 30 */ |
592d1631 L |
7228 | { Bad_Opcode }, |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
4e7d34a6 | 7236 | /* 38 */ |
592d1631 L |
7237 | { Bad_Opcode }, |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
d5d7db8e | 7245 | /* 40 */ |
592d1631 L |
7246 | { Bad_Opcode }, |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
85f10a01 | 7254 | /* 48 */ |
592d1631 L |
7255 | { Bad_Opcode }, |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
d5d7db8e | 7263 | /* 50 */ |
976f1fde | 7264 | { MOD_TABLE (MOD_VEX_50) }, |
c0f3af97 L |
7265 | { PREFIX_TABLE (PREFIX_VEX_51) }, |
7266 | { PREFIX_TABLE (PREFIX_VEX_52) }, | |
7267 | { PREFIX_TABLE (PREFIX_VEX_53) }, | |
7268 | { "vandpX", { XM, Vex, EXx } }, | |
7269 | { "vandnpX", { XM, Vex, EXx } }, | |
7270 | { "vorpX", { XM, Vex, EXx } }, | |
7271 | { "vxorpX", { XM, Vex, EXx } }, | |
7272 | /* 58 */ | |
7273 | { PREFIX_TABLE (PREFIX_VEX_58) }, | |
7274 | { PREFIX_TABLE (PREFIX_VEX_59) }, | |
7275 | { PREFIX_TABLE (PREFIX_VEX_5A) }, | |
7276 | { PREFIX_TABLE (PREFIX_VEX_5B) }, | |
7277 | { PREFIX_TABLE (PREFIX_VEX_5C) }, | |
7278 | { PREFIX_TABLE (PREFIX_VEX_5D) }, | |
7279 | { PREFIX_TABLE (PREFIX_VEX_5E) }, | |
7280 | { PREFIX_TABLE (PREFIX_VEX_5F) }, | |
7281 | /* 60 */ | |
7282 | { PREFIX_TABLE (PREFIX_VEX_60) }, | |
7283 | { PREFIX_TABLE (PREFIX_VEX_61) }, | |
7284 | { PREFIX_TABLE (PREFIX_VEX_62) }, | |
7285 | { PREFIX_TABLE (PREFIX_VEX_63) }, | |
7286 | { PREFIX_TABLE (PREFIX_VEX_64) }, | |
7287 | { PREFIX_TABLE (PREFIX_VEX_65) }, | |
7288 | { PREFIX_TABLE (PREFIX_VEX_66) }, | |
7289 | { PREFIX_TABLE (PREFIX_VEX_67) }, | |
7290 | /* 68 */ | |
7291 | { PREFIX_TABLE (PREFIX_VEX_68) }, | |
7292 | { PREFIX_TABLE (PREFIX_VEX_69) }, | |
7293 | { PREFIX_TABLE (PREFIX_VEX_6A) }, | |
7294 | { PREFIX_TABLE (PREFIX_VEX_6B) }, | |
7295 | { PREFIX_TABLE (PREFIX_VEX_6C) }, | |
7296 | { PREFIX_TABLE (PREFIX_VEX_6D) }, | |
7297 | { PREFIX_TABLE (PREFIX_VEX_6E) }, | |
7298 | { PREFIX_TABLE (PREFIX_VEX_6F) }, | |
7299 | /* 70 */ | |
7300 | { PREFIX_TABLE (PREFIX_VEX_70) }, | |
7301 | { REG_TABLE (REG_VEX_71) }, | |
7302 | { REG_TABLE (REG_VEX_72) }, | |
7303 | { REG_TABLE (REG_VEX_73) }, | |
7304 | { PREFIX_TABLE (PREFIX_VEX_74) }, | |
7305 | { PREFIX_TABLE (PREFIX_VEX_75) }, | |
7306 | { PREFIX_TABLE (PREFIX_VEX_76) }, | |
7307 | { PREFIX_TABLE (PREFIX_VEX_77) }, | |
7308 | /* 78 */ | |
592d1631 L |
7309 | { Bad_Opcode }, |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
c0f3af97 L |
7313 | { PREFIX_TABLE (PREFIX_VEX_7C) }, |
7314 | { PREFIX_TABLE (PREFIX_VEX_7D) }, | |
7315 | { PREFIX_TABLE (PREFIX_VEX_7E) }, | |
7316 | { PREFIX_TABLE (PREFIX_VEX_7F) }, | |
7317 | /* 80 */ | |
592d1631 L |
7318 | { Bad_Opcode }, |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
c0f3af97 | 7326 | /* 88 */ |
592d1631 L |
7327 | { Bad_Opcode }, |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
c0f3af97 | 7335 | /* 90 */ |
592d1631 L |
7336 | { Bad_Opcode }, |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
c0f3af97 | 7344 | /* 98 */ |
592d1631 L |
7345 | { Bad_Opcode }, |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
c0f3af97 | 7353 | /* a0 */ |
592d1631 L |
7354 | { Bad_Opcode }, |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
c0f3af97 | 7362 | /* a8 */ |
592d1631 L |
7363 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
c0f3af97 | 7369 | { REG_TABLE (REG_VEX_AE) }, |
592d1631 | 7370 | { Bad_Opcode }, |
c0f3af97 | 7371 | /* b0 */ |
592d1631 L |
7372 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
c0f3af97 | 7380 | /* b8 */ |
592d1631 L |
7381 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
c0f3af97 | 7389 | /* c0 */ |
592d1631 L |
7390 | { Bad_Opcode }, |
7391 | { Bad_Opcode }, | |
c0f3af97 | 7392 | { PREFIX_TABLE (PREFIX_VEX_C2) }, |
592d1631 | 7393 | { Bad_Opcode }, |
c0f3af97 L |
7394 | { PREFIX_TABLE (PREFIX_VEX_C4) }, |
7395 | { PREFIX_TABLE (PREFIX_VEX_C5) }, | |
7396 | { "vshufpX", { XM, Vex, EXx, Ib } }, | |
592d1631 | 7397 | { Bad_Opcode }, |
c0f3af97 | 7398 | /* c8 */ |
592d1631 L |
7399 | { Bad_Opcode }, |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
c0f3af97 L |
7407 | /* d0 */ |
7408 | { PREFIX_TABLE (PREFIX_VEX_D0) }, | |
7409 | { PREFIX_TABLE (PREFIX_VEX_D1) }, | |
7410 | { PREFIX_TABLE (PREFIX_VEX_D2) }, | |
7411 | { PREFIX_TABLE (PREFIX_VEX_D3) }, | |
7412 | { PREFIX_TABLE (PREFIX_VEX_D4) }, | |
7413 | { PREFIX_TABLE (PREFIX_VEX_D5) }, | |
7414 | { PREFIX_TABLE (PREFIX_VEX_D6) }, | |
7415 | { PREFIX_TABLE (PREFIX_VEX_D7) }, | |
7416 | /* d8 */ | |
7417 | { PREFIX_TABLE (PREFIX_VEX_D8) }, | |
7418 | { PREFIX_TABLE (PREFIX_VEX_D9) }, | |
7419 | { PREFIX_TABLE (PREFIX_VEX_DA) }, | |
7420 | { PREFIX_TABLE (PREFIX_VEX_DB) }, | |
7421 | { PREFIX_TABLE (PREFIX_VEX_DC) }, | |
7422 | { PREFIX_TABLE (PREFIX_VEX_DD) }, | |
7423 | { PREFIX_TABLE (PREFIX_VEX_DE) }, | |
7424 | { PREFIX_TABLE (PREFIX_VEX_DF) }, | |
7425 | /* e0 */ | |
7426 | { PREFIX_TABLE (PREFIX_VEX_E0) }, | |
7427 | { PREFIX_TABLE (PREFIX_VEX_E1) }, | |
7428 | { PREFIX_TABLE (PREFIX_VEX_E2) }, | |
7429 | { PREFIX_TABLE (PREFIX_VEX_E3) }, | |
7430 | { PREFIX_TABLE (PREFIX_VEX_E4) }, | |
7431 | { PREFIX_TABLE (PREFIX_VEX_E5) }, | |
7432 | { PREFIX_TABLE (PREFIX_VEX_E6) }, | |
7433 | { PREFIX_TABLE (PREFIX_VEX_E7) }, | |
7434 | /* e8 */ | |
7435 | { PREFIX_TABLE (PREFIX_VEX_E8) }, | |
7436 | { PREFIX_TABLE (PREFIX_VEX_E9) }, | |
7437 | { PREFIX_TABLE (PREFIX_VEX_EA) }, | |
7438 | { PREFIX_TABLE (PREFIX_VEX_EB) }, | |
7439 | { PREFIX_TABLE (PREFIX_VEX_EC) }, | |
7440 | { PREFIX_TABLE (PREFIX_VEX_ED) }, | |
7441 | { PREFIX_TABLE (PREFIX_VEX_EE) }, | |
7442 | { PREFIX_TABLE (PREFIX_VEX_EF) }, | |
7443 | /* f0 */ | |
7444 | { PREFIX_TABLE (PREFIX_VEX_F0) }, | |
7445 | { PREFIX_TABLE (PREFIX_VEX_F1) }, | |
7446 | { PREFIX_TABLE (PREFIX_VEX_F2) }, | |
7447 | { PREFIX_TABLE (PREFIX_VEX_F3) }, | |
7448 | { PREFIX_TABLE (PREFIX_VEX_F4) }, | |
7449 | { PREFIX_TABLE (PREFIX_VEX_F5) }, | |
7450 | { PREFIX_TABLE (PREFIX_VEX_F6) }, | |
7451 | { PREFIX_TABLE (PREFIX_VEX_F7) }, | |
7452 | /* f8 */ | |
7453 | { PREFIX_TABLE (PREFIX_VEX_F8) }, | |
7454 | { PREFIX_TABLE (PREFIX_VEX_F9) }, | |
7455 | { PREFIX_TABLE (PREFIX_VEX_FA) }, | |
7456 | { PREFIX_TABLE (PREFIX_VEX_FB) }, | |
7457 | { PREFIX_TABLE (PREFIX_VEX_FC) }, | |
7458 | { PREFIX_TABLE (PREFIX_VEX_FD) }, | |
7459 | { PREFIX_TABLE (PREFIX_VEX_FE) }, | |
592d1631 | 7460 | { Bad_Opcode }, |
c0f3af97 L |
7461 | }, |
7462 | /* VEX_0F38 */ | |
7463 | { | |
7464 | /* 00 */ | |
7465 | { PREFIX_TABLE (PREFIX_VEX_3800) }, | |
7466 | { PREFIX_TABLE (PREFIX_VEX_3801) }, | |
7467 | { PREFIX_TABLE (PREFIX_VEX_3802) }, | |
7468 | { PREFIX_TABLE (PREFIX_VEX_3803) }, | |
7469 | { PREFIX_TABLE (PREFIX_VEX_3804) }, | |
7470 | { PREFIX_TABLE (PREFIX_VEX_3805) }, | |
7471 | { PREFIX_TABLE (PREFIX_VEX_3806) }, | |
7472 | { PREFIX_TABLE (PREFIX_VEX_3807) }, | |
7473 | /* 08 */ | |
7474 | { PREFIX_TABLE (PREFIX_VEX_3808) }, | |
7475 | { PREFIX_TABLE (PREFIX_VEX_3809) }, | |
7476 | { PREFIX_TABLE (PREFIX_VEX_380A) }, | |
7477 | { PREFIX_TABLE (PREFIX_VEX_380B) }, | |
7478 | { PREFIX_TABLE (PREFIX_VEX_380C) }, | |
7479 | { PREFIX_TABLE (PREFIX_VEX_380D) }, | |
7480 | { PREFIX_TABLE (PREFIX_VEX_380E) }, | |
7481 | { PREFIX_TABLE (PREFIX_VEX_380F) }, | |
7482 | /* 10 */ | |
592d1631 L |
7483 | { Bad_Opcode }, |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
c0f3af97 L |
7490 | { PREFIX_TABLE (PREFIX_VEX_3817) }, |
7491 | /* 18 */ | |
7492 | { PREFIX_TABLE (PREFIX_VEX_3818) }, | |
7493 | { PREFIX_TABLE (PREFIX_VEX_3819) }, | |
7494 | { PREFIX_TABLE (PREFIX_VEX_381A) }, | |
592d1631 | 7495 | { Bad_Opcode }, |
c0f3af97 L |
7496 | { PREFIX_TABLE (PREFIX_VEX_381C) }, |
7497 | { PREFIX_TABLE (PREFIX_VEX_381D) }, | |
7498 | { PREFIX_TABLE (PREFIX_VEX_381E) }, | |
592d1631 | 7499 | { Bad_Opcode }, |
c0f3af97 L |
7500 | /* 20 */ |
7501 | { PREFIX_TABLE (PREFIX_VEX_3820) }, | |
7502 | { PREFIX_TABLE (PREFIX_VEX_3821) }, | |
7503 | { PREFIX_TABLE (PREFIX_VEX_3822) }, | |
7504 | { PREFIX_TABLE (PREFIX_VEX_3823) }, | |
7505 | { PREFIX_TABLE (PREFIX_VEX_3824) }, | |
7506 | { PREFIX_TABLE (PREFIX_VEX_3825) }, | |
592d1631 L |
7507 | { Bad_Opcode }, |
7508 | { Bad_Opcode }, | |
c0f3af97 L |
7509 | /* 28 */ |
7510 | { PREFIX_TABLE (PREFIX_VEX_3828) }, | |
7511 | { PREFIX_TABLE (PREFIX_VEX_3829) }, | |
7512 | { PREFIX_TABLE (PREFIX_VEX_382A) }, | |
7513 | { PREFIX_TABLE (PREFIX_VEX_382B) }, | |
7514 | { PREFIX_TABLE (PREFIX_VEX_382C) }, | |
7515 | { PREFIX_TABLE (PREFIX_VEX_382D) }, | |
7516 | { PREFIX_TABLE (PREFIX_VEX_382E) }, | |
7517 | { PREFIX_TABLE (PREFIX_VEX_382F) }, | |
7518 | /* 30 */ | |
7519 | { PREFIX_TABLE (PREFIX_VEX_3830) }, | |
7520 | { PREFIX_TABLE (PREFIX_VEX_3831) }, | |
7521 | { PREFIX_TABLE (PREFIX_VEX_3832) }, | |
7522 | { PREFIX_TABLE (PREFIX_VEX_3833) }, | |
7523 | { PREFIX_TABLE (PREFIX_VEX_3834) }, | |
7524 | { PREFIX_TABLE (PREFIX_VEX_3835) }, | |
592d1631 | 7525 | { Bad_Opcode }, |
c0f3af97 L |
7526 | { PREFIX_TABLE (PREFIX_VEX_3837) }, |
7527 | /* 38 */ | |
7528 | { PREFIX_TABLE (PREFIX_VEX_3838) }, | |
7529 | { PREFIX_TABLE (PREFIX_VEX_3839) }, | |
7530 | { PREFIX_TABLE (PREFIX_VEX_383A) }, | |
7531 | { PREFIX_TABLE (PREFIX_VEX_383B) }, | |
7532 | { PREFIX_TABLE (PREFIX_VEX_383C) }, | |
7533 | { PREFIX_TABLE (PREFIX_VEX_383D) }, | |
7534 | { PREFIX_TABLE (PREFIX_VEX_383E) }, | |
7535 | { PREFIX_TABLE (PREFIX_VEX_383F) }, | |
7536 | /* 40 */ | |
7537 | { PREFIX_TABLE (PREFIX_VEX_3840) }, | |
7538 | { PREFIX_TABLE (PREFIX_VEX_3841) }, | |
592d1631 L |
7539 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
c0f3af97 | 7545 | /* 48 */ |
592d1631 L |
7546 | { Bad_Opcode }, |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
c0f3af97 | 7554 | /* 50 */ |
592d1631 L |
7555 | { Bad_Opcode }, |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
c0f3af97 | 7563 | /* 58 */ |
592d1631 L |
7564 | { Bad_Opcode }, |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
c0f3af97 | 7572 | /* 60 */ |
592d1631 L |
7573 | { Bad_Opcode }, |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
c0f3af97 | 7581 | /* 68 */ |
592d1631 L |
7582 | { Bad_Opcode }, |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
c0f3af97 | 7590 | /* 70 */ |
592d1631 L |
7591 | { Bad_Opcode }, |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
c0f3af97 | 7599 | /* 78 */ |
592d1631 L |
7600 | { Bad_Opcode }, |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
c0f3af97 | 7608 | /* 80 */ |
592d1631 L |
7609 | { Bad_Opcode }, |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
c0f3af97 | 7617 | /* 88 */ |
592d1631 L |
7618 | { Bad_Opcode }, |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
c0f3af97 | 7626 | /* 90 */ |
592d1631 L |
7627 | { Bad_Opcode }, |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
0bfee649 L |
7633 | { PREFIX_TABLE (PREFIX_VEX_3896) }, |
7634 | { PREFIX_TABLE (PREFIX_VEX_3897) }, | |
c0f3af97 | 7635 | /* 98 */ |
0bfee649 L |
7636 | { PREFIX_TABLE (PREFIX_VEX_3898) }, |
7637 | { PREFIX_TABLE (PREFIX_VEX_3899) }, | |
7638 | { PREFIX_TABLE (PREFIX_VEX_389A) }, | |
7639 | { PREFIX_TABLE (PREFIX_VEX_389B) }, | |
7640 | { PREFIX_TABLE (PREFIX_VEX_389C) }, | |
7641 | { PREFIX_TABLE (PREFIX_VEX_389D) }, | |
7642 | { PREFIX_TABLE (PREFIX_VEX_389E) }, | |
7643 | { PREFIX_TABLE (PREFIX_VEX_389F) }, | |
c0f3af97 | 7644 | /* a0 */ |
592d1631 L |
7645 | { Bad_Opcode }, |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
0bfee649 L |
7651 | { PREFIX_TABLE (PREFIX_VEX_38A6) }, |
7652 | { PREFIX_TABLE (PREFIX_VEX_38A7) }, | |
c0f3af97 | 7653 | /* a8 */ |
0bfee649 L |
7654 | { PREFIX_TABLE (PREFIX_VEX_38A8) }, |
7655 | { PREFIX_TABLE (PREFIX_VEX_38A9) }, | |
7656 | { PREFIX_TABLE (PREFIX_VEX_38AA) }, | |
7657 | { PREFIX_TABLE (PREFIX_VEX_38AB) }, | |
7658 | { PREFIX_TABLE (PREFIX_VEX_38AC) }, | |
7659 | { PREFIX_TABLE (PREFIX_VEX_38AD) }, | |
7660 | { PREFIX_TABLE (PREFIX_VEX_38AE) }, | |
7661 | { PREFIX_TABLE (PREFIX_VEX_38AF) }, | |
c0f3af97 | 7662 | /* b0 */ |
592d1631 L |
7663 | { Bad_Opcode }, |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
0bfee649 L |
7669 | { PREFIX_TABLE (PREFIX_VEX_38B6) }, |
7670 | { PREFIX_TABLE (PREFIX_VEX_38B7) }, | |
c0f3af97 | 7671 | /* b8 */ |
0bfee649 L |
7672 | { PREFIX_TABLE (PREFIX_VEX_38B8) }, |
7673 | { PREFIX_TABLE (PREFIX_VEX_38B9) }, | |
7674 | { PREFIX_TABLE (PREFIX_VEX_38BA) }, | |
7675 | { PREFIX_TABLE (PREFIX_VEX_38BB) }, | |
7676 | { PREFIX_TABLE (PREFIX_VEX_38BC) }, | |
7677 | { PREFIX_TABLE (PREFIX_VEX_38BD) }, | |
7678 | { PREFIX_TABLE (PREFIX_VEX_38BE) }, | |
7679 | { PREFIX_TABLE (PREFIX_VEX_38BF) }, | |
c0f3af97 | 7680 | /* c0 */ |
592d1631 L |
7681 | { Bad_Opcode }, |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
c0f3af97 | 7689 | /* c8 */ |
592d1631 L |
7690 | { Bad_Opcode }, |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
c0f3af97 | 7698 | /* d0 */ |
592d1631 L |
7699 | { Bad_Opcode }, |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
c0f3af97 | 7707 | /* d8 */ |
592d1631 L |
7708 | { Bad_Opcode }, |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
a5ff0eb2 L |
7711 | { PREFIX_TABLE (PREFIX_VEX_38DB) }, |
7712 | { PREFIX_TABLE (PREFIX_VEX_38DC) }, | |
7713 | { PREFIX_TABLE (PREFIX_VEX_38DD) }, | |
7714 | { PREFIX_TABLE (PREFIX_VEX_38DE) }, | |
7715 | { PREFIX_TABLE (PREFIX_VEX_38DF) }, | |
c0f3af97 | 7716 | /* e0 */ |
592d1631 L |
7717 | { Bad_Opcode }, |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
c0f3af97 | 7725 | /* e8 */ |
592d1631 L |
7726 | { Bad_Opcode }, |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
c0f3af97 | 7734 | /* f0 */ |
592d1631 L |
7735 | { Bad_Opcode }, |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
c0f3af97 | 7743 | /* f8 */ |
592d1631 L |
7744 | { Bad_Opcode }, |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
c0f3af97 L |
7752 | }, |
7753 | /* VEX_0F3A */ | |
7754 | { | |
7755 | /* 00 */ | |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
c0f3af97 L |
7760 | { PREFIX_TABLE (PREFIX_VEX_3A04) }, |
7761 | { PREFIX_TABLE (PREFIX_VEX_3A05) }, | |
7762 | { PREFIX_TABLE (PREFIX_VEX_3A06) }, | |
592d1631 | 7763 | { Bad_Opcode }, |
c0f3af97 L |
7764 | /* 08 */ |
7765 | { PREFIX_TABLE (PREFIX_VEX_3A08) }, | |
7766 | { PREFIX_TABLE (PREFIX_VEX_3A09) }, | |
7767 | { PREFIX_TABLE (PREFIX_VEX_3A0A) }, | |
7768 | { PREFIX_TABLE (PREFIX_VEX_3A0B) }, | |
7769 | { PREFIX_TABLE (PREFIX_VEX_3A0C) }, | |
7770 | { PREFIX_TABLE (PREFIX_VEX_3A0D) }, | |
7771 | { PREFIX_TABLE (PREFIX_VEX_3A0E) }, | |
7772 | { PREFIX_TABLE (PREFIX_VEX_3A0F) }, | |
7773 | /* 10 */ | |
592d1631 L |
7774 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
c0f3af97 L |
7778 | { PREFIX_TABLE (PREFIX_VEX_3A14) }, |
7779 | { PREFIX_TABLE (PREFIX_VEX_3A15) }, | |
7780 | { PREFIX_TABLE (PREFIX_VEX_3A16) }, | |
7781 | { PREFIX_TABLE (PREFIX_VEX_3A17) }, | |
7782 | /* 18 */ | |
7783 | { PREFIX_TABLE (PREFIX_VEX_3A18) }, | |
7784 | { PREFIX_TABLE (PREFIX_VEX_3A19) }, | |
592d1631 L |
7785 | { Bad_Opcode }, |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
c0f3af97 L |
7791 | /* 20 */ |
7792 | { PREFIX_TABLE (PREFIX_VEX_3A20) }, | |
7793 | { PREFIX_TABLE (PREFIX_VEX_3A21) }, | |
7794 | { PREFIX_TABLE (PREFIX_VEX_3A22) }, | |
592d1631 L |
7795 | { Bad_Opcode }, |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
c0f3af97 | 7800 | /* 28 */ |
592d1631 L |
7801 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
c0f3af97 | 7809 | /* 30 */ |
592d1631 L |
7810 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
c0f3af97 | 7818 | /* 38 */ |
592d1631 L |
7819 | { Bad_Opcode }, |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
c0f3af97 L |
7827 | /* 40 */ |
7828 | { PREFIX_TABLE (PREFIX_VEX_3A40) }, | |
7829 | { PREFIX_TABLE (PREFIX_VEX_3A41) }, | |
7830 | { PREFIX_TABLE (PREFIX_VEX_3A42) }, | |
592d1631 | 7831 | { Bad_Opcode }, |
ce2f5b3c | 7832 | { PREFIX_TABLE (PREFIX_VEX_3A44) }, |
592d1631 L |
7833 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
c0f3af97 | 7836 | /* 48 */ |
592d1631 L |
7837 | { Bad_Opcode }, |
7838 | { Bad_Opcode }, | |
c0f3af97 L |
7839 | { PREFIX_TABLE (PREFIX_VEX_3A4A) }, |
7840 | { PREFIX_TABLE (PREFIX_VEX_3A4B) }, | |
7841 | { PREFIX_TABLE (PREFIX_VEX_3A4C) }, | |
592d1631 L |
7842 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
c0f3af97 | 7845 | /* 50 */ |
592d1631 L |
7846 | { Bad_Opcode }, |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
c0f3af97 | 7854 | /* 58 */ |
592d1631 L |
7855 | { Bad_Opcode }, |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
922d8de8 DR |
7859 | { PREFIX_TABLE (PREFIX_VEX_3A5C) }, |
7860 | { PREFIX_TABLE (PREFIX_VEX_3A5D) }, | |
7861 | { PREFIX_TABLE (PREFIX_VEX_3A5E) }, | |
7862 | { PREFIX_TABLE (PREFIX_VEX_3A5F) }, | |
c0f3af97 L |
7863 | /* 60 */ |
7864 | { PREFIX_TABLE (PREFIX_VEX_3A60) }, | |
7865 | { PREFIX_TABLE (PREFIX_VEX_3A61) }, | |
7866 | { PREFIX_TABLE (PREFIX_VEX_3A62) }, | |
7867 | { PREFIX_TABLE (PREFIX_VEX_3A63) }, | |
592d1631 L |
7868 | { Bad_Opcode }, |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
c0f3af97 | 7872 | /* 68 */ |
922d8de8 DR |
7873 | { PREFIX_TABLE (PREFIX_VEX_3A68) }, |
7874 | { PREFIX_TABLE (PREFIX_VEX_3A69) }, | |
7875 | { PREFIX_TABLE (PREFIX_VEX_3A6A) }, | |
7876 | { PREFIX_TABLE (PREFIX_VEX_3A6B) }, | |
7877 | { PREFIX_TABLE (PREFIX_VEX_3A6C) }, | |
7878 | { PREFIX_TABLE (PREFIX_VEX_3A6D) }, | |
7879 | { PREFIX_TABLE (PREFIX_VEX_3A6E) }, | |
7880 | { PREFIX_TABLE (PREFIX_VEX_3A6F) }, | |
c0f3af97 | 7881 | /* 70 */ |
592d1631 L |
7882 | { Bad_Opcode }, |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
c0f3af97 | 7890 | /* 78 */ |
922d8de8 DR |
7891 | { PREFIX_TABLE (PREFIX_VEX_3A78) }, |
7892 | { PREFIX_TABLE (PREFIX_VEX_3A79) }, | |
7893 | { PREFIX_TABLE (PREFIX_VEX_3A7A) }, | |
7894 | { PREFIX_TABLE (PREFIX_VEX_3A7B) }, | |
7895 | { PREFIX_TABLE (PREFIX_VEX_3A7C) }, | |
7896 | { PREFIX_TABLE (PREFIX_VEX_3A7D) }, | |
7897 | { PREFIX_TABLE (PREFIX_VEX_3A7E) }, | |
7898 | { PREFIX_TABLE (PREFIX_VEX_3A7F) }, | |
c0f3af97 | 7899 | /* 80 */ |
592d1631 L |
7900 | { Bad_Opcode }, |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
c0f3af97 | 7908 | /* 88 */ |
592d1631 L |
7909 | { Bad_Opcode }, |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
c0f3af97 | 7917 | /* 90 */ |
592d1631 L |
7918 | { Bad_Opcode }, |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
c0f3af97 | 7926 | /* 98 */ |
592d1631 L |
7927 | { Bad_Opcode }, |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
c0f3af97 | 7935 | /* a0 */ |
592d1631 L |
7936 | { Bad_Opcode }, |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
c0f3af97 | 7944 | /* a8 */ |
592d1631 L |
7945 | { Bad_Opcode }, |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
c0f3af97 | 7953 | /* b0 */ |
592d1631 L |
7954 | { Bad_Opcode }, |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
c0f3af97 | 7962 | /* b8 */ |
592d1631 L |
7963 | { Bad_Opcode }, |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
c0f3af97 | 7971 | /* c0 */ |
592d1631 L |
7972 | { Bad_Opcode }, |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
c0f3af97 | 7980 | /* c8 */ |
592d1631 L |
7981 | { Bad_Opcode }, |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
c0f3af97 | 7989 | /* d0 */ |
592d1631 L |
7990 | { Bad_Opcode }, |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
c0f3af97 | 7998 | /* d8 */ |
592d1631 L |
7999 | { Bad_Opcode }, |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
a5ff0eb2 | 8006 | { PREFIX_TABLE (PREFIX_VEX_3ADF) }, |
c0f3af97 | 8007 | /* e0 */ |
592d1631 L |
8008 | { Bad_Opcode }, |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
c0f3af97 | 8016 | /* e8 */ |
592d1631 L |
8017 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
c0f3af97 | 8025 | /* f0 */ |
592d1631 L |
8026 | { Bad_Opcode }, |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
c0f3af97 | 8034 | /* f8 */ |
592d1631 L |
8035 | { Bad_Opcode }, |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
c0f3af97 L |
8043 | }, |
8044 | }; | |
8045 | ||
8046 | static const struct dis386 vex_len_table[][2] = { | |
8047 | /* VEX_LEN_10_P_1 */ | |
8048 | { | |
9e30b8e0 | 8049 | { VEX_W_TABLE (VEX_W_10_P_1) }, |
c0f3af97 L |
8050 | }, |
8051 | ||
8052 | /* VEX_LEN_10_P_3 */ | |
8053 | { | |
9e30b8e0 | 8054 | { VEX_W_TABLE (VEX_W_10_P_3) }, |
c0f3af97 L |
8055 | }, |
8056 | ||
8057 | /* VEX_LEN_11_P_1 */ | |
8058 | { | |
9e30b8e0 | 8059 | { VEX_W_TABLE (VEX_W_11_P_1) }, |
c0f3af97 L |
8060 | }, |
8061 | ||
8062 | /* VEX_LEN_11_P_3 */ | |
8063 | { | |
9e30b8e0 | 8064 | { VEX_W_TABLE (VEX_W_11_P_3) }, |
c0f3af97 L |
8065 | }, |
8066 | ||
8067 | /* VEX_LEN_12_P_0_M_0 */ | |
8068 | { | |
9e30b8e0 | 8069 | { VEX_W_TABLE (VEX_W_12_P_0_M_0) }, |
c0f3af97 L |
8070 | }, |
8071 | ||
8072 | /* VEX_LEN_12_P_0_M_1 */ | |
8073 | { | |
9e30b8e0 | 8074 | { VEX_W_TABLE (VEX_W_12_P_0_M_1) }, |
c0f3af97 L |
8075 | }, |
8076 | ||
8077 | /* VEX_LEN_12_P_2 */ | |
8078 | { | |
9e30b8e0 | 8079 | { VEX_W_TABLE (VEX_W_12_P_2) }, |
c0f3af97 L |
8080 | }, |
8081 | ||
8082 | /* VEX_LEN_13_M_0 */ | |
8083 | { | |
9e30b8e0 | 8084 | { VEX_W_TABLE (VEX_W_13_M_0) }, |
c0f3af97 L |
8085 | }, |
8086 | ||
8087 | /* VEX_LEN_16_P_0_M_0 */ | |
8088 | { | |
9e30b8e0 | 8089 | { VEX_W_TABLE (VEX_W_16_P_0_M_0) }, |
c0f3af97 L |
8090 | }, |
8091 | ||
8092 | /* VEX_LEN_16_P_0_M_1 */ | |
8093 | { | |
9e30b8e0 | 8094 | { VEX_W_TABLE (VEX_W_16_P_0_M_1) }, |
c0f3af97 L |
8095 | }, |
8096 | ||
8097 | /* VEX_LEN_16_P_2 */ | |
8098 | { | |
9e30b8e0 | 8099 | { VEX_W_TABLE (VEX_W_16_P_2) }, |
c0f3af97 L |
8100 | }, |
8101 | ||
8102 | /* VEX_LEN_17_M_0 */ | |
8103 | { | |
9e30b8e0 | 8104 | { VEX_W_TABLE (VEX_W_17_M_0) }, |
c0f3af97 L |
8105 | }, |
8106 | ||
8107 | /* VEX_LEN_2A_P_1 */ | |
8108 | { | |
8109 | { "vcvtsi2ss%LQ", { XM, Vex128, Ev } }, | |
c0f3af97 L |
8110 | }, |
8111 | ||
8112 | /* VEX_LEN_2A_P_3 */ | |
8113 | { | |
8114 | { "vcvtsi2sd%LQ", { XM, Vex128, Ev } }, | |
c0f3af97 L |
8115 | }, |
8116 | ||
c0f3af97 L |
8117 | /* VEX_LEN_2C_P_1 */ |
8118 | { | |
8119 | { "vcvttss2siY", { Gv, EXd } }, | |
c0f3af97 L |
8120 | }, |
8121 | ||
8122 | /* VEX_LEN_2C_P_3 */ | |
8123 | { | |
8124 | { "vcvttsd2siY", { Gv, EXq } }, | |
c0f3af97 L |
8125 | }, |
8126 | ||
8127 | /* VEX_LEN_2D_P_1 */ | |
8128 | { | |
8129 | { "vcvtss2siY", { Gv, EXd } }, | |
c0f3af97 L |
8130 | }, |
8131 | ||
8132 | /* VEX_LEN_2D_P_3 */ | |
8133 | { | |
8134 | { "vcvtsd2siY", { Gv, EXq } }, | |
c0f3af97 L |
8135 | }, |
8136 | ||
8137 | /* VEX_LEN_2E_P_0 */ | |
8138 | { | |
9e30b8e0 | 8139 | { VEX_W_TABLE (VEX_W_2E_P_0) }, |
c0f3af97 L |
8140 | }, |
8141 | ||
8142 | /* VEX_LEN_2E_P_2 */ | |
8143 | { | |
9e30b8e0 | 8144 | { VEX_W_TABLE (VEX_W_2E_P_2) }, |
c0f3af97 L |
8145 | }, |
8146 | ||
8147 | /* VEX_LEN_2F_P_0 */ | |
8148 | { | |
9e30b8e0 | 8149 | { VEX_W_TABLE (VEX_W_2F_P_0) }, |
c0f3af97 L |
8150 | }, |
8151 | ||
8152 | /* VEX_LEN_2F_P_2 */ | |
8153 | { | |
9e30b8e0 | 8154 | { VEX_W_TABLE (VEX_W_2F_P_2) }, |
c0f3af97 L |
8155 | }, |
8156 | ||
8157 | /* VEX_LEN_51_P_1 */ | |
8158 | { | |
9e30b8e0 | 8159 | { VEX_W_TABLE (VEX_W_51_P_1) }, |
c0f3af97 L |
8160 | }, |
8161 | ||
8162 | /* VEX_LEN_51_P_3 */ | |
8163 | { | |
9e30b8e0 | 8164 | { VEX_W_TABLE (VEX_W_51_P_3) }, |
c0f3af97 L |
8165 | }, |
8166 | ||
8167 | /* VEX_LEN_52_P_1 */ | |
8168 | { | |
9e30b8e0 | 8169 | { VEX_W_TABLE (VEX_W_52_P_1) }, |
c0f3af97 L |
8170 | }, |
8171 | ||
8172 | /* VEX_LEN_53_P_1 */ | |
8173 | { | |
9e30b8e0 | 8174 | { VEX_W_TABLE (VEX_W_53_P_1) }, |
c0f3af97 L |
8175 | }, |
8176 | ||
8177 | /* VEX_LEN_58_P_1 */ | |
8178 | { | |
9e30b8e0 | 8179 | { VEX_W_TABLE (VEX_W_58_P_1) }, |
c0f3af97 L |
8180 | }, |
8181 | ||
8182 | /* VEX_LEN_58_P_3 */ | |
8183 | { | |
9e30b8e0 | 8184 | { VEX_W_TABLE (VEX_W_58_P_3) }, |
c0f3af97 L |
8185 | }, |
8186 | ||
8187 | /* VEX_LEN_59_P_1 */ | |
8188 | { | |
9e30b8e0 | 8189 | { VEX_W_TABLE (VEX_W_59_P_1) }, |
c0f3af97 L |
8190 | }, |
8191 | ||
8192 | /* VEX_LEN_59_P_3 */ | |
8193 | { | |
9e30b8e0 | 8194 | { VEX_W_TABLE (VEX_W_59_P_3) }, |
c0f3af97 L |
8195 | }, |
8196 | ||
8197 | /* VEX_LEN_5A_P_1 */ | |
8198 | { | |
9e30b8e0 | 8199 | { VEX_W_TABLE (VEX_W_5A_P_1) }, |
c0f3af97 L |
8200 | }, |
8201 | ||
8202 | /* VEX_LEN_5A_P_3 */ | |
8203 | { | |
9e30b8e0 | 8204 | { VEX_W_TABLE (VEX_W_5A_P_3) }, |
c0f3af97 L |
8205 | }, |
8206 | ||
8207 | /* VEX_LEN_5C_P_1 */ | |
8208 | { | |
9e30b8e0 | 8209 | { VEX_W_TABLE (VEX_W_5C_P_1) }, |
c0f3af97 L |
8210 | }, |
8211 | ||
8212 | /* VEX_LEN_5C_P_3 */ | |
8213 | { | |
9e30b8e0 | 8214 | { VEX_W_TABLE (VEX_W_5C_P_3) }, |
c0f3af97 L |
8215 | }, |
8216 | ||
8217 | /* VEX_LEN_5D_P_1 */ | |
8218 | { | |
9e30b8e0 | 8219 | { VEX_W_TABLE (VEX_W_5D_P_1) }, |
c0f3af97 L |
8220 | }, |
8221 | ||
8222 | /* VEX_LEN_5D_P_3 */ | |
8223 | { | |
9e30b8e0 | 8224 | { VEX_W_TABLE (VEX_W_5D_P_3) }, |
c0f3af97 L |
8225 | }, |
8226 | ||
8227 | /* VEX_LEN_5E_P_1 */ | |
8228 | { | |
9e30b8e0 | 8229 | { VEX_W_TABLE (VEX_W_5E_P_1) }, |
c0f3af97 L |
8230 | }, |
8231 | ||
8232 | /* VEX_LEN_5E_P_3 */ | |
8233 | { | |
9e30b8e0 | 8234 | { VEX_W_TABLE (VEX_W_5E_P_3) }, |
c0f3af97 L |
8235 | }, |
8236 | ||
8237 | /* VEX_LEN_5F_P_1 */ | |
8238 | { | |
9e30b8e0 | 8239 | { VEX_W_TABLE (VEX_W_5F_P_1) }, |
c0f3af97 L |
8240 | }, |
8241 | ||
8242 | /* VEX_LEN_5F_P_3 */ | |
8243 | { | |
9e30b8e0 | 8244 | { VEX_W_TABLE (VEX_W_5F_P_3) }, |
c0f3af97 L |
8245 | }, |
8246 | ||
8247 | /* VEX_LEN_60_P_2 */ | |
8248 | { | |
9e30b8e0 | 8249 | { VEX_W_TABLE (VEX_W_60_P_2) }, |
c0f3af97 L |
8250 | }, |
8251 | ||
8252 | /* VEX_LEN_61_P_2 */ | |
8253 | { | |
9e30b8e0 | 8254 | { VEX_W_TABLE (VEX_W_61_P_2) }, |
c0f3af97 L |
8255 | }, |
8256 | ||
8257 | /* VEX_LEN_62_P_2 */ | |
8258 | { | |
9e30b8e0 | 8259 | { VEX_W_TABLE (VEX_W_62_P_2) }, |
c0f3af97 L |
8260 | }, |
8261 | ||
8262 | /* VEX_LEN_63_P_2 */ | |
8263 | { | |
9e30b8e0 | 8264 | { VEX_W_TABLE (VEX_W_63_P_2) }, |
c0f3af97 L |
8265 | }, |
8266 | ||
8267 | /* VEX_LEN_64_P_2 */ | |
8268 | { | |
9e30b8e0 | 8269 | { VEX_W_TABLE (VEX_W_64_P_2) }, |
c0f3af97 L |
8270 | }, |
8271 | ||
8272 | /* VEX_LEN_65_P_2 */ | |
8273 | { | |
9e30b8e0 | 8274 | { VEX_W_TABLE (VEX_W_65_P_2) }, |
c0f3af97 L |
8275 | }, |
8276 | ||
8277 | /* VEX_LEN_66_P_2 */ | |
8278 | { | |
9e30b8e0 | 8279 | { VEX_W_TABLE (VEX_W_66_P_2) }, |
c0f3af97 L |
8280 | }, |
8281 | ||
8282 | /* VEX_LEN_67_P_2 */ | |
8283 | { | |
9e30b8e0 | 8284 | { VEX_W_TABLE (VEX_W_67_P_2) }, |
c0f3af97 L |
8285 | }, |
8286 | ||
8287 | /* VEX_LEN_68_P_2 */ | |
8288 | { | |
9e30b8e0 | 8289 | { VEX_W_TABLE (VEX_W_68_P_2) }, |
c0f3af97 L |
8290 | }, |
8291 | ||
8292 | /* VEX_LEN_69_P_2 */ | |
8293 | { | |
9e30b8e0 | 8294 | { VEX_W_TABLE (VEX_W_69_P_2) }, |
c0f3af97 L |
8295 | }, |
8296 | ||
8297 | /* VEX_LEN_6A_P_2 */ | |
8298 | { | |
9e30b8e0 | 8299 | { VEX_W_TABLE (VEX_W_6A_P_2) }, |
c0f3af97 L |
8300 | }, |
8301 | ||
8302 | /* VEX_LEN_6B_P_2 */ | |
8303 | { | |
9e30b8e0 | 8304 | { VEX_W_TABLE (VEX_W_6B_P_2) }, |
c0f3af97 L |
8305 | }, |
8306 | ||
8307 | /* VEX_LEN_6C_P_2 */ | |
8308 | { | |
9e30b8e0 | 8309 | { VEX_W_TABLE (VEX_W_6C_P_2) }, |
c0f3af97 L |
8310 | }, |
8311 | ||
8312 | /* VEX_LEN_6D_P_2 */ | |
8313 | { | |
9e30b8e0 | 8314 | { VEX_W_TABLE (VEX_W_6D_P_2) }, |
c0f3af97 L |
8315 | }, |
8316 | ||
8317 | /* VEX_LEN_6E_P_2 */ | |
8318 | { | |
8319 | { "vmovK", { XM, Edq } }, | |
c0f3af97 L |
8320 | }, |
8321 | ||
8322 | /* VEX_LEN_70_P_1 */ | |
8323 | { | |
9e30b8e0 | 8324 | { VEX_W_TABLE (VEX_W_70_P_1) }, |
c0f3af97 L |
8325 | }, |
8326 | ||
8327 | /* VEX_LEN_70_P_2 */ | |
8328 | { | |
9e30b8e0 | 8329 | { VEX_W_TABLE (VEX_W_70_P_2) }, |
c0f3af97 L |
8330 | }, |
8331 | ||
8332 | /* VEX_LEN_70_P_3 */ | |
8333 | { | |
9e30b8e0 | 8334 | { VEX_W_TABLE (VEX_W_70_P_3) }, |
c0f3af97 L |
8335 | }, |
8336 | ||
8337 | /* VEX_LEN_71_R_2_P_2 */ | |
8338 | { | |
9e30b8e0 | 8339 | { VEX_W_TABLE (VEX_W_71_R_2_P_2) }, |
c0f3af97 L |
8340 | }, |
8341 | ||
8342 | /* VEX_LEN_71_R_4_P_2 */ | |
8343 | { | |
9e30b8e0 | 8344 | { VEX_W_TABLE (VEX_W_71_R_4_P_2) }, |
c0f3af97 L |
8345 | }, |
8346 | ||
8347 | /* VEX_LEN_71_R_6_P_2 */ | |
8348 | { | |
9e30b8e0 | 8349 | { VEX_W_TABLE (VEX_W_71_R_6_P_2) }, |
c0f3af97 L |
8350 | }, |
8351 | ||
8352 | /* VEX_LEN_72_R_2_P_2 */ | |
8353 | { | |
9e30b8e0 | 8354 | { VEX_W_TABLE (VEX_W_72_R_2_P_2) }, |
c0f3af97 L |
8355 | }, |
8356 | ||
8357 | /* VEX_LEN_72_R_4_P_2 */ | |
8358 | { | |
9e30b8e0 | 8359 | { VEX_W_TABLE (VEX_W_72_R_4_P_2) }, |
c0f3af97 L |
8360 | }, |
8361 | ||
8362 | /* VEX_LEN_72_R_6_P_2 */ | |
8363 | { | |
9e30b8e0 | 8364 | { VEX_W_TABLE (VEX_W_72_R_6_P_2) }, |
c0f3af97 L |
8365 | }, |
8366 | ||
8367 | /* VEX_LEN_73_R_2_P_2 */ | |
8368 | { | |
9e30b8e0 | 8369 | { VEX_W_TABLE (VEX_W_73_R_2_P_2) }, |
c0f3af97 L |
8370 | }, |
8371 | ||
8372 | /* VEX_LEN_73_R_3_P_2 */ | |
8373 | { | |
9e30b8e0 | 8374 | { VEX_W_TABLE (VEX_W_73_R_3_P_2) }, |
c0f3af97 L |
8375 | }, |
8376 | ||
8377 | /* VEX_LEN_73_R_6_P_2 */ | |
8378 | { | |
9e30b8e0 | 8379 | { VEX_W_TABLE (VEX_W_73_R_6_P_2) }, |
c0f3af97 L |
8380 | }, |
8381 | ||
8382 | /* VEX_LEN_73_R_7_P_2 */ | |
8383 | { | |
9e30b8e0 | 8384 | { VEX_W_TABLE (VEX_W_73_R_7_P_2) }, |
c0f3af97 L |
8385 | }, |
8386 | ||
8387 | /* VEX_LEN_74_P_2 */ | |
8388 | { | |
9e30b8e0 | 8389 | { VEX_W_TABLE (VEX_W_74_P_2) }, |
c0f3af97 L |
8390 | }, |
8391 | ||
8392 | /* VEX_LEN_75_P_2 */ | |
8393 | { | |
9e30b8e0 | 8394 | { VEX_W_TABLE (VEX_W_75_P_2) }, |
c0f3af97 L |
8395 | }, |
8396 | ||
8397 | /* VEX_LEN_76_P_2 */ | |
8398 | { | |
9e30b8e0 | 8399 | { VEX_W_TABLE (VEX_W_76_P_2) }, |
c0f3af97 L |
8400 | }, |
8401 | ||
8402 | /* VEX_LEN_7E_P_1 */ | |
8403 | { | |
9e30b8e0 | 8404 | { VEX_W_TABLE (VEX_W_7E_P_1) }, |
c0f3af97 L |
8405 | }, |
8406 | ||
8407 | /* VEX_LEN_7E_P_2 */ | |
8408 | { | |
8409 | { "vmovK", { Edq, XM } }, | |
c0f3af97 L |
8410 | }, |
8411 | ||
9daa0d29 | 8412 | /* VEX_LEN_AE_R_2_M_0 */ |
c0f3af97 | 8413 | { |
9e30b8e0 | 8414 | { VEX_W_TABLE (VEX_W_AE_R_2_M_0) }, |
c0f3af97 L |
8415 | }, |
8416 | ||
9daa0d29 | 8417 | /* VEX_LEN_AE_R_3_M_0 */ |
c0f3af97 | 8418 | { |
9e30b8e0 | 8419 | { VEX_W_TABLE (VEX_W_AE_R_3_M_0) }, |
c0f3af97 L |
8420 | }, |
8421 | ||
8422 | /* VEX_LEN_C2_P_1 */ | |
8423 | { | |
9e30b8e0 | 8424 | { VEX_W_TABLE (VEX_W_C2_P_1) }, |
c0f3af97 L |
8425 | }, |
8426 | ||
8427 | /* VEX_LEN_C2_P_3 */ | |
8428 | { | |
9e30b8e0 | 8429 | { VEX_W_TABLE (VEX_W_C2_P_3) }, |
c0f3af97 L |
8430 | }, |
8431 | ||
8432 | /* VEX_LEN_C4_P_2 */ | |
8433 | { | |
9e30b8e0 | 8434 | { VEX_W_TABLE (VEX_W_C4_P_2) }, |
c0f3af97 L |
8435 | }, |
8436 | ||
8437 | /* VEX_LEN_C5_P_2 */ | |
8438 | { | |
9e30b8e0 | 8439 | { VEX_W_TABLE (VEX_W_C5_P_2) }, |
c0f3af97 L |
8440 | }, |
8441 | ||
8442 | /* VEX_LEN_D1_P_2 */ | |
8443 | { | |
9e30b8e0 | 8444 | { VEX_W_TABLE (VEX_W_D1_P_2) }, |
c0f3af97 L |
8445 | }, |
8446 | ||
8447 | /* VEX_LEN_D2_P_2 */ | |
8448 | { | |
9e30b8e0 | 8449 | { VEX_W_TABLE (VEX_W_D2_P_2) }, |
c0f3af97 L |
8450 | }, |
8451 | ||
8452 | /* VEX_LEN_D3_P_2 */ | |
8453 | { | |
9e30b8e0 | 8454 | { VEX_W_TABLE (VEX_W_D3_P_2) }, |
c0f3af97 L |
8455 | }, |
8456 | ||
8457 | /* VEX_LEN_D4_P_2 */ | |
8458 | { | |
9e30b8e0 | 8459 | { VEX_W_TABLE (VEX_W_D4_P_2) }, |
c0f3af97 L |
8460 | }, |
8461 | ||
8462 | /* VEX_LEN_D5_P_2 */ | |
8463 | { | |
9e30b8e0 | 8464 | { VEX_W_TABLE (VEX_W_D5_P_2) }, |
c0f3af97 L |
8465 | }, |
8466 | ||
8467 | /* VEX_LEN_D6_P_2 */ | |
8468 | { | |
9e30b8e0 | 8469 | { VEX_W_TABLE (VEX_W_D6_P_2) }, |
c0f3af97 L |
8470 | }, |
8471 | ||
8472 | /* VEX_LEN_D7_P_2_M_1 */ | |
8473 | { | |
9e30b8e0 | 8474 | { VEX_W_TABLE (VEX_W_D7_P_2_M_1) }, |
c0f3af97 L |
8475 | }, |
8476 | ||
8477 | /* VEX_LEN_D8_P_2 */ | |
8478 | { | |
9e30b8e0 | 8479 | { VEX_W_TABLE (VEX_W_D8_P_2) }, |
c0f3af97 L |
8480 | }, |
8481 | ||
8482 | /* VEX_LEN_D9_P_2 */ | |
8483 | { | |
9e30b8e0 | 8484 | { VEX_W_TABLE (VEX_W_D9_P_2) }, |
c0f3af97 L |
8485 | }, |
8486 | ||
8487 | /* VEX_LEN_DA_P_2 */ | |
8488 | { | |
9e30b8e0 | 8489 | { VEX_W_TABLE (VEX_W_DA_P_2) }, |
c0f3af97 L |
8490 | }, |
8491 | ||
8492 | /* VEX_LEN_DB_P_2 */ | |
8493 | { | |
9e30b8e0 | 8494 | { VEX_W_TABLE (VEX_W_DB_P_2) }, |
c0f3af97 L |
8495 | }, |
8496 | ||
8497 | /* VEX_LEN_DC_P_2 */ | |
8498 | { | |
9e30b8e0 | 8499 | { VEX_W_TABLE (VEX_W_DC_P_2) }, |
c0f3af97 L |
8500 | }, |
8501 | ||
8502 | /* VEX_LEN_DD_P_2 */ | |
8503 | { | |
9e30b8e0 | 8504 | { VEX_W_TABLE (VEX_W_DD_P_2) }, |
c0f3af97 L |
8505 | }, |
8506 | ||
8507 | /* VEX_LEN_DE_P_2 */ | |
8508 | { | |
9e30b8e0 | 8509 | { VEX_W_TABLE (VEX_W_DE_P_2) }, |
c0f3af97 L |
8510 | }, |
8511 | ||
8512 | /* VEX_LEN_DF_P_2 */ | |
8513 | { | |
9e30b8e0 | 8514 | { VEX_W_TABLE (VEX_W_DF_P_2) }, |
c0f3af97 L |
8515 | }, |
8516 | ||
8517 | /* VEX_LEN_E0_P_2 */ | |
8518 | { | |
9e30b8e0 | 8519 | { VEX_W_TABLE (VEX_W_E0_P_2) }, |
c0f3af97 L |
8520 | }, |
8521 | ||
8522 | /* VEX_LEN_E1_P_2 */ | |
8523 | { | |
9e30b8e0 | 8524 | { VEX_W_TABLE (VEX_W_E1_P_2) }, |
c0f3af97 L |
8525 | }, |
8526 | ||
8527 | /* VEX_LEN_E2_P_2 */ | |
8528 | { | |
9e30b8e0 | 8529 | { VEX_W_TABLE (VEX_W_E2_P_2) }, |
c0f3af97 L |
8530 | }, |
8531 | ||
8532 | /* VEX_LEN_E3_P_2 */ | |
8533 | { | |
9e30b8e0 | 8534 | { VEX_W_TABLE (VEX_W_E3_P_2) }, |
c0f3af97 L |
8535 | }, |
8536 | ||
8537 | /* VEX_LEN_E4_P_2 */ | |
8538 | { | |
9e30b8e0 | 8539 | { VEX_W_TABLE (VEX_W_E4_P_2) }, |
c0f3af97 L |
8540 | }, |
8541 | ||
8542 | /* VEX_LEN_E5_P_2 */ | |
8543 | { | |
9e30b8e0 | 8544 | { VEX_W_TABLE (VEX_W_E5_P_2) }, |
c0f3af97 L |
8545 | }, |
8546 | ||
c0f3af97 L |
8547 | /* VEX_LEN_E8_P_2 */ |
8548 | { | |
9e30b8e0 | 8549 | { VEX_W_TABLE (VEX_W_E8_P_2) }, |
c0f3af97 L |
8550 | }, |
8551 | ||
8552 | /* VEX_LEN_E9_P_2 */ | |
8553 | { | |
9e30b8e0 | 8554 | { VEX_W_TABLE (VEX_W_E9_P_2) }, |
c0f3af97 L |
8555 | }, |
8556 | ||
8557 | /* VEX_LEN_EA_P_2 */ | |
8558 | { | |
9e30b8e0 | 8559 | { VEX_W_TABLE (VEX_W_EA_P_2) }, |
c0f3af97 L |
8560 | }, |
8561 | ||
8562 | /* VEX_LEN_EB_P_2 */ | |
8563 | { | |
9e30b8e0 | 8564 | { VEX_W_TABLE (VEX_W_EB_P_2) }, |
c0f3af97 L |
8565 | }, |
8566 | ||
8567 | /* VEX_LEN_EC_P_2 */ | |
8568 | { | |
9e30b8e0 | 8569 | { VEX_W_TABLE (VEX_W_EC_P_2) }, |
c0f3af97 L |
8570 | }, |
8571 | ||
8572 | /* VEX_LEN_ED_P_2 */ | |
8573 | { | |
9e30b8e0 | 8574 | { VEX_W_TABLE (VEX_W_ED_P_2) }, |
c0f3af97 L |
8575 | }, |
8576 | ||
8577 | /* VEX_LEN_EE_P_2 */ | |
8578 | { | |
9e30b8e0 | 8579 | { VEX_W_TABLE (VEX_W_EE_P_2) }, |
c0f3af97 L |
8580 | }, |
8581 | ||
8582 | /* VEX_LEN_EF_P_2 */ | |
8583 | { | |
9e30b8e0 | 8584 | { VEX_W_TABLE (VEX_W_EF_P_2) }, |
c0f3af97 L |
8585 | }, |
8586 | ||
8587 | /* VEX_LEN_F1_P_2 */ | |
8588 | { | |
9e30b8e0 | 8589 | { VEX_W_TABLE (VEX_W_F1_P_2) }, |
c0f3af97 L |
8590 | }, |
8591 | ||
8592 | /* VEX_LEN_F2_P_2 */ | |
8593 | { | |
9e30b8e0 | 8594 | { VEX_W_TABLE (VEX_W_F2_P_2) }, |
c0f3af97 L |
8595 | }, |
8596 | ||
8597 | /* VEX_LEN_F3_P_2 */ | |
8598 | { | |
9e30b8e0 | 8599 | { VEX_W_TABLE (VEX_W_F3_P_2) }, |
c0f3af97 L |
8600 | }, |
8601 | ||
8602 | /* VEX_LEN_F4_P_2 */ | |
8603 | { | |
9e30b8e0 | 8604 | { VEX_W_TABLE (VEX_W_F4_P_2) }, |
c0f3af97 L |
8605 | }, |
8606 | ||
8607 | /* VEX_LEN_F5_P_2 */ | |
8608 | { | |
9e30b8e0 | 8609 | { VEX_W_TABLE (VEX_W_F5_P_2) }, |
c0f3af97 L |
8610 | }, |
8611 | ||
8612 | /* VEX_LEN_F6_P_2 */ | |
8613 | { | |
9e30b8e0 | 8614 | { VEX_W_TABLE (VEX_W_F6_P_2) }, |
c0f3af97 L |
8615 | }, |
8616 | ||
8617 | /* VEX_LEN_F7_P_2 */ | |
8618 | { | |
9e30b8e0 | 8619 | { VEX_W_TABLE (VEX_W_F7_P_2) }, |
c0f3af97 L |
8620 | }, |
8621 | ||
8622 | /* VEX_LEN_F8_P_2 */ | |
8623 | { | |
9e30b8e0 | 8624 | { VEX_W_TABLE (VEX_W_F8_P_2) }, |
c0f3af97 L |
8625 | }, |
8626 | ||
8627 | /* VEX_LEN_F9_P_2 */ | |
8628 | { | |
9e30b8e0 | 8629 | { VEX_W_TABLE (VEX_W_F9_P_2) }, |
c0f3af97 L |
8630 | }, |
8631 | ||
8632 | /* VEX_LEN_FA_P_2 */ | |
8633 | { | |
9e30b8e0 | 8634 | { VEX_W_TABLE (VEX_W_FA_P_2) }, |
c0f3af97 L |
8635 | }, |
8636 | ||
8637 | /* VEX_LEN_FB_P_2 */ | |
8638 | { | |
9e30b8e0 | 8639 | { VEX_W_TABLE (VEX_W_FB_P_2) }, |
c0f3af97 L |
8640 | }, |
8641 | ||
8642 | /* VEX_LEN_FC_P_2 */ | |
8643 | { | |
9e30b8e0 | 8644 | { VEX_W_TABLE (VEX_W_FC_P_2) }, |
c0f3af97 L |
8645 | }, |
8646 | ||
8647 | /* VEX_LEN_FD_P_2 */ | |
8648 | { | |
9e30b8e0 | 8649 | { VEX_W_TABLE (VEX_W_FD_P_2) }, |
c0f3af97 L |
8650 | }, |
8651 | ||
8652 | /* VEX_LEN_FE_P_2 */ | |
8653 | { | |
9e30b8e0 | 8654 | { VEX_W_TABLE (VEX_W_FE_P_2) }, |
c0f3af97 L |
8655 | }, |
8656 | ||
8657 | /* VEX_LEN_3800_P_2 */ | |
8658 | { | |
9e30b8e0 | 8659 | { VEX_W_TABLE (VEX_W_3800_P_2) }, |
c0f3af97 L |
8660 | }, |
8661 | ||
8662 | /* VEX_LEN_3801_P_2 */ | |
8663 | { | |
9e30b8e0 | 8664 | { VEX_W_TABLE (VEX_W_3801_P_2) }, |
c0f3af97 L |
8665 | }, |
8666 | ||
8667 | /* VEX_LEN_3802_P_2 */ | |
8668 | { | |
9e30b8e0 | 8669 | { VEX_W_TABLE (VEX_W_3802_P_2) }, |
c0f3af97 L |
8670 | }, |
8671 | ||
8672 | /* VEX_LEN_3803_P_2 */ | |
8673 | { | |
9e30b8e0 | 8674 | { VEX_W_TABLE (VEX_W_3803_P_2) }, |
c0f3af97 L |
8675 | }, |
8676 | ||
8677 | /* VEX_LEN_3804_P_2 */ | |
8678 | { | |
9e30b8e0 | 8679 | { VEX_W_TABLE (VEX_W_3804_P_2) }, |
c0f3af97 L |
8680 | }, |
8681 | ||
8682 | /* VEX_LEN_3805_P_2 */ | |
8683 | { | |
9e30b8e0 | 8684 | { VEX_W_TABLE (VEX_W_3805_P_2) }, |
c0f3af97 L |
8685 | }, |
8686 | ||
8687 | /* VEX_LEN_3806_P_2 */ | |
8688 | { | |
9e30b8e0 | 8689 | { VEX_W_TABLE (VEX_W_3806_P_2) }, |
c0f3af97 L |
8690 | }, |
8691 | ||
8692 | /* VEX_LEN_3807_P_2 */ | |
8693 | { | |
9e30b8e0 | 8694 | { VEX_W_TABLE (VEX_W_3807_P_2) }, |
c0f3af97 L |
8695 | }, |
8696 | ||
8697 | /* VEX_LEN_3808_P_2 */ | |
8698 | { | |
9e30b8e0 | 8699 | { VEX_W_TABLE (VEX_W_3808_P_2) }, |
c0f3af97 L |
8700 | }, |
8701 | ||
8702 | /* VEX_LEN_3809_P_2 */ | |
8703 | { | |
9e30b8e0 | 8704 | { VEX_W_TABLE (VEX_W_3809_P_2) }, |
c0f3af97 L |
8705 | }, |
8706 | ||
8707 | /* VEX_LEN_380A_P_2 */ | |
8708 | { | |
9e30b8e0 | 8709 | { VEX_W_TABLE (VEX_W_380A_P_2) }, |
c0f3af97 L |
8710 | }, |
8711 | ||
8712 | /* VEX_LEN_380B_P_2 */ | |
8713 | { | |
9e30b8e0 | 8714 | { VEX_W_TABLE (VEX_W_380B_P_2) }, |
c0f3af97 L |
8715 | }, |
8716 | ||
8717 | /* VEX_LEN_3819_P_2_M_0 */ | |
8718 | { | |
592d1631 | 8719 | { Bad_Opcode }, |
9e30b8e0 | 8720 | { VEX_W_TABLE (VEX_W_3819_P_2_M_0) }, |
c0f3af97 L |
8721 | }, |
8722 | ||
8723 | /* VEX_LEN_381A_P_2_M_0 */ | |
8724 | { | |
592d1631 | 8725 | { Bad_Opcode }, |
9e30b8e0 | 8726 | { VEX_W_TABLE (VEX_W_381A_P_2_M_0) }, |
c0f3af97 L |
8727 | }, |
8728 | ||
8729 | /* VEX_LEN_381C_P_2 */ | |
8730 | { | |
9e30b8e0 | 8731 | { VEX_W_TABLE (VEX_W_381C_P_2) }, |
c0f3af97 L |
8732 | }, |
8733 | ||
8734 | /* VEX_LEN_381D_P_2 */ | |
8735 | { | |
9e30b8e0 | 8736 | { VEX_W_TABLE (VEX_W_381D_P_2) }, |
c0f3af97 L |
8737 | }, |
8738 | ||
8739 | /* VEX_LEN_381E_P_2 */ | |
8740 | { | |
9e30b8e0 | 8741 | { VEX_W_TABLE (VEX_W_381E_P_2) }, |
c0f3af97 L |
8742 | }, |
8743 | ||
8744 | /* VEX_LEN_3820_P_2 */ | |
8745 | { | |
9e30b8e0 | 8746 | { VEX_W_TABLE (VEX_W_3820_P_2) }, |
c0f3af97 L |
8747 | }, |
8748 | ||
8749 | /* VEX_LEN_3821_P_2 */ | |
8750 | { | |
9e30b8e0 | 8751 | { VEX_W_TABLE (VEX_W_3821_P_2) }, |
c0f3af97 L |
8752 | }, |
8753 | ||
8754 | /* VEX_LEN_3822_P_2 */ | |
8755 | { | |
9e30b8e0 | 8756 | { VEX_W_TABLE (VEX_W_3822_P_2) }, |
c0f3af97 L |
8757 | }, |
8758 | ||
8759 | /* VEX_LEN_3823_P_2 */ | |
8760 | { | |
9e30b8e0 | 8761 | { VEX_W_TABLE (VEX_W_3823_P_2) }, |
c0f3af97 L |
8762 | }, |
8763 | ||
8764 | /* VEX_LEN_3824_P_2 */ | |
8765 | { | |
9e30b8e0 | 8766 | { VEX_W_TABLE (VEX_W_3824_P_2) }, |
c0f3af97 L |
8767 | }, |
8768 | ||
8769 | /* VEX_LEN_3825_P_2 */ | |
8770 | { | |
9e30b8e0 | 8771 | { VEX_W_TABLE (VEX_W_3825_P_2) }, |
c0f3af97 L |
8772 | }, |
8773 | ||
8774 | /* VEX_LEN_3828_P_2 */ | |
8775 | { | |
9e30b8e0 | 8776 | { VEX_W_TABLE (VEX_W_3828_P_2) }, |
c0f3af97 L |
8777 | }, |
8778 | ||
8779 | /* VEX_LEN_3829_P_2 */ | |
8780 | { | |
9e30b8e0 | 8781 | { VEX_W_TABLE (VEX_W_3829_P_2) }, |
c0f3af97 L |
8782 | }, |
8783 | ||
8784 | /* VEX_LEN_382A_P_2_M_0 */ | |
8785 | { | |
9e30b8e0 | 8786 | { VEX_W_TABLE (VEX_W_382A_P_2_M_0) }, |
c0f3af97 L |
8787 | }, |
8788 | ||
8789 | /* VEX_LEN_382B_P_2 */ | |
8790 | { | |
9e30b8e0 | 8791 | { VEX_W_TABLE (VEX_W_382B_P_2) }, |
c0f3af97 L |
8792 | }, |
8793 | ||
8794 | /* VEX_LEN_3830_P_2 */ | |
8795 | { | |
9e30b8e0 | 8796 | { VEX_W_TABLE (VEX_W_3830_P_2) }, |
c0f3af97 L |
8797 | }, |
8798 | ||
8799 | /* VEX_LEN_3831_P_2 */ | |
8800 | { | |
9e30b8e0 | 8801 | { VEX_W_TABLE (VEX_W_3831_P_2) }, |
c0f3af97 L |
8802 | }, |
8803 | ||
8804 | /* VEX_LEN_3832_P_2 */ | |
8805 | { | |
9e30b8e0 | 8806 | { VEX_W_TABLE (VEX_W_3832_P_2) }, |
c0f3af97 L |
8807 | }, |
8808 | ||
8809 | /* VEX_LEN_3833_P_2 */ | |
8810 | { | |
9e30b8e0 | 8811 | { VEX_W_TABLE (VEX_W_3833_P_2) }, |
c0f3af97 L |
8812 | }, |
8813 | ||
8814 | /* VEX_LEN_3834_P_2 */ | |
8815 | { | |
9e30b8e0 | 8816 | { VEX_W_TABLE (VEX_W_3834_P_2) }, |
c0f3af97 L |
8817 | }, |
8818 | ||
8819 | /* VEX_LEN_3835_P_2 */ | |
8820 | { | |
9e30b8e0 | 8821 | { VEX_W_TABLE (VEX_W_3835_P_2) }, |
c0f3af97 L |
8822 | }, |
8823 | ||
8824 | /* VEX_LEN_3837_P_2 */ | |
8825 | { | |
9e30b8e0 | 8826 | { VEX_W_TABLE (VEX_W_3837_P_2) }, |
c0f3af97 L |
8827 | }, |
8828 | ||
8829 | /* VEX_LEN_3838_P_2 */ | |
8830 | { | |
9e30b8e0 | 8831 | { VEX_W_TABLE (VEX_W_3838_P_2) }, |
c0f3af97 L |
8832 | }, |
8833 | ||
8834 | /* VEX_LEN_3839_P_2 */ | |
8835 | { | |
9e30b8e0 | 8836 | { VEX_W_TABLE (VEX_W_3839_P_2) }, |
c0f3af97 L |
8837 | }, |
8838 | ||
8839 | /* VEX_LEN_383A_P_2 */ | |
8840 | { | |
9e30b8e0 | 8841 | { VEX_W_TABLE (VEX_W_383A_P_2) }, |
c0f3af97 L |
8842 | }, |
8843 | ||
8844 | /* VEX_LEN_383B_P_2 */ | |
8845 | { | |
9e30b8e0 | 8846 | { VEX_W_TABLE (VEX_W_383B_P_2) }, |
c0f3af97 L |
8847 | }, |
8848 | ||
8849 | /* VEX_LEN_383C_P_2 */ | |
8850 | { | |
9e30b8e0 | 8851 | { VEX_W_TABLE (VEX_W_383C_P_2) }, |
c0f3af97 L |
8852 | }, |
8853 | ||
8854 | /* VEX_LEN_383D_P_2 */ | |
8855 | { | |
9e30b8e0 | 8856 | { VEX_W_TABLE (VEX_W_383D_P_2) }, |
c0f3af97 L |
8857 | }, |
8858 | ||
8859 | /* VEX_LEN_383E_P_2 */ | |
8860 | { | |
9e30b8e0 | 8861 | { VEX_W_TABLE (VEX_W_383E_P_2) }, |
c0f3af97 L |
8862 | }, |
8863 | ||
8864 | /* VEX_LEN_383F_P_2 */ | |
8865 | { | |
9e30b8e0 | 8866 | { VEX_W_TABLE (VEX_W_383F_P_2) }, |
c0f3af97 L |
8867 | }, |
8868 | ||
8869 | /* VEX_LEN_3840_P_2 */ | |
8870 | { | |
9e30b8e0 | 8871 | { VEX_W_TABLE (VEX_W_3840_P_2) }, |
c0f3af97 L |
8872 | }, |
8873 | ||
8874 | /* VEX_LEN_3841_P_2 */ | |
8875 | { | |
9e30b8e0 | 8876 | { VEX_W_TABLE (VEX_W_3841_P_2) }, |
c0f3af97 L |
8877 | }, |
8878 | ||
a5ff0eb2 L |
8879 | /* VEX_LEN_38DB_P_2 */ |
8880 | { | |
9e30b8e0 | 8881 | { VEX_W_TABLE (VEX_W_38DB_P_2) }, |
a5ff0eb2 L |
8882 | }, |
8883 | ||
8884 | /* VEX_LEN_38DC_P_2 */ | |
8885 | { | |
9e30b8e0 | 8886 | { VEX_W_TABLE (VEX_W_38DC_P_2) }, |
a5ff0eb2 L |
8887 | }, |
8888 | ||
8889 | /* VEX_LEN_38DD_P_2 */ | |
8890 | { | |
9e30b8e0 | 8891 | { VEX_W_TABLE (VEX_W_38DD_P_2) }, |
a5ff0eb2 L |
8892 | }, |
8893 | ||
8894 | /* VEX_LEN_38DE_P_2 */ | |
8895 | { | |
9e30b8e0 | 8896 | { VEX_W_TABLE (VEX_W_38DE_P_2) }, |
a5ff0eb2 L |
8897 | }, |
8898 | ||
8899 | /* VEX_LEN_38DF_P_2 */ | |
8900 | { | |
9e30b8e0 | 8901 | { VEX_W_TABLE (VEX_W_38DF_P_2) }, |
a5ff0eb2 L |
8902 | }, |
8903 | ||
c0f3af97 L |
8904 | /* VEX_LEN_3A06_P_2 */ |
8905 | { | |
592d1631 | 8906 | { Bad_Opcode }, |
9e30b8e0 | 8907 | { VEX_W_TABLE (VEX_W_3A06_P_2) }, |
c0f3af97 L |
8908 | }, |
8909 | ||
8910 | /* VEX_LEN_3A0A_P_2 */ | |
8911 | { | |
9e30b8e0 | 8912 | { VEX_W_TABLE (VEX_W_3A0A_P_2) }, |
c0f3af97 L |
8913 | }, |
8914 | ||
8915 | /* VEX_LEN_3A0B_P_2 */ | |
8916 | { | |
9e30b8e0 | 8917 | { VEX_W_TABLE (VEX_W_3A0B_P_2) }, |
c0f3af97 L |
8918 | }, |
8919 | ||
8920 | /* VEX_LEN_3A0E_P_2 */ | |
8921 | { | |
9e30b8e0 | 8922 | { VEX_W_TABLE (VEX_W_3A0E_P_2) }, |
c0f3af97 L |
8923 | }, |
8924 | ||
8925 | /* VEX_LEN_3A0F_P_2 */ | |
8926 | { | |
9e30b8e0 | 8927 | { VEX_W_TABLE (VEX_W_3A0F_P_2) }, |
c0f3af97 L |
8928 | }, |
8929 | ||
8930 | /* VEX_LEN_3A14_P_2 */ | |
8931 | { | |
9e30b8e0 | 8932 | { VEX_W_TABLE (VEX_W_3A14_P_2) }, |
c0f3af97 L |
8933 | }, |
8934 | ||
8935 | /* VEX_LEN_3A15_P_2 */ | |
8936 | { | |
9e30b8e0 | 8937 | { VEX_W_TABLE (VEX_W_3A15_P_2) }, |
c0f3af97 L |
8938 | }, |
8939 | ||
8940 | /* VEX_LEN_3A16_P_2 */ | |
8941 | { | |
8942 | { "vpextrK", { Edq, XM, Ib } }, | |
c0f3af97 L |
8943 | }, |
8944 | ||
8945 | /* VEX_LEN_3A17_P_2 */ | |
8946 | { | |
8947 | { "vextractps", { Edqd, XM, Ib } }, | |
c0f3af97 L |
8948 | }, |
8949 | ||
8950 | /* VEX_LEN_3A18_P_2 */ | |
8951 | { | |
592d1631 | 8952 | { Bad_Opcode }, |
9e30b8e0 | 8953 | { VEX_W_TABLE (VEX_W_3A18_P_2) }, |
c0f3af97 L |
8954 | }, |
8955 | ||
8956 | /* VEX_LEN_3A19_P_2 */ | |
8957 | { | |
592d1631 | 8958 | { Bad_Opcode }, |
9e30b8e0 | 8959 | { VEX_W_TABLE (VEX_W_3A19_P_2) }, |
c0f3af97 L |
8960 | }, |
8961 | ||
8962 | /* VEX_LEN_3A20_P_2 */ | |
8963 | { | |
9e30b8e0 | 8964 | { VEX_W_TABLE (VEX_W_3A20_P_2) }, |
c0f3af97 L |
8965 | }, |
8966 | ||
8967 | /* VEX_LEN_3A21_P_2 */ | |
8968 | { | |
9e30b8e0 | 8969 | { VEX_W_TABLE (VEX_W_3A21_P_2) }, |
c0f3af97 L |
8970 | }, |
8971 | ||
8972 | /* VEX_LEN_3A22_P_2 */ | |
8973 | { | |
8974 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
c0f3af97 L |
8975 | }, |
8976 | ||
8977 | /* VEX_LEN_3A41_P_2 */ | |
8978 | { | |
9e30b8e0 | 8979 | { VEX_W_TABLE (VEX_W_3A41_P_2) }, |
c0f3af97 L |
8980 | }, |
8981 | ||
8982 | /* VEX_LEN_3A42_P_2 */ | |
8983 | { | |
9e30b8e0 | 8984 | { VEX_W_TABLE (VEX_W_3A42_P_2) }, |
c0f3af97 L |
8985 | }, |
8986 | ||
ce2f5b3c L |
8987 | /* VEX_LEN_3A44_P_2 */ |
8988 | { | |
9e30b8e0 | 8989 | { VEX_W_TABLE (VEX_W_3A44_P_2) }, |
ce2f5b3c L |
8990 | }, |
8991 | ||
c0f3af97 L |
8992 | /* VEX_LEN_3A4C_P_2 */ |
8993 | { | |
9e30b8e0 | 8994 | { VEX_W_TABLE (VEX_W_3A4C_P_2) }, |
c0f3af97 L |
8995 | }, |
8996 | ||
8997 | /* VEX_LEN_3A60_P_2 */ | |
8998 | { | |
9e30b8e0 | 8999 | { VEX_W_TABLE (VEX_W_3A60_P_2) }, |
c0f3af97 L |
9000 | }, |
9001 | ||
9002 | /* VEX_LEN_3A61_P_2 */ | |
9003 | { | |
9e30b8e0 | 9004 | { VEX_W_TABLE (VEX_W_3A61_P_2) }, |
c0f3af97 L |
9005 | }, |
9006 | ||
9007 | /* VEX_LEN_3A62_P_2 */ | |
9008 | { | |
9e30b8e0 | 9009 | { VEX_W_TABLE (VEX_W_3A62_P_2) }, |
c0f3af97 L |
9010 | }, |
9011 | ||
9012 | /* VEX_LEN_3A63_P_2 */ | |
9013 | { | |
9e30b8e0 | 9014 | { VEX_W_TABLE (VEX_W_3A63_P_2) }, |
c0f3af97 L |
9015 | }, |
9016 | ||
922d8de8 DR |
9017 | /* VEX_LEN_3A6A_P_2 */ |
9018 | { | |
206c2556 | 9019 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9020 | }, |
9021 | ||
9022 | /* VEX_LEN_3A6B_P_2 */ | |
9023 | { | |
206c2556 | 9024 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9025 | }, |
9026 | ||
9027 | /* VEX_LEN_3A6E_P_2 */ | |
9028 | { | |
206c2556 | 9029 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9030 | }, |
9031 | ||
9032 | /* VEX_LEN_3A6F_P_2 */ | |
9033 | { | |
206c2556 | 9034 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9035 | }, |
9036 | ||
9037 | /* VEX_LEN_3A7A_P_2 */ | |
9038 | { | |
206c2556 | 9039 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9040 | }, |
9041 | ||
9042 | /* VEX_LEN_3A7B_P_2 */ | |
9043 | { | |
206c2556 | 9044 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9045 | }, |
9046 | ||
9047 | /* VEX_LEN_3A7E_P_2 */ | |
9048 | { | |
206c2556 | 9049 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9050 | }, |
9051 | ||
9052 | /* VEX_LEN_3A7F_P_2 */ | |
9053 | { | |
206c2556 | 9054 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9055 | }, |
9056 | ||
a5ff0eb2 L |
9057 | /* VEX_LEN_3ADF_P_2 */ |
9058 | { | |
9e30b8e0 | 9059 | { VEX_W_TABLE (VEX_W_3ADF_P_2) }, |
a5ff0eb2 | 9060 | }, |
4c807e72 | 9061 | |
5dd85c99 SP |
9062 | /* VEX_LEN_XOP_09_80 */ |
9063 | { | |
4c807e72 L |
9064 | { "vfrczps", { XM, EXxmm } }, |
9065 | { "vfrczps", { XM, EXymmq } }, | |
5dd85c99 | 9066 | }, |
4c807e72 | 9067 | |
5dd85c99 SP |
9068 | /* VEX_LEN_XOP_09_81 */ |
9069 | { | |
4c807e72 L |
9070 | { "vfrczpd", { XM, EXxmm } }, |
9071 | { "vfrczpd", { XM, EXymmq } }, | |
5dd85c99 | 9072 | }, |
331d2d0d L |
9073 | }; |
9074 | ||
9e30b8e0 | 9075 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 9076 | { |
9e30b8e0 L |
9077 | /* VEX_W_10_P_0 */ |
9078 | { "vmovups", { XM, EXx } }, | |
d8faab4e L |
9079 | }, |
9080 | { | |
9e30b8e0 L |
9081 | /* VEX_W_10_P_1 */ |
9082 | { "vmovss", { XMVex, Vex128, EXd } }, | |
d8faab4e L |
9083 | }, |
9084 | { | |
9e30b8e0 L |
9085 | /* VEX_W_10_P_2 */ |
9086 | { "vmovupd", { XM, EXx } }, | |
d8faab4e L |
9087 | }, |
9088 | { | |
9e30b8e0 L |
9089 | /* VEX_W_10_P_3 */ |
9090 | { "vmovsd", { XMVex, Vex128, EXq } }, | |
d8faab4e L |
9091 | }, |
9092 | { | |
9e30b8e0 L |
9093 | /* VEX_W_11_P_0 */ |
9094 | { "vmovups", { EXxS, XM } }, | |
d8faab4e L |
9095 | }, |
9096 | { | |
9e30b8e0 L |
9097 | /* VEX_W_11_P_1 */ |
9098 | { "vmovss", { EXdVexS, Vex128, XM } }, | |
b844680a L |
9099 | }, |
9100 | { | |
9e30b8e0 L |
9101 | /* VEX_W_11_P_2 */ |
9102 | { "vmovupd", { EXxS, XM } }, | |
b844680a L |
9103 | }, |
9104 | { | |
9e30b8e0 L |
9105 | /* VEX_W_11_P_3 */ |
9106 | { "vmovsd", { EXqVexS, Vex128, XM } }, | |
d8faab4e L |
9107 | }, |
9108 | { | |
9e30b8e0 L |
9109 | /* VEX_W_12_P_0_M_0 */ |
9110 | { "vmovlps", { XM, Vex128, EXq } }, | |
b844680a L |
9111 | }, |
9112 | { | |
9e30b8e0 L |
9113 | /* VEX_W_12_P_0_M_1 */ |
9114 | { "vmovhlps", { XM, Vex128, EXq } }, | |
b844680a L |
9115 | }, |
9116 | { | |
9e30b8e0 L |
9117 | /* VEX_W_12_P_1 */ |
9118 | { "vmovsldup", { XM, EXx } }, | |
b844680a L |
9119 | }, |
9120 | { | |
9e30b8e0 L |
9121 | /* VEX_W_12_P_2 */ |
9122 | { "vmovlpd", { XM, Vex128, EXq } }, | |
b844680a L |
9123 | }, |
9124 | { | |
9e30b8e0 L |
9125 | /* VEX_W_12_P_3 */ |
9126 | { "vmovddup", { XM, EXymmq } }, | |
b844680a L |
9127 | }, |
9128 | { | |
9e30b8e0 L |
9129 | /* VEX_W_13_M_0 */ |
9130 | { "vmovlpX", { EXq, XM } }, | |
b844680a L |
9131 | }, |
9132 | { | |
9e30b8e0 L |
9133 | /* VEX_W_14 */ |
9134 | { "vunpcklpX", { XM, Vex, EXx } }, | |
b844680a L |
9135 | }, |
9136 | { | |
9e30b8e0 L |
9137 | /* VEX_W_15 */ |
9138 | { "vunpckhpX", { XM, Vex, EXx } }, | |
b844680a L |
9139 | }, |
9140 | { | |
9e30b8e0 L |
9141 | /* VEX_W_16_P_0_M_0 */ |
9142 | { "vmovhps", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9143 | }, |
9144 | { | |
9145 | /* VEX_W_16_P_0_M_1 */ | |
9146 | { "vmovlhps", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9147 | }, |
9148 | { | |
9149 | /* VEX_W_16_P_1 */ | |
9150 | { "vmovshdup", { XM, EXx } }, | |
9e30b8e0 L |
9151 | }, |
9152 | { | |
9153 | /* VEX_W_16_P_2 */ | |
9154 | { "vmovhpd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9155 | }, |
9156 | { | |
9157 | /* VEX_W_17_M_0 */ | |
9158 | { "vmovhpX", { EXq, XM } }, | |
9e30b8e0 L |
9159 | }, |
9160 | { | |
9161 | /* VEX_W_28 */ | |
9162 | { "vmovapX", { XM, EXx } }, | |
9e30b8e0 L |
9163 | }, |
9164 | { | |
9165 | /* VEX_W_29 */ | |
9166 | { "vmovapX", { EXxS, XM } }, | |
9e30b8e0 L |
9167 | }, |
9168 | { | |
9169 | /* VEX_W_2B_M_0 */ | |
9170 | { "vmovntpX", { Mx, XM } }, | |
9e30b8e0 L |
9171 | }, |
9172 | { | |
9173 | /* VEX_W_2E_P_0 */ | |
9174 | { "vucomiss", { XM, EXd } }, | |
9e30b8e0 L |
9175 | }, |
9176 | { | |
9177 | /* VEX_W_2E_P_2 */ | |
9178 | { "vucomisd", { XM, EXq } }, | |
9e30b8e0 L |
9179 | }, |
9180 | { | |
9181 | /* VEX_W_2F_P_0 */ | |
9182 | { "vcomiss", { XM, EXd } }, | |
9e30b8e0 L |
9183 | }, |
9184 | { | |
9185 | /* VEX_W_2F_P_2 */ | |
9186 | { "vcomisd", { XM, EXq } }, | |
9e30b8e0 L |
9187 | }, |
9188 | { | |
9189 | /* VEX_W_50_M_0 */ | |
9190 | { "vmovmskpX", { Gdq, XS } }, | |
9e30b8e0 L |
9191 | }, |
9192 | { | |
9193 | /* VEX_W_51_P_0 */ | |
9194 | { "vsqrtps", { XM, EXx } }, | |
9e30b8e0 L |
9195 | }, |
9196 | { | |
9197 | /* VEX_W_51_P_1 */ | |
9198 | { "vsqrtss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9199 | }, |
9200 | { | |
9201 | /* VEX_W_51_P_2 */ | |
9202 | { "vsqrtpd", { XM, EXx } }, | |
9e30b8e0 L |
9203 | }, |
9204 | { | |
9205 | /* VEX_W_51_P_3 */ | |
9206 | { "vsqrtsd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9207 | }, |
9208 | { | |
9209 | /* VEX_W_52_P_0 */ | |
9210 | { "vrsqrtps", { XM, EXx } }, | |
9e30b8e0 L |
9211 | }, |
9212 | { | |
9213 | /* VEX_W_52_P_1 */ | |
9214 | { "vrsqrtss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9215 | }, |
9216 | { | |
9217 | /* VEX_W_53_P_0 */ | |
9218 | { "vrcpps", { XM, EXx } }, | |
9e30b8e0 L |
9219 | }, |
9220 | { | |
9221 | /* VEX_W_53_P_1 */ | |
9222 | { "vrcpss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9223 | }, |
9224 | { | |
9225 | /* VEX_W_58_P_0 */ | |
9226 | { "vaddps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9227 | }, |
9228 | { | |
9229 | /* VEX_W_58_P_1 */ | |
9230 | { "vaddss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9231 | }, |
9232 | { | |
9233 | /* VEX_W_58_P_2 */ | |
9234 | { "vaddpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9235 | }, |
9236 | { | |
9237 | /* VEX_W_58_P_3 */ | |
9238 | { "vaddsd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9239 | }, |
9240 | { | |
9241 | /* VEX_W_59_P_0 */ | |
9242 | { "vmulps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9243 | }, |
9244 | { | |
9245 | /* VEX_W_59_P_1 */ | |
9246 | { "vmulss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9247 | }, |
9248 | { | |
9249 | /* VEX_W_59_P_2 */ | |
9250 | { "vmulpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9251 | }, |
9252 | { | |
9253 | /* VEX_W_59_P_3 */ | |
9254 | { "vmulsd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9255 | }, |
9256 | { | |
9257 | /* VEX_W_5A_P_0 */ | |
9258 | { "vcvtps2pd", { XM, EXxmmq } }, | |
9e30b8e0 L |
9259 | }, |
9260 | { | |
9261 | /* VEX_W_5A_P_1 */ | |
9262 | { "vcvtss2sd", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9263 | }, |
9264 | { | |
9265 | /* VEX_W_5A_P_3 */ | |
9266 | { "vcvtsd2ss", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9267 | }, |
9268 | { | |
9269 | /* VEX_W_5B_P_0 */ | |
9270 | { "vcvtdq2ps", { XM, EXx } }, | |
9e30b8e0 L |
9271 | }, |
9272 | { | |
9273 | /* VEX_W_5B_P_1 */ | |
9274 | { "vcvttps2dq", { XM, EXx } }, | |
9e30b8e0 L |
9275 | }, |
9276 | { | |
9277 | /* VEX_W_5B_P_2 */ | |
9278 | { "vcvtps2dq", { XM, EXx } }, | |
9e30b8e0 L |
9279 | }, |
9280 | { | |
9281 | /* VEX_W_5C_P_0 */ | |
9282 | { "vsubps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9283 | }, |
9284 | { | |
9285 | /* VEX_W_5C_P_1 */ | |
9286 | { "vsubss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9287 | }, |
9288 | { | |
9289 | /* VEX_W_5C_P_2 */ | |
9290 | { "vsubpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9291 | }, |
9292 | { | |
9293 | /* VEX_W_5C_P_3 */ | |
9294 | { "vsubsd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9295 | }, |
9296 | { | |
9297 | /* VEX_W_5D_P_0 */ | |
9298 | { "vminps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9299 | }, |
9300 | { | |
9301 | /* VEX_W_5D_P_1 */ | |
9302 | { "vminss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9303 | }, |
9304 | { | |
9305 | /* VEX_W_5D_P_2 */ | |
9306 | { "vminpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9307 | }, |
9308 | { | |
9309 | /* VEX_W_5D_P_3 */ | |
9310 | { "vminsd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9311 | }, |
9312 | { | |
9313 | /* VEX_W_5E_P_0 */ | |
9314 | { "vdivps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9315 | }, |
9316 | { | |
9317 | /* VEX_W_5E_P_1 */ | |
9318 | { "vdivss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9319 | }, |
9320 | { | |
9321 | /* VEX_W_5E_P_2 */ | |
9322 | { "vdivpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9323 | }, |
9324 | { | |
9325 | /* VEX_W_5E_P_3 */ | |
9326 | { "vdivsd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9327 | }, |
9328 | { | |
9329 | /* VEX_W_5F_P_0 */ | |
9330 | { "vmaxps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9331 | }, |
9332 | { | |
9333 | /* VEX_W_5F_P_1 */ | |
9334 | { "vmaxss", { XM, Vex128, EXd } }, | |
9e30b8e0 L |
9335 | }, |
9336 | { | |
9337 | /* VEX_W_5F_P_2 */ | |
9338 | { "vmaxpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9339 | }, |
9340 | { | |
9341 | /* VEX_W_5F_P_3 */ | |
9342 | { "vmaxsd", { XM, Vex128, EXq } }, | |
9e30b8e0 L |
9343 | }, |
9344 | { | |
9345 | /* VEX_W_60_P_2 */ | |
9346 | { "vpunpcklbw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9347 | }, |
9348 | { | |
9349 | /* VEX_W_61_P_2 */ | |
9350 | { "vpunpcklwd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9351 | }, |
9352 | { | |
9353 | /* VEX_W_62_P_2 */ | |
9354 | { "vpunpckldq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9355 | }, |
9356 | { | |
9357 | /* VEX_W_63_P_2 */ | |
9358 | { "vpacksswb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9359 | }, |
9360 | { | |
9361 | /* VEX_W_64_P_2 */ | |
9362 | { "vpcmpgtb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9363 | }, |
9364 | { | |
9365 | /* VEX_W_65_P_2 */ | |
9366 | { "vpcmpgtw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9367 | }, |
9368 | { | |
9369 | /* VEX_W_66_P_2 */ | |
9370 | { "vpcmpgtd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9371 | }, |
9372 | { | |
9373 | /* VEX_W_67_P_2 */ | |
9374 | { "vpackuswb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9375 | }, |
9376 | { | |
9377 | /* VEX_W_68_P_2 */ | |
9378 | { "vpunpckhbw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9379 | }, |
9380 | { | |
9381 | /* VEX_W_69_P_2 */ | |
9382 | { "vpunpckhwd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9383 | }, |
9384 | { | |
9385 | /* VEX_W_6A_P_2 */ | |
9386 | { "vpunpckhdq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9387 | }, |
9388 | { | |
9389 | /* VEX_W_6B_P_2 */ | |
9390 | { "vpackssdw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9391 | }, |
9392 | { | |
9393 | /* VEX_W_6C_P_2 */ | |
9394 | { "vpunpcklqdq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9395 | }, |
9396 | { | |
9397 | /* VEX_W_6D_P_2 */ | |
9398 | { "vpunpckhqdq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9399 | }, |
9400 | { | |
9401 | /* VEX_W_6F_P_1 */ | |
efdb52b7 | 9402 | { "vmovdqu", { XM, EXx } }, |
9e30b8e0 L |
9403 | }, |
9404 | { | |
9405 | /* VEX_W_6F_P_2 */ | |
efdb52b7 | 9406 | { "vmovdqa", { XM, EXx } }, |
9e30b8e0 L |
9407 | }, |
9408 | { | |
9409 | /* VEX_W_70_P_1 */ | |
9410 | { "vpshufhw", { XM, EXx, Ib } }, | |
9e30b8e0 L |
9411 | }, |
9412 | { | |
9413 | /* VEX_W_70_P_2 */ | |
9414 | { "vpshufd", { XM, EXx, Ib } }, | |
9e30b8e0 L |
9415 | }, |
9416 | { | |
9417 | /* VEX_W_70_P_3 */ | |
9418 | { "vpshuflw", { XM, EXx, Ib } }, | |
9e30b8e0 L |
9419 | }, |
9420 | { | |
9421 | /* VEX_W_71_R_2_P_2 */ | |
9422 | { "vpsrlw", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9423 | }, |
9424 | { | |
9425 | /* VEX_W_71_R_4_P_2 */ | |
9426 | { "vpsraw", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9427 | }, |
9428 | { | |
9429 | /* VEX_W_71_R_6_P_2 */ | |
9430 | { "vpsllw", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9431 | }, |
9432 | { | |
9433 | /* VEX_W_72_R_2_P_2 */ | |
9434 | { "vpsrld", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9435 | }, |
9436 | { | |
9437 | /* VEX_W_72_R_4_P_2 */ | |
9438 | { "vpsrad", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9439 | }, |
9440 | { | |
9441 | /* VEX_W_72_R_6_P_2 */ | |
9442 | { "vpslld", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9443 | }, |
9444 | { | |
9445 | /* VEX_W_73_R_2_P_2 */ | |
9446 | { "vpsrlq", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9447 | }, |
9448 | { | |
9449 | /* VEX_W_73_R_3_P_2 */ | |
9450 | { "vpsrldq", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9451 | }, |
9452 | { | |
9453 | /* VEX_W_73_R_6_P_2 */ | |
9454 | { "vpsllq", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9455 | }, |
9456 | { | |
9457 | /* VEX_W_73_R_7_P_2 */ | |
9458 | { "vpslldq", { Vex128, XS, Ib } }, | |
9e30b8e0 L |
9459 | }, |
9460 | { | |
9461 | /* VEX_W_74_P_2 */ | |
9462 | { "vpcmpeqb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9463 | }, |
9464 | { | |
9465 | /* VEX_W_75_P_2 */ | |
9466 | { "vpcmpeqw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9467 | }, |
9468 | { | |
9469 | /* VEX_W_76_P_2 */ | |
9470 | { "vpcmpeqd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9471 | }, |
9472 | { | |
9473 | /* VEX_W_77_P_0 */ | |
9474 | { "", { VZERO } }, | |
9e30b8e0 L |
9475 | }, |
9476 | { | |
9477 | /* VEX_W_7C_P_2 */ | |
9478 | { "vhaddpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9479 | }, |
9480 | { | |
9481 | /* VEX_W_7C_P_3 */ | |
9482 | { "vhaddps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9483 | }, |
9484 | { | |
9485 | /* VEX_W_7D_P_2 */ | |
9486 | { "vhsubpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9487 | }, |
9488 | { | |
9489 | /* VEX_W_7D_P_3 */ | |
9490 | { "vhsubps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9491 | }, |
9492 | { | |
9493 | /* VEX_W_7E_P_1 */ | |
9494 | { "vmovq", { XM, EXq } }, | |
9e30b8e0 L |
9495 | }, |
9496 | { | |
9497 | /* VEX_W_7F_P_1 */ | |
9498 | { "vmovdqu", { EXxS, XM } }, | |
9e30b8e0 L |
9499 | }, |
9500 | { | |
9501 | /* VEX_W_7F_P_2 */ | |
9502 | { "vmovdqa", { EXxS, XM } }, | |
9e30b8e0 L |
9503 | }, |
9504 | { | |
9505 | /* VEX_W_AE_R_2_M_0 */ | |
9506 | { "vldmxcsr", { Md } }, | |
9e30b8e0 L |
9507 | }, |
9508 | { | |
9509 | /* VEX_W_AE_R_3_M_0 */ | |
9510 | { "vstmxcsr", { Md } }, | |
9e30b8e0 L |
9511 | }, |
9512 | { | |
9513 | /* VEX_W_C2_P_0 */ | |
9514 | { "vcmpps", { XM, Vex, EXx, VCMP } }, | |
9e30b8e0 L |
9515 | }, |
9516 | { | |
9517 | /* VEX_W_C2_P_1 */ | |
9518 | { "vcmpss", { XM, Vex128, EXd, VCMP } }, | |
9e30b8e0 L |
9519 | }, |
9520 | { | |
9521 | /* VEX_W_C2_P_2 */ | |
9522 | { "vcmppd", { XM, Vex, EXx, VCMP } }, | |
9e30b8e0 L |
9523 | }, |
9524 | { | |
9525 | /* VEX_W_C2_P_3 */ | |
9526 | { "vcmpsd", { XM, Vex128, EXq, VCMP } }, | |
9e30b8e0 L |
9527 | }, |
9528 | { | |
9529 | /* VEX_W_C4_P_2 */ | |
9530 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, | |
9e30b8e0 L |
9531 | }, |
9532 | { | |
9533 | /* VEX_W_C5_P_2 */ | |
9534 | { "vpextrw", { Gdq, XS, Ib } }, | |
9e30b8e0 L |
9535 | }, |
9536 | { | |
9537 | /* VEX_W_D0_P_2 */ | |
9538 | { "vaddsubpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9539 | }, |
9540 | { | |
9541 | /* VEX_W_D0_P_3 */ | |
9542 | { "vaddsubps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9543 | }, |
9544 | { | |
9545 | /* VEX_W_D1_P_2 */ | |
9546 | { "vpsrlw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9547 | }, |
9548 | { | |
9549 | /* VEX_W_D2_P_2 */ | |
9550 | { "vpsrld", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9551 | }, |
9552 | { | |
9553 | /* VEX_W_D3_P_2 */ | |
9554 | { "vpsrlq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9555 | }, |
9556 | { | |
9557 | /* VEX_W_D4_P_2 */ | |
9558 | { "vpaddq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9559 | }, |
9560 | { | |
9561 | /* VEX_W_D5_P_2 */ | |
9562 | { "vpmullw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9563 | }, |
9564 | { | |
9565 | /* VEX_W_D6_P_2 */ | |
9566 | { "vmovq", { EXqS, XM } }, | |
9e30b8e0 L |
9567 | }, |
9568 | { | |
9569 | /* VEX_W_D7_P_2_M_1 */ | |
9570 | { "vpmovmskb", { Gdq, XS } }, | |
9e30b8e0 L |
9571 | }, |
9572 | { | |
9573 | /* VEX_W_D8_P_2 */ | |
9574 | { "vpsubusb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9575 | }, |
9576 | { | |
9577 | /* VEX_W_D9_P_2 */ | |
9578 | { "vpsubusw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9579 | }, |
9580 | { | |
9581 | /* VEX_W_DA_P_2 */ | |
9582 | { "vpminub", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9583 | }, |
9584 | { | |
9585 | /* VEX_W_DB_P_2 */ | |
9586 | { "vpand", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9587 | }, |
9588 | { | |
9589 | /* VEX_W_DC_P_2 */ | |
9590 | { "vpaddusb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9591 | }, |
9592 | { | |
9593 | /* VEX_W_DD_P_2 */ | |
9594 | { "vpaddusw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9595 | }, |
9596 | { | |
9597 | /* VEX_W_DE_P_2 */ | |
9598 | { "vpmaxub", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9599 | }, |
9600 | { | |
9601 | /* VEX_W_DF_P_2 */ | |
9602 | { "vpandn", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9603 | }, |
9604 | { | |
9605 | /* VEX_W_E0_P_2 */ | |
9606 | { "vpavgb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9607 | }, |
9608 | { | |
9609 | /* VEX_W_E1_P_2 */ | |
9610 | { "vpsraw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9611 | }, |
9612 | { | |
9613 | /* VEX_W_E2_P_2 */ | |
9614 | { "vpsrad", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9615 | }, |
9616 | { | |
9617 | /* VEX_W_E3_P_2 */ | |
9618 | { "vpavgw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9619 | }, |
9620 | { | |
9621 | /* VEX_W_E4_P_2 */ | |
9622 | { "vpmulhuw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9623 | }, |
9624 | { | |
9625 | /* VEX_W_E5_P_2 */ | |
9626 | { "vpmulhw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9627 | }, |
9628 | { | |
9629 | /* VEX_W_E6_P_1 */ | |
efdb52b7 | 9630 | { "vcvtdq2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
9631 | }, |
9632 | { | |
9633 | /* VEX_W_E6_P_2 */ | |
a179a9fd | 9634 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
9635 | }, |
9636 | { | |
9637 | /* VEX_W_E6_P_3 */ | |
a179a9fd | 9638 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
9639 | }, |
9640 | { | |
9641 | /* VEX_W_E7_P_2_M_0 */ | |
9642 | { "vmovntdq", { Mx, XM } }, | |
9e30b8e0 L |
9643 | }, |
9644 | { | |
9645 | /* VEX_W_E8_P_2 */ | |
9646 | { "vpsubsb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9647 | }, |
9648 | { | |
9649 | /* VEX_W_E9_P_2 */ | |
9650 | { "vpsubsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9651 | }, |
9652 | { | |
9653 | /* VEX_W_EA_P_2 */ | |
9654 | { "vpminsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9655 | }, |
9656 | { | |
9657 | /* VEX_W_EB_P_2 */ | |
9658 | { "vpor", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9659 | }, |
9660 | { | |
9661 | /* VEX_W_EC_P_2 */ | |
9662 | { "vpaddsb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9663 | }, |
9664 | { | |
9665 | /* VEX_W_ED_P_2 */ | |
9666 | { "vpaddsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9667 | }, |
9668 | { | |
9669 | /* VEX_W_EE_P_2 */ | |
9670 | { "vpmaxsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9671 | }, |
9672 | { | |
9673 | /* VEX_W_EF_P_2 */ | |
9674 | { "vpxor", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9675 | }, |
9676 | { | |
9677 | /* VEX_W_F0_P_3_M_0 */ | |
9678 | { "vlddqu", { XM, M } }, | |
9e30b8e0 L |
9679 | }, |
9680 | { | |
9681 | /* VEX_W_F1_P_2 */ | |
9682 | { "vpsllw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9683 | }, |
9684 | { | |
9685 | /* VEX_W_F2_P_2 */ | |
9686 | { "vpslld", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9687 | }, |
9688 | { | |
9689 | /* VEX_W_F3_P_2 */ | |
9690 | { "vpsllq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9691 | }, |
9692 | { | |
9693 | /* VEX_W_F4_P_2 */ | |
9694 | { "vpmuludq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9695 | }, |
9696 | { | |
9697 | /* VEX_W_F5_P_2 */ | |
9698 | { "vpmaddwd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9699 | }, |
9700 | { | |
9701 | /* VEX_W_F6_P_2 */ | |
9702 | { "vpsadbw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9703 | }, |
9704 | { | |
9705 | /* VEX_W_F7_P_2 */ | |
9706 | { "vmaskmovdqu", { XM, XS } }, | |
9e30b8e0 L |
9707 | }, |
9708 | { | |
9709 | /* VEX_W_F8_P_2 */ | |
9710 | { "vpsubb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9711 | }, |
9712 | { | |
9713 | /* VEX_W_F9_P_2 */ | |
9714 | { "vpsubw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9715 | }, |
9716 | { | |
9717 | /* VEX_W_FA_P_2 */ | |
9718 | { "vpsubd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9719 | }, |
9720 | { | |
9721 | /* VEX_W_FB_P_2 */ | |
9722 | { "vpsubq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9723 | }, |
9724 | { | |
9725 | /* VEX_W_FC_P_2 */ | |
9726 | { "vpaddb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9727 | }, |
9728 | { | |
9729 | /* VEX_W_FD_P_2 */ | |
9730 | { "vpaddw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9731 | }, |
9732 | { | |
9733 | /* VEX_W_FE_P_2 */ | |
9734 | { "vpaddd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9735 | }, |
9736 | { | |
9737 | /* VEX_W_3800_P_2 */ | |
9738 | { "vpshufb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9739 | }, |
9740 | { | |
9741 | /* VEX_W_3801_P_2 */ | |
9742 | { "vphaddw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9743 | }, |
9744 | { | |
9745 | /* VEX_W_3802_P_2 */ | |
9746 | { "vphaddd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9747 | }, |
9748 | { | |
9749 | /* VEX_W_3803_P_2 */ | |
9750 | { "vphaddsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9751 | }, |
9752 | { | |
9753 | /* VEX_W_3804_P_2 */ | |
9754 | { "vpmaddubsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9755 | }, |
9756 | { | |
9757 | /* VEX_W_3805_P_2 */ | |
9758 | { "vphsubw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9759 | }, |
9760 | { | |
9761 | /* VEX_W_3806_P_2 */ | |
9762 | { "vphsubd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9763 | }, |
9764 | { | |
9765 | /* VEX_W_3807_P_2 */ | |
9766 | { "vphsubsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9767 | }, |
9768 | { | |
9769 | /* VEX_W_3808_P_2 */ | |
9770 | { "vpsignb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9771 | }, |
9772 | { | |
9773 | /* VEX_W_3809_P_2 */ | |
9774 | { "vpsignw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9775 | }, |
9776 | { | |
9777 | /* VEX_W_380A_P_2 */ | |
9778 | { "vpsignd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9779 | }, |
9780 | { | |
9781 | /* VEX_W_380B_P_2 */ | |
9782 | { "vpmulhrsw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9783 | }, |
9784 | { | |
9785 | /* VEX_W_380C_P_2 */ | |
9786 | { "vpermilps", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9787 | }, |
9788 | { | |
9789 | /* VEX_W_380D_P_2 */ | |
9790 | { "vpermilpd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9791 | }, |
9792 | { | |
9793 | /* VEX_W_380E_P_2 */ | |
9794 | { "vtestps", { XM, EXx } }, | |
9e30b8e0 L |
9795 | }, |
9796 | { | |
9797 | /* VEX_W_380F_P_2 */ | |
9798 | { "vtestpd", { XM, EXx } }, | |
9e30b8e0 L |
9799 | }, |
9800 | { | |
9801 | /* VEX_W_3817_P_2 */ | |
9802 | { "vptest", { XM, EXx } }, | |
9e30b8e0 | 9803 | }, |
bcf2684f L |
9804 | { |
9805 | /* VEX_W_3818_P_2_M_0 */ | |
9806 | { "vbroadcastss", { XM, Md } }, | |
bcf2684f | 9807 | }, |
9e30b8e0 L |
9808 | { |
9809 | /* VEX_W_3819_P_2_M_0 */ | |
9810 | { "vbroadcastsd", { XM, Mq } }, | |
9e30b8e0 L |
9811 | }, |
9812 | { | |
9813 | /* VEX_W_381A_P_2_M_0 */ | |
9814 | { "vbroadcastf128", { XM, Mxmm } }, | |
9e30b8e0 L |
9815 | }, |
9816 | { | |
9817 | /* VEX_W_381C_P_2 */ | |
9818 | { "vpabsb", { XM, EXx } }, | |
9e30b8e0 L |
9819 | }, |
9820 | { | |
9821 | /* VEX_W_381D_P_2 */ | |
9822 | { "vpabsw", { XM, EXx } }, | |
9e30b8e0 L |
9823 | }, |
9824 | { | |
9825 | /* VEX_W_381E_P_2 */ | |
9826 | { "vpabsd", { XM, EXx } }, | |
9e30b8e0 L |
9827 | }, |
9828 | { | |
9829 | /* VEX_W_3820_P_2 */ | |
9830 | { "vpmovsxbw", { XM, EXq } }, | |
9e30b8e0 L |
9831 | }, |
9832 | { | |
9833 | /* VEX_W_3821_P_2 */ | |
9834 | { "vpmovsxbd", { XM, EXd } }, | |
9e30b8e0 L |
9835 | }, |
9836 | { | |
9837 | /* VEX_W_3822_P_2 */ | |
9838 | { "vpmovsxbq", { XM, EXw } }, | |
9e30b8e0 L |
9839 | }, |
9840 | { | |
9841 | /* VEX_W_3823_P_2 */ | |
9842 | { "vpmovsxwd", { XM, EXq } }, | |
9e30b8e0 L |
9843 | }, |
9844 | { | |
9845 | /* VEX_W_3824_P_2 */ | |
9846 | { "vpmovsxwq", { XM, EXd } }, | |
9e30b8e0 L |
9847 | }, |
9848 | { | |
9849 | /* VEX_W_3825_P_2 */ | |
9850 | { "vpmovsxdq", { XM, EXq } }, | |
9e30b8e0 L |
9851 | }, |
9852 | { | |
9853 | /* VEX_W_3828_P_2 */ | |
9854 | { "vpmuldq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9855 | }, |
9856 | { | |
9857 | /* VEX_W_3829_P_2 */ | |
9858 | { "vpcmpeqq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9859 | }, |
9860 | { | |
9861 | /* VEX_W_382A_P_2_M_0 */ | |
9862 | { "vmovntdqa", { XM, Mx } }, | |
9e30b8e0 L |
9863 | }, |
9864 | { | |
9865 | /* VEX_W_382B_P_2 */ | |
9866 | { "vpackusdw", { XM, Vex128, EXx } }, | |
9e30b8e0 | 9867 | }, |
53aa04a0 L |
9868 | { |
9869 | /* VEX_W_382C_P_2_M_0 */ | |
9870 | { "vmaskmovps", { XM, Vex, Mx } }, | |
53aa04a0 L |
9871 | }, |
9872 | { | |
9873 | /* VEX_W_382D_P_2_M_0 */ | |
9874 | { "vmaskmovpd", { XM, Vex, Mx } }, | |
53aa04a0 L |
9875 | }, |
9876 | { | |
9877 | /* VEX_W_382E_P_2_M_0 */ | |
9878 | { "vmaskmovps", { Mx, Vex, XM } }, | |
53aa04a0 L |
9879 | }, |
9880 | { | |
9881 | /* VEX_W_382F_P_2_M_0 */ | |
9882 | { "vmaskmovpd", { Mx, Vex, XM } }, | |
53aa04a0 | 9883 | }, |
9e30b8e0 L |
9884 | { |
9885 | /* VEX_W_3830_P_2 */ | |
9886 | { "vpmovzxbw", { XM, EXq } }, | |
9e30b8e0 L |
9887 | }, |
9888 | { | |
9889 | /* VEX_W_3831_P_2 */ | |
9890 | { "vpmovzxbd", { XM, EXd } }, | |
9e30b8e0 L |
9891 | }, |
9892 | { | |
9893 | /* VEX_W_3832_P_2 */ | |
9894 | { "vpmovzxbq", { XM, EXw } }, | |
9e30b8e0 L |
9895 | }, |
9896 | { | |
9897 | /* VEX_W_3833_P_2 */ | |
9898 | { "vpmovzxwd", { XM, EXq } }, | |
9e30b8e0 L |
9899 | }, |
9900 | { | |
9901 | /* VEX_W_3834_P_2 */ | |
9902 | { "vpmovzxwq", { XM, EXd } }, | |
9e30b8e0 L |
9903 | }, |
9904 | { | |
9905 | /* VEX_W_3835_P_2 */ | |
9906 | { "vpmovzxdq", { XM, EXq } }, | |
9e30b8e0 L |
9907 | }, |
9908 | { | |
9909 | /* VEX_W_3837_P_2 */ | |
9910 | { "vpcmpgtq", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9911 | }, |
9912 | { | |
9913 | /* VEX_W_3838_P_2 */ | |
9914 | { "vpminsb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9915 | }, |
9916 | { | |
9917 | /* VEX_W_3839_P_2 */ | |
9918 | { "vpminsd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9919 | }, |
9920 | { | |
9921 | /* VEX_W_383A_P_2 */ | |
9922 | { "vpminuw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9923 | }, |
9924 | { | |
9925 | /* VEX_W_383B_P_2 */ | |
9926 | { "vpminud", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9927 | }, |
9928 | { | |
9929 | /* VEX_W_383C_P_2 */ | |
9930 | { "vpmaxsb", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9931 | }, |
9932 | { | |
9933 | /* VEX_W_383D_P_2 */ | |
9934 | { "vpmaxsd", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9935 | }, |
9936 | { | |
9937 | /* VEX_W_383E_P_2 */ | |
9938 | { "vpmaxuw", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9939 | }, |
9940 | { | |
9941 | /* VEX_W_383F_P_2 */ | |
9942 | { "vpmaxud", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9943 | }, |
9944 | { | |
9945 | /* VEX_W_3840_P_2 */ | |
9946 | { "vpmulld", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9947 | }, |
9948 | { | |
9949 | /* VEX_W_3841_P_2 */ | |
9950 | { "vphminposuw", { XM, EXx } }, | |
9e30b8e0 L |
9951 | }, |
9952 | { | |
9953 | /* VEX_W_38DB_P_2 */ | |
9954 | { "vaesimc", { XM, EXx } }, | |
9e30b8e0 L |
9955 | }, |
9956 | { | |
9957 | /* VEX_W_38DC_P_2 */ | |
9958 | { "vaesenc", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9959 | }, |
9960 | { | |
9961 | /* VEX_W_38DD_P_2 */ | |
9962 | { "vaesenclast", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9963 | }, |
9964 | { | |
9965 | /* VEX_W_38DE_P_2 */ | |
9966 | { "vaesdec", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9967 | }, |
9968 | { | |
9969 | /* VEX_W_38DF_P_2 */ | |
9970 | { "vaesdeclast", { XM, Vex128, EXx } }, | |
9e30b8e0 L |
9971 | }, |
9972 | { | |
9973 | /* VEX_W_3A04_P_2 */ | |
9974 | { "vpermilps", { XM, EXx, Ib } }, | |
9e30b8e0 L |
9975 | }, |
9976 | { | |
9977 | /* VEX_W_3A05_P_2 */ | |
9978 | { "vpermilpd", { XM, EXx, Ib } }, | |
9e30b8e0 L |
9979 | }, |
9980 | { | |
9981 | /* VEX_W_3A06_P_2 */ | |
9982 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, | |
9e30b8e0 L |
9983 | }, |
9984 | { | |
9985 | /* VEX_W_3A08_P_2 */ | |
9986 | { "vroundps", { XM, EXx, Ib } }, | |
9e30b8e0 L |
9987 | }, |
9988 | { | |
9989 | /* VEX_W_3A09_P_2 */ | |
9990 | { "vroundpd", { XM, EXx, Ib } }, | |
9e30b8e0 L |
9991 | }, |
9992 | { | |
9993 | /* VEX_W_3A0A_P_2 */ | |
9994 | { "vroundss", { XM, Vex128, EXd, Ib } }, | |
9e30b8e0 L |
9995 | }, |
9996 | { | |
9997 | /* VEX_W_3A0B_P_2 */ | |
9998 | { "vroundsd", { XM, Vex128, EXq, Ib } }, | |
9e30b8e0 L |
9999 | }, |
10000 | { | |
10001 | /* VEX_W_3A0C_P_2 */ | |
10002 | { "vblendps", { XM, Vex, EXx, Ib } }, | |
9e30b8e0 L |
10003 | }, |
10004 | { | |
10005 | /* VEX_W_3A0D_P_2 */ | |
10006 | { "vblendpd", { XM, Vex, EXx, Ib } }, | |
9e30b8e0 L |
10007 | }, |
10008 | { | |
10009 | /* VEX_W_3A0E_P_2 */ | |
10010 | { "vpblendw", { XM, Vex128, EXx, Ib } }, | |
9e30b8e0 L |
10011 | }, |
10012 | { | |
10013 | /* VEX_W_3A0F_P_2 */ | |
10014 | { "vpalignr", { XM, Vex128, EXx, Ib } }, | |
9e30b8e0 L |
10015 | }, |
10016 | { | |
10017 | /* VEX_W_3A14_P_2 */ | |
10018 | { "vpextrb", { Edqb, XM, Ib } }, | |
9e30b8e0 L |
10019 | }, |
10020 | { | |
10021 | /* VEX_W_3A15_P_2 */ | |
10022 | { "vpextrw", { Edqw, XM, Ib } }, | |
9e30b8e0 L |
10023 | }, |
10024 | { | |
10025 | /* VEX_W_3A18_P_2 */ | |
10026 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, | |
9e30b8e0 L |
10027 | }, |
10028 | { | |
10029 | /* VEX_W_3A19_P_2 */ | |
10030 | { "vextractf128", { EXxmm, XM, Ib } }, | |
9e30b8e0 L |
10031 | }, |
10032 | { | |
10033 | /* VEX_W_3A20_P_2 */ | |
10034 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, | |
9e30b8e0 L |
10035 | }, |
10036 | { | |
10037 | /* VEX_W_3A21_P_2 */ | |
10038 | { "vinsertps", { XM, Vex128, EXd, Ib } }, | |
9e30b8e0 L |
10039 | }, |
10040 | { | |
10041 | /* VEX_W_3A40_P_2 */ | |
10042 | { "vdpps", { XM, Vex, EXx, Ib } }, | |
9e30b8e0 L |
10043 | }, |
10044 | { | |
10045 | /* VEX_W_3A41_P_2 */ | |
10046 | { "vdppd", { XM, Vex128, EXx, Ib } }, | |
9e30b8e0 L |
10047 | }, |
10048 | { | |
10049 | /* VEX_W_3A42_P_2 */ | |
10050 | { "vmpsadbw", { XM, Vex128, EXx, Ib } }, | |
9e30b8e0 L |
10051 | }, |
10052 | { | |
10053 | /* VEX_W_3A44_P_2 */ | |
10054 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, | |
9e30b8e0 L |
10055 | }, |
10056 | { | |
10057 | /* VEX_W_3A4A_P_2 */ | |
10058 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, | |
9e30b8e0 L |
10059 | }, |
10060 | { | |
10061 | /* VEX_W_3A4B_P_2 */ | |
10062 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, | |
9e30b8e0 L |
10063 | }, |
10064 | { | |
10065 | /* VEX_W_3A4C_P_2 */ | |
10066 | { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } }, | |
9e30b8e0 L |
10067 | }, |
10068 | { | |
10069 | /* VEX_W_3A60_P_2 */ | |
10070 | { "vpcmpestrm", { XM, EXx, Ib } }, | |
9e30b8e0 L |
10071 | }, |
10072 | { | |
10073 | /* VEX_W_3A61_P_2 */ | |
10074 | { "vpcmpestri", { XM, EXx, Ib } }, | |
9e30b8e0 L |
10075 | }, |
10076 | { | |
10077 | /* VEX_W_3A62_P_2 */ | |
10078 | { "vpcmpistrm", { XM, EXx, Ib } }, | |
9e30b8e0 L |
10079 | }, |
10080 | { | |
10081 | /* VEX_W_3A63_P_2 */ | |
10082 | { "vpcmpistri", { XM, EXx, Ib } }, | |
9e30b8e0 L |
10083 | }, |
10084 | { | |
10085 | /* VEX_W_3ADF_P_2 */ | |
10086 | { "vaeskeygenassist", { XM, EXx, Ib } }, | |
9e30b8e0 L |
10087 | }, |
10088 | }; | |
10089 | ||
10090 | static const struct dis386 mod_table[][2] = { | |
10091 | { | |
10092 | /* MOD_8D */ | |
10093 | { "leaS", { Gv, M } }, | |
9e30b8e0 L |
10094 | }, |
10095 | { | |
10096 | /* MOD_0F01_REG_0 */ | |
10097 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10098 | { RM_TABLE (RM_0F01_REG_0) }, | |
10099 | }, | |
10100 | { | |
10101 | /* MOD_0F01_REG_1 */ | |
10102 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10103 | { RM_TABLE (RM_0F01_REG_1) }, | |
10104 | }, | |
10105 | { | |
10106 | /* MOD_0F01_REG_2 */ | |
10107 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10108 | { RM_TABLE (RM_0F01_REG_2) }, | |
10109 | }, | |
10110 | { | |
10111 | /* MOD_0F01_REG_3 */ | |
10112 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10113 | { RM_TABLE (RM_0F01_REG_3) }, | |
10114 | }, | |
10115 | { | |
10116 | /* MOD_0F01_REG_7 */ | |
10117 | { "invlpg", { Mb } }, | |
10118 | { RM_TABLE (RM_0F01_REG_7) }, | |
10119 | }, | |
10120 | { | |
10121 | /* MOD_0F12_PREFIX_0 */ | |
10122 | { "movlps", { XM, EXq } }, | |
10123 | { "movhlps", { XM, EXq } }, | |
10124 | }, | |
10125 | { | |
10126 | /* MOD_0F13 */ | |
10127 | { "movlpX", { EXq, XM } }, | |
9e30b8e0 L |
10128 | }, |
10129 | { | |
10130 | /* MOD_0F16_PREFIX_0 */ | |
10131 | { "movhps", { XM, EXq } }, | |
10132 | { "movlhps", { XM, EXq } }, | |
10133 | }, | |
10134 | { | |
10135 | /* MOD_0F17 */ | |
10136 | { "movhpX", { EXq, XM } }, | |
9e30b8e0 L |
10137 | }, |
10138 | { | |
10139 | /* MOD_0F18_REG_0 */ | |
10140 | { "prefetchnta", { Mb } }, | |
9e30b8e0 L |
10141 | }, |
10142 | { | |
10143 | /* MOD_0F18_REG_1 */ | |
10144 | { "prefetcht0", { Mb } }, | |
9e30b8e0 L |
10145 | }, |
10146 | { | |
10147 | /* MOD_0F18_REG_2 */ | |
10148 | { "prefetcht1", { Mb } }, | |
9e30b8e0 L |
10149 | }, |
10150 | { | |
10151 | /* MOD_0F18_REG_3 */ | |
10152 | { "prefetcht2", { Mb } }, | |
9e30b8e0 L |
10153 | }, |
10154 | { | |
10155 | /* MOD_0F20 */ | |
592d1631 | 10156 | { Bad_Opcode }, |
9e30b8e0 L |
10157 | { "movZ", { Rm, Cm } }, |
10158 | }, | |
10159 | { | |
10160 | /* MOD_0F21 */ | |
592d1631 | 10161 | { Bad_Opcode }, |
9e30b8e0 L |
10162 | { "movZ", { Rm, Dm } }, |
10163 | }, | |
10164 | { | |
10165 | /* MOD_0F22 */ | |
592d1631 | 10166 | { Bad_Opcode }, |
9e30b8e0 | 10167 | { "movZ", { Cm, Rm } }, |
b844680a L |
10168 | }, |
10169 | { | |
92fddf8e | 10170 | /* MOD_0F23 */ |
592d1631 | 10171 | { Bad_Opcode }, |
92fddf8e | 10172 | { "movZ", { Dm, Rm } }, |
b844680a L |
10173 | }, |
10174 | { | |
92fddf8e | 10175 | /* MOD_0F24 */ |
592d1631 | 10176 | { Bad_Opcode }, |
92fddf8e | 10177 | { "movL", { Rd, Td } }, |
b844680a L |
10178 | }, |
10179 | { | |
92fddf8e | 10180 | /* MOD_0F26 */ |
592d1631 | 10181 | { Bad_Opcode }, |
92fddf8e | 10182 | { "movL", { Td, Rd } }, |
b844680a | 10183 | }, |
75c135a8 L |
10184 | { |
10185 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 10186 | {"movntps", { Mx, XM } }, |
75c135a8 L |
10187 | }, |
10188 | { | |
10189 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 10190 | {"movntss", { Md, XM } }, |
75c135a8 L |
10191 | }, |
10192 | { | |
10193 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 10194 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
10195 | }, |
10196 | { | |
10197 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 10198 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
10199 | }, |
10200 | { | |
10201 | /* MOD_0F51 */ | |
592d1631 | 10202 | { Bad_Opcode }, |
75c135a8 L |
10203 | { "movmskpX", { Gdq, XS } }, |
10204 | }, | |
b844680a | 10205 | { |
1ceb70f8 | 10206 | /* MOD_0F71_REG_2 */ |
592d1631 | 10207 | { Bad_Opcode }, |
4e7d34a6 | 10208 | { "psrlw", { MS, Ib } }, |
b844680a L |
10209 | }, |
10210 | { | |
1ceb70f8 | 10211 | /* MOD_0F71_REG_4 */ |
592d1631 | 10212 | { Bad_Opcode }, |
4e7d34a6 | 10213 | { "psraw", { MS, Ib } }, |
b844680a L |
10214 | }, |
10215 | { | |
1ceb70f8 | 10216 | /* MOD_0F71_REG_6 */ |
592d1631 | 10217 | { Bad_Opcode }, |
4e7d34a6 | 10218 | { "psllw", { MS, Ib } }, |
b844680a L |
10219 | }, |
10220 | { | |
1ceb70f8 | 10221 | /* MOD_0F72_REG_2 */ |
592d1631 | 10222 | { Bad_Opcode }, |
4e7d34a6 | 10223 | { "psrld", { MS, Ib } }, |
b844680a L |
10224 | }, |
10225 | { | |
1ceb70f8 | 10226 | /* MOD_0F72_REG_4 */ |
592d1631 | 10227 | { Bad_Opcode }, |
4e7d34a6 | 10228 | { "psrad", { MS, Ib } }, |
b844680a L |
10229 | }, |
10230 | { | |
1ceb70f8 | 10231 | /* MOD_0F72_REG_6 */ |
592d1631 | 10232 | { Bad_Opcode }, |
4e7d34a6 | 10233 | { "pslld", { MS, Ib } }, |
b844680a L |
10234 | }, |
10235 | { | |
1ceb70f8 | 10236 | /* MOD_0F73_REG_2 */ |
592d1631 | 10237 | { Bad_Opcode }, |
4e7d34a6 | 10238 | { "psrlq", { MS, Ib } }, |
b844680a L |
10239 | }, |
10240 | { | |
1ceb70f8 | 10241 | /* MOD_0F73_REG_3 */ |
592d1631 | 10242 | { Bad_Opcode }, |
c0f3af97 L |
10243 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10244 | }, | |
10245 | { | |
10246 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10247 | { Bad_Opcode }, |
c0f3af97 L |
10248 | { "psllq", { MS, Ib } }, |
10249 | }, | |
10250 | { | |
10251 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10252 | { Bad_Opcode }, |
c0f3af97 L |
10253 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10254 | }, | |
10255 | { | |
10256 | /* MOD_0FAE_REG_0 */ | |
eacc9c89 | 10257 | { "fxsave", { FXSAVE } }, |
c0f3af97 L |
10258 | }, |
10259 | { | |
10260 | /* MOD_0FAE_REG_1 */ | |
eacc9c89 | 10261 | { "fxrstor", { FXSAVE } }, |
c0f3af97 L |
10262 | }, |
10263 | { | |
10264 | /* MOD_0FAE_REG_2 */ | |
10265 | { "ldmxcsr", { Md } }, | |
c0f3af97 L |
10266 | }, |
10267 | { | |
10268 | /* MOD_0FAE_REG_3 */ | |
10269 | { "stmxcsr", { Md } }, | |
c0f3af97 L |
10270 | }, |
10271 | { | |
10272 | /* MOD_0FAE_REG_4 */ | |
73bb6729 | 10273 | { "xsave", { FXSAVE } }, |
c0f3af97 L |
10274 | }, |
10275 | { | |
10276 | /* MOD_0FAE_REG_5 */ | |
73bb6729 | 10277 | { "xrstor", { FXSAVE } }, |
c0f3af97 L |
10278 | { RM_TABLE (RM_0FAE_REG_5) }, |
10279 | }, | |
10280 | { | |
10281 | /* MOD_0FAE_REG_6 */ | |
592d1631 | 10282 | { Bad_Opcode }, |
c0f3af97 L |
10283 | { RM_TABLE (RM_0FAE_REG_6) }, |
10284 | }, | |
10285 | { | |
10286 | /* MOD_0FAE_REG_7 */ | |
10287 | { "clflush", { Mb } }, | |
10288 | { RM_TABLE (RM_0FAE_REG_7) }, | |
10289 | }, | |
10290 | { | |
10291 | /* MOD_0FB2 */ | |
10292 | { "lssS", { Gv, Mp } }, | |
c0f3af97 L |
10293 | }, |
10294 | { | |
10295 | /* MOD_0FB4 */ | |
10296 | { "lfsS", { Gv, Mp } }, | |
c0f3af97 L |
10297 | }, |
10298 | { | |
10299 | /* MOD_0FB5 */ | |
10300 | { "lgsS", { Gv, Mp } }, | |
c0f3af97 L |
10301 | }, |
10302 | { | |
10303 | /* MOD_0FC7_REG_6 */ | |
10304 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
c0f3af97 L |
10305 | }, |
10306 | { | |
10307 | /* MOD_0FC7_REG_7 */ | |
10308 | { "vmptrst", { Mq } }, | |
c0f3af97 L |
10309 | }, |
10310 | { | |
10311 | /* MOD_0FD7 */ | |
592d1631 | 10312 | { Bad_Opcode }, |
c0f3af97 L |
10313 | { "pmovmskb", { Gdq, MS } }, |
10314 | }, | |
10315 | { | |
10316 | /* MOD_0FE7_PREFIX_2 */ | |
10317 | { "movntdq", { Mx, XM } }, | |
c0f3af97 L |
10318 | }, |
10319 | { | |
10320 | /* MOD_0FF0_PREFIX_3 */ | |
10321 | { "lddqu", { XM, M } }, | |
c0f3af97 L |
10322 | }, |
10323 | { | |
10324 | /* MOD_0F382A_PREFIX_2 */ | |
10325 | { "movntdqa", { XM, Mx } }, | |
c0f3af97 L |
10326 | }, |
10327 | { | |
10328 | /* MOD_62_32BIT */ | |
10329 | { "bound{S|}", { Gv, Ma } }, | |
c0f3af97 L |
10330 | }, |
10331 | { | |
10332 | /* MOD_C4_32BIT */ | |
10333 | { "lesS", { Gv, Mp } }, | |
10334 | { VEX_C4_TABLE (VEX_0F) }, | |
10335 | }, | |
10336 | { | |
10337 | /* MOD_C5_32BIT */ | |
10338 | { "ldsS", { Gv, Mp } }, | |
10339 | { VEX_C5_TABLE (VEX_0F) }, | |
10340 | }, | |
10341 | { | |
10342 | /* MOD_VEX_12_PREFIX_0 */ | |
10343 | { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) }, | |
10344 | { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) }, | |
10345 | }, | |
10346 | { | |
10347 | /* MOD_VEX_13 */ | |
10348 | { VEX_LEN_TABLE (VEX_LEN_13_M_0) }, | |
c0f3af97 L |
10349 | }, |
10350 | { | |
10351 | /* MOD_VEX_16_PREFIX_0 */ | |
10352 | { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) }, | |
10353 | { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) }, | |
10354 | }, | |
10355 | { | |
10356 | /* MOD_VEX_17 */ | |
10357 | { VEX_LEN_TABLE (VEX_LEN_17_M_0) }, | |
c0f3af97 L |
10358 | }, |
10359 | { | |
10360 | /* MOD_VEX_2B */ | |
9e30b8e0 | 10361 | { VEX_W_TABLE (VEX_W_2B_M_0) }, |
c0f3af97 L |
10362 | }, |
10363 | { | |
976f1fde | 10364 | /* MOD_VEX_50 */ |
592d1631 | 10365 | { Bad_Opcode }, |
9e30b8e0 | 10366 | { VEX_W_TABLE (VEX_W_50_M_0) }, |
c0f3af97 L |
10367 | }, |
10368 | { | |
10369 | /* MOD_VEX_71_REG_2 */ | |
592d1631 | 10370 | { Bad_Opcode }, |
c0f3af97 | 10371 | { PREFIX_TABLE (PREFIX_VEX_71_REG_2) }, |
b844680a L |
10372 | }, |
10373 | { | |
c0f3af97 | 10374 | /* MOD_VEX_71_REG_4 */ |
592d1631 | 10375 | { Bad_Opcode }, |
c0f3af97 | 10376 | { PREFIX_TABLE (PREFIX_VEX_71_REG_4) }, |
b844680a L |
10377 | }, |
10378 | { | |
c0f3af97 | 10379 | /* MOD_VEX_71_REG_6 */ |
592d1631 | 10380 | { Bad_Opcode }, |
c0f3af97 | 10381 | { PREFIX_TABLE (PREFIX_VEX_71_REG_6) }, |
b844680a L |
10382 | }, |
10383 | { | |
c0f3af97 | 10384 | /* MOD_VEX_72_REG_2 */ |
592d1631 | 10385 | { Bad_Opcode }, |
c0f3af97 | 10386 | { PREFIX_TABLE (PREFIX_VEX_72_REG_2) }, |
b844680a | 10387 | }, |
d8faab4e | 10388 | { |
c0f3af97 | 10389 | /* MOD_VEX_72_REG_4 */ |
592d1631 | 10390 | { Bad_Opcode }, |
c0f3af97 | 10391 | { PREFIX_TABLE (PREFIX_VEX_72_REG_4) }, |
d8faab4e L |
10392 | }, |
10393 | { | |
c0f3af97 | 10394 | /* MOD_VEX_72_REG_6 */ |
592d1631 | 10395 | { Bad_Opcode }, |
c0f3af97 | 10396 | { PREFIX_TABLE (PREFIX_VEX_72_REG_6) }, |
d8faab4e | 10397 | }, |
876d4bfa | 10398 | { |
c0f3af97 | 10399 | /* MOD_VEX_73_REG_2 */ |
592d1631 | 10400 | { Bad_Opcode }, |
c0f3af97 | 10401 | { PREFIX_TABLE (PREFIX_VEX_73_REG_2) }, |
876d4bfa L |
10402 | }, |
10403 | { | |
c0f3af97 | 10404 | /* MOD_VEX_73_REG_3 */ |
592d1631 | 10405 | { Bad_Opcode }, |
c0f3af97 | 10406 | { PREFIX_TABLE (PREFIX_VEX_73_REG_3) }, |
475a2301 L |
10407 | }, |
10408 | { | |
c0f3af97 | 10409 | /* MOD_VEX_73_REG_6 */ |
592d1631 | 10410 | { Bad_Opcode }, |
c0f3af97 | 10411 | { PREFIX_TABLE (PREFIX_VEX_73_REG_6) }, |
876d4bfa L |
10412 | }, |
10413 | { | |
c0f3af97 | 10414 | /* MOD_VEX_73_REG_7 */ |
592d1631 | 10415 | { Bad_Opcode }, |
c0f3af97 | 10416 | { PREFIX_TABLE (PREFIX_VEX_73_REG_7) }, |
876d4bfa L |
10417 | }, |
10418 | { | |
c0f3af97 L |
10419 | /* MOD_VEX_AE_REG_2 */ |
10420 | { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) }, | |
876d4bfa | 10421 | }, |
bbedc832 | 10422 | { |
c0f3af97 L |
10423 | /* MOD_VEX_AE_REG_3 */ |
10424 | { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) }, | |
bbedc832 | 10425 | }, |
144c41d9 | 10426 | { |
c0f3af97 | 10427 | /* MOD_VEX_D7_PREFIX_2 */ |
592d1631 | 10428 | { Bad_Opcode }, |
c0f3af97 | 10429 | { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) }, |
144c41d9 | 10430 | }, |
1afd85e3 | 10431 | { |
c0f3af97 | 10432 | /* MOD_VEX_E7_PREFIX_2 */ |
9e30b8e0 | 10433 | { VEX_W_TABLE (VEX_W_E7_P_2_M_0) }, |
1afd85e3 L |
10434 | }, |
10435 | { | |
c0f3af97 | 10436 | /* MOD_VEX_F0_PREFIX_3 */ |
9e30b8e0 | 10437 | { VEX_W_TABLE (VEX_W_F0_P_3_M_0) }, |
92fddf8e L |
10438 | }, |
10439 | { | |
c0f3af97 | 10440 | /* MOD_VEX_3818_PREFIX_2 */ |
bcf2684f | 10441 | { VEX_W_TABLE (VEX_W_3818_P_2_M_0) }, |
1afd85e3 | 10442 | }, |
75c135a8 | 10443 | { |
c0f3af97 L |
10444 | /* MOD_VEX_3819_PREFIX_2 */ |
10445 | { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) }, | |
75c135a8 L |
10446 | }, |
10447 | { | |
c0f3af97 L |
10448 | /* MOD_VEX_381A_PREFIX_2 */ |
10449 | { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) }, | |
75c135a8 | 10450 | }, |
1afd85e3 | 10451 | { |
c0f3af97 L |
10452 | /* MOD_VEX_382A_PREFIX_2 */ |
10453 | { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) }, | |
1afd85e3 | 10454 | }, |
75c135a8 | 10455 | { |
c0f3af97 | 10456 | /* MOD_VEX_382C_PREFIX_2 */ |
53aa04a0 | 10457 | { VEX_W_TABLE (VEX_W_382C_P_2_M_0) }, |
75c135a8 | 10458 | }, |
1afd85e3 | 10459 | { |
c0f3af97 | 10460 | /* MOD_VEX_382D_PREFIX_2 */ |
53aa04a0 | 10461 | { VEX_W_TABLE (VEX_W_382D_P_2_M_0) }, |
1afd85e3 L |
10462 | }, |
10463 | { | |
c0f3af97 | 10464 | /* MOD_VEX_382E_PREFIX_2 */ |
53aa04a0 | 10465 | { VEX_W_TABLE (VEX_W_382E_P_2_M_0) }, |
1afd85e3 L |
10466 | }, |
10467 | { | |
c0f3af97 | 10468 | /* MOD_VEX_382F_PREFIX_2 */ |
53aa04a0 | 10469 | { VEX_W_TABLE (VEX_W_382F_P_2_M_0) }, |
1afd85e3 | 10470 | }, |
b844680a L |
10471 | }; |
10472 | ||
1ceb70f8 | 10473 | static const struct dis386 rm_table[][8] = { |
b844680a | 10474 | { |
1ceb70f8 | 10475 | /* RM_0F01_REG_0 */ |
592d1631 | 10476 | { Bad_Opcode }, |
b844680a L |
10477 | { "vmcall", { Skip_MODRM } }, |
10478 | { "vmlaunch", { Skip_MODRM } }, | |
10479 | { "vmresume", { Skip_MODRM } }, | |
10480 | { "vmxoff", { Skip_MODRM } }, | |
b844680a L |
10481 | }, |
10482 | { | |
1ceb70f8 | 10483 | /* RM_0F01_REG_1 */ |
b844680a L |
10484 | { "monitor", { { OP_Monitor, 0 } } }, |
10485 | { "mwait", { { OP_Mwait, 0 } } }, | |
b844680a | 10486 | }, |
475a2301 L |
10487 | { |
10488 | /* RM_0F01_REG_2 */ | |
10489 | { "xgetbv", { Skip_MODRM } }, | |
10490 | { "xsetbv", { Skip_MODRM } }, | |
475a2301 | 10491 | }, |
b844680a | 10492 | { |
1ceb70f8 | 10493 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
10494 | { "vmrun", { Skip_MODRM } }, |
10495 | { "vmmcall", { Skip_MODRM } }, | |
10496 | { "vmload", { Skip_MODRM } }, | |
10497 | { "vmsave", { Skip_MODRM } }, | |
10498 | { "stgi", { Skip_MODRM } }, | |
10499 | { "clgi", { Skip_MODRM } }, | |
10500 | { "skinit", { Skip_MODRM } }, | |
10501 | { "invlpga", { Skip_MODRM } }, | |
10502 | }, | |
10503 | { | |
1ceb70f8 | 10504 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
10505 | { "swapgs", { Skip_MODRM } }, |
10506 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
10507 | }, |
10508 | { | |
1ceb70f8 | 10509 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 10510 | { "lfence", { Skip_MODRM } }, |
b844680a L |
10511 | }, |
10512 | { | |
1ceb70f8 | 10513 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 10514 | { "mfence", { Skip_MODRM } }, |
b844680a | 10515 | }, |
bbedc832 | 10516 | { |
1ceb70f8 | 10517 | /* RM_0FAE_REG_7 */ |
4e7d34a6 | 10518 | { "sfence", { Skip_MODRM } }, |
144c41d9 | 10519 | }, |
b844680a L |
10520 | }; |
10521 | ||
c608c12e AM |
10522 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
10523 | ||
f16cd0d5 L |
10524 | /* We use the high bit to indicate different name for the same |
10525 | prefix. */ | |
10526 | #define ADDR16_PREFIX (0x67 | 0x100) | |
10527 | #define ADDR32_PREFIX (0x67 | 0x200) | |
10528 | #define DATA16_PREFIX (0x66 | 0x100) | |
10529 | #define DATA32_PREFIX (0x66 | 0x200) | |
10530 | #define REP_PREFIX (0xf3 | 0x100) | |
10531 | ||
10532 | static int | |
26ca5450 | 10533 | ckprefix (void) |
252b5132 | 10534 | { |
f16cd0d5 | 10535 | int newrex, i, length; |
52b15da3 | 10536 | rex = 0; |
c0f3af97 | 10537 | rex_ignored = 0; |
252b5132 | 10538 | prefixes = 0; |
7d421014 | 10539 | used_prefixes = 0; |
52b15da3 | 10540 | rex_used = 0; |
f16cd0d5 L |
10541 | last_lock_prefix = -1; |
10542 | last_repz_prefix = -1; | |
10543 | last_repnz_prefix = -1; | |
10544 | last_data_prefix = -1; | |
10545 | last_addr_prefix = -1; | |
10546 | last_rex_prefix = -1; | |
10547 | last_seg_prefix = -1; | |
f310f33d L |
10548 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
10549 | all_prefixes[i] = 0; | |
10550 | i = 0; | |
f16cd0d5 L |
10551 | length = 0; |
10552 | /* The maximum instruction length is 15bytes. */ | |
10553 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
10554 | { |
10555 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 10556 | newrex = 0; |
252b5132 RH |
10557 | switch (*codep) |
10558 | { | |
52b15da3 JH |
10559 | /* REX prefixes family. */ |
10560 | case 0x40: | |
10561 | case 0x41: | |
10562 | case 0x42: | |
10563 | case 0x43: | |
10564 | case 0x44: | |
10565 | case 0x45: | |
10566 | case 0x46: | |
10567 | case 0x47: | |
10568 | case 0x48: | |
10569 | case 0x49: | |
10570 | case 0x4a: | |
10571 | case 0x4b: | |
10572 | case 0x4c: | |
10573 | case 0x4d: | |
10574 | case 0x4e: | |
10575 | case 0x4f: | |
f16cd0d5 L |
10576 | if (address_mode == mode_64bit) |
10577 | newrex = *codep; | |
10578 | else | |
10579 | return 1; | |
10580 | last_rex_prefix = i; | |
52b15da3 | 10581 | break; |
252b5132 RH |
10582 | case 0xf3: |
10583 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 10584 | last_repz_prefix = i; |
252b5132 RH |
10585 | break; |
10586 | case 0xf2: | |
10587 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 10588 | last_repnz_prefix = i; |
252b5132 RH |
10589 | break; |
10590 | case 0xf0: | |
10591 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 10592 | last_lock_prefix = i; |
252b5132 RH |
10593 | break; |
10594 | case 0x2e: | |
10595 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 10596 | last_seg_prefix = i; |
252b5132 RH |
10597 | break; |
10598 | case 0x36: | |
10599 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 10600 | last_seg_prefix = i; |
252b5132 RH |
10601 | break; |
10602 | case 0x3e: | |
10603 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 10604 | last_seg_prefix = i; |
252b5132 RH |
10605 | break; |
10606 | case 0x26: | |
10607 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 10608 | last_seg_prefix = i; |
252b5132 RH |
10609 | break; |
10610 | case 0x64: | |
10611 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 10612 | last_seg_prefix = i; |
252b5132 RH |
10613 | break; |
10614 | case 0x65: | |
10615 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 10616 | last_seg_prefix = i; |
252b5132 RH |
10617 | break; |
10618 | case 0x66: | |
10619 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 10620 | last_data_prefix = i; |
252b5132 RH |
10621 | break; |
10622 | case 0x67: | |
10623 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 10624 | last_addr_prefix = i; |
252b5132 | 10625 | break; |
5076851f | 10626 | case FWAIT_OPCODE: |
252b5132 RH |
10627 | /* fwait is really an instruction. If there are prefixes |
10628 | before the fwait, they belong to the fwait, *not* to the | |
10629 | following instruction. */ | |
3e7d61b2 | 10630 | if (prefixes || rex) |
252b5132 RH |
10631 | { |
10632 | prefixes |= PREFIX_FWAIT; | |
10633 | codep++; | |
f16cd0d5 | 10634 | return 1; |
252b5132 RH |
10635 | } |
10636 | prefixes = PREFIX_FWAIT; | |
10637 | break; | |
10638 | default: | |
f16cd0d5 | 10639 | return 1; |
252b5132 | 10640 | } |
52b15da3 JH |
10641 | /* Rex is ignored when followed by another prefix. */ |
10642 | if (rex) | |
10643 | { | |
3e7d61b2 | 10644 | rex_used = rex; |
f16cd0d5 | 10645 | return 1; |
52b15da3 | 10646 | } |
f16cd0d5 L |
10647 | if (*codep != FWAIT_OPCODE) |
10648 | all_prefixes[i++] = *codep; | |
52b15da3 | 10649 | rex = newrex; |
252b5132 | 10650 | codep++; |
f16cd0d5 L |
10651 | length++; |
10652 | } | |
10653 | return 0; | |
10654 | } | |
10655 | ||
10656 | static int | |
10657 | seg_prefix (int pref) | |
10658 | { | |
10659 | switch (pref) | |
10660 | { | |
10661 | case 0x2e: | |
10662 | return PREFIX_CS; | |
10663 | case 0x36: | |
10664 | return PREFIX_SS; | |
10665 | case 0x3e: | |
10666 | return PREFIX_DS; | |
10667 | case 0x26: | |
10668 | return PREFIX_ES; | |
10669 | case 0x64: | |
10670 | return PREFIX_FS; | |
10671 | case 0x65: | |
10672 | return PREFIX_GS; | |
10673 | default: | |
10674 | return 0; | |
252b5132 RH |
10675 | } |
10676 | } | |
10677 | ||
7d421014 ILT |
10678 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
10679 | prefix byte. */ | |
10680 | ||
10681 | static const char * | |
26ca5450 | 10682 | prefix_name (int pref, int sizeflag) |
7d421014 | 10683 | { |
0003779b L |
10684 | static const char *rexes [16] = |
10685 | { | |
10686 | "rex", /* 0x40 */ | |
10687 | "rex.B", /* 0x41 */ | |
10688 | "rex.X", /* 0x42 */ | |
10689 | "rex.XB", /* 0x43 */ | |
10690 | "rex.R", /* 0x44 */ | |
10691 | "rex.RB", /* 0x45 */ | |
10692 | "rex.RX", /* 0x46 */ | |
10693 | "rex.RXB", /* 0x47 */ | |
10694 | "rex.W", /* 0x48 */ | |
10695 | "rex.WB", /* 0x49 */ | |
10696 | "rex.WX", /* 0x4a */ | |
10697 | "rex.WXB", /* 0x4b */ | |
10698 | "rex.WR", /* 0x4c */ | |
10699 | "rex.WRB", /* 0x4d */ | |
10700 | "rex.WRX", /* 0x4e */ | |
10701 | "rex.WRXB", /* 0x4f */ | |
10702 | }; | |
10703 | ||
7d421014 ILT |
10704 | switch (pref) |
10705 | { | |
52b15da3 JH |
10706 | /* REX prefixes family. */ |
10707 | case 0x40: | |
52b15da3 | 10708 | case 0x41: |
52b15da3 | 10709 | case 0x42: |
52b15da3 | 10710 | case 0x43: |
52b15da3 | 10711 | case 0x44: |
52b15da3 | 10712 | case 0x45: |
52b15da3 | 10713 | case 0x46: |
52b15da3 | 10714 | case 0x47: |
52b15da3 | 10715 | case 0x48: |
52b15da3 | 10716 | case 0x49: |
52b15da3 | 10717 | case 0x4a: |
52b15da3 | 10718 | case 0x4b: |
52b15da3 | 10719 | case 0x4c: |
52b15da3 | 10720 | case 0x4d: |
52b15da3 | 10721 | case 0x4e: |
52b15da3 | 10722 | case 0x4f: |
0003779b | 10723 | return rexes [pref - 0x40]; |
7d421014 ILT |
10724 | case 0xf3: |
10725 | return "repz"; | |
10726 | case 0xf2: | |
10727 | return "repnz"; | |
10728 | case 0xf0: | |
10729 | return "lock"; | |
10730 | case 0x2e: | |
10731 | return "cs"; | |
10732 | case 0x36: | |
10733 | return "ss"; | |
10734 | case 0x3e: | |
10735 | return "ds"; | |
10736 | case 0x26: | |
10737 | return "es"; | |
10738 | case 0x64: | |
10739 | return "fs"; | |
10740 | case 0x65: | |
10741 | return "gs"; | |
10742 | case 0x66: | |
10743 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
10744 | case 0x67: | |
cb712a9e | 10745 | if (address_mode == mode_64bit) |
db6eb5be | 10746 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 10747 | else |
2888cb7a | 10748 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
10749 | case FWAIT_OPCODE: |
10750 | return "fwait"; | |
f16cd0d5 L |
10751 | case ADDR16_PREFIX: |
10752 | return "addr16"; | |
10753 | case ADDR32_PREFIX: | |
10754 | return "addr32"; | |
10755 | case DATA16_PREFIX: | |
10756 | return "data16"; | |
10757 | case DATA32_PREFIX: | |
10758 | return "data32"; | |
10759 | case REP_PREFIX: | |
10760 | return "rep"; | |
7d421014 ILT |
10761 | default: |
10762 | return NULL; | |
10763 | } | |
10764 | } | |
10765 | ||
ce518a5f L |
10766 | static char op_out[MAX_OPERANDS][100]; |
10767 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 10768 | static int two_source_ops; |
ce518a5f L |
10769 | static bfd_vma op_address[MAX_OPERANDS]; |
10770 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 10771 | static bfd_vma start_pc; |
ce518a5f | 10772 | |
252b5132 RH |
10773 | /* |
10774 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
10775 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
10776 | * section of the "Virtual 8086 Mode" chapter.) | |
10777 | * 'pc' should be the address of this instruction, it will | |
10778 | * be used to print the target address if this is a relative jump or call | |
10779 | * The function returns the length of this instruction in bytes. | |
10780 | */ | |
10781 | ||
252b5132 | 10782 | static char intel_syntax; |
9d141669 | 10783 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
10784 | static char open_char; |
10785 | static char close_char; | |
10786 | static char separator_char; | |
10787 | static char scale_char; | |
10788 | ||
e396998b AM |
10789 | /* Here for backwards compatibility. When gdb stops using |
10790 | print_insn_i386_att and print_insn_i386_intel these functions can | |
10791 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 10792 | int |
26ca5450 | 10793 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
10794 | { |
10795 | intel_syntax = 0; | |
e396998b AM |
10796 | |
10797 | return print_insn (pc, info); | |
252b5132 RH |
10798 | } |
10799 | ||
10800 | int | |
26ca5450 | 10801 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
10802 | { |
10803 | intel_syntax = 1; | |
e396998b AM |
10804 | |
10805 | return print_insn (pc, info); | |
252b5132 RH |
10806 | } |
10807 | ||
e396998b | 10808 | int |
26ca5450 | 10809 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
10810 | { |
10811 | intel_syntax = -1; | |
10812 | ||
10813 | return print_insn (pc, info); | |
10814 | } | |
10815 | ||
f59a29b9 L |
10816 | void |
10817 | print_i386_disassembler_options (FILE *stream) | |
10818 | { | |
10819 | fprintf (stream, _("\n\ | |
10820 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
10821 | with the -M switch (multiple options should be separated by commas):\n")); | |
10822 | ||
10823 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
10824 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
10825 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
10826 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
10827 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
10828 | fprintf (stream, _(" att-mnemonic\n" |
10829 | " Display instruction in AT&T mnemonic\n")); | |
10830 | fprintf (stream, _(" intel-mnemonic\n" | |
10831 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
10832 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
10833 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
10834 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
10835 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
10836 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
10837 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
10838 | } | |
10839 | ||
592d1631 L |
10840 | /* Bad opcode. */ |
10841 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; | |
10842 | ||
b844680a L |
10843 | /* Get a pointer to struct dis386 with a valid name. */ |
10844 | ||
10845 | static const struct dis386 * | |
8bb15339 | 10846 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 10847 | { |
91d6fa6a | 10848 | int vindex, vex_table_index; |
b844680a L |
10849 | |
10850 | if (dp->name != NULL) | |
10851 | return dp; | |
10852 | ||
10853 | switch (dp->op[0].bytemode) | |
10854 | { | |
1ceb70f8 L |
10855 | case USE_REG_TABLE: |
10856 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
10857 | break; | |
10858 | ||
10859 | case USE_MOD_TABLE: | |
91d6fa6a NC |
10860 | vindex = modrm.mod == 0x3 ? 1 : 0; |
10861 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
10862 | break; |
10863 | ||
10864 | case USE_RM_TABLE: | |
10865 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
10866 | break; |
10867 | ||
4e7d34a6 | 10868 | case USE_PREFIX_TABLE: |
c0f3af97 | 10869 | if (need_vex) |
b844680a | 10870 | { |
c0f3af97 L |
10871 | /* The prefix in VEX is implicit. */ |
10872 | switch (vex.prefix) | |
10873 | { | |
10874 | case 0: | |
91d6fa6a | 10875 | vindex = 0; |
c0f3af97 L |
10876 | break; |
10877 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 10878 | vindex = 1; |
c0f3af97 L |
10879 | break; |
10880 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 10881 | vindex = 2; |
c0f3af97 L |
10882 | break; |
10883 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 10884 | vindex = 3; |
c0f3af97 L |
10885 | break; |
10886 | default: | |
10887 | abort (); | |
10888 | break; | |
10889 | } | |
b844680a | 10890 | } |
c0f3af97 | 10891 | else |
b844680a | 10892 | { |
91d6fa6a | 10893 | vindex = 0; |
c0f3af97 L |
10894 | used_prefixes |= (prefixes & PREFIX_REPZ); |
10895 | if (prefixes & PREFIX_REPZ) | |
b844680a | 10896 | { |
91d6fa6a | 10897 | vindex = 1; |
f16cd0d5 | 10898 | all_prefixes[last_repz_prefix] = 0; |
b844680a L |
10899 | } |
10900 | else | |
10901 | { | |
c0f3af97 L |
10902 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
10903 | PREFIX_DATA. */ | |
10904 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
10905 | if (prefixes & PREFIX_REPNZ) | |
10906 | { | |
91d6fa6a | 10907 | vindex = 3; |
f16cd0d5 | 10908 | all_prefixes[last_repnz_prefix] = 0; |
c0f3af97 L |
10909 | } |
10910 | else | |
b844680a | 10911 | { |
c0f3af97 L |
10912 | used_prefixes |= (prefixes & PREFIX_DATA); |
10913 | if (prefixes & PREFIX_DATA) | |
10914 | { | |
91d6fa6a | 10915 | vindex = 2; |
f16cd0d5 | 10916 | all_prefixes[last_data_prefix] = 0; |
c0f3af97 | 10917 | } |
b844680a L |
10918 | } |
10919 | } | |
10920 | } | |
91d6fa6a | 10921 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
10922 | break; |
10923 | ||
4e7d34a6 | 10924 | case USE_X86_64_TABLE: |
91d6fa6a NC |
10925 | vindex = address_mode == mode_64bit ? 1 : 0; |
10926 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
10927 | break; |
10928 | ||
4e7d34a6 | 10929 | case USE_3BYTE_TABLE: |
8bb15339 | 10930 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
10931 | vindex = *codep++; |
10932 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
8bb15339 L |
10933 | modrm.mod = (*codep >> 6) & 3; |
10934 | modrm.reg = (*codep >> 3) & 7; | |
10935 | modrm.rm = *codep & 7; | |
10936 | break; | |
10937 | ||
c0f3af97 L |
10938 | case USE_VEX_LEN_TABLE: |
10939 | if (!need_vex) | |
10940 | abort (); | |
10941 | ||
10942 | switch (vex.length) | |
10943 | { | |
10944 | case 128: | |
91d6fa6a | 10945 | vindex = 0; |
c0f3af97 L |
10946 | break; |
10947 | case 256: | |
91d6fa6a | 10948 | vindex = 1; |
c0f3af97 L |
10949 | break; |
10950 | default: | |
10951 | abort (); | |
10952 | break; | |
10953 | } | |
10954 | ||
91d6fa6a | 10955 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
10956 | break; |
10957 | ||
f88c9eb0 SP |
10958 | case USE_XOP_8F_TABLE: |
10959 | FETCH_DATA (info, codep + 3); | |
10960 | /* All bits in the REX prefix are ignored. */ | |
10961 | rex_ignored = rex; | |
10962 | rex = ~(*codep >> 5) & 0x7; | |
10963 | ||
10964 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
10965 | switch ((*codep & 0x1f)) | |
10966 | { | |
10967 | default: | |
10968 | BadOp (); | |
5dd85c99 SP |
10969 | case 0x8: |
10970 | vex_table_index = XOP_08; | |
10971 | break; | |
f88c9eb0 SP |
10972 | case 0x9: |
10973 | vex_table_index = XOP_09; | |
10974 | break; | |
10975 | case 0xa: | |
10976 | vex_table_index = XOP_0A; | |
10977 | break; | |
10978 | } | |
10979 | codep++; | |
10980 | vex.w = *codep & 0x80; | |
10981 | if (vex.w && address_mode == mode_64bit) | |
10982 | rex |= REX_W; | |
10983 | ||
10984 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
10985 | if (address_mode != mode_64bit | |
10986 | && vex.register_specifier > 0x7) | |
10987 | BadOp (); | |
10988 | ||
10989 | vex.length = (*codep & 0x4) ? 256 : 128; | |
10990 | switch ((*codep & 0x3)) | |
10991 | { | |
10992 | case 0: | |
10993 | vex.prefix = 0; | |
10994 | break; | |
10995 | case 1: | |
10996 | vex.prefix = DATA_PREFIX_OPCODE; | |
10997 | break; | |
10998 | case 2: | |
10999 | vex.prefix = REPE_PREFIX_OPCODE; | |
11000 | break; | |
11001 | case 3: | |
11002 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11003 | break; | |
11004 | } | |
11005 | need_vex = 1; | |
11006 | need_vex_reg = 1; | |
11007 | codep++; | |
91d6fa6a NC |
11008 | vindex = *codep++; |
11009 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 SP |
11010 | |
11011 | FETCH_DATA (info, codep + 1); | |
11012 | modrm.mod = (*codep >> 6) & 3; | |
11013 | modrm.reg = (*codep >> 3) & 7; | |
11014 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11015 | break; |
11016 | ||
c0f3af97 L |
11017 | case USE_VEX_C4_TABLE: |
11018 | FETCH_DATA (info, codep + 3); | |
11019 | /* All bits in the REX prefix are ignored. */ | |
11020 | rex_ignored = rex; | |
11021 | rex = ~(*codep >> 5) & 0x7; | |
11022 | switch ((*codep & 0x1f)) | |
11023 | { | |
11024 | default: | |
11025 | BadOp (); | |
11026 | case 0x1: | |
f88c9eb0 | 11027 | vex_table_index = VEX_0F; |
c0f3af97 L |
11028 | break; |
11029 | case 0x2: | |
f88c9eb0 | 11030 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11031 | break; |
11032 | case 0x3: | |
f88c9eb0 | 11033 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11034 | break; |
11035 | } | |
11036 | codep++; | |
11037 | vex.w = *codep & 0x80; | |
11038 | if (vex.w && address_mode == mode_64bit) | |
11039 | rex |= REX_W; | |
11040 | ||
11041 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11042 | if (address_mode != mode_64bit | |
11043 | && vex.register_specifier > 0x7) | |
11044 | BadOp (); | |
11045 | ||
11046 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11047 | switch ((*codep & 0x3)) | |
11048 | { | |
11049 | case 0: | |
11050 | vex.prefix = 0; | |
11051 | break; | |
11052 | case 1: | |
11053 | vex.prefix = DATA_PREFIX_OPCODE; | |
11054 | break; | |
11055 | case 2: | |
11056 | vex.prefix = REPE_PREFIX_OPCODE; | |
11057 | break; | |
11058 | case 3: | |
11059 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11060 | break; | |
11061 | } | |
11062 | need_vex = 1; | |
11063 | need_vex_reg = 1; | |
11064 | codep++; | |
91d6fa6a NC |
11065 | vindex = *codep++; |
11066 | dp = &vex_table[vex_table_index][vindex]; | |
c0f3af97 | 11067 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 11068 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
11069 | { |
11070 | FETCH_DATA (info, codep + 1); | |
11071 | modrm.mod = (*codep >> 6) & 3; | |
11072 | modrm.reg = (*codep >> 3) & 7; | |
11073 | modrm.rm = *codep & 7; | |
11074 | } | |
11075 | break; | |
11076 | ||
11077 | case USE_VEX_C5_TABLE: | |
11078 | FETCH_DATA (info, codep + 2); | |
11079 | /* All bits in the REX prefix are ignored. */ | |
11080 | rex_ignored = rex; | |
11081 | rex = (*codep & 0x80) ? 0 : REX_R; | |
11082 | ||
11083 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11084 | if (address_mode != mode_64bit | |
11085 | && vex.register_specifier > 0x7) | |
11086 | BadOp (); | |
11087 | ||
759a05ce L |
11088 | vex.w = 0; |
11089 | ||
c0f3af97 L |
11090 | vex.length = (*codep & 0x4) ? 256 : 128; |
11091 | switch ((*codep & 0x3)) | |
11092 | { | |
11093 | case 0: | |
11094 | vex.prefix = 0; | |
11095 | break; | |
11096 | case 1: | |
11097 | vex.prefix = DATA_PREFIX_OPCODE; | |
11098 | break; | |
11099 | case 2: | |
11100 | vex.prefix = REPE_PREFIX_OPCODE; | |
11101 | break; | |
11102 | case 3: | |
11103 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11104 | break; | |
11105 | } | |
11106 | need_vex = 1; | |
11107 | need_vex_reg = 1; | |
11108 | codep++; | |
91d6fa6a NC |
11109 | vindex = *codep++; |
11110 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
c0f3af97 | 11111 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 11112 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
11113 | { |
11114 | FETCH_DATA (info, codep + 1); | |
11115 | modrm.mod = (*codep >> 6) & 3; | |
11116 | modrm.reg = (*codep >> 3) & 7; | |
11117 | modrm.rm = *codep & 7; | |
11118 | } | |
11119 | break; | |
11120 | ||
9e30b8e0 L |
11121 | case USE_VEX_W_TABLE: |
11122 | if (!need_vex) | |
11123 | abort (); | |
11124 | ||
11125 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11126 | break; | |
11127 | ||
592d1631 L |
11128 | case 0: |
11129 | dp = &bad_opcode; | |
11130 | break; | |
11131 | ||
b844680a | 11132 | default: |
d34b5006 | 11133 | abort (); |
b844680a L |
11134 | } |
11135 | ||
11136 | if (dp->name != NULL) | |
11137 | return dp; | |
11138 | else | |
8bb15339 | 11139 | return get_valid_dis386 (dp, info); |
b844680a L |
11140 | } |
11141 | ||
e396998b | 11142 | static int |
26ca5450 | 11143 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11144 | { |
2da11e11 | 11145 | const struct dis386 *dp; |
252b5132 | 11146 | int i; |
ce518a5f | 11147 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11148 | int needcomma; |
e396998b AM |
11149 | int sizeflag; |
11150 | const char *p; | |
252b5132 | 11151 | struct dis_private priv; |
eec0f4ca | 11152 | unsigned char op; |
f16cd0d5 L |
11153 | int prefix_length; |
11154 | int default_prefixes; | |
252b5132 | 11155 | |
cb712a9e | 11156 | if (info->mach == bfd_mach_x86_64_intel_syntax |
8a9036a4 L |
11157 | || info->mach == bfd_mach_x86_64 |
11158 | || info->mach == bfd_mach_l1om | |
11159 | || info->mach == bfd_mach_l1om_intel_syntax) | |
cb712a9e L |
11160 | address_mode = mode_64bit; |
11161 | else | |
11162 | address_mode = mode_32bit; | |
52b15da3 | 11163 | |
8373f971 | 11164 | if (intel_syntax == (char) -1) |
e396998b | 11165 | intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax |
8a9036a4 L |
11166 | || info->mach == bfd_mach_x86_64_intel_syntax |
11167 | || info->mach == bfd_mach_l1om_intel_syntax); | |
e396998b | 11168 | |
2da11e11 | 11169 | if (info->mach == bfd_mach_i386_i386 |
52b15da3 | 11170 | || info->mach == bfd_mach_x86_64 |
8a9036a4 | 11171 | || info->mach == bfd_mach_l1om |
52b15da3 | 11172 | || info->mach == bfd_mach_i386_i386_intel_syntax |
8a9036a4 L |
11173 | || info->mach == bfd_mach_x86_64_intel_syntax |
11174 | || info->mach == bfd_mach_l1om_intel_syntax) | |
e396998b | 11175 | priv.orig_sizeflag = AFLAG | DFLAG; |
2da11e11 | 11176 | else if (info->mach == bfd_mach_i386_i8086) |
e396998b | 11177 | priv.orig_sizeflag = 0; |
2da11e11 AM |
11178 | else |
11179 | abort (); | |
e396998b AM |
11180 | |
11181 | for (p = info->disassembler_options; p != NULL; ) | |
11182 | { | |
0112cd26 | 11183 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 11184 | { |
cb712a9e | 11185 | address_mode = mode_64bit; |
e396998b AM |
11186 | priv.orig_sizeflag = AFLAG | DFLAG; |
11187 | } | |
0112cd26 | 11188 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11189 | { |
cb712a9e | 11190 | address_mode = mode_32bit; |
e396998b AM |
11191 | priv.orig_sizeflag = AFLAG | DFLAG; |
11192 | } | |
0112cd26 | 11193 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11194 | { |
cb712a9e | 11195 | address_mode = mode_16bit; |
e396998b AM |
11196 | priv.orig_sizeflag = 0; |
11197 | } | |
0112cd26 | 11198 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11199 | { |
11200 | intel_syntax = 1; | |
9d141669 L |
11201 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11202 | intel_mnemonic = 1; | |
e396998b | 11203 | } |
0112cd26 | 11204 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11205 | { |
11206 | intel_syntax = 0; | |
9d141669 L |
11207 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11208 | intel_mnemonic = 0; | |
e396998b | 11209 | } |
0112cd26 | 11210 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11211 | { |
f59a29b9 L |
11212 | if (address_mode == mode_64bit) |
11213 | { | |
11214 | if (p[4] == '3' && p[5] == '2') | |
11215 | priv.orig_sizeflag &= ~AFLAG; | |
11216 | else if (p[4] == '6' && p[5] == '4') | |
11217 | priv.orig_sizeflag |= AFLAG; | |
11218 | } | |
11219 | else | |
11220 | { | |
11221 | if (p[4] == '1' && p[5] == '6') | |
11222 | priv.orig_sizeflag &= ~AFLAG; | |
11223 | else if (p[4] == '3' && p[5] == '2') | |
11224 | priv.orig_sizeflag |= AFLAG; | |
11225 | } | |
e396998b | 11226 | } |
0112cd26 | 11227 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11228 | { |
11229 | if (p[4] == '1' && p[5] == '6') | |
11230 | priv.orig_sizeflag &= ~DFLAG; | |
11231 | else if (p[4] == '3' && p[5] == '2') | |
11232 | priv.orig_sizeflag |= DFLAG; | |
11233 | } | |
0112cd26 | 11234 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11235 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11236 | ||
11237 | p = strchr (p, ','); | |
11238 | if (p != NULL) | |
11239 | p++; | |
11240 | } | |
11241 | ||
11242 | if (intel_syntax) | |
11243 | { | |
11244 | names64 = intel_names64; | |
11245 | names32 = intel_names32; | |
11246 | names16 = intel_names16; | |
11247 | names8 = intel_names8; | |
11248 | names8rex = intel_names8rex; | |
11249 | names_seg = intel_names_seg; | |
b9733481 L |
11250 | names_mm = intel_names_mm; |
11251 | names_xmm = intel_names_xmm; | |
11252 | names_ymm = intel_names_ymm; | |
db51cc60 L |
11253 | index64 = intel_index64; |
11254 | index32 = intel_index32; | |
e396998b AM |
11255 | index16 = intel_index16; |
11256 | open_char = '['; | |
11257 | close_char = ']'; | |
11258 | separator_char = '+'; | |
11259 | scale_char = '*'; | |
11260 | } | |
11261 | else | |
11262 | { | |
11263 | names64 = att_names64; | |
11264 | names32 = att_names32; | |
11265 | names16 = att_names16; | |
11266 | names8 = att_names8; | |
11267 | names8rex = att_names8rex; | |
11268 | names_seg = att_names_seg; | |
b9733481 L |
11269 | names_mm = att_names_mm; |
11270 | names_xmm = att_names_xmm; | |
11271 | names_ymm = att_names_ymm; | |
db51cc60 L |
11272 | index64 = att_index64; |
11273 | index32 = att_index32; | |
e396998b AM |
11274 | index16 = att_index16; |
11275 | open_char = '('; | |
11276 | close_char = ')'; | |
11277 | separator_char = ','; | |
11278 | scale_char = ','; | |
11279 | } | |
2da11e11 | 11280 | |
4fe53c98 | 11281 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11282 | puts most long word instructions on a single line. Use 8 bytes |
11283 | for Intel L1OM. */ | |
11284 | if (info->mach == bfd_mach_l1om | |
11285 | || info->mach == bfd_mach_l1om_intel_syntax) | |
11286 | info->bytes_per_line = 8; | |
11287 | else | |
11288 | info->bytes_per_line = 7; | |
252b5132 | 11289 | |
26ca5450 | 11290 | info->private_data = &priv; |
252b5132 RH |
11291 | priv.max_fetched = priv.the_buffer; |
11292 | priv.insn_start = pc; | |
252b5132 RH |
11293 | |
11294 | obuf[0] = 0; | |
ce518a5f L |
11295 | for (i = 0; i < MAX_OPERANDS; ++i) |
11296 | { | |
11297 | op_out[i][0] = 0; | |
11298 | op_index[i] = -1; | |
11299 | } | |
252b5132 RH |
11300 | |
11301 | the_info = info; | |
11302 | start_pc = pc; | |
e396998b AM |
11303 | start_codep = priv.the_buffer; |
11304 | codep = priv.the_buffer; | |
252b5132 | 11305 | |
5076851f ILT |
11306 | if (setjmp (priv.bailout) != 0) |
11307 | { | |
7d421014 ILT |
11308 | const char *name; |
11309 | ||
5076851f | 11310 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11311 | means we have an incomplete instruction of some sort. Just |
11312 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11313 | if (codep > priv.the_buffer) | |
5076851f | 11314 | { |
e396998b | 11315 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11316 | if (name != NULL) |
11317 | (*info->fprintf_func) (info->stream, "%s", name); | |
11318 | else | |
5076851f | 11319 | { |
7d421014 ILT |
11320 | /* Just print the first byte as a .byte instruction. */ |
11321 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11322 | (unsigned int) priv.the_buffer[0]); |
5076851f | 11323 | } |
5076851f | 11324 | |
7d421014 | 11325 | return 1; |
5076851f ILT |
11326 | } |
11327 | ||
11328 | return -1; | |
11329 | } | |
11330 | ||
52b15da3 | 11331 | obufp = obuf; |
f16cd0d5 L |
11332 | sizeflag = priv.orig_sizeflag; |
11333 | ||
11334 | if (!ckprefix () || rex_used) | |
11335 | { | |
11336 | /* Too many prefixes or unused REX prefixes. */ | |
11337 | for (i = 0; | |
11338 | all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes); | |
11339 | i++) | |
11340 | (*info->fprintf_func) (info->stream, "%s", | |
11341 | prefix_name (all_prefixes[i], sizeflag)); | |
11342 | return 1; | |
11343 | } | |
252b5132 RH |
11344 | |
11345 | insn_codep = codep; | |
11346 | ||
11347 | FETCH_DATA (info, codep + 1); | |
11348 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
11349 | ||
3e7d61b2 | 11350 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 11351 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 11352 | { |
f16cd0d5 | 11353 | (*info->fprintf_func) (info->stream, "fwait"); |
7d421014 | 11354 | return 1; |
252b5132 RH |
11355 | } |
11356 | ||
eec0f4ca | 11357 | op = 0; |
c1e679ec | 11358 | |
252b5132 RH |
11359 | if (*codep == 0x0f) |
11360 | { | |
eec0f4ca | 11361 | unsigned char threebyte; |
252b5132 | 11362 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
11363 | threebyte = *++codep; |
11364 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 11365 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 11366 | codep++; |
252b5132 RH |
11367 | } |
11368 | else | |
11369 | { | |
6439fc28 | 11370 | dp = &dis386[*codep]; |
252b5132 | 11371 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 11372 | codep++; |
252b5132 | 11373 | } |
246c51aa | 11374 | |
b844680a | 11375 | if ((prefixes & PREFIX_REPZ)) |
f16cd0d5 | 11376 | used_prefixes |= PREFIX_REPZ; |
b844680a | 11377 | if ((prefixes & PREFIX_REPNZ)) |
f16cd0d5 | 11378 | used_prefixes |= PREFIX_REPNZ; |
b844680a | 11379 | if ((prefixes & PREFIX_LOCK)) |
f16cd0d5 | 11380 | used_prefixes |= PREFIX_LOCK; |
c608c12e | 11381 | |
f16cd0d5 | 11382 | default_prefixes = 0; |
c608c12e AM |
11383 | if (prefixes & PREFIX_ADDR) |
11384 | { | |
11385 | sizeflag ^= AFLAG; | |
ce518a5f | 11386 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 11387 | { |
cb712a9e | 11388 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
f16cd0d5 | 11389 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
3ffd33cf | 11390 | else |
f16cd0d5 L |
11391 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
11392 | default_prefixes |= PREFIX_ADDR; | |
3ffd33cf AM |
11393 | } |
11394 | } | |
11395 | ||
b844680a | 11396 | if ((prefixes & PREFIX_DATA)) |
3ffd33cf AM |
11397 | { |
11398 | sizeflag ^= DFLAG; | |
ce518a5f L |
11399 | if (dp->op[2].bytemode == cond_jump_mode |
11400 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 11401 | && !intel_syntax) |
3ffd33cf AM |
11402 | { |
11403 | if (sizeflag & DFLAG) | |
f16cd0d5 | 11404 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
3ffd33cf | 11405 | else |
f16cd0d5 L |
11406 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
11407 | default_prefixes |= PREFIX_DATA; | |
11408 | } | |
11409 | else if (rex & REX_W) | |
11410 | { | |
11411 | /* REX_W will override PREFIX_DATA. */ | |
11412 | default_prefixes |= PREFIX_DATA; | |
3ffd33cf AM |
11413 | } |
11414 | } | |
11415 | ||
8bb15339 | 11416 | if (need_modrm) |
252b5132 RH |
11417 | { |
11418 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
11419 | modrm.mod = (*codep >> 6) & 3; |
11420 | modrm.reg = (*codep >> 3) & 7; | |
11421 | modrm.rm = *codep & 7; | |
252b5132 RH |
11422 | } |
11423 | ||
55b126d4 L |
11424 | need_vex = 0; |
11425 | need_vex_reg = 0; | |
11426 | vex_w_done = 0; | |
11427 | ||
ce518a5f | 11428 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 RH |
11429 | { |
11430 | dofloat (sizeflag); | |
11431 | } | |
11432 | else | |
11433 | { | |
8bb15339 | 11434 | dp = get_valid_dis386 (dp, info); |
b844680a | 11435 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
ce518a5f L |
11436 | { |
11437 | for (i = 0; i < MAX_OPERANDS; ++i) | |
11438 | { | |
246c51aa | 11439 | obufp = op_out[i]; |
ce518a5f L |
11440 | op_ad = MAX_OPERANDS - 1 - i; |
11441 | if (dp->op[i].rtn) | |
11442 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
11443 | } | |
6439fc28 | 11444 | } |
252b5132 RH |
11445 | } |
11446 | ||
7d421014 ILT |
11447 | /* See if any prefixes were not used. If so, print the first one |
11448 | separately. If we don't do this, we'll wind up printing an | |
11449 | instruction stream which does not precisely correspond to the | |
11450 | bytes we are disassembling. */ | |
f16cd0d5 | 11451 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
7d421014 | 11452 | { |
f16cd0d5 L |
11453 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11454 | if (all_prefixes[i]) | |
11455 | { | |
11456 | const char *name; | |
11457 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); | |
11458 | if (name == NULL) | |
11459 | name = INTERNAL_DISASSEMBLER_ERROR; | |
11460 | (*info->fprintf_func) (info->stream, "%s", name); | |
11461 | return 1; | |
11462 | } | |
52b15da3 | 11463 | } |
7d421014 | 11464 | |
d869730d | 11465 | /* Check if the REX prefix is used. */ |
2a70cca4 | 11466 | if (rex_ignored == 0 && (rex ^ rex_used) == 0) |
f16cd0d5 L |
11467 | all_prefixes[last_rex_prefix] = 0; |
11468 | ||
5e6718e4 | 11469 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
11470 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
11471 | | PREFIX_FS | PREFIX_GS)) != 0 | |
11472 | && (used_prefixes | |
11473 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) | |
11474 | all_prefixes[last_seg_prefix] = 0; | |
11475 | ||
5e6718e4 | 11476 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
11477 | if ((prefixes & PREFIX_ADDR) != 0 |
11478 | && (used_prefixes & PREFIX_ADDR) != 0) | |
11479 | all_prefixes[last_addr_prefix] = 0; | |
11480 | ||
5e6718e4 | 11481 | /* Check if the DATA prefix is used. */ |
f16cd0d5 L |
11482 | if ((prefixes & PREFIX_DATA) != 0 |
11483 | && (used_prefixes & PREFIX_DATA) != 0) | |
11484 | all_prefixes[last_data_prefix] = 0; | |
11485 | ||
11486 | prefix_length = 0; | |
f310f33d | 11487 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
11488 | if (all_prefixes[i]) |
11489 | { | |
11490 | const char *name; | |
11491 | name = prefix_name (all_prefixes[i], sizeflag); | |
11492 | if (name == NULL) | |
11493 | abort (); | |
11494 | prefix_length += strlen (name) + 1; | |
11495 | (*info->fprintf_func) (info->stream, "%s ", name); | |
11496 | } | |
b844680a | 11497 | |
f16cd0d5 L |
11498 | /* Check maximum code length. */ |
11499 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
11500 | { | |
11501 | (*info->fprintf_func) (info->stream, "(bad)"); | |
11502 | return MAX_CODE_LENGTH; | |
11503 | } | |
b844680a | 11504 | |
ea397f5b | 11505 | obufp = mnemonicendp; |
f16cd0d5 | 11506 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
11507 | oappend (" "); |
11508 | oappend (" "); | |
11509 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
11510 | ||
11511 | /* The enter and bound instructions are printed with operands in the same | |
11512 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 11513 | if (intel_syntax || two_source_ops) |
252b5132 | 11514 | { |
185b1163 L |
11515 | bfd_vma riprel; |
11516 | ||
ce518a5f L |
11517 | for (i = 0; i < MAX_OPERANDS; ++i) |
11518 | op_txt[i] = op_out[i]; | |
246c51aa | 11519 | |
ce518a5f L |
11520 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
11521 | { | |
11522 | op_ad = op_index[i]; | |
11523 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
11524 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
11525 | riprel = op_riprel[i]; |
11526 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
11527 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 11528 | } |
252b5132 RH |
11529 | } |
11530 | else | |
11531 | { | |
ce518a5f L |
11532 | for (i = 0; i < MAX_OPERANDS; ++i) |
11533 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; | |
050dfa73 MM |
11534 | } |
11535 | ||
ce518a5f L |
11536 | needcomma = 0; |
11537 | for (i = 0; i < MAX_OPERANDS; ++i) | |
11538 | if (*op_txt[i]) | |
11539 | { | |
11540 | if (needcomma) | |
11541 | (*info->fprintf_func) (info->stream, ","); | |
11542 | if (op_index[i] != -1 && !op_riprel[i]) | |
11543 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
11544 | else | |
11545 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
11546 | needcomma = 1; | |
11547 | } | |
050dfa73 | 11548 | |
ce518a5f | 11549 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
11550 | if (op_index[i] != -1 && op_riprel[i]) |
11551 | { | |
11552 | (*info->fprintf_func) (info->stream, " # "); | |
11553 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
11554 | + op_address[op_index[i]]), info); | |
185b1163 | 11555 | break; |
52b15da3 | 11556 | } |
e396998b | 11557 | return codep - priv.the_buffer; |
252b5132 RH |
11558 | } |
11559 | ||
6439fc28 | 11560 | static const char *float_mem[] = { |
252b5132 | 11561 | /* d8 */ |
7c52e0e8 L |
11562 | "fadd{s|}", |
11563 | "fmul{s|}", | |
11564 | "fcom{s|}", | |
11565 | "fcomp{s|}", | |
11566 | "fsub{s|}", | |
11567 | "fsubr{s|}", | |
11568 | "fdiv{s|}", | |
11569 | "fdivr{s|}", | |
db6eb5be | 11570 | /* d9 */ |
7c52e0e8 | 11571 | "fld{s|}", |
252b5132 | 11572 | "(bad)", |
7c52e0e8 L |
11573 | "fst{s|}", |
11574 | "fstp{s|}", | |
9306ca4a | 11575 | "fldenvIC", |
252b5132 | 11576 | "fldcw", |
9306ca4a | 11577 | "fNstenvIC", |
252b5132 RH |
11578 | "fNstcw", |
11579 | /* da */ | |
7c52e0e8 L |
11580 | "fiadd{l|}", |
11581 | "fimul{l|}", | |
11582 | "ficom{l|}", | |
11583 | "ficomp{l|}", | |
11584 | "fisub{l|}", | |
11585 | "fisubr{l|}", | |
11586 | "fidiv{l|}", | |
11587 | "fidivr{l|}", | |
252b5132 | 11588 | /* db */ |
7c52e0e8 L |
11589 | "fild{l|}", |
11590 | "fisttp{l|}", | |
11591 | "fist{l|}", | |
11592 | "fistp{l|}", | |
252b5132 | 11593 | "(bad)", |
6439fc28 | 11594 | "fld{t||t|}", |
252b5132 | 11595 | "(bad)", |
6439fc28 | 11596 | "fstp{t||t|}", |
252b5132 | 11597 | /* dc */ |
7c52e0e8 L |
11598 | "fadd{l|}", |
11599 | "fmul{l|}", | |
11600 | "fcom{l|}", | |
11601 | "fcomp{l|}", | |
11602 | "fsub{l|}", | |
11603 | "fsubr{l|}", | |
11604 | "fdiv{l|}", | |
11605 | "fdivr{l|}", | |
252b5132 | 11606 | /* dd */ |
7c52e0e8 L |
11607 | "fld{l|}", |
11608 | "fisttp{ll|}", | |
11609 | "fst{l||}", | |
11610 | "fstp{l|}", | |
9306ca4a | 11611 | "frstorIC", |
252b5132 | 11612 | "(bad)", |
9306ca4a | 11613 | "fNsaveIC", |
252b5132 RH |
11614 | "fNstsw", |
11615 | /* de */ | |
11616 | "fiadd", | |
11617 | "fimul", | |
11618 | "ficom", | |
11619 | "ficomp", | |
11620 | "fisub", | |
11621 | "fisubr", | |
11622 | "fidiv", | |
11623 | "fidivr", | |
11624 | /* df */ | |
11625 | "fild", | |
ca164297 | 11626 | "fisttp", |
252b5132 RH |
11627 | "fist", |
11628 | "fistp", | |
11629 | "fbld", | |
7c52e0e8 | 11630 | "fild{ll|}", |
252b5132 | 11631 | "fbstp", |
7c52e0e8 | 11632 | "fistp{ll|}", |
1d9f512f AM |
11633 | }; |
11634 | ||
11635 | static const unsigned char float_mem_mode[] = { | |
11636 | /* d8 */ | |
11637 | d_mode, | |
11638 | d_mode, | |
11639 | d_mode, | |
11640 | d_mode, | |
11641 | d_mode, | |
11642 | d_mode, | |
11643 | d_mode, | |
11644 | d_mode, | |
11645 | /* d9 */ | |
11646 | d_mode, | |
11647 | 0, | |
11648 | d_mode, | |
11649 | d_mode, | |
11650 | 0, | |
11651 | w_mode, | |
11652 | 0, | |
11653 | w_mode, | |
11654 | /* da */ | |
11655 | d_mode, | |
11656 | d_mode, | |
11657 | d_mode, | |
11658 | d_mode, | |
11659 | d_mode, | |
11660 | d_mode, | |
11661 | d_mode, | |
11662 | d_mode, | |
11663 | /* db */ | |
11664 | d_mode, | |
11665 | d_mode, | |
11666 | d_mode, | |
11667 | d_mode, | |
11668 | 0, | |
9306ca4a | 11669 | t_mode, |
1d9f512f | 11670 | 0, |
9306ca4a | 11671 | t_mode, |
1d9f512f AM |
11672 | /* dc */ |
11673 | q_mode, | |
11674 | q_mode, | |
11675 | q_mode, | |
11676 | q_mode, | |
11677 | q_mode, | |
11678 | q_mode, | |
11679 | q_mode, | |
11680 | q_mode, | |
11681 | /* dd */ | |
11682 | q_mode, | |
11683 | q_mode, | |
11684 | q_mode, | |
11685 | q_mode, | |
11686 | 0, | |
11687 | 0, | |
11688 | 0, | |
11689 | w_mode, | |
11690 | /* de */ | |
11691 | w_mode, | |
11692 | w_mode, | |
11693 | w_mode, | |
11694 | w_mode, | |
11695 | w_mode, | |
11696 | w_mode, | |
11697 | w_mode, | |
11698 | w_mode, | |
11699 | /* df */ | |
11700 | w_mode, | |
11701 | w_mode, | |
11702 | w_mode, | |
11703 | w_mode, | |
9306ca4a | 11704 | t_mode, |
1d9f512f | 11705 | q_mode, |
9306ca4a | 11706 | t_mode, |
1d9f512f | 11707 | q_mode |
252b5132 RH |
11708 | }; |
11709 | ||
ce518a5f L |
11710 | #define ST { OP_ST, 0 } |
11711 | #define STi { OP_STi, 0 } | |
252b5132 | 11712 | |
4efba78c L |
11713 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
11714 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
11715 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
11716 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
11717 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
11718 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
11719 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
11720 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
11721 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 11722 | |
2da11e11 | 11723 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
11724 | /* d8 */ |
11725 | { | |
ce518a5f L |
11726 | { "fadd", { ST, STi } }, |
11727 | { "fmul", { ST, STi } }, | |
11728 | { "fcom", { STi } }, | |
11729 | { "fcomp", { STi } }, | |
11730 | { "fsub", { ST, STi } }, | |
11731 | { "fsubr", { ST, STi } }, | |
11732 | { "fdiv", { ST, STi } }, | |
11733 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
11734 | }, |
11735 | /* d9 */ | |
11736 | { | |
ce518a5f L |
11737 | { "fld", { STi } }, |
11738 | { "fxch", { STi } }, | |
252b5132 | 11739 | { FGRPd9_2 }, |
592d1631 | 11740 | { Bad_Opcode }, |
252b5132 RH |
11741 | { FGRPd9_4 }, |
11742 | { FGRPd9_5 }, | |
11743 | { FGRPd9_6 }, | |
11744 | { FGRPd9_7 }, | |
11745 | }, | |
11746 | /* da */ | |
11747 | { | |
ce518a5f L |
11748 | { "fcmovb", { ST, STi } }, |
11749 | { "fcmove", { ST, STi } }, | |
11750 | { "fcmovbe",{ ST, STi } }, | |
11751 | { "fcmovu", { ST, STi } }, | |
592d1631 | 11752 | { Bad_Opcode }, |
252b5132 | 11753 | { FGRPda_5 }, |
592d1631 L |
11754 | { Bad_Opcode }, |
11755 | { Bad_Opcode }, | |
252b5132 RH |
11756 | }, |
11757 | /* db */ | |
11758 | { | |
ce518a5f L |
11759 | { "fcmovnb",{ ST, STi } }, |
11760 | { "fcmovne",{ ST, STi } }, | |
11761 | { "fcmovnbe",{ ST, STi } }, | |
11762 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 11763 | { FGRPdb_4 }, |
ce518a5f L |
11764 | { "fucomi", { ST, STi } }, |
11765 | { "fcomi", { ST, STi } }, | |
592d1631 | 11766 | { Bad_Opcode }, |
252b5132 RH |
11767 | }, |
11768 | /* dc */ | |
11769 | { | |
ce518a5f L |
11770 | { "fadd", { STi, ST } }, |
11771 | { "fmul", { STi, ST } }, | |
592d1631 L |
11772 | { Bad_Opcode }, |
11773 | { Bad_Opcode }, | |
9d141669 L |
11774 | { "fsub!M", { STi, ST } }, |
11775 | { "fsubM", { STi, ST } }, | |
11776 | { "fdiv!M", { STi, ST } }, | |
11777 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
11778 | }, |
11779 | /* dd */ | |
11780 | { | |
ce518a5f | 11781 | { "ffree", { STi } }, |
592d1631 | 11782 | { Bad_Opcode }, |
ce518a5f L |
11783 | { "fst", { STi } }, |
11784 | { "fstp", { STi } }, | |
11785 | { "fucom", { STi } }, | |
11786 | { "fucomp", { STi } }, | |
592d1631 L |
11787 | { Bad_Opcode }, |
11788 | { Bad_Opcode }, | |
252b5132 RH |
11789 | }, |
11790 | /* de */ | |
11791 | { | |
ce518a5f L |
11792 | { "faddp", { STi, ST } }, |
11793 | { "fmulp", { STi, ST } }, | |
592d1631 | 11794 | { Bad_Opcode }, |
252b5132 | 11795 | { FGRPde_3 }, |
9d141669 L |
11796 | { "fsub!Mp", { STi, ST } }, |
11797 | { "fsubMp", { STi, ST } }, | |
11798 | { "fdiv!Mp", { STi, ST } }, | |
11799 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
11800 | }, |
11801 | /* df */ | |
11802 | { | |
ce518a5f | 11803 | { "ffreep", { STi } }, |
592d1631 L |
11804 | { Bad_Opcode }, |
11805 | { Bad_Opcode }, | |
11806 | { Bad_Opcode }, | |
252b5132 | 11807 | { FGRPdf_4 }, |
ce518a5f L |
11808 | { "fucomip", { ST, STi } }, |
11809 | { "fcomip", { ST, STi } }, | |
592d1631 | 11810 | { Bad_Opcode }, |
252b5132 RH |
11811 | }, |
11812 | }; | |
11813 | ||
252b5132 RH |
11814 | static char *fgrps[][8] = { |
11815 | /* d9_2 0 */ | |
11816 | { | |
11817 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
11818 | }, | |
11819 | ||
11820 | /* d9_4 1 */ | |
11821 | { | |
11822 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
11823 | }, | |
11824 | ||
11825 | /* d9_5 2 */ | |
11826 | { | |
11827 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
11828 | }, | |
11829 | ||
11830 | /* d9_6 3 */ | |
11831 | { | |
11832 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
11833 | }, | |
11834 | ||
11835 | /* d9_7 4 */ | |
11836 | { | |
11837 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
11838 | }, | |
11839 | ||
11840 | /* da_5 5 */ | |
11841 | { | |
11842 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
11843 | }, | |
11844 | ||
11845 | /* db_4 6 */ | |
11846 | { | |
309d3373 JB |
11847 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
11848 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
11849 | }, |
11850 | ||
11851 | /* de_3 7 */ | |
11852 | { | |
11853 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
11854 | }, | |
11855 | ||
11856 | /* df_4 8 */ | |
11857 | { | |
11858 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
11859 | }, | |
11860 | }; | |
11861 | ||
b6169b20 L |
11862 | static void |
11863 | swap_operand (void) | |
11864 | { | |
11865 | mnemonicendp[0] = '.'; | |
11866 | mnemonicendp[1] = 's'; | |
11867 | mnemonicendp += 2; | |
11868 | } | |
11869 | ||
b844680a L |
11870 | static void |
11871 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
11872 | int sizeflag ATTRIBUTE_UNUSED) | |
11873 | { | |
11874 | /* Skip mod/rm byte. */ | |
11875 | MODRM_CHECK; | |
11876 | codep++; | |
11877 | } | |
11878 | ||
252b5132 | 11879 | static void |
26ca5450 | 11880 | dofloat (int sizeflag) |
252b5132 | 11881 | { |
2da11e11 | 11882 | const struct dis386 *dp; |
252b5132 RH |
11883 | unsigned char floatop; |
11884 | ||
11885 | floatop = codep[-1]; | |
11886 | ||
7967e09e | 11887 | if (modrm.mod != 3) |
252b5132 | 11888 | { |
7967e09e | 11889 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
11890 | |
11891 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 11892 | obufp = op_out[0]; |
6e50d963 | 11893 | op_ad = 2; |
1d9f512f | 11894 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
11895 | return; |
11896 | } | |
6608db57 | 11897 | /* Skip mod/rm byte. */ |
4bba6815 | 11898 | MODRM_CHECK; |
252b5132 RH |
11899 | codep++; |
11900 | ||
7967e09e | 11901 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
11902 | if (dp->name == NULL) |
11903 | { | |
7967e09e | 11904 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 11905 | |
6608db57 | 11906 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 11907 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 11908 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
11909 | } |
11910 | else | |
11911 | { | |
11912 | putop (dp->name, sizeflag); | |
11913 | ||
ce518a5f | 11914 | obufp = op_out[0]; |
6e50d963 | 11915 | op_ad = 2; |
ce518a5f L |
11916 | if (dp->op[0].rtn) |
11917 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 11918 | |
ce518a5f | 11919 | obufp = op_out[1]; |
6e50d963 | 11920 | op_ad = 1; |
ce518a5f L |
11921 | if (dp->op[1].rtn) |
11922 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
11923 | } |
11924 | } | |
11925 | ||
252b5132 | 11926 | static void |
26ca5450 | 11927 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11928 | { |
422673a9 | 11929 | oappend ("%st" + intel_syntax); |
252b5132 RH |
11930 | } |
11931 | ||
252b5132 | 11932 | static void |
26ca5450 | 11933 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11934 | { |
7967e09e | 11935 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
d708bcba | 11936 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11937 | } |
11938 | ||
6608db57 | 11939 | /* Capital letters in template are macros. */ |
6439fc28 | 11940 | static int |
d3ce72d0 | 11941 | putop (const char *in_template, int sizeflag) |
252b5132 | 11942 | { |
2da11e11 | 11943 | const char *p; |
9306ca4a | 11944 | int alt = 0; |
9d141669 | 11945 | int cond = 1; |
98b528ac L |
11946 | unsigned int l = 0, len = 1; |
11947 | char last[4]; | |
11948 | ||
11949 | #define SAVE_LAST(c) \ | |
11950 | if (l < len && l < sizeof (last)) \ | |
11951 | last[l++] = c; \ | |
11952 | else \ | |
11953 | abort (); | |
252b5132 | 11954 | |
d3ce72d0 | 11955 | for (p = in_template; *p; p++) |
252b5132 RH |
11956 | { |
11957 | switch (*p) | |
11958 | { | |
11959 | default: | |
11960 | *obufp++ = *p; | |
11961 | break; | |
98b528ac L |
11962 | case '%': |
11963 | len++; | |
11964 | break; | |
9d141669 L |
11965 | case '!': |
11966 | cond = 0; | |
11967 | break; | |
6439fc28 AM |
11968 | case '{': |
11969 | alt = 0; | |
11970 | if (intel_syntax) | |
6439fc28 AM |
11971 | { |
11972 | while (*++p != '|') | |
7c52e0e8 L |
11973 | if (*p == '}' || *p == '\0') |
11974 | abort (); | |
6439fc28 | 11975 | } |
9306ca4a JB |
11976 | /* Fall through. */ |
11977 | case 'I': | |
11978 | alt = 1; | |
11979 | continue; | |
6439fc28 AM |
11980 | case '|': |
11981 | while (*++p != '}') | |
11982 | { | |
11983 | if (*p == '\0') | |
11984 | abort (); | |
11985 | } | |
11986 | break; | |
11987 | case '}': | |
11988 | break; | |
252b5132 | 11989 | case 'A': |
db6eb5be AM |
11990 | if (intel_syntax) |
11991 | break; | |
7967e09e | 11992 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
11993 | *obufp++ = 'b'; |
11994 | break; | |
11995 | case 'B': | |
4b06377f L |
11996 | if (l == 0 && len == 1) |
11997 | { | |
11998 | case_B: | |
11999 | if (intel_syntax) | |
12000 | break; | |
12001 | if (sizeflag & SUFFIX_ALWAYS) | |
12002 | *obufp++ = 'b'; | |
12003 | } | |
12004 | else | |
12005 | { | |
12006 | if (l != 1 | |
12007 | || len != 2 | |
12008 | || last[0] != 'L') | |
12009 | { | |
12010 | SAVE_LAST (*p); | |
12011 | break; | |
12012 | } | |
12013 | ||
12014 | if (address_mode == mode_64bit | |
12015 | && !(prefixes & PREFIX_ADDR)) | |
12016 | { | |
12017 | *obufp++ = 'a'; | |
12018 | *obufp++ = 'b'; | |
12019 | *obufp++ = 's'; | |
12020 | } | |
12021 | ||
12022 | goto case_B; | |
12023 | } | |
252b5132 | 12024 | break; |
9306ca4a JB |
12025 | case 'C': |
12026 | if (intel_syntax && !alt) | |
12027 | break; | |
12028 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12029 | { | |
12030 | if (sizeflag & DFLAG) | |
12031 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12032 | else | |
12033 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12034 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12035 | } | |
12036 | break; | |
ed7841b3 JB |
12037 | case 'D': |
12038 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12039 | break; | |
161a04f6 | 12040 | USED_REX (REX_W); |
7967e09e | 12041 | if (modrm.mod == 3) |
ed7841b3 | 12042 | { |
161a04f6 | 12043 | if (rex & REX_W) |
ed7841b3 | 12044 | *obufp++ = 'q'; |
ed7841b3 | 12045 | else |
f16cd0d5 L |
12046 | { |
12047 | if (sizeflag & DFLAG) | |
12048 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12049 | else | |
12050 | *obufp++ = 'w'; | |
12051 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12052 | } | |
ed7841b3 JB |
12053 | } |
12054 | else | |
12055 | *obufp++ = 'w'; | |
12056 | break; | |
252b5132 | 12057 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12058 | if (address_mode == mode_64bit) |
c1a64871 JH |
12059 | { |
12060 | if (sizeflag & AFLAG) | |
12061 | *obufp++ = 'r'; | |
12062 | else | |
12063 | *obufp++ = 'e'; | |
12064 | } | |
12065 | else | |
12066 | if (sizeflag & AFLAG) | |
12067 | *obufp++ = 'e'; | |
3ffd33cf AM |
12068 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12069 | break; | |
12070 | case 'F': | |
db6eb5be AM |
12071 | if (intel_syntax) |
12072 | break; | |
e396998b | 12073 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12074 | { |
12075 | if (sizeflag & AFLAG) | |
cb712a9e | 12076 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12077 | else |
cb712a9e | 12078 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12079 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12080 | } | |
252b5132 | 12081 | break; |
52fd6d94 JB |
12082 | case 'G': |
12083 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12084 | break; | |
161a04f6 | 12085 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12086 | *obufp++ = 'l'; |
12087 | else | |
12088 | *obufp++ = 'w'; | |
161a04f6 | 12089 | if (!(rex & REX_W)) |
52fd6d94 JB |
12090 | used_prefixes |= (prefixes & PREFIX_DATA); |
12091 | break; | |
5dd0794d | 12092 | case 'H': |
db6eb5be AM |
12093 | if (intel_syntax) |
12094 | break; | |
5dd0794d AM |
12095 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12096 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12097 | { | |
12098 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12099 | *obufp++ = ','; | |
12100 | *obufp++ = 'p'; | |
12101 | if (prefixes & PREFIX_DS) | |
12102 | *obufp++ = 't'; | |
12103 | else | |
12104 | *obufp++ = 'n'; | |
12105 | } | |
12106 | break; | |
9306ca4a JB |
12107 | case 'J': |
12108 | if (intel_syntax) | |
12109 | break; | |
12110 | *obufp++ = 'l'; | |
12111 | break; | |
42903f7f L |
12112 | case 'K': |
12113 | USED_REX (REX_W); | |
12114 | if (rex & REX_W) | |
12115 | *obufp++ = 'q'; | |
12116 | else | |
12117 | *obufp++ = 'd'; | |
12118 | break; | |
6dd5059a L |
12119 | case 'Z': |
12120 | if (intel_syntax) | |
12121 | break; | |
12122 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12123 | { | |
12124 | *obufp++ = 'q'; | |
12125 | break; | |
12126 | } | |
12127 | /* Fall through. */ | |
98b528ac | 12128 | goto case_L; |
252b5132 | 12129 | case 'L': |
98b528ac L |
12130 | if (l != 0 || len != 1) |
12131 | { | |
12132 | SAVE_LAST (*p); | |
12133 | break; | |
12134 | } | |
12135 | case_L: | |
db6eb5be AM |
12136 | if (intel_syntax) |
12137 | break; | |
252b5132 RH |
12138 | if (sizeflag & SUFFIX_ALWAYS) |
12139 | *obufp++ = 'l'; | |
252b5132 | 12140 | break; |
9d141669 L |
12141 | case 'M': |
12142 | if (intel_mnemonic != cond) | |
12143 | *obufp++ = 'r'; | |
12144 | break; | |
252b5132 RH |
12145 | case 'N': |
12146 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12147 | *obufp++ = 'n'; | |
7d421014 ILT |
12148 | else |
12149 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12150 | break; |
52b15da3 | 12151 | case 'O': |
161a04f6 L |
12152 | USED_REX (REX_W); |
12153 | if (rex & REX_W) | |
6439fc28 | 12154 | *obufp++ = 'o'; |
a35ca55a JB |
12155 | else if (intel_syntax && (sizeflag & DFLAG)) |
12156 | *obufp++ = 'q'; | |
52b15da3 JH |
12157 | else |
12158 | *obufp++ = 'd'; | |
161a04f6 | 12159 | if (!(rex & REX_W)) |
a35ca55a | 12160 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12161 | break; |
6439fc28 | 12162 | case 'T': |
db6eb5be AM |
12163 | if (intel_syntax) |
12164 | break; | |
cb712a9e | 12165 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
12166 | { |
12167 | *obufp++ = 'q'; | |
12168 | break; | |
12169 | } | |
6608db57 | 12170 | /* Fall through. */ |
252b5132 | 12171 | case 'P': |
db6eb5be AM |
12172 | if (intel_syntax) |
12173 | break; | |
252b5132 | 12174 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 12175 | || (rex & REX_W) |
e396998b | 12176 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 12177 | { |
161a04f6 L |
12178 | USED_REX (REX_W); |
12179 | if (rex & REX_W) | |
52b15da3 | 12180 | *obufp++ = 'q'; |
c2419411 | 12181 | else |
52b15da3 JH |
12182 | { |
12183 | if (sizeflag & DFLAG) | |
12184 | *obufp++ = 'l'; | |
12185 | else | |
12186 | *obufp++ = 'w'; | |
f16cd0d5 | 12187 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12188 | } |
252b5132 RH |
12189 | } |
12190 | break; | |
6439fc28 | 12191 | case 'U': |
db6eb5be AM |
12192 | if (intel_syntax) |
12193 | break; | |
cb712a9e | 12194 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 | 12195 | { |
7967e09e | 12196 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 12197 | *obufp++ = 'q'; |
6439fc28 AM |
12198 | break; |
12199 | } | |
6608db57 | 12200 | /* Fall through. */ |
98b528ac | 12201 | goto case_Q; |
252b5132 | 12202 | case 'Q': |
98b528ac | 12203 | if (l == 0 && len == 1) |
252b5132 | 12204 | { |
98b528ac L |
12205 | case_Q: |
12206 | if (intel_syntax && !alt) | |
12207 | break; | |
12208 | USED_REX (REX_W); | |
12209 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12210 | { |
98b528ac L |
12211 | if (rex & REX_W) |
12212 | *obufp++ = 'q'; | |
52b15da3 | 12213 | else |
98b528ac L |
12214 | { |
12215 | if (sizeflag & DFLAG) | |
12216 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12217 | else | |
12218 | *obufp++ = 'w'; | |
f16cd0d5 | 12219 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 12220 | } |
52b15da3 | 12221 | } |
98b528ac L |
12222 | } |
12223 | else | |
12224 | { | |
12225 | if (l != 1 || len != 2 || last[0] != 'L') | |
12226 | { | |
12227 | SAVE_LAST (*p); | |
12228 | break; | |
12229 | } | |
12230 | if (intel_syntax | |
12231 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
12232 | break; | |
12233 | if ((rex & REX_W)) | |
12234 | { | |
12235 | USED_REX (REX_W); | |
12236 | *obufp++ = 'q'; | |
12237 | } | |
12238 | else | |
12239 | *obufp++ = 'l'; | |
252b5132 RH |
12240 | } |
12241 | break; | |
12242 | case 'R': | |
161a04f6 L |
12243 | USED_REX (REX_W); |
12244 | if (rex & REX_W) | |
a35ca55a JB |
12245 | *obufp++ = 'q'; |
12246 | else if (sizeflag & DFLAG) | |
c608c12e | 12247 | { |
a35ca55a | 12248 | if (intel_syntax) |
c608c12e | 12249 | *obufp++ = 'd'; |
c608c12e | 12250 | else |
a35ca55a | 12251 | *obufp++ = 'l'; |
c608c12e | 12252 | } |
252b5132 | 12253 | else |
a35ca55a JB |
12254 | *obufp++ = 'w'; |
12255 | if (intel_syntax && !p[1] | |
161a04f6 | 12256 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 12257 | *obufp++ = 'e'; |
161a04f6 | 12258 | if (!(rex & REX_W)) |
52b15da3 | 12259 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 12260 | break; |
1a114b12 | 12261 | case 'V': |
4b06377f | 12262 | if (l == 0 && len == 1) |
1a114b12 | 12263 | { |
4b06377f L |
12264 | if (intel_syntax) |
12265 | break; | |
12266 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) | |
12267 | { | |
12268 | if (sizeflag & SUFFIX_ALWAYS) | |
12269 | *obufp++ = 'q'; | |
12270 | break; | |
12271 | } | |
12272 | } | |
12273 | else | |
12274 | { | |
12275 | if (l != 1 | |
12276 | || len != 2 | |
12277 | || last[0] != 'L') | |
12278 | { | |
12279 | SAVE_LAST (*p); | |
12280 | break; | |
12281 | } | |
12282 | ||
12283 | if (rex & REX_W) | |
12284 | { | |
12285 | *obufp++ = 'a'; | |
12286 | *obufp++ = 'b'; | |
12287 | *obufp++ = 's'; | |
12288 | } | |
1a114b12 JB |
12289 | } |
12290 | /* Fall through. */ | |
4b06377f | 12291 | goto case_S; |
252b5132 | 12292 | case 'S': |
4b06377f | 12293 | if (l == 0 && len == 1) |
252b5132 | 12294 | { |
4b06377f L |
12295 | case_S: |
12296 | if (intel_syntax) | |
12297 | break; | |
12298 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 12299 | { |
4b06377f L |
12300 | if (rex & REX_W) |
12301 | *obufp++ = 'q'; | |
52b15da3 | 12302 | else |
4b06377f L |
12303 | { |
12304 | if (sizeflag & DFLAG) | |
12305 | *obufp++ = 'l'; | |
12306 | else | |
12307 | *obufp++ = 'w'; | |
12308 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12309 | } | |
12310 | } | |
12311 | } | |
12312 | else | |
12313 | { | |
12314 | if (l != 1 | |
12315 | || len != 2 | |
12316 | || last[0] != 'L') | |
12317 | { | |
12318 | SAVE_LAST (*p); | |
12319 | break; | |
52b15da3 | 12320 | } |
4b06377f L |
12321 | |
12322 | if (address_mode == mode_64bit | |
12323 | && !(prefixes & PREFIX_ADDR)) | |
12324 | { | |
12325 | *obufp++ = 'a'; | |
12326 | *obufp++ = 'b'; | |
12327 | *obufp++ = 's'; | |
12328 | } | |
12329 | ||
12330 | goto case_S; | |
252b5132 | 12331 | } |
252b5132 | 12332 | break; |
041bd2e0 | 12333 | case 'X': |
c0f3af97 L |
12334 | if (l != 0 || len != 1) |
12335 | { | |
12336 | SAVE_LAST (*p); | |
12337 | break; | |
12338 | } | |
12339 | if (need_vex && vex.prefix) | |
12340 | { | |
12341 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
12342 | *obufp++ = 'd'; | |
12343 | else | |
12344 | *obufp++ = 's'; | |
12345 | } | |
041bd2e0 | 12346 | else |
f16cd0d5 L |
12347 | { |
12348 | if (prefixes & PREFIX_DATA) | |
12349 | *obufp++ = 'd'; | |
12350 | else | |
12351 | *obufp++ = 's'; | |
12352 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12353 | } | |
041bd2e0 | 12354 | break; |
76f227a5 | 12355 | case 'Y': |
c0f3af97 | 12356 | if (l == 0 && len == 1) |
76f227a5 | 12357 | { |
c0f3af97 L |
12358 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
12359 | break; | |
12360 | if (rex & REX_W) | |
12361 | { | |
12362 | USED_REX (REX_W); | |
12363 | *obufp++ = 'q'; | |
12364 | } | |
12365 | break; | |
12366 | } | |
12367 | else | |
12368 | { | |
12369 | if (l != 1 || len != 2 || last[0] != 'X') | |
12370 | { | |
12371 | SAVE_LAST (*p); | |
12372 | break; | |
12373 | } | |
12374 | if (!need_vex) | |
12375 | abort (); | |
12376 | if (intel_syntax | |
12377 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
12378 | break; | |
12379 | switch (vex.length) | |
12380 | { | |
12381 | case 128: | |
12382 | *obufp++ = 'x'; | |
12383 | break; | |
12384 | case 256: | |
12385 | *obufp++ = 'y'; | |
12386 | break; | |
12387 | default: | |
12388 | abort (); | |
12389 | } | |
76f227a5 JH |
12390 | } |
12391 | break; | |
252b5132 | 12392 | case 'W': |
0bfee649 | 12393 | if (l == 0 && len == 1) |
a35ca55a | 12394 | { |
0bfee649 L |
12395 | /* operand size flag for cwtl, cbtw */ |
12396 | USED_REX (REX_W); | |
12397 | if (rex & REX_W) | |
12398 | { | |
12399 | if (intel_syntax) | |
12400 | *obufp++ = 'd'; | |
12401 | else | |
12402 | *obufp++ = 'l'; | |
12403 | } | |
12404 | else if (sizeflag & DFLAG) | |
12405 | *obufp++ = 'w'; | |
a35ca55a | 12406 | else |
0bfee649 L |
12407 | *obufp++ = 'b'; |
12408 | if (!(rex & REX_W)) | |
12409 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 12410 | } |
252b5132 | 12411 | else |
0bfee649 L |
12412 | { |
12413 | if (l != 1 || len != 2 || last[0] != 'X') | |
12414 | { | |
12415 | SAVE_LAST (*p); | |
12416 | break; | |
12417 | } | |
12418 | if (!need_vex) | |
12419 | abort (); | |
12420 | *obufp++ = vex.w ? 'd': 's'; | |
12421 | } | |
252b5132 RH |
12422 | break; |
12423 | } | |
9306ca4a | 12424 | alt = 0; |
252b5132 RH |
12425 | } |
12426 | *obufp = 0; | |
ea397f5b | 12427 | mnemonicendp = obufp; |
6439fc28 | 12428 | return 0; |
252b5132 RH |
12429 | } |
12430 | ||
12431 | static void | |
26ca5450 | 12432 | oappend (const char *s) |
252b5132 | 12433 | { |
ea397f5b | 12434 | obufp = stpcpy (obufp, s); |
252b5132 RH |
12435 | } |
12436 | ||
12437 | static void | |
26ca5450 | 12438 | append_seg (void) |
252b5132 RH |
12439 | { |
12440 | if (prefixes & PREFIX_CS) | |
7d421014 | 12441 | { |
7d421014 | 12442 | used_prefixes |= PREFIX_CS; |
d708bcba | 12443 | oappend ("%cs:" + intel_syntax); |
7d421014 | 12444 | } |
252b5132 | 12445 | if (prefixes & PREFIX_DS) |
7d421014 | 12446 | { |
7d421014 | 12447 | used_prefixes |= PREFIX_DS; |
d708bcba | 12448 | oappend ("%ds:" + intel_syntax); |
7d421014 | 12449 | } |
252b5132 | 12450 | if (prefixes & PREFIX_SS) |
7d421014 | 12451 | { |
7d421014 | 12452 | used_prefixes |= PREFIX_SS; |
d708bcba | 12453 | oappend ("%ss:" + intel_syntax); |
7d421014 | 12454 | } |
252b5132 | 12455 | if (prefixes & PREFIX_ES) |
7d421014 | 12456 | { |
7d421014 | 12457 | used_prefixes |= PREFIX_ES; |
d708bcba | 12458 | oappend ("%es:" + intel_syntax); |
7d421014 | 12459 | } |
252b5132 | 12460 | if (prefixes & PREFIX_FS) |
7d421014 | 12461 | { |
7d421014 | 12462 | used_prefixes |= PREFIX_FS; |
d708bcba | 12463 | oappend ("%fs:" + intel_syntax); |
7d421014 | 12464 | } |
252b5132 | 12465 | if (prefixes & PREFIX_GS) |
7d421014 | 12466 | { |
7d421014 | 12467 | used_prefixes |= PREFIX_GS; |
d708bcba | 12468 | oappend ("%gs:" + intel_syntax); |
7d421014 | 12469 | } |
252b5132 RH |
12470 | } |
12471 | ||
12472 | static void | |
26ca5450 | 12473 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
12474 | { |
12475 | if (!intel_syntax) | |
12476 | oappend ("*"); | |
12477 | OP_E (bytemode, sizeflag); | |
12478 | } | |
12479 | ||
52b15da3 | 12480 | static void |
26ca5450 | 12481 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 12482 | { |
cb712a9e | 12483 | if (address_mode == mode_64bit) |
52b15da3 JH |
12484 | { |
12485 | if (hex) | |
12486 | { | |
12487 | char tmp[30]; | |
12488 | int i; | |
12489 | buf[0] = '0'; | |
12490 | buf[1] = 'x'; | |
12491 | sprintf_vma (tmp, disp); | |
6608db57 | 12492 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
12493 | strcpy (buf + 2, tmp + i); |
12494 | } | |
12495 | else | |
12496 | { | |
12497 | bfd_signed_vma v = disp; | |
12498 | char tmp[30]; | |
12499 | int i; | |
12500 | if (v < 0) | |
12501 | { | |
12502 | *(buf++) = '-'; | |
12503 | v = -disp; | |
6608db57 | 12504 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
12505 | if (v < 0) |
12506 | { | |
12507 | strcpy (buf, "9223372036854775808"); | |
12508 | return; | |
12509 | } | |
12510 | } | |
12511 | if (!v) | |
12512 | { | |
12513 | strcpy (buf, "0"); | |
12514 | return; | |
12515 | } | |
12516 | ||
12517 | i = 0; | |
12518 | tmp[29] = 0; | |
12519 | while (v) | |
12520 | { | |
6608db57 | 12521 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
12522 | v /= 10; |
12523 | i++; | |
12524 | } | |
12525 | strcpy (buf, tmp + 29 - i); | |
12526 | } | |
12527 | } | |
12528 | else | |
12529 | { | |
12530 | if (hex) | |
12531 | sprintf (buf, "0x%x", (unsigned int) disp); | |
12532 | else | |
12533 | sprintf (buf, "%d", (int) disp); | |
12534 | } | |
12535 | } | |
12536 | ||
5d669648 L |
12537 | /* Put DISP in BUF as signed hex number. */ |
12538 | ||
12539 | static void | |
12540 | print_displacement (char *buf, bfd_vma disp) | |
12541 | { | |
12542 | bfd_signed_vma val = disp; | |
12543 | char tmp[30]; | |
12544 | int i, j = 0; | |
12545 | ||
12546 | if (val < 0) | |
12547 | { | |
12548 | buf[j++] = '-'; | |
12549 | val = -disp; | |
12550 | ||
12551 | /* Check for possible overflow. */ | |
12552 | if (val < 0) | |
12553 | { | |
12554 | switch (address_mode) | |
12555 | { | |
12556 | case mode_64bit: | |
12557 | strcpy (buf + j, "0x8000000000000000"); | |
12558 | break; | |
12559 | case mode_32bit: | |
12560 | strcpy (buf + j, "0x80000000"); | |
12561 | break; | |
12562 | case mode_16bit: | |
12563 | strcpy (buf + j, "0x8000"); | |
12564 | break; | |
12565 | } | |
12566 | return; | |
12567 | } | |
12568 | } | |
12569 | ||
12570 | buf[j++] = '0'; | |
12571 | buf[j++] = 'x'; | |
12572 | ||
0af1713e | 12573 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
12574 | for (i = 0; tmp[i] == '0'; i++) |
12575 | continue; | |
12576 | if (tmp[i] == '\0') | |
12577 | i--; | |
12578 | strcpy (buf + j, tmp + i); | |
12579 | } | |
12580 | ||
3f31e633 JB |
12581 | static void |
12582 | intel_operand_size (int bytemode, int sizeflag) | |
12583 | { | |
12584 | switch (bytemode) | |
12585 | { | |
12586 | case b_mode: | |
b6169b20 | 12587 | case b_swap_mode: |
42903f7f | 12588 | case dqb_mode: |
3f31e633 JB |
12589 | oappend ("BYTE PTR "); |
12590 | break; | |
12591 | case w_mode: | |
12592 | case dqw_mode: | |
12593 | oappend ("WORD PTR "); | |
12594 | break; | |
1a114b12 | 12595 | case stack_v_mode: |
cb712a9e | 12596 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
3f31e633 JB |
12597 | { |
12598 | oappend ("QWORD PTR "); | |
3f31e633 JB |
12599 | break; |
12600 | } | |
12601 | /* FALLTHRU */ | |
12602 | case v_mode: | |
b6169b20 | 12603 | case v_swap_mode: |
3f31e633 | 12604 | case dq_mode: |
161a04f6 L |
12605 | USED_REX (REX_W); |
12606 | if (rex & REX_W) | |
3f31e633 | 12607 | oappend ("QWORD PTR "); |
3f31e633 | 12608 | else |
f16cd0d5 L |
12609 | { |
12610 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
12611 | oappend ("DWORD PTR "); | |
12612 | else | |
12613 | oappend ("WORD PTR "); | |
12614 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12615 | } | |
3f31e633 | 12616 | break; |
52fd6d94 | 12617 | case z_mode: |
161a04f6 | 12618 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12619 | *obufp++ = 'D'; |
12620 | oappend ("WORD PTR "); | |
161a04f6 | 12621 | if (!(rex & REX_W)) |
52fd6d94 JB |
12622 | used_prefixes |= (prefixes & PREFIX_DATA); |
12623 | break; | |
34b772a6 JB |
12624 | case a_mode: |
12625 | if (sizeflag & DFLAG) | |
12626 | oappend ("QWORD PTR "); | |
12627 | else | |
12628 | oappend ("DWORD PTR "); | |
12629 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12630 | break; | |
3f31e633 | 12631 | case d_mode: |
fa99fab2 | 12632 | case d_swap_mode: |
42903f7f | 12633 | case dqd_mode: |
3f31e633 JB |
12634 | oappend ("DWORD PTR "); |
12635 | break; | |
12636 | case q_mode: | |
b6169b20 | 12637 | case q_swap_mode: |
3f31e633 JB |
12638 | oappend ("QWORD PTR "); |
12639 | break; | |
12640 | case m_mode: | |
cb712a9e | 12641 | if (address_mode == mode_64bit) |
3f31e633 JB |
12642 | oappend ("QWORD PTR "); |
12643 | else | |
12644 | oappend ("DWORD PTR "); | |
12645 | break; | |
12646 | case f_mode: | |
12647 | if (sizeflag & DFLAG) | |
12648 | oappend ("FWORD PTR "); | |
12649 | else | |
12650 | oappend ("DWORD PTR "); | |
12651 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12652 | break; | |
12653 | case t_mode: | |
12654 | oappend ("TBYTE PTR "); | |
12655 | break; | |
12656 | case x_mode: | |
b6169b20 | 12657 | case x_swap_mode: |
c0f3af97 L |
12658 | if (need_vex) |
12659 | { | |
12660 | switch (vex.length) | |
12661 | { | |
12662 | case 128: | |
12663 | oappend ("XMMWORD PTR "); | |
12664 | break; | |
12665 | case 256: | |
12666 | oappend ("YMMWORD PTR "); | |
12667 | break; | |
12668 | default: | |
12669 | abort (); | |
12670 | } | |
12671 | } | |
12672 | else | |
12673 | oappend ("XMMWORD PTR "); | |
12674 | break; | |
12675 | case xmm_mode: | |
3f31e633 JB |
12676 | oappend ("XMMWORD PTR "); |
12677 | break; | |
c0f3af97 L |
12678 | case xmmq_mode: |
12679 | if (!need_vex) | |
12680 | abort (); | |
12681 | ||
12682 | switch (vex.length) | |
12683 | { | |
12684 | case 128: | |
12685 | oappend ("QWORD PTR "); | |
12686 | break; | |
12687 | case 256: | |
12688 | oappend ("XMMWORD PTR "); | |
12689 | break; | |
12690 | default: | |
12691 | abort (); | |
12692 | } | |
12693 | break; | |
12694 | case ymmq_mode: | |
12695 | if (!need_vex) | |
12696 | abort (); | |
12697 | ||
12698 | switch (vex.length) | |
12699 | { | |
12700 | case 128: | |
12701 | oappend ("QWORD PTR "); | |
12702 | break; | |
12703 | case 256: | |
12704 | oappend ("YMMWORD PTR "); | |
12705 | break; | |
12706 | default: | |
12707 | abort (); | |
12708 | } | |
12709 | break; | |
fb9c77c7 L |
12710 | case o_mode: |
12711 | oappend ("OWORD PTR "); | |
12712 | break; | |
0bfee649 L |
12713 | case vex_w_dq_mode: |
12714 | if (!need_vex) | |
12715 | abort (); | |
12716 | ||
12717 | if (vex.w) | |
12718 | oappend ("QWORD PTR "); | |
12719 | else | |
12720 | oappend ("DWORD PTR "); | |
12721 | break; | |
3f31e633 JB |
12722 | default: |
12723 | break; | |
12724 | } | |
12725 | } | |
12726 | ||
252b5132 | 12727 | static void |
c0f3af97 | 12728 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 12729 | { |
c0f3af97 L |
12730 | int reg = modrm.rm; |
12731 | const char **names; | |
252b5132 | 12732 | |
c0f3af97 L |
12733 | USED_REX (REX_B); |
12734 | if ((rex & REX_B)) | |
12735 | reg += 8; | |
252b5132 | 12736 | |
b6169b20 L |
12737 | if ((sizeflag & SUFFIX_ALWAYS) |
12738 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) | |
12739 | swap_operand (); | |
12740 | ||
c0f3af97 | 12741 | switch (bytemode) |
252b5132 | 12742 | { |
c0f3af97 | 12743 | case b_mode: |
b6169b20 | 12744 | case b_swap_mode: |
c0f3af97 L |
12745 | USED_REX (0); |
12746 | if (rex) | |
12747 | names = names8rex; | |
12748 | else | |
12749 | names = names8; | |
12750 | break; | |
12751 | case w_mode: | |
12752 | names = names16; | |
12753 | break; | |
12754 | case d_mode: | |
12755 | names = names32; | |
12756 | break; | |
12757 | case q_mode: | |
12758 | names = names64; | |
12759 | break; | |
12760 | case m_mode: | |
12761 | names = address_mode == mode_64bit ? names64 : names32; | |
12762 | break; | |
12763 | case stack_v_mode: | |
12764 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) | |
252b5132 | 12765 | { |
c0f3af97 | 12766 | names = names64; |
252b5132 | 12767 | break; |
252b5132 | 12768 | } |
c0f3af97 L |
12769 | bytemode = v_mode; |
12770 | /* FALLTHRU */ | |
12771 | case v_mode: | |
b6169b20 | 12772 | case v_swap_mode: |
c0f3af97 L |
12773 | case dq_mode: |
12774 | case dqb_mode: | |
12775 | case dqd_mode: | |
12776 | case dqw_mode: | |
12777 | USED_REX (REX_W); | |
12778 | if (rex & REX_W) | |
12779 | names = names64; | |
c0f3af97 | 12780 | else |
f16cd0d5 L |
12781 | { |
12782 | if ((sizeflag & DFLAG) | |
12783 | || (bytemode != v_mode | |
12784 | && bytemode != v_swap_mode)) | |
12785 | names = names32; | |
12786 | else | |
12787 | names = names16; | |
12788 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12789 | } | |
c0f3af97 L |
12790 | break; |
12791 | case 0: | |
12792 | return; | |
12793 | default: | |
12794 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
12795 | return; |
12796 | } | |
c0f3af97 L |
12797 | oappend (names[reg]); |
12798 | } | |
12799 | ||
12800 | static void | |
c1e679ec | 12801 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
12802 | { |
12803 | bfd_vma disp = 0; | |
12804 | int add = (rex & REX_B) ? 8 : 0; | |
12805 | int riprel = 0; | |
252b5132 | 12806 | |
c0f3af97 | 12807 | USED_REX (REX_B); |
3f31e633 JB |
12808 | if (intel_syntax) |
12809 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
12810 | append_seg (); |
12811 | ||
5d669648 | 12812 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 12813 | { |
5d669648 L |
12814 | /* 32/64 bit address mode */ |
12815 | int havedisp; | |
252b5132 RH |
12816 | int havesib; |
12817 | int havebase; | |
0f7da397 | 12818 | int haveindex; |
20afcfb7 | 12819 | int needindex; |
82c18208 | 12820 | int base, rbase; |
91d6fa6a | 12821 | int vindex = 0; |
252b5132 RH |
12822 | int scale = 0; |
12823 | ||
12824 | havesib = 0; | |
12825 | havebase = 1; | |
0f7da397 | 12826 | haveindex = 0; |
7967e09e | 12827 | base = modrm.rm; |
252b5132 RH |
12828 | |
12829 | if (base == 4) | |
12830 | { | |
12831 | havesib = 1; | |
12832 | FETCH_DATA (the_info, codep + 1); | |
91d6fa6a | 12833 | vindex = (*codep >> 3) & 7; |
db51cc60 | 12834 | scale = (*codep >> 6) & 3; |
252b5132 | 12835 | base = *codep & 7; |
161a04f6 L |
12836 | USED_REX (REX_X); |
12837 | if (rex & REX_X) | |
91d6fa6a NC |
12838 | vindex += 8; |
12839 | haveindex = vindex != 4; | |
252b5132 RH |
12840 | codep++; |
12841 | } | |
82c18208 | 12842 | rbase = base + add; |
252b5132 | 12843 | |
7967e09e | 12844 | switch (modrm.mod) |
252b5132 RH |
12845 | { |
12846 | case 0: | |
82c18208 | 12847 | if (base == 5) |
252b5132 RH |
12848 | { |
12849 | havebase = 0; | |
cb712a9e | 12850 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
12851 | riprel = 1; |
12852 | disp = get32s (); | |
252b5132 RH |
12853 | } |
12854 | break; | |
12855 | case 1: | |
12856 | FETCH_DATA (the_info, codep + 1); | |
12857 | disp = *codep++; | |
12858 | if ((disp & 0x80) != 0) | |
12859 | disp -= 0x100; | |
12860 | break; | |
12861 | case 2: | |
52b15da3 | 12862 | disp = get32s (); |
252b5132 RH |
12863 | break; |
12864 | } | |
12865 | ||
20afcfb7 L |
12866 | /* In 32bit mode, we need index register to tell [offset] from |
12867 | [eiz*1 + offset]. */ | |
12868 | needindex = (havesib | |
12869 | && !havebase | |
12870 | && !haveindex | |
12871 | && address_mode == mode_32bit); | |
12872 | havedisp = (havebase | |
12873 | || needindex | |
12874 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 12875 | |
252b5132 | 12876 | if (!intel_syntax) |
82c18208 | 12877 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 12878 | { |
5d669648 L |
12879 | if (havedisp || riprel) |
12880 | print_displacement (scratchbuf, disp); | |
12881 | else | |
12882 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 12883 | oappend (scratchbuf); |
52b15da3 JH |
12884 | if (riprel) |
12885 | { | |
12886 | set_op (disp, 1); | |
87767711 | 12887 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 12888 | } |
db6eb5be | 12889 | } |
2da11e11 | 12890 | |
87767711 JB |
12891 | if (havebase || haveindex || riprel) |
12892 | used_prefixes |= PREFIX_ADDR; | |
12893 | ||
5d669648 | 12894 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 12895 | { |
252b5132 | 12896 | *obufp++ = open_char; |
52b15da3 | 12897 | if (intel_syntax && riprel) |
185b1163 L |
12898 | { |
12899 | set_op (disp, 1); | |
87767711 | 12900 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 12901 | } |
db6eb5be | 12902 | *obufp = '\0'; |
252b5132 | 12903 | if (havebase) |
cb712a9e | 12904 | oappend (address_mode == mode_64bit && (sizeflag & AFLAG) |
82c18208 | 12905 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
12906 | if (havesib) |
12907 | { | |
db51cc60 L |
12908 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
12909 | print index to tell base + index from base. */ | |
12910 | if (scale != 0 | |
20afcfb7 | 12911 | || needindex |
db51cc60 L |
12912 | || haveindex |
12913 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 12914 | { |
9306ca4a | 12915 | if (!intel_syntax || havebase) |
db6eb5be | 12916 | { |
9306ca4a JB |
12917 | *obufp++ = separator_char; |
12918 | *obufp = '\0'; | |
db6eb5be | 12919 | } |
db51cc60 L |
12920 | if (haveindex) |
12921 | oappend (address_mode == mode_64bit | |
12922 | && (sizeflag & AFLAG) | |
91d6fa6a | 12923 | ? names64[vindex] : names32[vindex]); |
db51cc60 L |
12924 | else |
12925 | oappend (address_mode == mode_64bit | |
12926 | && (sizeflag & AFLAG) | |
12927 | ? index64 : index32); | |
12928 | ||
db6eb5be AM |
12929 | *obufp++ = scale_char; |
12930 | *obufp = '\0'; | |
12931 | sprintf (scratchbuf, "%d", 1 << scale); | |
12932 | oappend (scratchbuf); | |
12933 | } | |
252b5132 | 12934 | } |
185b1163 | 12935 | if (intel_syntax |
82c18208 | 12936 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 12937 | { |
db51cc60 | 12938 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
12939 | { |
12940 | *obufp++ = '+'; | |
12941 | *obufp = '\0'; | |
12942 | } | |
05203043 | 12943 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
12944 | { |
12945 | *obufp++ = '-'; | |
12946 | *obufp = '\0'; | |
12947 | disp = - (bfd_signed_vma) disp; | |
12948 | } | |
12949 | ||
db51cc60 L |
12950 | if (havedisp) |
12951 | print_displacement (scratchbuf, disp); | |
12952 | else | |
12953 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
12954 | oappend (scratchbuf); |
12955 | } | |
252b5132 RH |
12956 | |
12957 | *obufp++ = close_char; | |
db6eb5be | 12958 | *obufp = '\0'; |
252b5132 RH |
12959 | } |
12960 | else if (intel_syntax) | |
db6eb5be | 12961 | { |
82c18208 | 12962 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 12963 | { |
252b5132 RH |
12964 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
12965 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
12966 | ; | |
12967 | else | |
12968 | { | |
d708bcba | 12969 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
12970 | oappend (":"); |
12971 | } | |
52b15da3 | 12972 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
12973 | oappend (scratchbuf); |
12974 | } | |
12975 | } | |
252b5132 RH |
12976 | } |
12977 | else | |
f16cd0d5 L |
12978 | { |
12979 | /* 16 bit address mode */ | |
12980 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 12981 | switch (modrm.mod) |
252b5132 RH |
12982 | { |
12983 | case 0: | |
7967e09e | 12984 | if (modrm.rm == 6) |
252b5132 RH |
12985 | { |
12986 | disp = get16 (); | |
12987 | if ((disp & 0x8000) != 0) | |
12988 | disp -= 0x10000; | |
12989 | } | |
12990 | break; | |
12991 | case 1: | |
12992 | FETCH_DATA (the_info, codep + 1); | |
12993 | disp = *codep++; | |
12994 | if ((disp & 0x80) != 0) | |
12995 | disp -= 0x100; | |
12996 | break; | |
12997 | case 2: | |
12998 | disp = get16 (); | |
12999 | if ((disp & 0x8000) != 0) | |
13000 | disp -= 0x10000; | |
13001 | break; | |
13002 | } | |
13003 | ||
13004 | if (!intel_syntax) | |
7967e09e | 13005 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 13006 | { |
5d669648 | 13007 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
13008 | oappend (scratchbuf); |
13009 | } | |
252b5132 | 13010 | |
7967e09e | 13011 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
13012 | { |
13013 | *obufp++ = open_char; | |
db6eb5be | 13014 | *obufp = '\0'; |
7967e09e | 13015 | oappend (index16[modrm.rm]); |
5d669648 L |
13016 | if (intel_syntax |
13017 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 13018 | { |
5d669648 | 13019 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
13020 | { |
13021 | *obufp++ = '+'; | |
13022 | *obufp = '\0'; | |
13023 | } | |
7967e09e | 13024 | else if (modrm.mod != 1) |
3d456fa1 JB |
13025 | { |
13026 | *obufp++ = '-'; | |
13027 | *obufp = '\0'; | |
13028 | disp = - (bfd_signed_vma) disp; | |
13029 | } | |
13030 | ||
5d669648 | 13031 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
13032 | oappend (scratchbuf); |
13033 | } | |
13034 | ||
db6eb5be AM |
13035 | *obufp++ = close_char; |
13036 | *obufp = '\0'; | |
252b5132 | 13037 | } |
3d456fa1 JB |
13038 | else if (intel_syntax) |
13039 | { | |
13040 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
13041 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
13042 | ; | |
13043 | else | |
13044 | { | |
13045 | oappend (names_seg[ds_reg - es_reg]); | |
13046 | oappend (":"); | |
13047 | } | |
13048 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
13049 | oappend (scratchbuf); | |
13050 | } | |
252b5132 RH |
13051 | } |
13052 | } | |
13053 | ||
c0f3af97 | 13054 | static void |
8b3f93e7 | 13055 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
13056 | { |
13057 | /* Skip mod/rm byte. */ | |
13058 | MODRM_CHECK; | |
13059 | codep++; | |
13060 | ||
13061 | if (modrm.mod == 3) | |
13062 | OP_E_register (bytemode, sizeflag); | |
13063 | else | |
c1e679ec | 13064 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
13065 | } |
13066 | ||
252b5132 | 13067 | static void |
26ca5450 | 13068 | OP_G (int bytemode, int sizeflag) |
252b5132 | 13069 | { |
52b15da3 | 13070 | int add = 0; |
161a04f6 L |
13071 | USED_REX (REX_R); |
13072 | if (rex & REX_R) | |
52b15da3 | 13073 | add += 8; |
252b5132 RH |
13074 | switch (bytemode) |
13075 | { | |
13076 | case b_mode: | |
52b15da3 JH |
13077 | USED_REX (0); |
13078 | if (rex) | |
7967e09e | 13079 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 13080 | else |
7967e09e | 13081 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
13082 | break; |
13083 | case w_mode: | |
7967e09e | 13084 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
13085 | break; |
13086 | case d_mode: | |
7967e09e | 13087 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
13088 | break; |
13089 | case q_mode: | |
7967e09e | 13090 | oappend (names64[modrm.reg + add]); |
252b5132 RH |
13091 | break; |
13092 | case v_mode: | |
9306ca4a | 13093 | case dq_mode: |
42903f7f L |
13094 | case dqb_mode: |
13095 | case dqd_mode: | |
9306ca4a | 13096 | case dqw_mode: |
161a04f6 L |
13097 | USED_REX (REX_W); |
13098 | if (rex & REX_W) | |
7967e09e | 13099 | oappend (names64[modrm.reg + add]); |
252b5132 | 13100 | else |
f16cd0d5 L |
13101 | { |
13102 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
13103 | oappend (names32[modrm.reg + add]); | |
13104 | else | |
13105 | oappend (names16[modrm.reg + add]); | |
13106 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13107 | } | |
252b5132 | 13108 | break; |
90700ea2 | 13109 | case m_mode: |
cb712a9e | 13110 | if (address_mode == mode_64bit) |
7967e09e | 13111 | oappend (names64[modrm.reg + add]); |
90700ea2 | 13112 | else |
7967e09e | 13113 | oappend (names32[modrm.reg + add]); |
90700ea2 | 13114 | break; |
252b5132 RH |
13115 | default: |
13116 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13117 | break; | |
13118 | } | |
13119 | } | |
13120 | ||
52b15da3 | 13121 | static bfd_vma |
26ca5450 | 13122 | get64 (void) |
52b15da3 | 13123 | { |
5dd0794d | 13124 | bfd_vma x; |
52b15da3 | 13125 | #ifdef BFD64 |
5dd0794d AM |
13126 | unsigned int a; |
13127 | unsigned int b; | |
13128 | ||
52b15da3 JH |
13129 | FETCH_DATA (the_info, codep + 8); |
13130 | a = *codep++ & 0xff; | |
13131 | a |= (*codep++ & 0xff) << 8; | |
13132 | a |= (*codep++ & 0xff) << 16; | |
13133 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 13134 | b = *codep++ & 0xff; |
52b15da3 JH |
13135 | b |= (*codep++ & 0xff) << 8; |
13136 | b |= (*codep++ & 0xff) << 16; | |
13137 | b |= (*codep++ & 0xff) << 24; | |
13138 | x = a + ((bfd_vma) b << 32); | |
13139 | #else | |
6608db57 | 13140 | abort (); |
5dd0794d | 13141 | x = 0; |
52b15da3 JH |
13142 | #endif |
13143 | return x; | |
13144 | } | |
13145 | ||
13146 | static bfd_signed_vma | |
26ca5450 | 13147 | get32 (void) |
252b5132 | 13148 | { |
52b15da3 | 13149 | bfd_signed_vma x = 0; |
252b5132 RH |
13150 | |
13151 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
13152 | x = *codep++ & (bfd_signed_vma) 0xff; |
13153 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
13154 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
13155 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
13156 | return x; | |
13157 | } | |
13158 | ||
13159 | static bfd_signed_vma | |
26ca5450 | 13160 | get32s (void) |
52b15da3 JH |
13161 | { |
13162 | bfd_signed_vma x = 0; | |
13163 | ||
13164 | FETCH_DATA (the_info, codep + 4); | |
13165 | x = *codep++ & (bfd_signed_vma) 0xff; | |
13166 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
13167 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
13168 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
13169 | ||
13170 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
13171 | ||
252b5132 RH |
13172 | return x; |
13173 | } | |
13174 | ||
13175 | static int | |
26ca5450 | 13176 | get16 (void) |
252b5132 RH |
13177 | { |
13178 | int x = 0; | |
13179 | ||
13180 | FETCH_DATA (the_info, codep + 2); | |
13181 | x = *codep++ & 0xff; | |
13182 | x |= (*codep++ & 0xff) << 8; | |
13183 | return x; | |
13184 | } | |
13185 | ||
13186 | static void | |
26ca5450 | 13187 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
13188 | { |
13189 | op_index[op_ad] = op_ad; | |
cb712a9e | 13190 | if (address_mode == mode_64bit) |
7081ff04 AJ |
13191 | { |
13192 | op_address[op_ad] = op; | |
13193 | op_riprel[op_ad] = riprel; | |
13194 | } | |
13195 | else | |
13196 | { | |
13197 | /* Mask to get a 32-bit address. */ | |
13198 | op_address[op_ad] = op & 0xffffffff; | |
13199 | op_riprel[op_ad] = riprel & 0xffffffff; | |
13200 | } | |
252b5132 RH |
13201 | } |
13202 | ||
13203 | static void | |
26ca5450 | 13204 | OP_REG (int code, int sizeflag) |
252b5132 | 13205 | { |
2da11e11 | 13206 | const char *s; |
9b60702d | 13207 | int add; |
161a04f6 L |
13208 | USED_REX (REX_B); |
13209 | if (rex & REX_B) | |
52b15da3 | 13210 | add = 8; |
9b60702d L |
13211 | else |
13212 | add = 0; | |
52b15da3 JH |
13213 | |
13214 | switch (code) | |
13215 | { | |
52b15da3 JH |
13216 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
13217 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
13218 | s = names16[code - ax_reg + add]; | |
13219 | break; | |
13220 | case es_reg: case ss_reg: case cs_reg: | |
13221 | case ds_reg: case fs_reg: case gs_reg: | |
13222 | s = names_seg[code - es_reg + add]; | |
13223 | break; | |
13224 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
13225 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
13226 | USED_REX (0); | |
13227 | if (rex) | |
13228 | s = names8rex[code - al_reg + add]; | |
13229 | else | |
13230 | s = names8[code - al_reg]; | |
13231 | break; | |
6439fc28 AM |
13232 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
13233 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
cb712a9e | 13234 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
13235 | { |
13236 | s = names64[code - rAX_reg + add]; | |
13237 | break; | |
13238 | } | |
13239 | code += eAX_reg - rAX_reg; | |
6608db57 | 13240 | /* Fall through. */ |
52b15da3 JH |
13241 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
13242 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
13243 | USED_REX (REX_W); |
13244 | if (rex & REX_W) | |
52b15da3 | 13245 | s = names64[code - eAX_reg + add]; |
52b15da3 | 13246 | else |
f16cd0d5 L |
13247 | { |
13248 | if (sizeflag & DFLAG) | |
13249 | s = names32[code - eAX_reg + add]; | |
13250 | else | |
13251 | s = names16[code - eAX_reg + add]; | |
13252 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13253 | } | |
52b15da3 | 13254 | break; |
52b15da3 JH |
13255 | default: |
13256 | s = INTERNAL_DISASSEMBLER_ERROR; | |
13257 | break; | |
13258 | } | |
13259 | oappend (s); | |
13260 | } | |
13261 | ||
13262 | static void | |
26ca5450 | 13263 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
13264 | { |
13265 | const char *s; | |
252b5132 RH |
13266 | |
13267 | switch (code) | |
13268 | { | |
13269 | case indir_dx_reg: | |
d708bcba | 13270 | if (intel_syntax) |
52fd6d94 | 13271 | s = "dx"; |
d708bcba | 13272 | else |
db6eb5be | 13273 | s = "(%dx)"; |
252b5132 RH |
13274 | break; |
13275 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
13276 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
13277 | s = names16[code - ax_reg]; | |
13278 | break; | |
13279 | case es_reg: case ss_reg: case cs_reg: | |
13280 | case ds_reg: case fs_reg: case gs_reg: | |
13281 | s = names_seg[code - es_reg]; | |
13282 | break; | |
13283 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
13284 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
13285 | USED_REX (0); |
13286 | if (rex) | |
13287 | s = names8rex[code - al_reg]; | |
13288 | else | |
13289 | s = names8[code - al_reg]; | |
252b5132 RH |
13290 | break; |
13291 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
13292 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
13293 | USED_REX (REX_W); |
13294 | if (rex & REX_W) | |
52b15da3 | 13295 | s = names64[code - eAX_reg]; |
252b5132 | 13296 | else |
f16cd0d5 L |
13297 | { |
13298 | if (sizeflag & DFLAG) | |
13299 | s = names32[code - eAX_reg]; | |
13300 | else | |
13301 | s = names16[code - eAX_reg]; | |
13302 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13303 | } | |
252b5132 | 13304 | break; |
52fd6d94 | 13305 | case z_mode_ax_reg: |
161a04f6 | 13306 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13307 | s = *names32; |
13308 | else | |
13309 | s = *names16; | |
161a04f6 | 13310 | if (!(rex & REX_W)) |
52fd6d94 JB |
13311 | used_prefixes |= (prefixes & PREFIX_DATA); |
13312 | break; | |
252b5132 RH |
13313 | default: |
13314 | s = INTERNAL_DISASSEMBLER_ERROR; | |
13315 | break; | |
13316 | } | |
13317 | oappend (s); | |
13318 | } | |
13319 | ||
13320 | static void | |
26ca5450 | 13321 | OP_I (int bytemode, int sizeflag) |
252b5132 | 13322 | { |
52b15da3 JH |
13323 | bfd_signed_vma op; |
13324 | bfd_signed_vma mask = -1; | |
252b5132 RH |
13325 | |
13326 | switch (bytemode) | |
13327 | { | |
13328 | case b_mode: | |
13329 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
13330 | op = *codep++; |
13331 | mask = 0xff; | |
13332 | break; | |
13333 | case q_mode: | |
cb712a9e | 13334 | if (address_mode == mode_64bit) |
6439fc28 AM |
13335 | { |
13336 | op = get32s (); | |
13337 | break; | |
13338 | } | |
6608db57 | 13339 | /* Fall through. */ |
252b5132 | 13340 | case v_mode: |
161a04f6 L |
13341 | USED_REX (REX_W); |
13342 | if (rex & REX_W) | |
52b15da3 | 13343 | op = get32s (); |
252b5132 | 13344 | else |
52b15da3 | 13345 | { |
f16cd0d5 L |
13346 | if (sizeflag & DFLAG) |
13347 | { | |
13348 | op = get32 (); | |
13349 | mask = 0xffffffff; | |
13350 | } | |
13351 | else | |
13352 | { | |
13353 | op = get16 (); | |
13354 | mask = 0xfffff; | |
13355 | } | |
13356 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 13357 | } |
252b5132 RH |
13358 | break; |
13359 | case w_mode: | |
52b15da3 | 13360 | mask = 0xfffff; |
252b5132 RH |
13361 | op = get16 (); |
13362 | break; | |
9306ca4a JB |
13363 | case const_1_mode: |
13364 | if (intel_syntax) | |
13365 | oappend ("1"); | |
13366 | return; | |
252b5132 RH |
13367 | default: |
13368 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13369 | return; | |
13370 | } | |
13371 | ||
52b15da3 JH |
13372 | op &= mask; |
13373 | scratchbuf[0] = '$'; | |
d708bcba AM |
13374 | print_operand_value (scratchbuf + 1, 1, op); |
13375 | oappend (scratchbuf + intel_syntax); | |
52b15da3 JH |
13376 | scratchbuf[0] = '\0'; |
13377 | } | |
13378 | ||
13379 | static void | |
26ca5450 | 13380 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
13381 | { |
13382 | bfd_signed_vma op; | |
13383 | bfd_signed_vma mask = -1; | |
13384 | ||
cb712a9e | 13385 | if (address_mode != mode_64bit) |
6439fc28 AM |
13386 | { |
13387 | OP_I (bytemode, sizeflag); | |
13388 | return; | |
13389 | } | |
13390 | ||
52b15da3 JH |
13391 | switch (bytemode) |
13392 | { | |
13393 | case b_mode: | |
13394 | FETCH_DATA (the_info, codep + 1); | |
13395 | op = *codep++; | |
13396 | mask = 0xff; | |
13397 | break; | |
13398 | case v_mode: | |
161a04f6 L |
13399 | USED_REX (REX_W); |
13400 | if (rex & REX_W) | |
52b15da3 | 13401 | op = get64 (); |
52b15da3 JH |
13402 | else |
13403 | { | |
f16cd0d5 L |
13404 | if (sizeflag & DFLAG) |
13405 | { | |
13406 | op = get32 (); | |
13407 | mask = 0xffffffff; | |
13408 | } | |
13409 | else | |
13410 | { | |
13411 | op = get16 (); | |
13412 | mask = 0xfffff; | |
13413 | } | |
13414 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 13415 | } |
52b15da3 JH |
13416 | break; |
13417 | case w_mode: | |
13418 | mask = 0xfffff; | |
13419 | op = get16 (); | |
13420 | break; | |
13421 | default: | |
13422 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13423 | return; | |
13424 | } | |
13425 | ||
13426 | op &= mask; | |
13427 | scratchbuf[0] = '$'; | |
d708bcba AM |
13428 | print_operand_value (scratchbuf + 1, 1, op); |
13429 | oappend (scratchbuf + intel_syntax); | |
252b5132 RH |
13430 | scratchbuf[0] = '\0'; |
13431 | } | |
13432 | ||
13433 | static void | |
26ca5450 | 13434 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 13435 | { |
52b15da3 JH |
13436 | bfd_signed_vma op; |
13437 | bfd_signed_vma mask = -1; | |
252b5132 RH |
13438 | |
13439 | switch (bytemode) | |
13440 | { | |
13441 | case b_mode: | |
13442 | FETCH_DATA (the_info, codep + 1); | |
13443 | op = *codep++; | |
13444 | if ((op & 0x80) != 0) | |
13445 | op -= 0x100; | |
52b15da3 | 13446 | mask = 0xffffffff; |
252b5132 RH |
13447 | break; |
13448 | case v_mode: | |
161a04f6 L |
13449 | USED_REX (REX_W); |
13450 | if (rex & REX_W) | |
52b15da3 | 13451 | op = get32s (); |
252b5132 RH |
13452 | else |
13453 | { | |
f16cd0d5 L |
13454 | if (sizeflag & DFLAG) |
13455 | { | |
13456 | op = get32s (); | |
13457 | mask = 0xffffffff; | |
13458 | } | |
13459 | else | |
13460 | { | |
13461 | mask = 0xffffffff; | |
13462 | op = get16 (); | |
13463 | if ((op & 0x8000) != 0) | |
13464 | op -= 0x10000; | |
13465 | } | |
13466 | used_prefixes |= (prefixes & PREFIX_DATA); | |
252b5132 RH |
13467 | } |
13468 | break; | |
13469 | case w_mode: | |
13470 | op = get16 (); | |
52b15da3 | 13471 | mask = 0xffffffff; |
252b5132 RH |
13472 | if ((op & 0x8000) != 0) |
13473 | op -= 0x10000; | |
13474 | break; | |
13475 | default: | |
13476 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13477 | return; | |
13478 | } | |
52b15da3 JH |
13479 | |
13480 | scratchbuf[0] = '$'; | |
13481 | print_operand_value (scratchbuf + 1, 1, op); | |
d708bcba | 13482 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
13483 | } |
13484 | ||
13485 | static void | |
26ca5450 | 13486 | OP_J (int bytemode, int sizeflag) |
252b5132 | 13487 | { |
52b15da3 | 13488 | bfd_vma disp; |
7081ff04 | 13489 | bfd_vma mask = -1; |
65ca155d | 13490 | bfd_vma segment = 0; |
252b5132 RH |
13491 | |
13492 | switch (bytemode) | |
13493 | { | |
13494 | case b_mode: | |
13495 | FETCH_DATA (the_info, codep + 1); | |
13496 | disp = *codep++; | |
13497 | if ((disp & 0x80) != 0) | |
13498 | disp -= 0x100; | |
13499 | break; | |
13500 | case v_mode: | |
f16cd0d5 | 13501 | USED_REX (REX_W); |
161a04f6 | 13502 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 13503 | disp = get32s (); |
252b5132 RH |
13504 | else |
13505 | { | |
13506 | disp = get16 (); | |
206717e8 L |
13507 | if ((disp & 0x8000) != 0) |
13508 | disp -= 0x10000; | |
65ca155d L |
13509 | /* In 16bit mode, address is wrapped around at 64k within |
13510 | the same segment. Otherwise, a data16 prefix on a jump | |
13511 | instruction means that the pc is masked to 16 bits after | |
13512 | the displacement is added! */ | |
13513 | mask = 0xffff; | |
13514 | if ((prefixes & PREFIX_DATA) == 0) | |
13515 | segment = ((start_pc + codep - start_codep) | |
13516 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 13517 | } |
f16cd0d5 L |
13518 | if (!(rex & REX_W)) |
13519 | used_prefixes |= (prefixes & PREFIX_DATA); | |
252b5132 RH |
13520 | break; |
13521 | default: | |
13522 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13523 | return; | |
13524 | } | |
65ca155d | 13525 | disp = ((start_pc + codep - start_codep + disp) & mask) | segment; |
52b15da3 JH |
13526 | set_op (disp, 0); |
13527 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
13528 | oappend (scratchbuf); |
13529 | } | |
13530 | ||
252b5132 | 13531 | static void |
ed7841b3 | 13532 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 13533 | { |
ed7841b3 | 13534 | if (bytemode == w_mode) |
7967e09e | 13535 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 13536 | else |
7967e09e | 13537 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
13538 | } |
13539 | ||
13540 | static void | |
26ca5450 | 13541 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
13542 | { |
13543 | int seg, offset; | |
13544 | ||
c608c12e | 13545 | if (sizeflag & DFLAG) |
252b5132 | 13546 | { |
c608c12e AM |
13547 | offset = get32 (); |
13548 | seg = get16 (); | |
252b5132 | 13549 | } |
c608c12e AM |
13550 | else |
13551 | { | |
13552 | offset = get16 (); | |
13553 | seg = get16 (); | |
13554 | } | |
7d421014 | 13555 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 13556 | if (intel_syntax) |
3f31e633 | 13557 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
13558 | else |
13559 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 13560 | oappend (scratchbuf); |
252b5132 RH |
13561 | } |
13562 | ||
252b5132 | 13563 | static void |
3f31e633 | 13564 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 13565 | { |
52b15da3 | 13566 | bfd_vma off; |
252b5132 | 13567 | |
3f31e633 JB |
13568 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
13569 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13570 | append_seg (); |
13571 | ||
cb712a9e | 13572 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
13573 | off = get32 (); |
13574 | else | |
13575 | off = get16 (); | |
13576 | ||
13577 | if (intel_syntax) | |
13578 | { | |
13579 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 13580 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 13581 | { |
d708bcba | 13582 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
13583 | oappend (":"); |
13584 | } | |
13585 | } | |
52b15da3 JH |
13586 | print_operand_value (scratchbuf, 1, off); |
13587 | oappend (scratchbuf); | |
13588 | } | |
6439fc28 | 13589 | |
52b15da3 | 13590 | static void |
3f31e633 | 13591 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
13592 | { |
13593 | bfd_vma off; | |
13594 | ||
539e75ad L |
13595 | if (address_mode != mode_64bit |
13596 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
13597 | { |
13598 | OP_OFF (bytemode, sizeflag); | |
13599 | return; | |
13600 | } | |
13601 | ||
3f31e633 JB |
13602 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
13603 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
13604 | append_seg (); |
13605 | ||
6608db57 | 13606 | off = get64 (); |
52b15da3 JH |
13607 | |
13608 | if (intel_syntax) | |
13609 | { | |
13610 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 13611 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 13612 | { |
d708bcba | 13613 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
13614 | oappend (":"); |
13615 | } | |
13616 | } | |
13617 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
13618 | oappend (scratchbuf); |
13619 | } | |
13620 | ||
13621 | static void | |
26ca5450 | 13622 | ptr_reg (int code, int sizeflag) |
252b5132 | 13623 | { |
2da11e11 | 13624 | const char *s; |
d708bcba | 13625 | |
1d9f512f | 13626 | *obufp++ = open_char; |
20f0a1fc | 13627 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 13628 | if (address_mode == mode_64bit) |
c1a64871 JH |
13629 | { |
13630 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 13631 | s = names32[code - eAX_reg]; |
c1a64871 | 13632 | else |
db6eb5be | 13633 | s = names64[code - eAX_reg]; |
c1a64871 | 13634 | } |
52b15da3 | 13635 | else if (sizeflag & AFLAG) |
252b5132 RH |
13636 | s = names32[code - eAX_reg]; |
13637 | else | |
13638 | s = names16[code - eAX_reg]; | |
13639 | oappend (s); | |
1d9f512f AM |
13640 | *obufp++ = close_char; |
13641 | *obufp = 0; | |
252b5132 RH |
13642 | } |
13643 | ||
13644 | static void | |
26ca5450 | 13645 | OP_ESreg (int code, int sizeflag) |
252b5132 | 13646 | { |
9306ca4a | 13647 | if (intel_syntax) |
52fd6d94 JB |
13648 | { |
13649 | switch (codep[-1]) | |
13650 | { | |
13651 | case 0x6d: /* insw/insl */ | |
13652 | intel_operand_size (z_mode, sizeflag); | |
13653 | break; | |
13654 | case 0xa5: /* movsw/movsl/movsq */ | |
13655 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
13656 | case 0xab: /* stosw/stosl */ | |
13657 | case 0xaf: /* scasw/scasl */ | |
13658 | intel_operand_size (v_mode, sizeflag); | |
13659 | break; | |
13660 | default: | |
13661 | intel_operand_size (b_mode, sizeflag); | |
13662 | } | |
13663 | } | |
d708bcba | 13664 | oappend ("%es:" + intel_syntax); |
252b5132 RH |
13665 | ptr_reg (code, sizeflag); |
13666 | } | |
13667 | ||
13668 | static void | |
26ca5450 | 13669 | OP_DSreg (int code, int sizeflag) |
252b5132 | 13670 | { |
9306ca4a | 13671 | if (intel_syntax) |
52fd6d94 JB |
13672 | { |
13673 | switch (codep[-1]) | |
13674 | { | |
13675 | case 0x6f: /* outsw/outsl */ | |
13676 | intel_operand_size (z_mode, sizeflag); | |
13677 | break; | |
13678 | case 0xa5: /* movsw/movsl/movsq */ | |
13679 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
13680 | case 0xad: /* lodsw/lodsl/lodsq */ | |
13681 | intel_operand_size (v_mode, sizeflag); | |
13682 | break; | |
13683 | default: | |
13684 | intel_operand_size (b_mode, sizeflag); | |
13685 | } | |
13686 | } | |
252b5132 RH |
13687 | if ((prefixes |
13688 | & (PREFIX_CS | |
13689 | | PREFIX_DS | |
13690 | | PREFIX_SS | |
13691 | | PREFIX_ES | |
13692 | | PREFIX_FS | |
13693 | | PREFIX_GS)) == 0) | |
13694 | prefixes |= PREFIX_DS; | |
6608db57 | 13695 | append_seg (); |
252b5132 RH |
13696 | ptr_reg (code, sizeflag); |
13697 | } | |
13698 | ||
252b5132 | 13699 | static void |
26ca5450 | 13700 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13701 | { |
9b60702d | 13702 | int add; |
161a04f6 | 13703 | if (rex & REX_R) |
c4a530c5 | 13704 | { |
161a04f6 | 13705 | USED_REX (REX_R); |
c4a530c5 JB |
13706 | add = 8; |
13707 | } | |
cb712a9e | 13708 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 13709 | { |
f16cd0d5 | 13710 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
13711 | used_prefixes |= PREFIX_LOCK; |
13712 | add = 8; | |
13713 | } | |
9b60702d L |
13714 | else |
13715 | add = 0; | |
7967e09e | 13716 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
d708bcba | 13717 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
13718 | } |
13719 | ||
252b5132 | 13720 | static void |
26ca5450 | 13721 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13722 | { |
9b60702d | 13723 | int add; |
161a04f6 L |
13724 | USED_REX (REX_R); |
13725 | if (rex & REX_R) | |
52b15da3 | 13726 | add = 8; |
9b60702d L |
13727 | else |
13728 | add = 0; | |
d708bcba | 13729 | if (intel_syntax) |
7967e09e | 13730 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 13731 | else |
7967e09e | 13732 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
13733 | oappend (scratchbuf); |
13734 | } | |
13735 | ||
252b5132 | 13736 | static void |
26ca5450 | 13737 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13738 | { |
7967e09e | 13739 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
d708bcba | 13740 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
13741 | } |
13742 | ||
13743 | static void | |
6f74c397 | 13744 | OP_R (int bytemode, int sizeflag) |
252b5132 | 13745 | { |
7967e09e | 13746 | if (modrm.mod == 3) |
2da11e11 AM |
13747 | OP_E (bytemode, sizeflag); |
13748 | else | |
6608db57 | 13749 | BadOp (); |
252b5132 RH |
13750 | } |
13751 | ||
13752 | static void | |
26ca5450 | 13753 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13754 | { |
b9733481 L |
13755 | int reg = modrm.reg; |
13756 | const char **names; | |
13757 | ||
041bd2e0 JH |
13758 | used_prefixes |= (prefixes & PREFIX_DATA); |
13759 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 13760 | { |
b9733481 | 13761 | names = names_xmm; |
161a04f6 L |
13762 | USED_REX (REX_R); |
13763 | if (rex & REX_R) | |
b9733481 | 13764 | reg += 8; |
20f0a1fc | 13765 | } |
041bd2e0 | 13766 | else |
b9733481 L |
13767 | names = names_mm; |
13768 | oappend (names[reg]); | |
252b5132 RH |
13769 | } |
13770 | ||
c608c12e | 13771 | static void |
c0f3af97 | 13772 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 13773 | { |
b9733481 L |
13774 | int reg = modrm.reg; |
13775 | const char **names; | |
13776 | ||
161a04f6 L |
13777 | USED_REX (REX_R); |
13778 | if (rex & REX_R) | |
b9733481 | 13779 | reg += 8; |
c0f3af97 L |
13780 | if (need_vex && bytemode != xmm_mode) |
13781 | { | |
13782 | switch (vex.length) | |
13783 | { | |
13784 | case 128: | |
b9733481 | 13785 | names = names_xmm; |
c0f3af97 L |
13786 | break; |
13787 | case 256: | |
b9733481 | 13788 | names = names_ymm; |
c0f3af97 L |
13789 | break; |
13790 | default: | |
13791 | abort (); | |
13792 | } | |
13793 | } | |
13794 | else | |
b9733481 L |
13795 | names = names_xmm; |
13796 | oappend (names[reg]); | |
c608c12e AM |
13797 | } |
13798 | ||
252b5132 | 13799 | static void |
26ca5450 | 13800 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 13801 | { |
b9733481 L |
13802 | int reg; |
13803 | const char **names; | |
13804 | ||
7967e09e | 13805 | if (modrm.mod != 3) |
252b5132 | 13806 | { |
b6169b20 L |
13807 | if (intel_syntax |
13808 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
13809 | { |
13810 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
13811 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13812 | } | |
252b5132 RH |
13813 | OP_E (bytemode, sizeflag); |
13814 | return; | |
13815 | } | |
13816 | ||
b6169b20 L |
13817 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
13818 | swap_operand (); | |
13819 | ||
6608db57 | 13820 | /* Skip mod/rm byte. */ |
4bba6815 | 13821 | MODRM_CHECK; |
252b5132 | 13822 | codep++; |
041bd2e0 | 13823 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 13824 | reg = modrm.rm; |
041bd2e0 | 13825 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 13826 | { |
b9733481 | 13827 | names = names_xmm; |
161a04f6 L |
13828 | USED_REX (REX_B); |
13829 | if (rex & REX_B) | |
b9733481 | 13830 | reg += 8; |
20f0a1fc | 13831 | } |
041bd2e0 | 13832 | else |
b9733481 L |
13833 | names = names_mm; |
13834 | oappend (names[reg]); | |
252b5132 RH |
13835 | } |
13836 | ||
246c51aa L |
13837 | /* cvt* are the only instructions in sse2 which have |
13838 | both SSE and MMX operands and also have 0x66 prefix | |
13839 | in their opcode. 0x66 was originally used to differentiate | |
13840 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
13841 | cvt* separately using OP_EMC and OP_MXC */ |
13842 | static void | |
13843 | OP_EMC (int bytemode, int sizeflag) | |
13844 | { | |
7967e09e | 13845 | if (modrm.mod != 3) |
4d9567e0 MM |
13846 | { |
13847 | if (intel_syntax && bytemode == v_mode) | |
13848 | { | |
13849 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
13850 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13851 | } | |
13852 | OP_E (bytemode, sizeflag); | |
13853 | return; | |
13854 | } | |
246c51aa | 13855 | |
4d9567e0 MM |
13856 | /* Skip mod/rm byte. */ |
13857 | MODRM_CHECK; | |
13858 | codep++; | |
13859 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 13860 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
13861 | } |
13862 | ||
13863 | static void | |
13864 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13865 | { | |
13866 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 13867 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
13868 | } |
13869 | ||
c608c12e | 13870 | static void |
26ca5450 | 13871 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 13872 | { |
b9733481 L |
13873 | int reg; |
13874 | const char **names; | |
d6f574e0 L |
13875 | |
13876 | /* Skip mod/rm byte. */ | |
13877 | MODRM_CHECK; | |
13878 | codep++; | |
13879 | ||
7967e09e | 13880 | if (modrm.mod != 3) |
c608c12e | 13881 | { |
c1e679ec | 13882 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
13883 | return; |
13884 | } | |
d6f574e0 | 13885 | |
b9733481 | 13886 | reg = modrm.rm; |
161a04f6 L |
13887 | USED_REX (REX_B); |
13888 | if (rex & REX_B) | |
b9733481 | 13889 | reg += 8; |
c608c12e | 13890 | |
b6169b20 | 13891 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
13892 | && (bytemode == x_swap_mode |
13893 | || bytemode == d_swap_mode | |
13894 | || bytemode == q_swap_mode)) | |
b6169b20 L |
13895 | swap_operand (); |
13896 | ||
c0f3af97 L |
13897 | if (need_vex |
13898 | && bytemode != xmm_mode | |
13899 | && bytemode != xmmq_mode) | |
13900 | { | |
13901 | switch (vex.length) | |
13902 | { | |
13903 | case 128: | |
b9733481 | 13904 | names = names_xmm; |
c0f3af97 L |
13905 | break; |
13906 | case 256: | |
b9733481 | 13907 | names = names_ymm; |
c0f3af97 L |
13908 | break; |
13909 | default: | |
13910 | abort (); | |
13911 | } | |
13912 | } | |
13913 | else | |
b9733481 L |
13914 | names = names_xmm; |
13915 | oappend (names[reg]); | |
c608c12e AM |
13916 | } |
13917 | ||
252b5132 | 13918 | static void |
26ca5450 | 13919 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 13920 | { |
7967e09e | 13921 | if (modrm.mod == 3) |
2da11e11 AM |
13922 | OP_EM (bytemode, sizeflag); |
13923 | else | |
6608db57 | 13924 | BadOp (); |
252b5132 RH |
13925 | } |
13926 | ||
992aaec9 | 13927 | static void |
26ca5450 | 13928 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 13929 | { |
7967e09e | 13930 | if (modrm.mod == 3) |
992aaec9 AM |
13931 | OP_EX (bytemode, sizeflag); |
13932 | else | |
6608db57 | 13933 | BadOp (); |
992aaec9 AM |
13934 | } |
13935 | ||
cc0ec051 AM |
13936 | static void |
13937 | OP_M (int bytemode, int sizeflag) | |
13938 | { | |
7967e09e | 13939 | if (modrm.mod == 3) |
75413a22 L |
13940 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
13941 | BadOp (); | |
cc0ec051 AM |
13942 | else |
13943 | OP_E (bytemode, sizeflag); | |
13944 | } | |
13945 | ||
13946 | static void | |
13947 | OP_0f07 (int bytemode, int sizeflag) | |
13948 | { | |
7967e09e | 13949 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
13950 | BadOp (); |
13951 | else | |
13952 | OP_E (bytemode, sizeflag); | |
13953 | } | |
13954 | ||
46e883c5 | 13955 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 13956 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 13957 | |
cc0ec051 | 13958 | static void |
46e883c5 | 13959 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 13960 | { |
8b38ad71 L |
13961 | if ((prefixes & PREFIX_DATA) != 0 |
13962 | || (rex != 0 | |
13963 | && rex != 0x48 | |
13964 | && address_mode == mode_64bit)) | |
46e883c5 L |
13965 | OP_REG (bytemode, sizeflag); |
13966 | else | |
13967 | strcpy (obuf, "nop"); | |
13968 | } | |
13969 | ||
13970 | static void | |
13971 | NOP_Fixup2 (int bytemode, int sizeflag) | |
13972 | { | |
8b38ad71 L |
13973 | if ((prefixes & PREFIX_DATA) != 0 |
13974 | || (rex != 0 | |
13975 | && rex != 0x48 | |
13976 | && address_mode == mode_64bit)) | |
46e883c5 | 13977 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
13978 | } |
13979 | ||
84037f8c | 13980 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
13981 | /* 00 */ NULL, NULL, NULL, NULL, |
13982 | /* 04 */ NULL, NULL, NULL, NULL, | |
13983 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13984 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
13985 | /* 10 */ NULL, NULL, NULL, NULL, |
13986 | /* 14 */ NULL, NULL, NULL, NULL, | |
13987 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13988 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
13989 | /* 20 */ NULL, NULL, NULL, NULL, |
13990 | /* 24 */ NULL, NULL, NULL, NULL, | |
13991 | /* 28 */ NULL, NULL, NULL, NULL, | |
13992 | /* 2C */ NULL, NULL, NULL, NULL, | |
13993 | /* 30 */ NULL, NULL, NULL, NULL, | |
13994 | /* 34 */ NULL, NULL, NULL, NULL, | |
13995 | /* 38 */ NULL, NULL, NULL, NULL, | |
13996 | /* 3C */ NULL, NULL, NULL, NULL, | |
13997 | /* 40 */ NULL, NULL, NULL, NULL, | |
13998 | /* 44 */ NULL, NULL, NULL, NULL, | |
13999 | /* 48 */ NULL, NULL, NULL, NULL, | |
14000 | /* 4C */ NULL, NULL, NULL, NULL, | |
14001 | /* 50 */ NULL, NULL, NULL, NULL, | |
14002 | /* 54 */ NULL, NULL, NULL, NULL, | |
14003 | /* 58 */ NULL, NULL, NULL, NULL, | |
14004 | /* 5C */ NULL, NULL, NULL, NULL, | |
14005 | /* 60 */ NULL, NULL, NULL, NULL, | |
14006 | /* 64 */ NULL, NULL, NULL, NULL, | |
14007 | /* 68 */ NULL, NULL, NULL, NULL, | |
14008 | /* 6C */ NULL, NULL, NULL, NULL, | |
14009 | /* 70 */ NULL, NULL, NULL, NULL, | |
14010 | /* 74 */ NULL, NULL, NULL, NULL, | |
14011 | /* 78 */ NULL, NULL, NULL, NULL, | |
14012 | /* 7C */ NULL, NULL, NULL, NULL, | |
14013 | /* 80 */ NULL, NULL, NULL, NULL, | |
14014 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
14015 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
14016 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
14017 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
14018 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
14019 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
14020 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
14021 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
14022 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
14023 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
14024 | /* AC */ NULL, NULL, "pfacc", NULL, | |
14025 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 14026 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 14027 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
14028 | /* BC */ NULL, NULL, NULL, "pavgusb", |
14029 | /* C0 */ NULL, NULL, NULL, NULL, | |
14030 | /* C4 */ NULL, NULL, NULL, NULL, | |
14031 | /* C8 */ NULL, NULL, NULL, NULL, | |
14032 | /* CC */ NULL, NULL, NULL, NULL, | |
14033 | /* D0 */ NULL, NULL, NULL, NULL, | |
14034 | /* D4 */ NULL, NULL, NULL, NULL, | |
14035 | /* D8 */ NULL, NULL, NULL, NULL, | |
14036 | /* DC */ NULL, NULL, NULL, NULL, | |
14037 | /* E0 */ NULL, NULL, NULL, NULL, | |
14038 | /* E4 */ NULL, NULL, NULL, NULL, | |
14039 | /* E8 */ NULL, NULL, NULL, NULL, | |
14040 | /* EC */ NULL, NULL, NULL, NULL, | |
14041 | /* F0 */ NULL, NULL, NULL, NULL, | |
14042 | /* F4 */ NULL, NULL, NULL, NULL, | |
14043 | /* F8 */ NULL, NULL, NULL, NULL, | |
14044 | /* FC */ NULL, NULL, NULL, NULL, | |
14045 | }; | |
14046 | ||
14047 | static void | |
26ca5450 | 14048 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
14049 | { |
14050 | const char *mnemonic; | |
14051 | ||
14052 | FETCH_DATA (the_info, codep + 1); | |
14053 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
14054 | place where an 8-bit immediate would normally go. ie. the last | |
14055 | byte of the instruction. */ | |
ea397f5b | 14056 | obufp = mnemonicendp; |
c608c12e | 14057 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 14058 | if (mnemonic) |
2da11e11 | 14059 | oappend (mnemonic); |
252b5132 RH |
14060 | else |
14061 | { | |
14062 | /* Since a variable sized modrm/sib chunk is between the start | |
14063 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
14064 | all the modrm processing first, and don't know until now that | |
14065 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
14066 | op_out[0][0] = '\0'; |
14067 | op_out[1][0] = '\0'; | |
6608db57 | 14068 | BadOp (); |
252b5132 | 14069 | } |
ea397f5b | 14070 | mnemonicendp = obufp; |
252b5132 | 14071 | } |
c608c12e | 14072 | |
ea397f5b L |
14073 | static struct op simd_cmp_op[] = |
14074 | { | |
14075 | { STRING_COMMA_LEN ("eq") }, | |
14076 | { STRING_COMMA_LEN ("lt") }, | |
14077 | { STRING_COMMA_LEN ("le") }, | |
14078 | { STRING_COMMA_LEN ("unord") }, | |
14079 | { STRING_COMMA_LEN ("neq") }, | |
14080 | { STRING_COMMA_LEN ("nlt") }, | |
14081 | { STRING_COMMA_LEN ("nle") }, | |
14082 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
14083 | }; |
14084 | ||
14085 | static void | |
ad19981d | 14086 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
14087 | { |
14088 | unsigned int cmp_type; | |
14089 | ||
14090 | FETCH_DATA (the_info, codep + 1); | |
14091 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 14092 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 14093 | { |
ad19981d | 14094 | char suffix [3]; |
ea397f5b | 14095 | char *p = mnemonicendp - 2; |
ad19981d L |
14096 | suffix[0] = p[0]; |
14097 | suffix[1] = p[1]; | |
14098 | suffix[2] = '\0'; | |
ea397f5b L |
14099 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
14100 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
14101 | } |
14102 | else | |
14103 | { | |
ad19981d L |
14104 | /* We have a reserved extension byte. Output it directly. */ |
14105 | scratchbuf[0] = '$'; | |
14106 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
14107 | oappend (scratchbuf + intel_syntax); | |
14108 | scratchbuf[0] = '\0'; | |
c608c12e AM |
14109 | } |
14110 | } | |
14111 | ||
ca164297 | 14112 | static void |
b844680a L |
14113 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
14114 | int sizeflag ATTRIBUTE_UNUSED) | |
14115 | { | |
14116 | /* mwait %eax,%ecx */ | |
14117 | if (!intel_syntax) | |
14118 | { | |
14119 | const char **names = (address_mode == mode_64bit | |
14120 | ? names64 : names32); | |
14121 | strcpy (op_out[0], names[0]); | |
14122 | strcpy (op_out[1], names[1]); | |
14123 | two_source_ops = 1; | |
14124 | } | |
14125 | /* Skip mod/rm byte. */ | |
14126 | MODRM_CHECK; | |
14127 | codep++; | |
14128 | } | |
14129 | ||
14130 | static void | |
14131 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
14132 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 14133 | { |
b844680a L |
14134 | /* monitor %eax,%ecx,%edx" */ |
14135 | if (!intel_syntax) | |
ca164297 | 14136 | { |
b844680a | 14137 | const char **op1_names; |
cb712a9e L |
14138 | const char **names = (address_mode == mode_64bit |
14139 | ? names64 : names32); | |
1d9f512f | 14140 | |
b844680a L |
14141 | if (!(prefixes & PREFIX_ADDR)) |
14142 | op1_names = (address_mode == mode_16bit | |
14143 | ? names16 : names); | |
ca164297 L |
14144 | else |
14145 | { | |
b844680a | 14146 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 14147 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
14148 | op1_names = (address_mode != mode_32bit |
14149 | ? names32 : names16); | |
14150 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 14151 | } |
b844680a L |
14152 | strcpy (op_out[0], op1_names[0]); |
14153 | strcpy (op_out[1], names[1]); | |
14154 | strcpy (op_out[2], names[2]); | |
14155 | two_source_ops = 1; | |
ca164297 | 14156 | } |
b844680a L |
14157 | /* Skip mod/rm byte. */ |
14158 | MODRM_CHECK; | |
14159 | codep++; | |
30123838 JB |
14160 | } |
14161 | ||
6608db57 KH |
14162 | static void |
14163 | BadOp (void) | |
2da11e11 | 14164 | { |
6608db57 KH |
14165 | /* Throw away prefixes and 1st. opcode byte. */ |
14166 | codep = insn_codep + 1; | |
2da11e11 AM |
14167 | oappend ("(bad)"); |
14168 | } | |
4cc91dba | 14169 | |
35c52694 L |
14170 | static void |
14171 | REP_Fixup (int bytemode, int sizeflag) | |
14172 | { | |
14173 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
14174 | lods and stos. */ | |
35c52694 | 14175 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 14176 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
14177 | |
14178 | switch (bytemode) | |
14179 | { | |
14180 | case al_reg: | |
14181 | case eAX_reg: | |
14182 | case indir_dx_reg: | |
14183 | OP_IMREG (bytemode, sizeflag); | |
14184 | break; | |
14185 | case eDI_reg: | |
14186 | OP_ESreg (bytemode, sizeflag); | |
14187 | break; | |
14188 | case eSI_reg: | |
14189 | OP_DSreg (bytemode, sizeflag); | |
14190 | break; | |
14191 | default: | |
14192 | abort (); | |
14193 | break; | |
14194 | } | |
14195 | } | |
f5804c90 L |
14196 | |
14197 | static void | |
14198 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
14199 | { | |
161a04f6 L |
14200 | USED_REX (REX_W); |
14201 | if (rex & REX_W) | |
f5804c90 L |
14202 | { |
14203 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
14204 | char *p = mnemonicendp - 2; |
14205 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 14206 | bytemode = o_mode; |
f5804c90 L |
14207 | } |
14208 | OP_M (bytemode, sizeflag); | |
14209 | } | |
42903f7f L |
14210 | |
14211 | static void | |
14212 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
14213 | { | |
b9733481 L |
14214 | const char **names; |
14215 | ||
c0f3af97 L |
14216 | if (need_vex) |
14217 | { | |
14218 | switch (vex.length) | |
14219 | { | |
14220 | case 128: | |
b9733481 | 14221 | names = names_xmm; |
c0f3af97 L |
14222 | break; |
14223 | case 256: | |
b9733481 | 14224 | names = names_ymm; |
c0f3af97 L |
14225 | break; |
14226 | default: | |
14227 | abort (); | |
14228 | } | |
14229 | } | |
14230 | else | |
b9733481 L |
14231 | names = names_xmm; |
14232 | oappend (names[reg]); | |
42903f7f | 14233 | } |
381d071f L |
14234 | |
14235 | static void | |
14236 | CRC32_Fixup (int bytemode, int sizeflag) | |
14237 | { | |
14238 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 14239 | char *p = mnemonicendp; |
381d071f L |
14240 | |
14241 | switch (bytemode) | |
14242 | { | |
14243 | case b_mode: | |
20592a94 | 14244 | if (intel_syntax) |
ea397f5b | 14245 | goto skip; |
20592a94 | 14246 | |
381d071f L |
14247 | *p++ = 'b'; |
14248 | break; | |
14249 | case v_mode: | |
20592a94 | 14250 | if (intel_syntax) |
ea397f5b | 14251 | goto skip; |
20592a94 | 14252 | |
381d071f L |
14253 | USED_REX (REX_W); |
14254 | if (rex & REX_W) | |
14255 | *p++ = 'q'; | |
f16cd0d5 L |
14256 | else |
14257 | { | |
14258 | if (sizeflag & DFLAG) | |
14259 | *p++ = 'l'; | |
14260 | else | |
14261 | *p++ = 'w'; | |
14262 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14263 | } | |
381d071f L |
14264 | break; |
14265 | default: | |
14266 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14267 | break; | |
14268 | } | |
ea397f5b | 14269 | mnemonicendp = p; |
381d071f L |
14270 | *p = '\0'; |
14271 | ||
ea397f5b | 14272 | skip: |
381d071f L |
14273 | if (modrm.mod == 3) |
14274 | { | |
14275 | int add; | |
14276 | ||
14277 | /* Skip mod/rm byte. */ | |
14278 | MODRM_CHECK; | |
14279 | codep++; | |
14280 | ||
14281 | USED_REX (REX_B); | |
14282 | add = (rex & REX_B) ? 8 : 0; | |
14283 | if (bytemode == b_mode) | |
14284 | { | |
14285 | USED_REX (0); | |
14286 | if (rex) | |
14287 | oappend (names8rex[modrm.rm + add]); | |
14288 | else | |
14289 | oappend (names8[modrm.rm + add]); | |
14290 | } | |
14291 | else | |
14292 | { | |
14293 | USED_REX (REX_W); | |
14294 | if (rex & REX_W) | |
14295 | oappend (names64[modrm.rm + add]); | |
14296 | else if ((prefixes & PREFIX_DATA)) | |
14297 | oappend (names16[modrm.rm + add]); | |
14298 | else | |
14299 | oappend (names32[modrm.rm + add]); | |
14300 | } | |
14301 | } | |
14302 | else | |
9344ff29 | 14303 | OP_E (bytemode, sizeflag); |
381d071f | 14304 | } |
85f10a01 | 14305 | |
eacc9c89 L |
14306 | static void |
14307 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
14308 | { | |
14309 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
14310 | USED_REX (REX_W); | |
14311 | if (rex & REX_W) | |
14312 | { | |
14313 | char *p = mnemonicendp; | |
14314 | *p++ = '6'; | |
14315 | *p++ = '4'; | |
14316 | *p = '\0'; | |
14317 | mnemonicendp = p; | |
14318 | } | |
14319 | OP_M (bytemode, sizeflag); | |
14320 | } | |
14321 | ||
c0f3af97 L |
14322 | /* Display the destination register operand for instructions with |
14323 | VEX. */ | |
14324 | ||
14325 | static void | |
14326 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14327 | { | |
b9733481 L |
14328 | const char **names; |
14329 | ||
c0f3af97 L |
14330 | if (!need_vex) |
14331 | abort (); | |
14332 | ||
14333 | if (!need_vex_reg) | |
14334 | return; | |
14335 | ||
14336 | switch (vex.length) | |
14337 | { | |
14338 | case 128: | |
14339 | switch (bytemode) | |
14340 | { | |
14341 | case vex_mode: | |
14342 | case vex128_mode: | |
14343 | break; | |
14344 | default: | |
14345 | abort (); | |
14346 | return; | |
14347 | } | |
14348 | ||
b9733481 | 14349 | names = names_xmm; |
c0f3af97 L |
14350 | break; |
14351 | case 256: | |
14352 | switch (bytemode) | |
14353 | { | |
14354 | case vex_mode: | |
14355 | case vex256_mode: | |
14356 | break; | |
14357 | default: | |
14358 | abort (); | |
14359 | return; | |
14360 | } | |
14361 | ||
b9733481 | 14362 | names = names_ymm; |
c0f3af97 L |
14363 | break; |
14364 | default: | |
14365 | abort (); | |
14366 | break; | |
14367 | } | |
b9733481 | 14368 | oappend (names[vex.register_specifier]); |
c0f3af97 L |
14369 | } |
14370 | ||
922d8de8 DR |
14371 | /* Get the VEX immediate byte without moving codep. */ |
14372 | ||
14373 | static unsigned char | |
ccc5981b | 14374 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
14375 | { |
14376 | int bytes_before_imm = 0; | |
14377 | ||
922d8de8 DR |
14378 | if (modrm.mod != 3) |
14379 | { | |
14380 | /* There are SIB/displacement bytes. */ | |
14381 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
02e647f9 | 14382 | { |
922d8de8 | 14383 | /* 32/64 bit address mode */ |
02e647f9 | 14384 | int base = modrm.rm; |
922d8de8 DR |
14385 | |
14386 | /* Check SIB byte. */ | |
02e647f9 SP |
14387 | if (base == 4) |
14388 | { | |
14389 | FETCH_DATA (the_info, codep + 1); | |
14390 | base = *codep & 7; | |
14391 | /* When decoding the third source, don't increase | |
14392 | bytes_before_imm as this has already been incremented | |
14393 | by one in OP_E_memory while decoding the second | |
14394 | source operand. */ | |
ccc5981b SP |
14395 | if (opnum == 0) |
14396 | bytes_before_imm++; | |
02e647f9 SP |
14397 | } |
14398 | ||
14399 | /* Don't increase bytes_before_imm when decoding the third source, | |
14400 | it has already been incremented by OP_E_memory while decoding | |
14401 | the second source operand. */ | |
14402 | if (opnum == 0) | |
14403 | { | |
14404 | switch (modrm.mod) | |
14405 | { | |
14406 | case 0: | |
14407 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
14408 | SIB == 5, there is a 4 byte displacement. */ | |
14409 | if (base != 5) | |
14410 | /* No displacement. */ | |
14411 | break; | |
14412 | case 2: | |
14413 | /* 4 byte displacement. */ | |
14414 | bytes_before_imm += 4; | |
14415 | break; | |
14416 | case 1: | |
14417 | /* 1 byte displacement. */ | |
14418 | bytes_before_imm++; | |
14419 | break; | |
14420 | } | |
14421 | } | |
14422 | } | |
922d8de8 | 14423 | else |
02e647f9 SP |
14424 | { |
14425 | /* 16 bit address mode */ | |
14426 | /* Don't increase bytes_before_imm when decoding the third source, | |
14427 | it has already been incremented by OP_E_memory while decoding | |
14428 | the second source operand. */ | |
14429 | if (opnum == 0) | |
14430 | { | |
14431 | switch (modrm.mod) | |
14432 | { | |
14433 | case 0: | |
14434 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
14435 | if (modrm.rm != 6) | |
14436 | /* No displacement. */ | |
14437 | break; | |
14438 | case 2: | |
14439 | /* 2 byte displacement. */ | |
14440 | bytes_before_imm += 2; | |
14441 | break; | |
14442 | case 1: | |
14443 | /* 1 byte displacement: when decoding the third source, | |
14444 | don't increase bytes_before_imm as this has already | |
14445 | been incremented by one in OP_E_memory while decoding | |
14446 | the second source operand. */ | |
14447 | if (opnum == 0) | |
14448 | bytes_before_imm++; | |
ccc5981b | 14449 | |
02e647f9 SP |
14450 | break; |
14451 | } | |
922d8de8 DR |
14452 | } |
14453 | } | |
14454 | } | |
14455 | ||
14456 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
14457 | return codep [bytes_before_imm]; | |
14458 | } | |
14459 | ||
14460 | static void | |
14461 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
14462 | { | |
b9733481 L |
14463 | const char **names; |
14464 | ||
922d8de8 DR |
14465 | if (reg == -1 && modrm.mod != 3) |
14466 | { | |
14467 | OP_E_memory (bytemode, sizeflag); | |
14468 | return; | |
14469 | } | |
14470 | else | |
14471 | { | |
14472 | if (reg == -1) | |
14473 | { | |
14474 | reg = modrm.rm; | |
14475 | USED_REX (REX_B); | |
14476 | if (rex & REX_B) | |
14477 | reg += 8; | |
14478 | } | |
14479 | else if (reg > 7 && address_mode != mode_64bit) | |
14480 | BadOp (); | |
14481 | } | |
14482 | ||
14483 | switch (vex.length) | |
14484 | { | |
14485 | case 128: | |
b9733481 | 14486 | names = names_xmm; |
922d8de8 DR |
14487 | break; |
14488 | case 256: | |
b9733481 | 14489 | names = names_ymm; |
922d8de8 DR |
14490 | break; |
14491 | default: | |
14492 | abort (); | |
14493 | } | |
b9733481 | 14494 | oappend (names[reg]); |
922d8de8 DR |
14495 | } |
14496 | ||
5dd85c99 SP |
14497 | static void |
14498 | OP_Vex_2src (int bytemode, int sizeflag) | |
14499 | { | |
14500 | if (modrm.mod == 3) | |
14501 | { | |
b9733481 | 14502 | int reg = modrm.rm; |
5dd85c99 | 14503 | USED_REX (REX_B); |
b9733481 L |
14504 | if (rex & REX_B) |
14505 | reg += 8; | |
14506 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
14507 | } |
14508 | else | |
14509 | { | |
14510 | if (intel_syntax | |
14511 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
14512 | { | |
14513 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
14514 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14515 | } | |
14516 | OP_E (bytemode, sizeflag); | |
14517 | } | |
14518 | } | |
14519 | ||
14520 | static void | |
14521 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
14522 | { | |
14523 | if (modrm.mod == 3) | |
14524 | { | |
14525 | /* Skip mod/rm byte. */ | |
14526 | MODRM_CHECK; | |
14527 | codep++; | |
14528 | } | |
14529 | ||
14530 | if (vex.w) | |
b9733481 | 14531 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
14532 | else |
14533 | OP_Vex_2src (bytemode, sizeflag); | |
14534 | } | |
14535 | ||
14536 | static void | |
14537 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
14538 | { | |
14539 | if (vex.w) | |
14540 | OP_Vex_2src (bytemode, sizeflag); | |
14541 | else | |
b9733481 | 14542 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
14543 | } |
14544 | ||
922d8de8 DR |
14545 | static void |
14546 | OP_EX_VexW (int bytemode, int sizeflag) | |
14547 | { | |
14548 | int reg = -1; | |
14549 | ||
14550 | if (!vex_w_done) | |
14551 | { | |
14552 | vex_w_done = 1; | |
41effecb SP |
14553 | |
14554 | /* Skip mod/rm byte. */ | |
14555 | MODRM_CHECK; | |
14556 | codep++; | |
14557 | ||
922d8de8 | 14558 | if (vex.w) |
ccc5981b | 14559 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
14560 | } |
14561 | else | |
14562 | { | |
14563 | if (!vex.w) | |
ccc5981b | 14564 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
14565 | } |
14566 | ||
14567 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
14568 | } | |
14569 | ||
922d8de8 DR |
14570 | static void |
14571 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
14572 | int sizeflag ATTRIBUTE_UNUSED) | |
14573 | { | |
14574 | /* Skip the immediate byte and check for invalid bits. */ | |
14575 | FETCH_DATA (the_info, codep + 1); | |
14576 | if (*codep++ & 0xf) | |
14577 | BadOp (); | |
14578 | } | |
14579 | ||
c0f3af97 L |
14580 | static void |
14581 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14582 | { | |
14583 | int reg; | |
b9733481 L |
14584 | const char **names; |
14585 | ||
c0f3af97 L |
14586 | FETCH_DATA (the_info, codep + 1); |
14587 | reg = *codep++; | |
14588 | ||
14589 | if (bytemode != x_mode) | |
14590 | abort (); | |
14591 | ||
14592 | if (reg & 0xf) | |
14593 | BadOp (); | |
14594 | ||
14595 | reg >>= 4; | |
dae39acc L |
14596 | if (reg > 7 && address_mode != mode_64bit) |
14597 | BadOp (); | |
14598 | ||
c0f3af97 L |
14599 | switch (vex.length) |
14600 | { | |
14601 | case 128: | |
b9733481 | 14602 | names = names_xmm; |
c0f3af97 L |
14603 | break; |
14604 | case 256: | |
b9733481 | 14605 | names = names_ymm; |
c0f3af97 L |
14606 | break; |
14607 | default: | |
14608 | abort (); | |
14609 | } | |
b9733481 | 14610 | oappend (names[reg]); |
c0f3af97 L |
14611 | } |
14612 | ||
922d8de8 DR |
14613 | static void |
14614 | OP_XMM_VexW (int bytemode, int sizeflag) | |
14615 | { | |
14616 | /* Turn off the REX.W bit since it is used for swapping operands | |
14617 | now. */ | |
14618 | rex &= ~REX_W; | |
14619 | OP_XMM (bytemode, sizeflag); | |
14620 | } | |
14621 | ||
c0f3af97 L |
14622 | static void |
14623 | OP_EX_Vex (int bytemode, int sizeflag) | |
14624 | { | |
14625 | if (modrm.mod != 3) | |
14626 | { | |
14627 | if (vex.register_specifier != 0) | |
14628 | BadOp (); | |
14629 | need_vex_reg = 0; | |
14630 | } | |
14631 | OP_EX (bytemode, sizeflag); | |
14632 | } | |
14633 | ||
14634 | static void | |
14635 | OP_XMM_Vex (int bytemode, int sizeflag) | |
14636 | { | |
14637 | if (modrm.mod != 3) | |
14638 | { | |
14639 | if (vex.register_specifier != 0) | |
14640 | BadOp (); | |
14641 | need_vex_reg = 0; | |
14642 | } | |
14643 | OP_XMM (bytemode, sizeflag); | |
14644 | } | |
14645 | ||
14646 | static void | |
14647 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
14648 | { | |
14649 | switch (vex.length) | |
14650 | { | |
14651 | case 128: | |
ea397f5b | 14652 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
14653 | break; |
14654 | case 256: | |
ea397f5b | 14655 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
14656 | break; |
14657 | default: | |
14658 | abort (); | |
14659 | } | |
14660 | } | |
14661 | ||
ea397f5b L |
14662 | static struct op vex_cmp_op[] = |
14663 | { | |
14664 | { STRING_COMMA_LEN ("eq") }, | |
14665 | { STRING_COMMA_LEN ("lt") }, | |
14666 | { STRING_COMMA_LEN ("le") }, | |
14667 | { STRING_COMMA_LEN ("unord") }, | |
14668 | { STRING_COMMA_LEN ("neq") }, | |
14669 | { STRING_COMMA_LEN ("nlt") }, | |
14670 | { STRING_COMMA_LEN ("nle") }, | |
14671 | { STRING_COMMA_LEN ("ord") }, | |
14672 | { STRING_COMMA_LEN ("eq_uq") }, | |
14673 | { STRING_COMMA_LEN ("nge") }, | |
14674 | { STRING_COMMA_LEN ("ngt") }, | |
14675 | { STRING_COMMA_LEN ("false") }, | |
14676 | { STRING_COMMA_LEN ("neq_oq") }, | |
14677 | { STRING_COMMA_LEN ("ge") }, | |
14678 | { STRING_COMMA_LEN ("gt") }, | |
14679 | { STRING_COMMA_LEN ("true") }, | |
14680 | { STRING_COMMA_LEN ("eq_os") }, | |
14681 | { STRING_COMMA_LEN ("lt_oq") }, | |
14682 | { STRING_COMMA_LEN ("le_oq") }, | |
14683 | { STRING_COMMA_LEN ("unord_s") }, | |
14684 | { STRING_COMMA_LEN ("neq_us") }, | |
14685 | { STRING_COMMA_LEN ("nlt_uq") }, | |
14686 | { STRING_COMMA_LEN ("nle_uq") }, | |
14687 | { STRING_COMMA_LEN ("ord_s") }, | |
14688 | { STRING_COMMA_LEN ("eq_us") }, | |
14689 | { STRING_COMMA_LEN ("nge_uq") }, | |
14690 | { STRING_COMMA_LEN ("ngt_uq") }, | |
14691 | { STRING_COMMA_LEN ("false_os") }, | |
14692 | { STRING_COMMA_LEN ("neq_os") }, | |
14693 | { STRING_COMMA_LEN ("ge_oq") }, | |
14694 | { STRING_COMMA_LEN ("gt_oq") }, | |
14695 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
14696 | }; |
14697 | ||
14698 | static void | |
14699 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
14700 | { | |
14701 | unsigned int cmp_type; | |
14702 | ||
14703 | FETCH_DATA (the_info, codep + 1); | |
14704 | cmp_type = *codep++ & 0xff; | |
14705 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
14706 | { | |
14707 | char suffix [3]; | |
ea397f5b | 14708 | char *p = mnemonicendp - 2; |
c0f3af97 L |
14709 | suffix[0] = p[0]; |
14710 | suffix[1] = p[1]; | |
14711 | suffix[2] = '\0'; | |
ea397f5b L |
14712 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
14713 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
14714 | } |
14715 | else | |
14716 | { | |
14717 | /* We have a reserved extension byte. Output it directly. */ | |
14718 | scratchbuf[0] = '$'; | |
14719 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
14720 | oappend (scratchbuf + intel_syntax); | |
14721 | scratchbuf[0] = '\0'; | |
14722 | } | |
14723 | } | |
14724 | ||
ea397f5b L |
14725 | static const struct op pclmul_op[] = |
14726 | { | |
14727 | { STRING_COMMA_LEN ("lql") }, | |
14728 | { STRING_COMMA_LEN ("hql") }, | |
14729 | { STRING_COMMA_LEN ("lqh") }, | |
14730 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
14731 | }; |
14732 | ||
14733 | static void | |
14734 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
14735 | int sizeflag ATTRIBUTE_UNUSED) | |
14736 | { | |
14737 | unsigned int pclmul_type; | |
14738 | ||
14739 | FETCH_DATA (the_info, codep + 1); | |
14740 | pclmul_type = *codep++ & 0xff; | |
14741 | switch (pclmul_type) | |
14742 | { | |
14743 | case 0x10: | |
14744 | pclmul_type = 2; | |
14745 | break; | |
14746 | case 0x11: | |
14747 | pclmul_type = 3; | |
14748 | break; | |
14749 | default: | |
14750 | break; | |
14751 | } | |
14752 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) | |
14753 | { | |
14754 | char suffix [4]; | |
ea397f5b | 14755 | char *p = mnemonicendp - 3; |
c0f3af97 L |
14756 | suffix[0] = p[0]; |
14757 | suffix[1] = p[1]; | |
14758 | suffix[2] = p[2]; | |
14759 | suffix[3] = '\0'; | |
ea397f5b L |
14760 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
14761 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
14762 | } |
14763 | else | |
14764 | { | |
14765 | /* We have a reserved extension byte. Output it directly. */ | |
14766 | scratchbuf[0] = '$'; | |
14767 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
14768 | oappend (scratchbuf + intel_syntax); | |
14769 | scratchbuf[0] = '\0'; | |
14770 | } | |
14771 | } | |
14772 | ||
f1f8f695 L |
14773 | static void |
14774 | MOVBE_Fixup (int bytemode, int sizeflag) | |
14775 | { | |
14776 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 14777 | char *p = mnemonicendp; |
f1f8f695 L |
14778 | |
14779 | switch (bytemode) | |
14780 | { | |
14781 | case v_mode: | |
14782 | if (intel_syntax) | |
ea397f5b | 14783 | goto skip; |
f1f8f695 L |
14784 | |
14785 | USED_REX (REX_W); | |
14786 | if (sizeflag & SUFFIX_ALWAYS) | |
14787 | { | |
14788 | if (rex & REX_W) | |
14789 | *p++ = 'q'; | |
f1f8f695 | 14790 | else |
f16cd0d5 L |
14791 | { |
14792 | if (sizeflag & DFLAG) | |
14793 | *p++ = 'l'; | |
14794 | else | |
14795 | *p++ = 'w'; | |
14796 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14797 | } | |
f1f8f695 | 14798 | } |
f1f8f695 L |
14799 | break; |
14800 | default: | |
14801 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14802 | break; | |
14803 | } | |
ea397f5b | 14804 | mnemonicendp = p; |
f1f8f695 L |
14805 | *p = '\0'; |
14806 | ||
ea397f5b | 14807 | skip: |
f1f8f695 L |
14808 | OP_M (bytemode, sizeflag); |
14809 | } | |
f88c9eb0 SP |
14810 | |
14811 | static void | |
14812 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
14813 | { | |
14814 | int reg; | |
14815 | const char **names; | |
14816 | ||
14817 | /* Skip mod/rm byte. */ | |
14818 | MODRM_CHECK; | |
14819 | codep++; | |
14820 | ||
14821 | if (vex.w) | |
14822 | names = names64; | |
14823 | else if (vex.length == 256) | |
14824 | names = names32; | |
14825 | else | |
14826 | names = names16; | |
14827 | ||
14828 | reg = modrm.rm; | |
14829 | USED_REX (REX_B); | |
14830 | if (rex & REX_B) | |
14831 | reg += 8; | |
14832 | ||
14833 | oappend (names[reg]); | |
14834 | } | |
14835 | ||
14836 | static void | |
14837 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
14838 | { | |
14839 | const char **names; | |
14840 | ||
14841 | if (vex.w) | |
14842 | names = names64; | |
14843 | else if (vex.length == 256) | |
14844 | names = names32; | |
14845 | else | |
14846 | names = names16; | |
14847 | ||
14848 | oappend (names[vex.register_specifier]); | |
14849 | } | |
14850 | ||
14851 | static void | |
14852 | OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag) | |
14853 | { | |
14854 | if (vex.w || vex.length == 256) | |
14855 | OP_I (q_mode, sizeflag); | |
14856 | else | |
14857 | OP_I (w_mode, sizeflag); | |
14858 | } | |
14859 |