Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
219d1afa | 2 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 L |
98 | static void VZERO_Fixup (int, int); |
99 | static void VCMP_Fixup (int, int); | |
43234a1e | 100 | static void VPCMP_Fixup (int, int); |
be92cb14 | 101 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
d869730d | 156 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 157 | static int rex_ignored; |
52b15da3 JH |
158 | /* Mark parts used in the REX prefix. When we are testing for |
159 | empty prefix (for 8bit register REX extension), just mask it | |
160 | out. Otherwise test for REX bit is excuse for existence of REX | |
161 | only in case value is nonzero. */ | |
162 | #define USED_REX(value) \ | |
163 | { \ | |
164 | if (value) \ | |
161a04f6 L |
165 | { \ |
166 | if ((rex & value)) \ | |
167 | rex_used |= (value) | REX_OPCODE; \ | |
168 | } \ | |
52b15da3 | 169 | else \ |
161a04f6 | 170 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
171 | } |
172 | ||
7d421014 ILT |
173 | /* Flags for prefixes which we somehow handled when printing the |
174 | current instruction. */ | |
175 | static int used_prefixes; | |
176 | ||
5076851f ILT |
177 | /* Flags stored in PREFIXES. */ |
178 | #define PREFIX_REPZ 1 | |
179 | #define PREFIX_REPNZ 2 | |
180 | #define PREFIX_LOCK 4 | |
181 | #define PREFIX_CS 8 | |
182 | #define PREFIX_SS 0x10 | |
183 | #define PREFIX_DS 0x20 | |
184 | #define PREFIX_ES 0x40 | |
185 | #define PREFIX_FS 0x80 | |
186 | #define PREFIX_GS 0x100 | |
187 | #define PREFIX_DATA 0x200 | |
188 | #define PREFIX_ADDR 0x400 | |
189 | #define PREFIX_FWAIT 0x800 | |
190 | ||
252b5132 RH |
191 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
192 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
193 | on error. */ | |
194 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 195 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
196 | ? 1 : fetch_data ((info), (addr))) |
197 | ||
198 | static int | |
26ca5450 | 199 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
200 | { |
201 | int status; | |
6608db57 | 202 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
203 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
204 | ||
0b1cf022 | 205 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
206 | status = (*info->read_memory_func) (start, |
207 | priv->max_fetched, | |
208 | addr - priv->max_fetched, | |
209 | info); | |
210 | else | |
211 | status = -1; | |
252b5132 RH |
212 | if (status != 0) |
213 | { | |
7d421014 | 214 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
215 | print_insn_i386 will do something sensible. Otherwise, print |
216 | an error. We do that here because this is where we know | |
217 | STATUS. */ | |
7d421014 | 218 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 219 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 220 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
221 | } |
222 | else | |
223 | priv->max_fetched = addr; | |
224 | return 1; | |
225 | } | |
226 | ||
bf890a93 | 227 | /* Possible values for prefix requirement. */ |
507bd325 L |
228 | #define PREFIX_IGNORED_SHIFT 16 |
229 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
233 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
234 | ||
235 | /* Opcode prefixes. */ | |
236 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
237 | | PREFIX_REPNZ \ | |
238 | | PREFIX_DATA) | |
239 | ||
240 | /* Prefixes ignored. */ | |
241 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
242 | | PREFIX_IGNORED_REPNZ \ | |
243 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 244 | |
ce518a5f | 245 | #define XX { NULL, 0 } |
507bd325 | 246 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
247 | |
248 | #define Eb { OP_E, b_mode } | |
7e8b059b | 249 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 250 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 251 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 252 | #define Ev { OP_E, v_mode } |
de89d0a3 | 253 | #define Eva { OP_E, va_mode } |
7e8b059b | 254 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 255 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
256 | #define Ed { OP_E, d_mode } |
257 | #define Edq { OP_E, dq_mode } | |
258 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 259 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
260 | #define Edb { OP_E, db_mode } |
261 | #define Edw { OP_E, dw_mode } | |
42903f7f | 262 | #define Edqd { OP_E, dqd_mode } |
d20dee9e | 263 | #define Edqa { OP_E, dqa_mode } |
09335d05 | 264 | #define Eq { OP_E, q_mode } |
07f5af7d | 265 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
266 | #define indirEp { OP_indirE, f_mode } |
267 | #define stackEv { OP_E, stack_v_mode } | |
268 | #define Em { OP_E, m_mode } | |
269 | #define Ew { OP_E, w_mode } | |
270 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 271 | #define Ma { OP_M, a_mode } |
b844680a | 272 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 273 | #define Md { OP_M, d_mode } |
f1f8f695 | 274 | #define Mo { OP_M, o_mode } |
ce518a5f L |
275 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
276 | #define Mq { OP_M, q_mode } | |
d276ec69 | 277 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 278 | #define Mx { OP_M, x_mode } |
c0f3af97 | 279 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 280 | #define Gb { OP_G, b_mode } |
7e8b059b | 281 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
282 | #define Gv { OP_G, v_mode } |
283 | #define Gd { OP_G, d_mode } | |
284 | #define Gdq { OP_G, dq_mode } | |
285 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 286 | #define Gva { OP_G, va_mode } |
ce518a5f | 287 | #define Gw { OP_G, w_mode } |
6f74c397 | 288 | #define Rd { OP_R, d_mode } |
43234a1e | 289 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 290 | #define Rm { OP_R, m_mode } |
ce518a5f L |
291 | #define Ib { OP_I, b_mode } |
292 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 293 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 294 | #define Iv { OP_I, v_mode } |
7bb15c6f | 295 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
296 | #define Iq { OP_I, q_mode } |
297 | #define Iv64 { OP_I64, v_mode } | |
298 | #define Iw { OP_I, w_mode } | |
299 | #define I1 { OP_I, const_1_mode } | |
300 | #define Jb { OP_J, b_mode } | |
301 | #define Jv { OP_J, v_mode } | |
302 | #define Cm { OP_C, m_mode } | |
303 | #define Dm { OP_D, m_mode } | |
304 | #define Td { OP_T, d_mode } | |
b844680a | 305 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
306 | |
307 | #define RMeAX { OP_REG, eAX_reg } | |
308 | #define RMeBX { OP_REG, eBX_reg } | |
309 | #define RMeCX { OP_REG, eCX_reg } | |
310 | #define RMeDX { OP_REG, eDX_reg } | |
311 | #define RMeSP { OP_REG, eSP_reg } | |
312 | #define RMeBP { OP_REG, eBP_reg } | |
313 | #define RMeSI { OP_REG, eSI_reg } | |
314 | #define RMeDI { OP_REG, eDI_reg } | |
315 | #define RMrAX { OP_REG, rAX_reg } | |
316 | #define RMrBX { OP_REG, rBX_reg } | |
317 | #define RMrCX { OP_REG, rCX_reg } | |
318 | #define RMrDX { OP_REG, rDX_reg } | |
319 | #define RMrSP { OP_REG, rSP_reg } | |
320 | #define RMrBP { OP_REG, rBP_reg } | |
321 | #define RMrSI { OP_REG, rSI_reg } | |
322 | #define RMrDI { OP_REG, rDI_reg } | |
323 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
324 | #define RMCL { OP_REG, cl_reg } |
325 | #define RMDL { OP_REG, dl_reg } | |
326 | #define RMBL { OP_REG, bl_reg } | |
327 | #define RMAH { OP_REG, ah_reg } | |
328 | #define RMCH { OP_REG, ch_reg } | |
329 | #define RMDH { OP_REG, dh_reg } | |
330 | #define RMBH { OP_REG, bh_reg } | |
331 | #define RMAX { OP_REG, ax_reg } | |
332 | #define RMDX { OP_REG, dx_reg } | |
333 | ||
334 | #define eAX { OP_IMREG, eAX_reg } | |
335 | #define eBX { OP_IMREG, eBX_reg } | |
336 | #define eCX { OP_IMREG, eCX_reg } | |
337 | #define eDX { OP_IMREG, eDX_reg } | |
338 | #define eSP { OP_IMREG, eSP_reg } | |
339 | #define eBP { OP_IMREG, eBP_reg } | |
340 | #define eSI { OP_IMREG, eSI_reg } | |
341 | #define eDI { OP_IMREG, eDI_reg } | |
342 | #define AL { OP_IMREG, al_reg } | |
343 | #define CL { OP_IMREG, cl_reg } | |
344 | #define DL { OP_IMREG, dl_reg } | |
345 | #define BL { OP_IMREG, bl_reg } | |
346 | #define AH { OP_IMREG, ah_reg } | |
347 | #define CH { OP_IMREG, ch_reg } | |
348 | #define DH { OP_IMREG, dh_reg } | |
349 | #define BH { OP_IMREG, bh_reg } | |
350 | #define AX { OP_IMREG, ax_reg } | |
351 | #define DX { OP_IMREG, dx_reg } | |
352 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
353 | #define indirDX { OP_IMREG, indir_dx_reg } | |
354 | ||
355 | #define Sw { OP_SEG, w_mode } | |
356 | #define Sv { OP_SEG, v_mode } | |
357 | #define Ap { OP_DIR, 0 } | |
358 | #define Ob { OP_OFF64, b_mode } | |
359 | #define Ov { OP_OFF64, v_mode } | |
360 | #define Xb { OP_DSreg, eSI_reg } | |
361 | #define Xv { OP_DSreg, eSI_reg } | |
362 | #define Xz { OP_DSreg, eSI_reg } | |
363 | #define Yb { OP_ESreg, eDI_reg } | |
364 | #define Yv { OP_ESreg, eDI_reg } | |
365 | #define DSBX { OP_DSreg, eBX_reg } | |
366 | ||
367 | #define es { OP_REG, es_reg } | |
368 | #define ss { OP_REG, ss_reg } | |
369 | #define cs { OP_REG, cs_reg } | |
370 | #define ds { OP_REG, ds_reg } | |
371 | #define fs { OP_REG, fs_reg } | |
372 | #define gs { OP_REG, gs_reg } | |
373 | ||
374 | #define MX { OP_MMX, 0 } | |
375 | #define XM { OP_XMM, 0 } | |
539f890d | 376 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 377 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 378 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 379 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 380 | #define EM { OP_EM, v_mode } |
b6169b20 | 381 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 382 | #define EMd { OP_EM, d_mode } |
14051056 | 383 | #define EMx { OP_EM, x_mode } |
53467f57 | 384 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 385 | #define EXw { OP_EX, w_mode } |
53467f57 | 386 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 387 | #define EXd { OP_EX, d_mode } |
539f890d | 388 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 389 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 390 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 391 | #define EXq { OP_EX, q_mode } |
539f890d L |
392 | #define EXqScalar { OP_EX, q_scalar_mode } |
393 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 394 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 395 | #define EXx { OP_EX, x_mode } |
b6169b20 | 396 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 397 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 398 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 399 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 400 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
401 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
402 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
403 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
404 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 405 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
406 | #define EXxmmdw { OP_EX, xmmdw_mode } |
407 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 408 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 409 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 410 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
411 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
412 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
413 | #define MS { OP_MS, v_mode } |
414 | #define XS { OP_XS, v_mode } | |
09335d05 | 415 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 416 | #define MXC { OP_MXC, 0 } |
ce518a5f | 417 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 418 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 419 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 420 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
421 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
422 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 423 | |
c0f3af97 | 424 | #define Vex { OP_VEX, vex_mode } |
539f890d | 425 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 426 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
427 | #define Vex128 { OP_VEX, vex128_mode } |
428 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 429 | #define VexGdq { OP_VEX, dq_mode } |
c0f3af97 | 430 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 431 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 432 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 433 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 434 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 435 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
436 | #define EXVexW { OP_EX_VexW, x_mode } |
437 | #define EXdVexW { OP_EX_VexW, d_mode } | |
438 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 439 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 440 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 441 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 442 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
443 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
444 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
445 | #define VZERO { VZERO_Fixup, 0 } | |
446 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e | 447 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 448 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
449 | |
450 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 451 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
452 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
453 | ||
454 | #define XMask { OP_Mask, mask_mode } | |
455 | #define MaskG { OP_G, mask_mode } | |
456 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 457 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
458 | #define MaskR { OP_R, mask_mode } |
459 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 460 | |
6c30d220 | 461 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 462 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 463 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 464 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 465 | |
35c52694 | 466 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
467 | #define Xbr { REP_Fixup, eSI_reg } |
468 | #define Xvr { REP_Fixup, eSI_reg } | |
469 | #define Ybr { REP_Fixup, eDI_reg } | |
470 | #define Yvr { REP_Fixup, eDI_reg } | |
471 | #define Yzr { REP_Fixup, eDI_reg } | |
472 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
473 | #define ALr { REP_Fixup, al_reg } | |
474 | #define eAXr { REP_Fixup, eAX_reg } | |
475 | ||
42164a71 L |
476 | /* Used handle HLE prefix for lockable instructions. */ |
477 | #define Ebh1 { HLE_Fixup1, b_mode } | |
478 | #define Evh1 { HLE_Fixup1, v_mode } | |
479 | #define Ebh2 { HLE_Fixup2, b_mode } | |
480 | #define Evh2 { HLE_Fixup2, v_mode } | |
481 | #define Ebh3 { HLE_Fixup3, b_mode } | |
482 | #define Evh3 { HLE_Fixup3, v_mode } | |
483 | ||
7e8b059b | 484 | #define BND { BND_Fixup, 0 } |
04ef582a | 485 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 486 | |
ce518a5f L |
487 | #define cond_jump_flag { NULL, cond_jump_mode } |
488 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 489 | |
252b5132 | 490 | /* bits in sizeflag */ |
252b5132 | 491 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
492 | #define AFLAG 2 |
493 | #define DFLAG 1 | |
494 | ||
51e7da1b L |
495 | enum |
496 | { | |
497 | /* byte operand */ | |
498 | b_mode = 1, | |
499 | /* byte operand with operand swapped */ | |
3873ba12 | 500 | b_swap_mode, |
e3949f17 L |
501 | /* byte operand, sign extend like 'T' suffix */ |
502 | b_T_mode, | |
51e7da1b | 503 | /* operand size depends on prefixes */ |
3873ba12 | 504 | v_mode, |
51e7da1b | 505 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 506 | v_swap_mode, |
de89d0a3 IT |
507 | /* operand size depends on address prefix */ |
508 | va_mode, | |
51e7da1b | 509 | /* word operand */ |
3873ba12 | 510 | w_mode, |
51e7da1b | 511 | /* double word operand */ |
3873ba12 | 512 | d_mode, |
51e7da1b | 513 | /* double word operand with operand swapped */ |
3873ba12 | 514 | d_swap_mode, |
51e7da1b | 515 | /* quad word operand */ |
3873ba12 | 516 | q_mode, |
51e7da1b | 517 | /* quad word operand with operand swapped */ |
3873ba12 | 518 | q_swap_mode, |
51e7da1b | 519 | /* ten-byte operand */ |
3873ba12 | 520 | t_mode, |
43234a1e L |
521 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
522 | broadcast enabled. */ | |
3873ba12 | 523 | x_mode, |
43234a1e L |
524 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
525 | evex_x_gscat_mode, | |
526 | /* Similar to x_mode, but with disabled broadcast. */ | |
527 | evex_x_nobcst_mode, | |
528 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
529 | in EVEX. */ | |
3873ba12 | 530 | x_swap_mode, |
51e7da1b | 531 | /* 16-byte XMM operand */ |
3873ba12 | 532 | xmm_mode, |
43234a1e L |
533 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
534 | memory operand (depending on vector length). Broadcast isn't | |
535 | allowed. */ | |
3873ba12 | 536 | xmmq_mode, |
43234a1e L |
537 | /* Same as xmmq_mode, but broadcast is allowed. */ |
538 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
539 | /* XMM register or byte memory operand */ |
540 | xmm_mb_mode, | |
541 | /* XMM register or word memory operand */ | |
542 | xmm_mw_mode, | |
543 | /* XMM register or double word memory operand */ | |
544 | xmm_md_mode, | |
545 | /* XMM register or quad word memory operand */ | |
546 | xmm_mq_mode, | |
43234a1e L |
547 | /* XMM register or double/quad word memory operand, depending on |
548 | VEX.W. */ | |
549 | xmm_mdq_mode, | |
550 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 551 | xmmdw_mode, |
43234a1e | 552 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 553 | xmmqd_mode, |
43234a1e L |
554 | /* 32-byte YMM operand */ |
555 | ymm_mode, | |
556 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 557 | ymmq_mode, |
6c30d220 L |
558 | /* 32-byte YMM or 16-byte word operand */ |
559 | ymmxmm_mode, | |
51e7da1b | 560 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 561 | m_mode, |
51e7da1b | 562 | /* pair of v_mode operands */ |
3873ba12 L |
563 | a_mode, |
564 | cond_jump_mode, | |
565 | loop_jcxz_mode, | |
7e8b059b | 566 | v_bnd_mode, |
d276ec69 JB |
567 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
568 | v_bndmk_mode, | |
51e7da1b | 569 | /* operand size depends on REX prefixes. */ |
3873ba12 | 570 | dq_mode, |
51e7da1b | 571 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 572 | dqw_mode, |
9f79e886 | 573 | /* bounds operand */ |
7e8b059b | 574 | bnd_mode, |
9f79e886 JB |
575 | /* bounds operand with operand swapped */ |
576 | bnd_swap_mode, | |
51e7da1b | 577 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
578 | f_mode, |
579 | const_1_mode, | |
07f5af7d L |
580 | /* v_mode for indirect branch opcodes. */ |
581 | indir_v_mode, | |
51e7da1b | 582 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 583 | stack_v_mode, |
51e7da1b | 584 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 585 | z_mode, |
51e7da1b | 586 | /* 16-byte operand */ |
3873ba12 | 587 | o_mode, |
51e7da1b | 588 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 589 | dqb_mode, |
1ba585e8 IT |
590 | /* registers like d_mode, memory like b_mode. */ |
591 | db_mode, | |
592 | /* registers like d_mode, memory like w_mode. */ | |
593 | dw_mode, | |
51e7da1b | 594 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 595 | dqd_mode, |
d20dee9e L |
596 | /* operand size depends on the W bit as well as address mode. */ |
597 | dqa_mode, | |
51e7da1b | 598 | /* normal vex mode */ |
3873ba12 | 599 | vex_mode, |
51e7da1b | 600 | /* 128bit vex mode */ |
3873ba12 | 601 | vex128_mode, |
51e7da1b | 602 | /* 256bit vex mode */ |
3873ba12 | 603 | vex256_mode, |
51e7da1b | 604 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 605 | vex_w_dq_mode, |
d55ee72f | 606 | |
6c30d220 L |
607 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
608 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
609 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
610 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
611 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
612 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
613 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
614 | vex_vsib_q_w_d_mode, | |
6c30d220 | 615 | |
539f890d L |
616 | /* scalar, ignore vector length. */ |
617 | scalar_mode, | |
53467f57 IT |
618 | /* like b_mode, ignore vector length. */ |
619 | b_scalar_mode, | |
620 | /* like w_mode, ignore vector length. */ | |
621 | w_scalar_mode, | |
539f890d L |
622 | /* like d_mode, ignore vector length. */ |
623 | d_scalar_mode, | |
624 | /* like d_swap_mode, ignore vector length. */ | |
625 | d_scalar_swap_mode, | |
626 | /* like q_mode, ignore vector length. */ | |
627 | q_scalar_mode, | |
628 | /* like q_swap_mode, ignore vector length. */ | |
629 | q_scalar_swap_mode, | |
630 | /* like vex_mode, ignore vector length. */ | |
631 | vex_scalar_mode, | |
1c480963 L |
632 | /* like vex_w_dq_mode, ignore vector length. */ |
633 | vex_scalar_w_dq_mode, | |
539f890d | 634 | |
43234a1e L |
635 | /* Static rounding. */ |
636 | evex_rounding_mode, | |
70df6fc9 L |
637 | /* Static rounding, 64-bit mode only. */ |
638 | evex_rounding_64_mode, | |
43234a1e L |
639 | /* Supress all exceptions. */ |
640 | evex_sae_mode, | |
641 | ||
642 | /* Mask register operand. */ | |
643 | mask_mode, | |
1ba585e8 IT |
644 | /* Mask register operand. */ |
645 | mask_bd_mode, | |
43234a1e | 646 | |
3873ba12 L |
647 | es_reg, |
648 | cs_reg, | |
649 | ss_reg, | |
650 | ds_reg, | |
651 | fs_reg, | |
652 | gs_reg, | |
d55ee72f | 653 | |
3873ba12 L |
654 | eAX_reg, |
655 | eCX_reg, | |
656 | eDX_reg, | |
657 | eBX_reg, | |
658 | eSP_reg, | |
659 | eBP_reg, | |
660 | eSI_reg, | |
661 | eDI_reg, | |
d55ee72f | 662 | |
3873ba12 L |
663 | al_reg, |
664 | cl_reg, | |
665 | dl_reg, | |
666 | bl_reg, | |
667 | ah_reg, | |
668 | ch_reg, | |
669 | dh_reg, | |
670 | bh_reg, | |
d55ee72f | 671 | |
3873ba12 L |
672 | ax_reg, |
673 | cx_reg, | |
674 | dx_reg, | |
675 | bx_reg, | |
676 | sp_reg, | |
677 | bp_reg, | |
678 | si_reg, | |
679 | di_reg, | |
d55ee72f | 680 | |
3873ba12 L |
681 | rAX_reg, |
682 | rCX_reg, | |
683 | rDX_reg, | |
684 | rBX_reg, | |
685 | rSP_reg, | |
686 | rBP_reg, | |
687 | rSI_reg, | |
688 | rDI_reg, | |
d55ee72f | 689 | |
3873ba12 L |
690 | z_mode_ax_reg, |
691 | indir_dx_reg | |
51e7da1b | 692 | }; |
252b5132 | 693 | |
51e7da1b L |
694 | enum |
695 | { | |
696 | FLOATCODE = 1, | |
3873ba12 L |
697 | USE_REG_TABLE, |
698 | USE_MOD_TABLE, | |
699 | USE_RM_TABLE, | |
700 | USE_PREFIX_TABLE, | |
701 | USE_X86_64_TABLE, | |
702 | USE_3BYTE_TABLE, | |
f88c9eb0 | 703 | USE_XOP_8F_TABLE, |
3873ba12 L |
704 | USE_VEX_C4_TABLE, |
705 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 706 | USE_VEX_LEN_TABLE, |
43234a1e L |
707 | USE_VEX_W_TABLE, |
708 | USE_EVEX_TABLE | |
51e7da1b | 709 | }; |
6439fc28 | 710 | |
bf890a93 | 711 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 712 | |
bf890a93 IT |
713 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
714 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
715 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
716 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
717 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
718 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
719 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
720 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 721 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 722 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
723 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
724 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
725 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 726 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 727 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 728 | |
51e7da1b L |
729 | enum |
730 | { | |
731 | REG_80 = 0, | |
3873ba12 | 732 | REG_81, |
7148c369 | 733 | REG_83, |
3873ba12 L |
734 | REG_8F, |
735 | REG_C0, | |
736 | REG_C1, | |
737 | REG_C6, | |
738 | REG_C7, | |
739 | REG_D0, | |
740 | REG_D1, | |
741 | REG_D2, | |
742 | REG_D3, | |
743 | REG_F6, | |
744 | REG_F7, | |
745 | REG_FE, | |
746 | REG_FF, | |
747 | REG_0F00, | |
748 | REG_0F01, | |
749 | REG_0F0D, | |
750 | REG_0F18, | |
c48935d7 | 751 | REG_0F1C_MOD_0, |
603555e5 | 752 | REG_0F1E_MOD_3, |
3873ba12 L |
753 | REG_0F71, |
754 | REG_0F72, | |
755 | REG_0F73, | |
756 | REG_0FA6, | |
757 | REG_0FA7, | |
758 | REG_0FAE, | |
759 | REG_0FBA, | |
760 | REG_0FC7, | |
592a252b L |
761 | REG_VEX_0F71, |
762 | REG_VEX_0F72, | |
763 | REG_VEX_0F73, | |
764 | REG_VEX_0FAE, | |
f12dc422 | 765 | REG_VEX_0F38F3, |
f88c9eb0 | 766 | REG_XOP_LWPCB, |
2a2a0f38 QN |
767 | REG_XOP_LWP, |
768 | REG_XOP_TBM_01, | |
43234a1e L |
769 | REG_XOP_TBM_02, |
770 | ||
1ba585e8 | 771 | REG_EVEX_0F71, |
43234a1e L |
772 | REG_EVEX_0F72, |
773 | REG_EVEX_0F73, | |
774 | REG_EVEX_0F38C6, | |
775 | REG_EVEX_0F38C7 | |
51e7da1b | 776 | }; |
1ceb70f8 | 777 | |
51e7da1b L |
778 | enum |
779 | { | |
780 | MOD_8D = 0, | |
42164a71 L |
781 | MOD_C6_REG_7, |
782 | MOD_C7_REG_7, | |
4a357820 MZ |
783 | MOD_FF_REG_3, |
784 | MOD_FF_REG_5, | |
3873ba12 L |
785 | MOD_0F01_REG_0, |
786 | MOD_0F01_REG_1, | |
787 | MOD_0F01_REG_2, | |
788 | MOD_0F01_REG_3, | |
8eab4136 | 789 | MOD_0F01_REG_5, |
3873ba12 L |
790 | MOD_0F01_REG_7, |
791 | MOD_0F12_PREFIX_0, | |
792 | MOD_0F13, | |
793 | MOD_0F16_PREFIX_0, | |
794 | MOD_0F17, | |
795 | MOD_0F18_REG_0, | |
796 | MOD_0F18_REG_1, | |
797 | MOD_0F18_REG_2, | |
798 | MOD_0F18_REG_3, | |
d7189fa5 RM |
799 | MOD_0F18_REG_4, |
800 | MOD_0F18_REG_5, | |
801 | MOD_0F18_REG_6, | |
802 | MOD_0F18_REG_7, | |
7e8b059b L |
803 | MOD_0F1A_PREFIX_0, |
804 | MOD_0F1B_PREFIX_0, | |
805 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 806 | MOD_0F1C_PREFIX_0, |
603555e5 | 807 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
808 | MOD_0F24, |
809 | MOD_0F26, | |
810 | MOD_0F2B_PREFIX_0, | |
811 | MOD_0F2B_PREFIX_1, | |
812 | MOD_0F2B_PREFIX_2, | |
813 | MOD_0F2B_PREFIX_3, | |
814 | MOD_0F51, | |
815 | MOD_0F71_REG_2, | |
816 | MOD_0F71_REG_4, | |
817 | MOD_0F71_REG_6, | |
818 | MOD_0F72_REG_2, | |
819 | MOD_0F72_REG_4, | |
820 | MOD_0F72_REG_6, | |
821 | MOD_0F73_REG_2, | |
822 | MOD_0F73_REG_3, | |
823 | MOD_0F73_REG_6, | |
824 | MOD_0F73_REG_7, | |
825 | MOD_0FAE_REG_0, | |
826 | MOD_0FAE_REG_1, | |
827 | MOD_0FAE_REG_2, | |
828 | MOD_0FAE_REG_3, | |
829 | MOD_0FAE_REG_4, | |
830 | MOD_0FAE_REG_5, | |
831 | MOD_0FAE_REG_6, | |
832 | MOD_0FAE_REG_7, | |
833 | MOD_0FB2, | |
834 | MOD_0FB4, | |
835 | MOD_0FB5, | |
a8484f96 | 836 | MOD_0FC3, |
963f3586 IT |
837 | MOD_0FC7_REG_3, |
838 | MOD_0FC7_REG_4, | |
839 | MOD_0FC7_REG_5, | |
3873ba12 L |
840 | MOD_0FC7_REG_6, |
841 | MOD_0FC7_REG_7, | |
842 | MOD_0FD7, | |
843 | MOD_0FE7_PREFIX_2, | |
844 | MOD_0FF0_PREFIX_3, | |
845 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
846 | MOD_0F38F5_PREFIX_2, |
847 | MOD_0F38F6_PREFIX_0, | |
c0a30a9f L |
848 | MOD_0F38F8_PREFIX_2, |
849 | MOD_0F38F9_PREFIX_0, | |
3873ba12 L |
850 | MOD_62_32BIT, |
851 | MOD_C4_32BIT, | |
852 | MOD_C5_32BIT, | |
592a252b L |
853 | MOD_VEX_0F12_PREFIX_0, |
854 | MOD_VEX_0F13, | |
855 | MOD_VEX_0F16_PREFIX_0, | |
856 | MOD_VEX_0F17, | |
857 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
858 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
859 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
860 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
861 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
862 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
863 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
864 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
865 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
866 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
867 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
868 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
869 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
870 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
871 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
872 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
873 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
874 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
875 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
876 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
877 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
878 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
879 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
880 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
881 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
882 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
883 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
884 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
885 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
886 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
887 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
888 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
889 | MOD_VEX_0F50, |
890 | MOD_VEX_0F71_REG_2, | |
891 | MOD_VEX_0F71_REG_4, | |
892 | MOD_VEX_0F71_REG_6, | |
893 | MOD_VEX_0F72_REG_2, | |
894 | MOD_VEX_0F72_REG_4, | |
895 | MOD_VEX_0F72_REG_6, | |
896 | MOD_VEX_0F73_REG_2, | |
897 | MOD_VEX_0F73_REG_3, | |
898 | MOD_VEX_0F73_REG_6, | |
899 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
900 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
901 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
902 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
903 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
904 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
905 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
906 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
907 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
908 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
909 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
910 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
911 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
912 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
913 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
914 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
915 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
916 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
917 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
918 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
919 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
920 | MOD_VEX_0FAE_REG_2, |
921 | MOD_VEX_0FAE_REG_3, | |
922 | MOD_VEX_0FD7_PREFIX_2, | |
923 | MOD_VEX_0FE7_PREFIX_2, | |
924 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
925 | MOD_VEX_0F381A_PREFIX_2, |
926 | MOD_VEX_0F382A_PREFIX_2, | |
927 | MOD_VEX_0F382C_PREFIX_2, | |
928 | MOD_VEX_0F382D_PREFIX_2, | |
929 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
930 | MOD_VEX_0F382F_PREFIX_2, |
931 | MOD_VEX_0F385A_PREFIX_2, | |
932 | MOD_VEX_0F388C_PREFIX_2, | |
933 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
934 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
935 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
936 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
937 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
938 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
939 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
940 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
941 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
942 | |
943 | MOD_EVEX_0F10_PREFIX_1, | |
944 | MOD_EVEX_0F10_PREFIX_3, | |
945 | MOD_EVEX_0F11_PREFIX_1, | |
946 | MOD_EVEX_0F11_PREFIX_3, | |
947 | MOD_EVEX_0F12_PREFIX_0, | |
948 | MOD_EVEX_0F16_PREFIX_0, | |
949 | MOD_EVEX_0F38C6_REG_1, | |
950 | MOD_EVEX_0F38C6_REG_2, | |
951 | MOD_EVEX_0F38C6_REG_5, | |
952 | MOD_EVEX_0F38C6_REG_6, | |
953 | MOD_EVEX_0F38C7_REG_1, | |
954 | MOD_EVEX_0F38C7_REG_2, | |
955 | MOD_EVEX_0F38C7_REG_5, | |
956 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 957 | }; |
1ceb70f8 | 958 | |
51e7da1b L |
959 | enum |
960 | { | |
42164a71 L |
961 | RM_C6_REG_7 = 0, |
962 | RM_C7_REG_7, | |
963 | RM_0F01_REG_0, | |
3873ba12 L |
964 | RM_0F01_REG_1, |
965 | RM_0F01_REG_2, | |
966 | RM_0F01_REG_3, | |
8eab4136 | 967 | RM_0F01_REG_5, |
3873ba12 | 968 | RM_0F01_REG_7, |
603555e5 | 969 | RM_0F1E_MOD_3_REG_7, |
3873ba12 L |
970 | RM_0FAE_REG_6, |
971 | RM_0FAE_REG_7 | |
51e7da1b | 972 | }; |
1ceb70f8 | 973 | |
51e7da1b L |
974 | enum |
975 | { | |
976 | PREFIX_90 = 0, | |
603555e5 | 977 | PREFIX_MOD_0_0F01_REG_5, |
2234eee6 | 978 | PREFIX_MOD_3_0F01_REG_5_RM_0, |
603555e5 | 979 | PREFIX_MOD_3_0F01_REG_5_RM_2, |
3233d7d0 | 980 | PREFIX_0F09, |
3873ba12 L |
981 | PREFIX_0F10, |
982 | PREFIX_0F11, | |
983 | PREFIX_0F12, | |
984 | PREFIX_0F16, | |
7e8b059b L |
985 | PREFIX_0F1A, |
986 | PREFIX_0F1B, | |
c48935d7 | 987 | PREFIX_0F1C, |
603555e5 | 988 | PREFIX_0F1E, |
3873ba12 L |
989 | PREFIX_0F2A, |
990 | PREFIX_0F2B, | |
991 | PREFIX_0F2C, | |
992 | PREFIX_0F2D, | |
993 | PREFIX_0F2E, | |
994 | PREFIX_0F2F, | |
995 | PREFIX_0F51, | |
996 | PREFIX_0F52, | |
997 | PREFIX_0F53, | |
998 | PREFIX_0F58, | |
999 | PREFIX_0F59, | |
1000 | PREFIX_0F5A, | |
1001 | PREFIX_0F5B, | |
1002 | PREFIX_0F5C, | |
1003 | PREFIX_0F5D, | |
1004 | PREFIX_0F5E, | |
1005 | PREFIX_0F5F, | |
1006 | PREFIX_0F60, | |
1007 | PREFIX_0F61, | |
1008 | PREFIX_0F62, | |
1009 | PREFIX_0F6C, | |
1010 | PREFIX_0F6D, | |
1011 | PREFIX_0F6F, | |
1012 | PREFIX_0F70, | |
1013 | PREFIX_0F73_REG_3, | |
1014 | PREFIX_0F73_REG_7, | |
1015 | PREFIX_0F78, | |
1016 | PREFIX_0F79, | |
1017 | PREFIX_0F7C, | |
1018 | PREFIX_0F7D, | |
1019 | PREFIX_0F7E, | |
1020 | PREFIX_0F7F, | |
c7b8aa3a L |
1021 | PREFIX_0FAE_REG_0, |
1022 | PREFIX_0FAE_REG_1, | |
1023 | PREFIX_0FAE_REG_2, | |
1024 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
1025 | PREFIX_MOD_0_0FAE_REG_4, |
1026 | PREFIX_MOD_3_0FAE_REG_4, | |
603555e5 | 1027 | PREFIX_MOD_0_0FAE_REG_5, |
2234eee6 | 1028 | PREFIX_MOD_3_0FAE_REG_5, |
de89d0a3 IT |
1029 | PREFIX_MOD_0_0FAE_REG_6, |
1030 | PREFIX_MOD_1_0FAE_REG_6, | |
963f3586 | 1031 | PREFIX_0FAE_REG_7, |
3873ba12 | 1032 | PREFIX_0FB8, |
f12dc422 | 1033 | PREFIX_0FBC, |
3873ba12 L |
1034 | PREFIX_0FBD, |
1035 | PREFIX_0FC2, | |
a8484f96 | 1036 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
1037 | PREFIX_MOD_0_0FC7_REG_6, |
1038 | PREFIX_MOD_3_0FC7_REG_6, | |
1039 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1040 | PREFIX_0FD0, |
1041 | PREFIX_0FD6, | |
1042 | PREFIX_0FE6, | |
1043 | PREFIX_0FE7, | |
1044 | PREFIX_0FF0, | |
1045 | PREFIX_0FF7, | |
1046 | PREFIX_0F3810, | |
1047 | PREFIX_0F3814, | |
1048 | PREFIX_0F3815, | |
1049 | PREFIX_0F3817, | |
1050 | PREFIX_0F3820, | |
1051 | PREFIX_0F3821, | |
1052 | PREFIX_0F3822, | |
1053 | PREFIX_0F3823, | |
1054 | PREFIX_0F3824, | |
1055 | PREFIX_0F3825, | |
1056 | PREFIX_0F3828, | |
1057 | PREFIX_0F3829, | |
1058 | PREFIX_0F382A, | |
1059 | PREFIX_0F382B, | |
1060 | PREFIX_0F3830, | |
1061 | PREFIX_0F3831, | |
1062 | PREFIX_0F3832, | |
1063 | PREFIX_0F3833, | |
1064 | PREFIX_0F3834, | |
1065 | PREFIX_0F3835, | |
1066 | PREFIX_0F3837, | |
1067 | PREFIX_0F3838, | |
1068 | PREFIX_0F3839, | |
1069 | PREFIX_0F383A, | |
1070 | PREFIX_0F383B, | |
1071 | PREFIX_0F383C, | |
1072 | PREFIX_0F383D, | |
1073 | PREFIX_0F383E, | |
1074 | PREFIX_0F383F, | |
1075 | PREFIX_0F3840, | |
1076 | PREFIX_0F3841, | |
1077 | PREFIX_0F3880, | |
1078 | PREFIX_0F3881, | |
6c30d220 | 1079 | PREFIX_0F3882, |
a0046408 L |
1080 | PREFIX_0F38C8, |
1081 | PREFIX_0F38C9, | |
1082 | PREFIX_0F38CA, | |
1083 | PREFIX_0F38CB, | |
1084 | PREFIX_0F38CC, | |
1085 | PREFIX_0F38CD, | |
48521003 | 1086 | PREFIX_0F38CF, |
3873ba12 L |
1087 | PREFIX_0F38DB, |
1088 | PREFIX_0F38DC, | |
1089 | PREFIX_0F38DD, | |
1090 | PREFIX_0F38DE, | |
1091 | PREFIX_0F38DF, | |
1092 | PREFIX_0F38F0, | |
1093 | PREFIX_0F38F1, | |
603555e5 | 1094 | PREFIX_0F38F5, |
e2e1fcde | 1095 | PREFIX_0F38F6, |
c0a30a9f L |
1096 | PREFIX_0F38F8, |
1097 | PREFIX_0F38F9, | |
3873ba12 L |
1098 | PREFIX_0F3A08, |
1099 | PREFIX_0F3A09, | |
1100 | PREFIX_0F3A0A, | |
1101 | PREFIX_0F3A0B, | |
1102 | PREFIX_0F3A0C, | |
1103 | PREFIX_0F3A0D, | |
1104 | PREFIX_0F3A0E, | |
1105 | PREFIX_0F3A14, | |
1106 | PREFIX_0F3A15, | |
1107 | PREFIX_0F3A16, | |
1108 | PREFIX_0F3A17, | |
1109 | PREFIX_0F3A20, | |
1110 | PREFIX_0F3A21, | |
1111 | PREFIX_0F3A22, | |
1112 | PREFIX_0F3A40, | |
1113 | PREFIX_0F3A41, | |
1114 | PREFIX_0F3A42, | |
1115 | PREFIX_0F3A44, | |
1116 | PREFIX_0F3A60, | |
1117 | PREFIX_0F3A61, | |
1118 | PREFIX_0F3A62, | |
1119 | PREFIX_0F3A63, | |
a0046408 | 1120 | PREFIX_0F3ACC, |
48521003 IT |
1121 | PREFIX_0F3ACE, |
1122 | PREFIX_0F3ACF, | |
3873ba12 | 1123 | PREFIX_0F3ADF, |
592a252b L |
1124 | PREFIX_VEX_0F10, |
1125 | PREFIX_VEX_0F11, | |
1126 | PREFIX_VEX_0F12, | |
1127 | PREFIX_VEX_0F16, | |
1128 | PREFIX_VEX_0F2A, | |
1129 | PREFIX_VEX_0F2C, | |
1130 | PREFIX_VEX_0F2D, | |
1131 | PREFIX_VEX_0F2E, | |
1132 | PREFIX_VEX_0F2F, | |
43234a1e L |
1133 | PREFIX_VEX_0F41, |
1134 | PREFIX_VEX_0F42, | |
1135 | PREFIX_VEX_0F44, | |
1136 | PREFIX_VEX_0F45, | |
1137 | PREFIX_VEX_0F46, | |
1138 | PREFIX_VEX_0F47, | |
1ba585e8 | 1139 | PREFIX_VEX_0F4A, |
43234a1e | 1140 | PREFIX_VEX_0F4B, |
592a252b L |
1141 | PREFIX_VEX_0F51, |
1142 | PREFIX_VEX_0F52, | |
1143 | PREFIX_VEX_0F53, | |
1144 | PREFIX_VEX_0F58, | |
1145 | PREFIX_VEX_0F59, | |
1146 | PREFIX_VEX_0F5A, | |
1147 | PREFIX_VEX_0F5B, | |
1148 | PREFIX_VEX_0F5C, | |
1149 | PREFIX_VEX_0F5D, | |
1150 | PREFIX_VEX_0F5E, | |
1151 | PREFIX_VEX_0F5F, | |
1152 | PREFIX_VEX_0F60, | |
1153 | PREFIX_VEX_0F61, | |
1154 | PREFIX_VEX_0F62, | |
1155 | PREFIX_VEX_0F63, | |
1156 | PREFIX_VEX_0F64, | |
1157 | PREFIX_VEX_0F65, | |
1158 | PREFIX_VEX_0F66, | |
1159 | PREFIX_VEX_0F67, | |
1160 | PREFIX_VEX_0F68, | |
1161 | PREFIX_VEX_0F69, | |
1162 | PREFIX_VEX_0F6A, | |
1163 | PREFIX_VEX_0F6B, | |
1164 | PREFIX_VEX_0F6C, | |
1165 | PREFIX_VEX_0F6D, | |
1166 | PREFIX_VEX_0F6E, | |
1167 | PREFIX_VEX_0F6F, | |
1168 | PREFIX_VEX_0F70, | |
1169 | PREFIX_VEX_0F71_REG_2, | |
1170 | PREFIX_VEX_0F71_REG_4, | |
1171 | PREFIX_VEX_0F71_REG_6, | |
1172 | PREFIX_VEX_0F72_REG_2, | |
1173 | PREFIX_VEX_0F72_REG_4, | |
1174 | PREFIX_VEX_0F72_REG_6, | |
1175 | PREFIX_VEX_0F73_REG_2, | |
1176 | PREFIX_VEX_0F73_REG_3, | |
1177 | PREFIX_VEX_0F73_REG_6, | |
1178 | PREFIX_VEX_0F73_REG_7, | |
1179 | PREFIX_VEX_0F74, | |
1180 | PREFIX_VEX_0F75, | |
1181 | PREFIX_VEX_0F76, | |
1182 | PREFIX_VEX_0F77, | |
1183 | PREFIX_VEX_0F7C, | |
1184 | PREFIX_VEX_0F7D, | |
1185 | PREFIX_VEX_0F7E, | |
1186 | PREFIX_VEX_0F7F, | |
43234a1e L |
1187 | PREFIX_VEX_0F90, |
1188 | PREFIX_VEX_0F91, | |
1189 | PREFIX_VEX_0F92, | |
1190 | PREFIX_VEX_0F93, | |
1191 | PREFIX_VEX_0F98, | |
1ba585e8 | 1192 | PREFIX_VEX_0F99, |
592a252b L |
1193 | PREFIX_VEX_0FC2, |
1194 | PREFIX_VEX_0FC4, | |
1195 | PREFIX_VEX_0FC5, | |
1196 | PREFIX_VEX_0FD0, | |
1197 | PREFIX_VEX_0FD1, | |
1198 | PREFIX_VEX_0FD2, | |
1199 | PREFIX_VEX_0FD3, | |
1200 | PREFIX_VEX_0FD4, | |
1201 | PREFIX_VEX_0FD5, | |
1202 | PREFIX_VEX_0FD6, | |
1203 | PREFIX_VEX_0FD7, | |
1204 | PREFIX_VEX_0FD8, | |
1205 | PREFIX_VEX_0FD9, | |
1206 | PREFIX_VEX_0FDA, | |
1207 | PREFIX_VEX_0FDB, | |
1208 | PREFIX_VEX_0FDC, | |
1209 | PREFIX_VEX_0FDD, | |
1210 | PREFIX_VEX_0FDE, | |
1211 | PREFIX_VEX_0FDF, | |
1212 | PREFIX_VEX_0FE0, | |
1213 | PREFIX_VEX_0FE1, | |
1214 | PREFIX_VEX_0FE2, | |
1215 | PREFIX_VEX_0FE3, | |
1216 | PREFIX_VEX_0FE4, | |
1217 | PREFIX_VEX_0FE5, | |
1218 | PREFIX_VEX_0FE6, | |
1219 | PREFIX_VEX_0FE7, | |
1220 | PREFIX_VEX_0FE8, | |
1221 | PREFIX_VEX_0FE9, | |
1222 | PREFIX_VEX_0FEA, | |
1223 | PREFIX_VEX_0FEB, | |
1224 | PREFIX_VEX_0FEC, | |
1225 | PREFIX_VEX_0FED, | |
1226 | PREFIX_VEX_0FEE, | |
1227 | PREFIX_VEX_0FEF, | |
1228 | PREFIX_VEX_0FF0, | |
1229 | PREFIX_VEX_0FF1, | |
1230 | PREFIX_VEX_0FF2, | |
1231 | PREFIX_VEX_0FF3, | |
1232 | PREFIX_VEX_0FF4, | |
1233 | PREFIX_VEX_0FF5, | |
1234 | PREFIX_VEX_0FF6, | |
1235 | PREFIX_VEX_0FF7, | |
1236 | PREFIX_VEX_0FF8, | |
1237 | PREFIX_VEX_0FF9, | |
1238 | PREFIX_VEX_0FFA, | |
1239 | PREFIX_VEX_0FFB, | |
1240 | PREFIX_VEX_0FFC, | |
1241 | PREFIX_VEX_0FFD, | |
1242 | PREFIX_VEX_0FFE, | |
1243 | PREFIX_VEX_0F3800, | |
1244 | PREFIX_VEX_0F3801, | |
1245 | PREFIX_VEX_0F3802, | |
1246 | PREFIX_VEX_0F3803, | |
1247 | PREFIX_VEX_0F3804, | |
1248 | PREFIX_VEX_0F3805, | |
1249 | PREFIX_VEX_0F3806, | |
1250 | PREFIX_VEX_0F3807, | |
1251 | PREFIX_VEX_0F3808, | |
1252 | PREFIX_VEX_0F3809, | |
1253 | PREFIX_VEX_0F380A, | |
1254 | PREFIX_VEX_0F380B, | |
1255 | PREFIX_VEX_0F380C, | |
1256 | PREFIX_VEX_0F380D, | |
1257 | PREFIX_VEX_0F380E, | |
1258 | PREFIX_VEX_0F380F, | |
1259 | PREFIX_VEX_0F3813, | |
6c30d220 | 1260 | PREFIX_VEX_0F3816, |
592a252b L |
1261 | PREFIX_VEX_0F3817, |
1262 | PREFIX_VEX_0F3818, | |
1263 | PREFIX_VEX_0F3819, | |
1264 | PREFIX_VEX_0F381A, | |
1265 | PREFIX_VEX_0F381C, | |
1266 | PREFIX_VEX_0F381D, | |
1267 | PREFIX_VEX_0F381E, | |
1268 | PREFIX_VEX_0F3820, | |
1269 | PREFIX_VEX_0F3821, | |
1270 | PREFIX_VEX_0F3822, | |
1271 | PREFIX_VEX_0F3823, | |
1272 | PREFIX_VEX_0F3824, | |
1273 | PREFIX_VEX_0F3825, | |
1274 | PREFIX_VEX_0F3828, | |
1275 | PREFIX_VEX_0F3829, | |
1276 | PREFIX_VEX_0F382A, | |
1277 | PREFIX_VEX_0F382B, | |
1278 | PREFIX_VEX_0F382C, | |
1279 | PREFIX_VEX_0F382D, | |
1280 | PREFIX_VEX_0F382E, | |
1281 | PREFIX_VEX_0F382F, | |
1282 | PREFIX_VEX_0F3830, | |
1283 | PREFIX_VEX_0F3831, | |
1284 | PREFIX_VEX_0F3832, | |
1285 | PREFIX_VEX_0F3833, | |
1286 | PREFIX_VEX_0F3834, | |
1287 | PREFIX_VEX_0F3835, | |
6c30d220 | 1288 | PREFIX_VEX_0F3836, |
592a252b L |
1289 | PREFIX_VEX_0F3837, |
1290 | PREFIX_VEX_0F3838, | |
1291 | PREFIX_VEX_0F3839, | |
1292 | PREFIX_VEX_0F383A, | |
1293 | PREFIX_VEX_0F383B, | |
1294 | PREFIX_VEX_0F383C, | |
1295 | PREFIX_VEX_0F383D, | |
1296 | PREFIX_VEX_0F383E, | |
1297 | PREFIX_VEX_0F383F, | |
1298 | PREFIX_VEX_0F3840, | |
1299 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1300 | PREFIX_VEX_0F3845, |
1301 | PREFIX_VEX_0F3846, | |
1302 | PREFIX_VEX_0F3847, | |
1303 | PREFIX_VEX_0F3858, | |
1304 | PREFIX_VEX_0F3859, | |
1305 | PREFIX_VEX_0F385A, | |
1306 | PREFIX_VEX_0F3878, | |
1307 | PREFIX_VEX_0F3879, | |
1308 | PREFIX_VEX_0F388C, | |
1309 | PREFIX_VEX_0F388E, | |
1310 | PREFIX_VEX_0F3890, | |
1311 | PREFIX_VEX_0F3891, | |
1312 | PREFIX_VEX_0F3892, | |
1313 | PREFIX_VEX_0F3893, | |
592a252b L |
1314 | PREFIX_VEX_0F3896, |
1315 | PREFIX_VEX_0F3897, | |
1316 | PREFIX_VEX_0F3898, | |
1317 | PREFIX_VEX_0F3899, | |
1318 | PREFIX_VEX_0F389A, | |
1319 | PREFIX_VEX_0F389B, | |
1320 | PREFIX_VEX_0F389C, | |
1321 | PREFIX_VEX_0F389D, | |
1322 | PREFIX_VEX_0F389E, | |
1323 | PREFIX_VEX_0F389F, | |
1324 | PREFIX_VEX_0F38A6, | |
1325 | PREFIX_VEX_0F38A7, | |
1326 | PREFIX_VEX_0F38A8, | |
1327 | PREFIX_VEX_0F38A9, | |
1328 | PREFIX_VEX_0F38AA, | |
1329 | PREFIX_VEX_0F38AB, | |
1330 | PREFIX_VEX_0F38AC, | |
1331 | PREFIX_VEX_0F38AD, | |
1332 | PREFIX_VEX_0F38AE, | |
1333 | PREFIX_VEX_0F38AF, | |
1334 | PREFIX_VEX_0F38B6, | |
1335 | PREFIX_VEX_0F38B7, | |
1336 | PREFIX_VEX_0F38B8, | |
1337 | PREFIX_VEX_0F38B9, | |
1338 | PREFIX_VEX_0F38BA, | |
1339 | PREFIX_VEX_0F38BB, | |
1340 | PREFIX_VEX_0F38BC, | |
1341 | PREFIX_VEX_0F38BD, | |
1342 | PREFIX_VEX_0F38BE, | |
1343 | PREFIX_VEX_0F38BF, | |
48521003 | 1344 | PREFIX_VEX_0F38CF, |
592a252b L |
1345 | PREFIX_VEX_0F38DB, |
1346 | PREFIX_VEX_0F38DC, | |
1347 | PREFIX_VEX_0F38DD, | |
1348 | PREFIX_VEX_0F38DE, | |
1349 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1350 | PREFIX_VEX_0F38F2, |
1351 | PREFIX_VEX_0F38F3_REG_1, | |
1352 | PREFIX_VEX_0F38F3_REG_2, | |
1353 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1354 | PREFIX_VEX_0F38F5, |
1355 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1356 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1357 | PREFIX_VEX_0F3A00, |
1358 | PREFIX_VEX_0F3A01, | |
1359 | PREFIX_VEX_0F3A02, | |
592a252b L |
1360 | PREFIX_VEX_0F3A04, |
1361 | PREFIX_VEX_0F3A05, | |
1362 | PREFIX_VEX_0F3A06, | |
1363 | PREFIX_VEX_0F3A08, | |
1364 | PREFIX_VEX_0F3A09, | |
1365 | PREFIX_VEX_0F3A0A, | |
1366 | PREFIX_VEX_0F3A0B, | |
1367 | PREFIX_VEX_0F3A0C, | |
1368 | PREFIX_VEX_0F3A0D, | |
1369 | PREFIX_VEX_0F3A0E, | |
1370 | PREFIX_VEX_0F3A0F, | |
1371 | PREFIX_VEX_0F3A14, | |
1372 | PREFIX_VEX_0F3A15, | |
1373 | PREFIX_VEX_0F3A16, | |
1374 | PREFIX_VEX_0F3A17, | |
1375 | PREFIX_VEX_0F3A18, | |
1376 | PREFIX_VEX_0F3A19, | |
1377 | PREFIX_VEX_0F3A1D, | |
1378 | PREFIX_VEX_0F3A20, | |
1379 | PREFIX_VEX_0F3A21, | |
1380 | PREFIX_VEX_0F3A22, | |
43234a1e | 1381 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1382 | PREFIX_VEX_0F3A31, |
43234a1e | 1383 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1384 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1385 | PREFIX_VEX_0F3A38, |
1386 | PREFIX_VEX_0F3A39, | |
592a252b L |
1387 | PREFIX_VEX_0F3A40, |
1388 | PREFIX_VEX_0F3A41, | |
1389 | PREFIX_VEX_0F3A42, | |
1390 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1391 | PREFIX_VEX_0F3A46, |
592a252b L |
1392 | PREFIX_VEX_0F3A48, |
1393 | PREFIX_VEX_0F3A49, | |
1394 | PREFIX_VEX_0F3A4A, | |
1395 | PREFIX_VEX_0F3A4B, | |
1396 | PREFIX_VEX_0F3A4C, | |
1397 | PREFIX_VEX_0F3A5C, | |
1398 | PREFIX_VEX_0F3A5D, | |
1399 | PREFIX_VEX_0F3A5E, | |
1400 | PREFIX_VEX_0F3A5F, | |
1401 | PREFIX_VEX_0F3A60, | |
1402 | PREFIX_VEX_0F3A61, | |
1403 | PREFIX_VEX_0F3A62, | |
1404 | PREFIX_VEX_0F3A63, | |
1405 | PREFIX_VEX_0F3A68, | |
1406 | PREFIX_VEX_0F3A69, | |
1407 | PREFIX_VEX_0F3A6A, | |
1408 | PREFIX_VEX_0F3A6B, | |
1409 | PREFIX_VEX_0F3A6C, | |
1410 | PREFIX_VEX_0F3A6D, | |
1411 | PREFIX_VEX_0F3A6E, | |
1412 | PREFIX_VEX_0F3A6F, | |
1413 | PREFIX_VEX_0F3A78, | |
1414 | PREFIX_VEX_0F3A79, | |
1415 | PREFIX_VEX_0F3A7A, | |
1416 | PREFIX_VEX_0F3A7B, | |
1417 | PREFIX_VEX_0F3A7C, | |
1418 | PREFIX_VEX_0F3A7D, | |
1419 | PREFIX_VEX_0F3A7E, | |
1420 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1421 | PREFIX_VEX_0F3ACE, |
1422 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1423 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1424 | PREFIX_VEX_0F3AF0, |
1425 | ||
1426 | PREFIX_EVEX_0F10, | |
1427 | PREFIX_EVEX_0F11, | |
1428 | PREFIX_EVEX_0F12, | |
1429 | PREFIX_EVEX_0F13, | |
1430 | PREFIX_EVEX_0F14, | |
1431 | PREFIX_EVEX_0F15, | |
1432 | PREFIX_EVEX_0F16, | |
1433 | PREFIX_EVEX_0F17, | |
1434 | PREFIX_EVEX_0F28, | |
1435 | PREFIX_EVEX_0F29, | |
1436 | PREFIX_EVEX_0F2A, | |
1437 | PREFIX_EVEX_0F2B, | |
1438 | PREFIX_EVEX_0F2C, | |
1439 | PREFIX_EVEX_0F2D, | |
1440 | PREFIX_EVEX_0F2E, | |
1441 | PREFIX_EVEX_0F2F, | |
1442 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1443 | PREFIX_EVEX_0F54, |
1444 | PREFIX_EVEX_0F55, | |
1445 | PREFIX_EVEX_0F56, | |
1446 | PREFIX_EVEX_0F57, | |
43234a1e L |
1447 | PREFIX_EVEX_0F58, |
1448 | PREFIX_EVEX_0F59, | |
1449 | PREFIX_EVEX_0F5A, | |
1450 | PREFIX_EVEX_0F5B, | |
1451 | PREFIX_EVEX_0F5C, | |
1452 | PREFIX_EVEX_0F5D, | |
1453 | PREFIX_EVEX_0F5E, | |
1454 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1455 | PREFIX_EVEX_0F60, |
1456 | PREFIX_EVEX_0F61, | |
43234a1e | 1457 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1458 | PREFIX_EVEX_0F63, |
1459 | PREFIX_EVEX_0F64, | |
1460 | PREFIX_EVEX_0F65, | |
43234a1e | 1461 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1462 | PREFIX_EVEX_0F67, |
1463 | PREFIX_EVEX_0F68, | |
1464 | PREFIX_EVEX_0F69, | |
43234a1e | 1465 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1466 | PREFIX_EVEX_0F6B, |
43234a1e L |
1467 | PREFIX_EVEX_0F6C, |
1468 | PREFIX_EVEX_0F6D, | |
1469 | PREFIX_EVEX_0F6E, | |
1470 | PREFIX_EVEX_0F6F, | |
1471 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1472 | PREFIX_EVEX_0F71_REG_2, |
1473 | PREFIX_EVEX_0F71_REG_4, | |
1474 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1475 | PREFIX_EVEX_0F72_REG_0, |
1476 | PREFIX_EVEX_0F72_REG_1, | |
1477 | PREFIX_EVEX_0F72_REG_2, | |
1478 | PREFIX_EVEX_0F72_REG_4, | |
1479 | PREFIX_EVEX_0F72_REG_6, | |
1480 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1481 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1482 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1483 | PREFIX_EVEX_0F73_REG_7, |
1484 | PREFIX_EVEX_0F74, | |
1485 | PREFIX_EVEX_0F75, | |
43234a1e L |
1486 | PREFIX_EVEX_0F76, |
1487 | PREFIX_EVEX_0F78, | |
1488 | PREFIX_EVEX_0F79, | |
1489 | PREFIX_EVEX_0F7A, | |
1490 | PREFIX_EVEX_0F7B, | |
1491 | PREFIX_EVEX_0F7E, | |
1492 | PREFIX_EVEX_0F7F, | |
1493 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1494 | PREFIX_EVEX_0FC4, |
1495 | PREFIX_EVEX_0FC5, | |
43234a1e | 1496 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1497 | PREFIX_EVEX_0FD1, |
43234a1e L |
1498 | PREFIX_EVEX_0FD2, |
1499 | PREFIX_EVEX_0FD3, | |
1500 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1501 | PREFIX_EVEX_0FD5, |
43234a1e | 1502 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1503 | PREFIX_EVEX_0FD8, |
1504 | PREFIX_EVEX_0FD9, | |
1505 | PREFIX_EVEX_0FDA, | |
43234a1e | 1506 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1507 | PREFIX_EVEX_0FDC, |
1508 | PREFIX_EVEX_0FDD, | |
1509 | PREFIX_EVEX_0FDE, | |
43234a1e | 1510 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1511 | PREFIX_EVEX_0FE0, |
1512 | PREFIX_EVEX_0FE1, | |
43234a1e | 1513 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1514 | PREFIX_EVEX_0FE3, |
1515 | PREFIX_EVEX_0FE4, | |
1516 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1517 | PREFIX_EVEX_0FE6, |
1518 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1519 | PREFIX_EVEX_0FE8, |
1520 | PREFIX_EVEX_0FE9, | |
1521 | PREFIX_EVEX_0FEA, | |
43234a1e | 1522 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1523 | PREFIX_EVEX_0FEC, |
1524 | PREFIX_EVEX_0FED, | |
1525 | PREFIX_EVEX_0FEE, | |
43234a1e | 1526 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1527 | PREFIX_EVEX_0FF1, |
43234a1e L |
1528 | PREFIX_EVEX_0FF2, |
1529 | PREFIX_EVEX_0FF3, | |
1530 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1531 | PREFIX_EVEX_0FF5, |
1532 | PREFIX_EVEX_0FF6, | |
1533 | PREFIX_EVEX_0FF8, | |
1534 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1535 | PREFIX_EVEX_0FFA, |
1536 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1537 | PREFIX_EVEX_0FFC, |
1538 | PREFIX_EVEX_0FFD, | |
43234a1e | 1539 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1540 | PREFIX_EVEX_0F3800, |
1541 | PREFIX_EVEX_0F3804, | |
1542 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1543 | PREFIX_EVEX_0F380C, |
1544 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1545 | PREFIX_EVEX_0F3810, |
43234a1e L |
1546 | PREFIX_EVEX_0F3811, |
1547 | PREFIX_EVEX_0F3812, | |
1548 | PREFIX_EVEX_0F3813, | |
1549 | PREFIX_EVEX_0F3814, | |
1550 | PREFIX_EVEX_0F3815, | |
1551 | PREFIX_EVEX_0F3816, | |
1552 | PREFIX_EVEX_0F3818, | |
1553 | PREFIX_EVEX_0F3819, | |
1554 | PREFIX_EVEX_0F381A, | |
1555 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1556 | PREFIX_EVEX_0F381C, |
1557 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1558 | PREFIX_EVEX_0F381E, |
1559 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1560 | PREFIX_EVEX_0F3820, |
43234a1e L |
1561 | PREFIX_EVEX_0F3821, |
1562 | PREFIX_EVEX_0F3822, | |
1563 | PREFIX_EVEX_0F3823, | |
1564 | PREFIX_EVEX_0F3824, | |
1565 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1566 | PREFIX_EVEX_0F3826, |
43234a1e L |
1567 | PREFIX_EVEX_0F3827, |
1568 | PREFIX_EVEX_0F3828, | |
1569 | PREFIX_EVEX_0F3829, | |
1570 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1571 | PREFIX_EVEX_0F382B, |
43234a1e L |
1572 | PREFIX_EVEX_0F382C, |
1573 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1574 | PREFIX_EVEX_0F3830, |
43234a1e L |
1575 | PREFIX_EVEX_0F3831, |
1576 | PREFIX_EVEX_0F3832, | |
1577 | PREFIX_EVEX_0F3833, | |
1578 | PREFIX_EVEX_0F3834, | |
1579 | PREFIX_EVEX_0F3835, | |
1580 | PREFIX_EVEX_0F3836, | |
1581 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1582 | PREFIX_EVEX_0F3838, |
43234a1e L |
1583 | PREFIX_EVEX_0F3839, |
1584 | PREFIX_EVEX_0F383A, | |
1585 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1586 | PREFIX_EVEX_0F383C, |
43234a1e | 1587 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1588 | PREFIX_EVEX_0F383E, |
43234a1e L |
1589 | PREFIX_EVEX_0F383F, |
1590 | PREFIX_EVEX_0F3840, | |
1591 | PREFIX_EVEX_0F3842, | |
1592 | PREFIX_EVEX_0F3843, | |
1593 | PREFIX_EVEX_0F3844, | |
1594 | PREFIX_EVEX_0F3845, | |
1595 | PREFIX_EVEX_0F3846, | |
1596 | PREFIX_EVEX_0F3847, | |
1597 | PREFIX_EVEX_0F384C, | |
1598 | PREFIX_EVEX_0F384D, | |
1599 | PREFIX_EVEX_0F384E, | |
1600 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1601 | PREFIX_EVEX_0F3850, |
1602 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1603 | PREFIX_EVEX_0F3852, |
1604 | PREFIX_EVEX_0F3853, | |
ee6872be | 1605 | PREFIX_EVEX_0F3854, |
620214f7 | 1606 | PREFIX_EVEX_0F3855, |
43234a1e L |
1607 | PREFIX_EVEX_0F3858, |
1608 | PREFIX_EVEX_0F3859, | |
1609 | PREFIX_EVEX_0F385A, | |
1610 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1611 | PREFIX_EVEX_0F3862, |
1612 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1613 | PREFIX_EVEX_0F3864, |
1614 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1615 | PREFIX_EVEX_0F3866, |
53467f57 IT |
1616 | PREFIX_EVEX_0F3870, |
1617 | PREFIX_EVEX_0F3871, | |
1618 | PREFIX_EVEX_0F3872, | |
1619 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1620 | PREFIX_EVEX_0F3875, |
43234a1e L |
1621 | PREFIX_EVEX_0F3876, |
1622 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1623 | PREFIX_EVEX_0F3878, |
1624 | PREFIX_EVEX_0F3879, | |
1625 | PREFIX_EVEX_0F387A, | |
1626 | PREFIX_EVEX_0F387B, | |
43234a1e | 1627 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1628 | PREFIX_EVEX_0F387D, |
43234a1e L |
1629 | PREFIX_EVEX_0F387E, |
1630 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1631 | PREFIX_EVEX_0F3883, |
43234a1e L |
1632 | PREFIX_EVEX_0F3888, |
1633 | PREFIX_EVEX_0F3889, | |
1634 | PREFIX_EVEX_0F388A, | |
1635 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1636 | PREFIX_EVEX_0F388D, |
ee6872be | 1637 | PREFIX_EVEX_0F388F, |
43234a1e L |
1638 | PREFIX_EVEX_0F3890, |
1639 | PREFIX_EVEX_0F3891, | |
1640 | PREFIX_EVEX_0F3892, | |
1641 | PREFIX_EVEX_0F3893, | |
1642 | PREFIX_EVEX_0F3896, | |
1643 | PREFIX_EVEX_0F3897, | |
1644 | PREFIX_EVEX_0F3898, | |
1645 | PREFIX_EVEX_0F3899, | |
1646 | PREFIX_EVEX_0F389A, | |
1647 | PREFIX_EVEX_0F389B, | |
1648 | PREFIX_EVEX_0F389C, | |
1649 | PREFIX_EVEX_0F389D, | |
1650 | PREFIX_EVEX_0F389E, | |
1651 | PREFIX_EVEX_0F389F, | |
1652 | PREFIX_EVEX_0F38A0, | |
1653 | PREFIX_EVEX_0F38A1, | |
1654 | PREFIX_EVEX_0F38A2, | |
1655 | PREFIX_EVEX_0F38A3, | |
1656 | PREFIX_EVEX_0F38A6, | |
1657 | PREFIX_EVEX_0F38A7, | |
1658 | PREFIX_EVEX_0F38A8, | |
1659 | PREFIX_EVEX_0F38A9, | |
1660 | PREFIX_EVEX_0F38AA, | |
1661 | PREFIX_EVEX_0F38AB, | |
1662 | PREFIX_EVEX_0F38AC, | |
1663 | PREFIX_EVEX_0F38AD, | |
1664 | PREFIX_EVEX_0F38AE, | |
1665 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1666 | PREFIX_EVEX_0F38B4, |
1667 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1668 | PREFIX_EVEX_0F38B6, |
1669 | PREFIX_EVEX_0F38B7, | |
1670 | PREFIX_EVEX_0F38B8, | |
1671 | PREFIX_EVEX_0F38B9, | |
1672 | PREFIX_EVEX_0F38BA, | |
1673 | PREFIX_EVEX_0F38BB, | |
1674 | PREFIX_EVEX_0F38BC, | |
1675 | PREFIX_EVEX_0F38BD, | |
1676 | PREFIX_EVEX_0F38BE, | |
1677 | PREFIX_EVEX_0F38BF, | |
1678 | PREFIX_EVEX_0F38C4, | |
1679 | PREFIX_EVEX_0F38C6_REG_1, | |
1680 | PREFIX_EVEX_0F38C6_REG_2, | |
1681 | PREFIX_EVEX_0F38C6_REG_5, | |
1682 | PREFIX_EVEX_0F38C6_REG_6, | |
1683 | PREFIX_EVEX_0F38C7_REG_1, | |
1684 | PREFIX_EVEX_0F38C7_REG_2, | |
1685 | PREFIX_EVEX_0F38C7_REG_5, | |
1686 | PREFIX_EVEX_0F38C7_REG_6, | |
1687 | PREFIX_EVEX_0F38C8, | |
1688 | PREFIX_EVEX_0F38CA, | |
1689 | PREFIX_EVEX_0F38CB, | |
1690 | PREFIX_EVEX_0F38CC, | |
1691 | PREFIX_EVEX_0F38CD, | |
48521003 | 1692 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1693 | PREFIX_EVEX_0F38DC, |
1694 | PREFIX_EVEX_0F38DD, | |
1695 | PREFIX_EVEX_0F38DE, | |
1696 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1697 | |
1698 | PREFIX_EVEX_0F3A00, | |
1699 | PREFIX_EVEX_0F3A01, | |
1700 | PREFIX_EVEX_0F3A03, | |
1701 | PREFIX_EVEX_0F3A04, | |
1702 | PREFIX_EVEX_0F3A05, | |
1703 | PREFIX_EVEX_0F3A08, | |
1704 | PREFIX_EVEX_0F3A09, | |
1705 | PREFIX_EVEX_0F3A0A, | |
1706 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1707 | PREFIX_EVEX_0F3A0F, |
1708 | PREFIX_EVEX_0F3A14, | |
1709 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1710 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1711 | PREFIX_EVEX_0F3A17, |
1712 | PREFIX_EVEX_0F3A18, | |
1713 | PREFIX_EVEX_0F3A19, | |
1714 | PREFIX_EVEX_0F3A1A, | |
1715 | PREFIX_EVEX_0F3A1B, | |
1716 | PREFIX_EVEX_0F3A1D, | |
1717 | PREFIX_EVEX_0F3A1E, | |
1718 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1719 | PREFIX_EVEX_0F3A20, |
43234a1e | 1720 | PREFIX_EVEX_0F3A21, |
90a915bf | 1721 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1722 | PREFIX_EVEX_0F3A23, |
1723 | PREFIX_EVEX_0F3A25, | |
1724 | PREFIX_EVEX_0F3A26, | |
1725 | PREFIX_EVEX_0F3A27, | |
1726 | PREFIX_EVEX_0F3A38, | |
1727 | PREFIX_EVEX_0F3A39, | |
1728 | PREFIX_EVEX_0F3A3A, | |
1729 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1730 | PREFIX_EVEX_0F3A3E, |
1731 | PREFIX_EVEX_0F3A3F, | |
1732 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1733 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1734 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1735 | PREFIX_EVEX_0F3A50, |
1736 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1737 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1738 | PREFIX_EVEX_0F3A55, |
1739 | PREFIX_EVEX_0F3A56, | |
1740 | PREFIX_EVEX_0F3A57, | |
1741 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1742 | PREFIX_EVEX_0F3A67, |
1743 | PREFIX_EVEX_0F3A70, | |
1744 | PREFIX_EVEX_0F3A71, | |
1745 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1746 | PREFIX_EVEX_0F3A73, |
1747 | PREFIX_EVEX_0F3ACE, | |
1748 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1749 | }; |
4e7d34a6 | 1750 | |
51e7da1b L |
1751 | enum |
1752 | { | |
1753 | X86_64_06 = 0, | |
3873ba12 L |
1754 | X86_64_07, |
1755 | X86_64_0D, | |
1756 | X86_64_16, | |
1757 | X86_64_17, | |
1758 | X86_64_1E, | |
1759 | X86_64_1F, | |
1760 | X86_64_27, | |
1761 | X86_64_2F, | |
1762 | X86_64_37, | |
1763 | X86_64_3F, | |
1764 | X86_64_60, | |
1765 | X86_64_61, | |
1766 | X86_64_62, | |
1767 | X86_64_63, | |
1768 | X86_64_6D, | |
1769 | X86_64_6F, | |
d039fef3 | 1770 | X86_64_82, |
3873ba12 L |
1771 | X86_64_9A, |
1772 | X86_64_C4, | |
1773 | X86_64_C5, | |
1774 | X86_64_CE, | |
1775 | X86_64_D4, | |
1776 | X86_64_D5, | |
a72d2af2 L |
1777 | X86_64_E8, |
1778 | X86_64_E9, | |
3873ba12 L |
1779 | X86_64_EA, |
1780 | X86_64_0F01_REG_0, | |
1781 | X86_64_0F01_REG_1, | |
1782 | X86_64_0F01_REG_2, | |
1783 | X86_64_0F01_REG_3 | |
51e7da1b | 1784 | }; |
4e7d34a6 | 1785 | |
51e7da1b L |
1786 | enum |
1787 | { | |
1788 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1789 | THREE_BYTE_0F3A |
51e7da1b | 1790 | }; |
4e7d34a6 | 1791 | |
f88c9eb0 SP |
1792 | enum |
1793 | { | |
5dd85c99 SP |
1794 | XOP_08 = 0, |
1795 | XOP_09, | |
f88c9eb0 SP |
1796 | XOP_0A |
1797 | }; | |
1798 | ||
51e7da1b L |
1799 | enum |
1800 | { | |
1801 | VEX_0F = 0, | |
3873ba12 L |
1802 | VEX_0F38, |
1803 | VEX_0F3A | |
51e7da1b | 1804 | }; |
c0f3af97 | 1805 | |
43234a1e L |
1806 | enum |
1807 | { | |
1808 | EVEX_0F = 0, | |
1809 | EVEX_0F38, | |
1810 | EVEX_0F3A | |
1811 | }; | |
1812 | ||
51e7da1b L |
1813 | enum |
1814 | { | |
592a252b L |
1815 | VEX_LEN_0F10_P_1 = 0, |
1816 | VEX_LEN_0F10_P_3, | |
1817 | VEX_LEN_0F11_P_1, | |
1818 | VEX_LEN_0F11_P_3, | |
1819 | VEX_LEN_0F12_P_0_M_0, | |
1820 | VEX_LEN_0F12_P_0_M_1, | |
1821 | VEX_LEN_0F12_P_2, | |
1822 | VEX_LEN_0F13_M_0, | |
1823 | VEX_LEN_0F16_P_0_M_0, | |
1824 | VEX_LEN_0F16_P_0_M_1, | |
1825 | VEX_LEN_0F16_P_2, | |
1826 | VEX_LEN_0F17_M_0, | |
1827 | VEX_LEN_0F2A_P_1, | |
1828 | VEX_LEN_0F2A_P_3, | |
1829 | VEX_LEN_0F2C_P_1, | |
1830 | VEX_LEN_0F2C_P_3, | |
1831 | VEX_LEN_0F2D_P_1, | |
1832 | VEX_LEN_0F2D_P_3, | |
1833 | VEX_LEN_0F2E_P_0, | |
1834 | VEX_LEN_0F2E_P_2, | |
1835 | VEX_LEN_0F2F_P_0, | |
1836 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1837 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1838 | VEX_LEN_0F41_P_2, |
43234a1e | 1839 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1840 | VEX_LEN_0F42_P_2, |
43234a1e | 1841 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1842 | VEX_LEN_0F44_P_2, |
43234a1e | 1843 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1844 | VEX_LEN_0F45_P_2, |
43234a1e | 1845 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1846 | VEX_LEN_0F46_P_2, |
43234a1e | 1847 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1848 | VEX_LEN_0F47_P_2, |
1849 | VEX_LEN_0F4A_P_0, | |
1850 | VEX_LEN_0F4A_P_2, | |
1851 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1852 | VEX_LEN_0F4B_P_2, |
592a252b L |
1853 | VEX_LEN_0F51_P_1, |
1854 | VEX_LEN_0F51_P_3, | |
1855 | VEX_LEN_0F52_P_1, | |
1856 | VEX_LEN_0F53_P_1, | |
1857 | VEX_LEN_0F58_P_1, | |
1858 | VEX_LEN_0F58_P_3, | |
1859 | VEX_LEN_0F59_P_1, | |
1860 | VEX_LEN_0F59_P_3, | |
1861 | VEX_LEN_0F5A_P_1, | |
1862 | VEX_LEN_0F5A_P_3, | |
1863 | VEX_LEN_0F5C_P_1, | |
1864 | VEX_LEN_0F5C_P_3, | |
1865 | VEX_LEN_0F5D_P_1, | |
1866 | VEX_LEN_0F5D_P_3, | |
1867 | VEX_LEN_0F5E_P_1, | |
1868 | VEX_LEN_0F5E_P_3, | |
1869 | VEX_LEN_0F5F_P_1, | |
1870 | VEX_LEN_0F5F_P_3, | |
592a252b | 1871 | VEX_LEN_0F6E_P_2, |
592a252b L |
1872 | VEX_LEN_0F7E_P_1, |
1873 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1874 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1875 | VEX_LEN_0F90_P_2, |
43234a1e | 1876 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1877 | VEX_LEN_0F91_P_2, |
43234a1e | 1878 | VEX_LEN_0F92_P_0, |
90a915bf | 1879 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1880 | VEX_LEN_0F92_P_3, |
43234a1e | 1881 | VEX_LEN_0F93_P_0, |
90a915bf | 1882 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1883 | VEX_LEN_0F93_P_3, |
43234a1e | 1884 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1885 | VEX_LEN_0F98_P_2, |
1886 | VEX_LEN_0F99_P_0, | |
1887 | VEX_LEN_0F99_P_2, | |
592a252b L |
1888 | VEX_LEN_0FAE_R_2_M_0, |
1889 | VEX_LEN_0FAE_R_3_M_0, | |
1890 | VEX_LEN_0FC2_P_1, | |
1891 | VEX_LEN_0FC2_P_3, | |
1892 | VEX_LEN_0FC4_P_2, | |
1893 | VEX_LEN_0FC5_P_2, | |
592a252b | 1894 | VEX_LEN_0FD6_P_2, |
592a252b | 1895 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1896 | VEX_LEN_0F3816_P_2, |
1897 | VEX_LEN_0F3819_P_2, | |
592a252b | 1898 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1899 | VEX_LEN_0F3836_P_2, |
592a252b | 1900 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1901 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1902 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1903 | VEX_LEN_0F38F2_P_0, |
1904 | VEX_LEN_0F38F3_R_1_P_0, | |
1905 | VEX_LEN_0F38F3_R_2_P_0, | |
1906 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1907 | VEX_LEN_0F38F5_P_0, |
1908 | VEX_LEN_0F38F5_P_1, | |
1909 | VEX_LEN_0F38F5_P_3, | |
1910 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1911 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1912 | VEX_LEN_0F38F7_P_1, |
1913 | VEX_LEN_0F38F7_P_2, | |
1914 | VEX_LEN_0F38F7_P_3, | |
1915 | VEX_LEN_0F3A00_P_2, | |
1916 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1917 | VEX_LEN_0F3A06_P_2, |
1918 | VEX_LEN_0F3A0A_P_2, | |
1919 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1920 | VEX_LEN_0F3A14_P_2, |
1921 | VEX_LEN_0F3A15_P_2, | |
1922 | VEX_LEN_0F3A16_P_2, | |
1923 | VEX_LEN_0F3A17_P_2, | |
1924 | VEX_LEN_0F3A18_P_2, | |
1925 | VEX_LEN_0F3A19_P_2, | |
1926 | VEX_LEN_0F3A20_P_2, | |
1927 | VEX_LEN_0F3A21_P_2, | |
1928 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1929 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1930 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1931 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1932 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1933 | VEX_LEN_0F3A38_P_2, |
1934 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1935 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1936 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1937 | VEX_LEN_0F3A60_P_2, |
1938 | VEX_LEN_0F3A61_P_2, | |
1939 | VEX_LEN_0F3A62_P_2, | |
1940 | VEX_LEN_0F3A63_P_2, | |
1941 | VEX_LEN_0F3A6A_P_2, | |
1942 | VEX_LEN_0F3A6B_P_2, | |
1943 | VEX_LEN_0F3A6E_P_2, | |
1944 | VEX_LEN_0F3A6F_P_2, | |
1945 | VEX_LEN_0F3A7A_P_2, | |
1946 | VEX_LEN_0F3A7B_P_2, | |
1947 | VEX_LEN_0F3A7E_P_2, | |
1948 | VEX_LEN_0F3A7F_P_2, | |
1949 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1950 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1951 | VEX_LEN_0FXOP_08_CC, |
1952 | VEX_LEN_0FXOP_08_CD, | |
1953 | VEX_LEN_0FXOP_08_CE, | |
1954 | VEX_LEN_0FXOP_08_CF, | |
1955 | VEX_LEN_0FXOP_08_EC, | |
1956 | VEX_LEN_0FXOP_08_ED, | |
1957 | VEX_LEN_0FXOP_08_EE, | |
1958 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1959 | VEX_LEN_0FXOP_09_80, |
1960 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1961 | }; |
c0f3af97 | 1962 | |
9e30b8e0 L |
1963 | enum |
1964 | { | |
592a252b L |
1965 | VEX_W_0F10_P_0 = 0, |
1966 | VEX_W_0F10_P_1, | |
1967 | VEX_W_0F10_P_2, | |
1968 | VEX_W_0F10_P_3, | |
1969 | VEX_W_0F11_P_0, | |
1970 | VEX_W_0F11_P_1, | |
1971 | VEX_W_0F11_P_2, | |
1972 | VEX_W_0F11_P_3, | |
1973 | VEX_W_0F12_P_0_M_0, | |
1974 | VEX_W_0F12_P_0_M_1, | |
1975 | VEX_W_0F12_P_1, | |
1976 | VEX_W_0F12_P_2, | |
1977 | VEX_W_0F12_P_3, | |
1978 | VEX_W_0F13_M_0, | |
1979 | VEX_W_0F14, | |
1980 | VEX_W_0F15, | |
1981 | VEX_W_0F16_P_0_M_0, | |
1982 | VEX_W_0F16_P_0_M_1, | |
1983 | VEX_W_0F16_P_1, | |
1984 | VEX_W_0F16_P_2, | |
1985 | VEX_W_0F17_M_0, | |
1986 | VEX_W_0F28, | |
1987 | VEX_W_0F29, | |
1988 | VEX_W_0F2B_M_0, | |
1989 | VEX_W_0F2E_P_0, | |
1990 | VEX_W_0F2E_P_2, | |
1991 | VEX_W_0F2F_P_0, | |
1992 | VEX_W_0F2F_P_2, | |
43234a1e | 1993 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1994 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1995 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1996 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1997 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1998 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1999 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 2000 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 2001 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 2002 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 2003 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
2004 | VEX_W_0F47_P_2_LEN_1, |
2005 | VEX_W_0F4A_P_0_LEN_1, | |
2006 | VEX_W_0F4A_P_2_LEN_1, | |
2007 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 2008 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
2009 | VEX_W_0F50_M_0, |
2010 | VEX_W_0F51_P_0, | |
2011 | VEX_W_0F51_P_1, | |
2012 | VEX_W_0F51_P_2, | |
2013 | VEX_W_0F51_P_3, | |
2014 | VEX_W_0F52_P_0, | |
2015 | VEX_W_0F52_P_1, | |
2016 | VEX_W_0F53_P_0, | |
2017 | VEX_W_0F53_P_1, | |
2018 | VEX_W_0F58_P_0, | |
2019 | VEX_W_0F58_P_1, | |
2020 | VEX_W_0F58_P_2, | |
2021 | VEX_W_0F58_P_3, | |
2022 | VEX_W_0F59_P_0, | |
2023 | VEX_W_0F59_P_1, | |
2024 | VEX_W_0F59_P_2, | |
2025 | VEX_W_0F59_P_3, | |
2026 | VEX_W_0F5A_P_0, | |
2027 | VEX_W_0F5A_P_1, | |
2028 | VEX_W_0F5A_P_3, | |
2029 | VEX_W_0F5B_P_0, | |
2030 | VEX_W_0F5B_P_1, | |
2031 | VEX_W_0F5B_P_2, | |
2032 | VEX_W_0F5C_P_0, | |
2033 | VEX_W_0F5C_P_1, | |
2034 | VEX_W_0F5C_P_2, | |
2035 | VEX_W_0F5C_P_3, | |
2036 | VEX_W_0F5D_P_0, | |
2037 | VEX_W_0F5D_P_1, | |
2038 | VEX_W_0F5D_P_2, | |
2039 | VEX_W_0F5D_P_3, | |
2040 | VEX_W_0F5E_P_0, | |
2041 | VEX_W_0F5E_P_1, | |
2042 | VEX_W_0F5E_P_2, | |
2043 | VEX_W_0F5E_P_3, | |
2044 | VEX_W_0F5F_P_0, | |
2045 | VEX_W_0F5F_P_1, | |
2046 | VEX_W_0F5F_P_2, | |
2047 | VEX_W_0F5F_P_3, | |
2048 | VEX_W_0F60_P_2, | |
2049 | VEX_W_0F61_P_2, | |
2050 | VEX_W_0F62_P_2, | |
2051 | VEX_W_0F63_P_2, | |
2052 | VEX_W_0F64_P_2, | |
2053 | VEX_W_0F65_P_2, | |
2054 | VEX_W_0F66_P_2, | |
2055 | VEX_W_0F67_P_2, | |
2056 | VEX_W_0F68_P_2, | |
2057 | VEX_W_0F69_P_2, | |
2058 | VEX_W_0F6A_P_2, | |
2059 | VEX_W_0F6B_P_2, | |
2060 | VEX_W_0F6C_P_2, | |
2061 | VEX_W_0F6D_P_2, | |
2062 | VEX_W_0F6F_P_1, | |
2063 | VEX_W_0F6F_P_2, | |
2064 | VEX_W_0F70_P_1, | |
2065 | VEX_W_0F70_P_2, | |
2066 | VEX_W_0F70_P_3, | |
2067 | VEX_W_0F71_R_2_P_2, | |
2068 | VEX_W_0F71_R_4_P_2, | |
2069 | VEX_W_0F71_R_6_P_2, | |
2070 | VEX_W_0F72_R_2_P_2, | |
2071 | VEX_W_0F72_R_4_P_2, | |
2072 | VEX_W_0F72_R_6_P_2, | |
2073 | VEX_W_0F73_R_2_P_2, | |
2074 | VEX_W_0F73_R_3_P_2, | |
2075 | VEX_W_0F73_R_6_P_2, | |
2076 | VEX_W_0F73_R_7_P_2, | |
2077 | VEX_W_0F74_P_2, | |
2078 | VEX_W_0F75_P_2, | |
2079 | VEX_W_0F76_P_2, | |
2080 | VEX_W_0F77_P_0, | |
2081 | VEX_W_0F7C_P_2, | |
2082 | VEX_W_0F7C_P_3, | |
2083 | VEX_W_0F7D_P_2, | |
2084 | VEX_W_0F7D_P_3, | |
2085 | VEX_W_0F7E_P_1, | |
2086 | VEX_W_0F7F_P_1, | |
2087 | VEX_W_0F7F_P_2, | |
43234a1e | 2088 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2089 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2090 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2091 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2092 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2093 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2094 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2095 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2096 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2097 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2098 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2099 | VEX_W_0F98_P_2_LEN_0, |
2100 | VEX_W_0F99_P_0_LEN_0, | |
2101 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2102 | VEX_W_0FAE_R_2_M_0, |
2103 | VEX_W_0FAE_R_3_M_0, | |
2104 | VEX_W_0FC2_P_0, | |
2105 | VEX_W_0FC2_P_1, | |
2106 | VEX_W_0FC2_P_2, | |
2107 | VEX_W_0FC2_P_3, | |
2108 | VEX_W_0FC4_P_2, | |
2109 | VEX_W_0FC5_P_2, | |
2110 | VEX_W_0FD0_P_2, | |
2111 | VEX_W_0FD0_P_3, | |
2112 | VEX_W_0FD1_P_2, | |
2113 | VEX_W_0FD2_P_2, | |
2114 | VEX_W_0FD3_P_2, | |
2115 | VEX_W_0FD4_P_2, | |
2116 | VEX_W_0FD5_P_2, | |
2117 | VEX_W_0FD6_P_2, | |
2118 | VEX_W_0FD7_P_2_M_1, | |
2119 | VEX_W_0FD8_P_2, | |
2120 | VEX_W_0FD9_P_2, | |
2121 | VEX_W_0FDA_P_2, | |
2122 | VEX_W_0FDB_P_2, | |
2123 | VEX_W_0FDC_P_2, | |
2124 | VEX_W_0FDD_P_2, | |
2125 | VEX_W_0FDE_P_2, | |
2126 | VEX_W_0FDF_P_2, | |
2127 | VEX_W_0FE0_P_2, | |
2128 | VEX_W_0FE1_P_2, | |
2129 | VEX_W_0FE2_P_2, | |
2130 | VEX_W_0FE3_P_2, | |
2131 | VEX_W_0FE4_P_2, | |
2132 | VEX_W_0FE5_P_2, | |
2133 | VEX_W_0FE6_P_1, | |
2134 | VEX_W_0FE6_P_2, | |
2135 | VEX_W_0FE6_P_3, | |
2136 | VEX_W_0FE7_P_2_M_0, | |
2137 | VEX_W_0FE8_P_2, | |
2138 | VEX_W_0FE9_P_2, | |
2139 | VEX_W_0FEA_P_2, | |
2140 | VEX_W_0FEB_P_2, | |
2141 | VEX_W_0FEC_P_2, | |
2142 | VEX_W_0FED_P_2, | |
2143 | VEX_W_0FEE_P_2, | |
2144 | VEX_W_0FEF_P_2, | |
2145 | VEX_W_0FF0_P_3_M_0, | |
2146 | VEX_W_0FF1_P_2, | |
2147 | VEX_W_0FF2_P_2, | |
2148 | VEX_W_0FF3_P_2, | |
2149 | VEX_W_0FF4_P_2, | |
2150 | VEX_W_0FF5_P_2, | |
2151 | VEX_W_0FF6_P_2, | |
2152 | VEX_W_0FF7_P_2, | |
2153 | VEX_W_0FF8_P_2, | |
2154 | VEX_W_0FF9_P_2, | |
2155 | VEX_W_0FFA_P_2, | |
2156 | VEX_W_0FFB_P_2, | |
2157 | VEX_W_0FFC_P_2, | |
2158 | VEX_W_0FFD_P_2, | |
2159 | VEX_W_0FFE_P_2, | |
2160 | VEX_W_0F3800_P_2, | |
2161 | VEX_W_0F3801_P_2, | |
2162 | VEX_W_0F3802_P_2, | |
2163 | VEX_W_0F3803_P_2, | |
2164 | VEX_W_0F3804_P_2, | |
2165 | VEX_W_0F3805_P_2, | |
2166 | VEX_W_0F3806_P_2, | |
2167 | VEX_W_0F3807_P_2, | |
2168 | VEX_W_0F3808_P_2, | |
2169 | VEX_W_0F3809_P_2, | |
2170 | VEX_W_0F380A_P_2, | |
2171 | VEX_W_0F380B_P_2, | |
2172 | VEX_W_0F380C_P_2, | |
2173 | VEX_W_0F380D_P_2, | |
2174 | VEX_W_0F380E_P_2, | |
2175 | VEX_W_0F380F_P_2, | |
6c30d220 | 2176 | VEX_W_0F3816_P_2, |
592a252b | 2177 | VEX_W_0F3817_P_2, |
6c30d220 L |
2178 | VEX_W_0F3818_P_2, |
2179 | VEX_W_0F3819_P_2, | |
592a252b L |
2180 | VEX_W_0F381A_P_2_M_0, |
2181 | VEX_W_0F381C_P_2, | |
2182 | VEX_W_0F381D_P_2, | |
2183 | VEX_W_0F381E_P_2, | |
2184 | VEX_W_0F3820_P_2, | |
2185 | VEX_W_0F3821_P_2, | |
2186 | VEX_W_0F3822_P_2, | |
2187 | VEX_W_0F3823_P_2, | |
2188 | VEX_W_0F3824_P_2, | |
2189 | VEX_W_0F3825_P_2, | |
2190 | VEX_W_0F3828_P_2, | |
2191 | VEX_W_0F3829_P_2, | |
2192 | VEX_W_0F382A_P_2_M_0, | |
2193 | VEX_W_0F382B_P_2, | |
2194 | VEX_W_0F382C_P_2_M_0, | |
2195 | VEX_W_0F382D_P_2_M_0, | |
2196 | VEX_W_0F382E_P_2_M_0, | |
2197 | VEX_W_0F382F_P_2_M_0, | |
2198 | VEX_W_0F3830_P_2, | |
2199 | VEX_W_0F3831_P_2, | |
2200 | VEX_W_0F3832_P_2, | |
2201 | VEX_W_0F3833_P_2, | |
2202 | VEX_W_0F3834_P_2, | |
2203 | VEX_W_0F3835_P_2, | |
6c30d220 | 2204 | VEX_W_0F3836_P_2, |
592a252b L |
2205 | VEX_W_0F3837_P_2, |
2206 | VEX_W_0F3838_P_2, | |
2207 | VEX_W_0F3839_P_2, | |
2208 | VEX_W_0F383A_P_2, | |
2209 | VEX_W_0F383B_P_2, | |
2210 | VEX_W_0F383C_P_2, | |
2211 | VEX_W_0F383D_P_2, | |
2212 | VEX_W_0F383E_P_2, | |
2213 | VEX_W_0F383F_P_2, | |
2214 | VEX_W_0F3840_P_2, | |
2215 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2216 | VEX_W_0F3846_P_2, |
2217 | VEX_W_0F3858_P_2, | |
2218 | VEX_W_0F3859_P_2, | |
2219 | VEX_W_0F385A_P_2_M_0, | |
2220 | VEX_W_0F3878_P_2, | |
2221 | VEX_W_0F3879_P_2, | |
48521003 | 2222 | VEX_W_0F38CF_P_2, |
592a252b | 2223 | VEX_W_0F38DB_P_2, |
6c30d220 L |
2224 | VEX_W_0F3A00_P_2, |
2225 | VEX_W_0F3A01_P_2, | |
2226 | VEX_W_0F3A02_P_2, | |
592a252b L |
2227 | VEX_W_0F3A04_P_2, |
2228 | VEX_W_0F3A05_P_2, | |
2229 | VEX_W_0F3A06_P_2, | |
2230 | VEX_W_0F3A08_P_2, | |
2231 | VEX_W_0F3A09_P_2, | |
2232 | VEX_W_0F3A0A_P_2, | |
2233 | VEX_W_0F3A0B_P_2, | |
2234 | VEX_W_0F3A0C_P_2, | |
2235 | VEX_W_0F3A0D_P_2, | |
2236 | VEX_W_0F3A0E_P_2, | |
2237 | VEX_W_0F3A0F_P_2, | |
2238 | VEX_W_0F3A14_P_2, | |
2239 | VEX_W_0F3A15_P_2, | |
2240 | VEX_W_0F3A18_P_2, | |
2241 | VEX_W_0F3A19_P_2, | |
2242 | VEX_W_0F3A20_P_2, | |
2243 | VEX_W_0F3A21_P_2, | |
43234a1e | 2244 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2245 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2246 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2247 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2248 | VEX_W_0F3A38_P_2, |
2249 | VEX_W_0F3A39_P_2, | |
592a252b L |
2250 | VEX_W_0F3A40_P_2, |
2251 | VEX_W_0F3A41_P_2, | |
2252 | VEX_W_0F3A42_P_2, | |
6c30d220 | 2253 | VEX_W_0F3A46_P_2, |
592a252b L |
2254 | VEX_W_0F3A48_P_2, |
2255 | VEX_W_0F3A49_P_2, | |
2256 | VEX_W_0F3A4A_P_2, | |
2257 | VEX_W_0F3A4B_P_2, | |
2258 | VEX_W_0F3A4C_P_2, | |
592a252b L |
2259 | VEX_W_0F3A62_P_2, |
2260 | VEX_W_0F3A63_P_2, | |
48521003 IT |
2261 | VEX_W_0F3ACE_P_2, |
2262 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2263 | VEX_W_0F3ADF_P_2, |
2264 | ||
2265 | EVEX_W_0F10_P_0, | |
2266 | EVEX_W_0F10_P_1_M_0, | |
2267 | EVEX_W_0F10_P_1_M_1, | |
2268 | EVEX_W_0F10_P_2, | |
2269 | EVEX_W_0F10_P_3_M_0, | |
2270 | EVEX_W_0F10_P_3_M_1, | |
2271 | EVEX_W_0F11_P_0, | |
2272 | EVEX_W_0F11_P_1_M_0, | |
2273 | EVEX_W_0F11_P_1_M_1, | |
2274 | EVEX_W_0F11_P_2, | |
2275 | EVEX_W_0F11_P_3_M_0, | |
2276 | EVEX_W_0F11_P_3_M_1, | |
2277 | EVEX_W_0F12_P_0_M_0, | |
2278 | EVEX_W_0F12_P_0_M_1, | |
2279 | EVEX_W_0F12_P_1, | |
2280 | EVEX_W_0F12_P_2, | |
2281 | EVEX_W_0F12_P_3, | |
2282 | EVEX_W_0F13_P_0, | |
2283 | EVEX_W_0F13_P_2, | |
2284 | EVEX_W_0F14_P_0, | |
2285 | EVEX_W_0F14_P_2, | |
2286 | EVEX_W_0F15_P_0, | |
2287 | EVEX_W_0F15_P_2, | |
2288 | EVEX_W_0F16_P_0_M_0, | |
2289 | EVEX_W_0F16_P_0_M_1, | |
2290 | EVEX_W_0F16_P_1, | |
2291 | EVEX_W_0F16_P_2, | |
2292 | EVEX_W_0F17_P_0, | |
2293 | EVEX_W_0F17_P_2, | |
2294 | EVEX_W_0F28_P_0, | |
2295 | EVEX_W_0F28_P_2, | |
2296 | EVEX_W_0F29_P_0, | |
2297 | EVEX_W_0F29_P_2, | |
2298 | EVEX_W_0F2A_P_1, | |
2299 | EVEX_W_0F2A_P_3, | |
2300 | EVEX_W_0F2B_P_0, | |
2301 | EVEX_W_0F2B_P_2, | |
2302 | EVEX_W_0F2E_P_0, | |
2303 | EVEX_W_0F2E_P_2, | |
2304 | EVEX_W_0F2F_P_0, | |
2305 | EVEX_W_0F2F_P_2, | |
2306 | EVEX_W_0F51_P_0, | |
2307 | EVEX_W_0F51_P_1, | |
2308 | EVEX_W_0F51_P_2, | |
2309 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2310 | EVEX_W_0F54_P_0, |
2311 | EVEX_W_0F54_P_2, | |
2312 | EVEX_W_0F55_P_0, | |
2313 | EVEX_W_0F55_P_2, | |
2314 | EVEX_W_0F56_P_0, | |
2315 | EVEX_W_0F56_P_2, | |
2316 | EVEX_W_0F57_P_0, | |
2317 | EVEX_W_0F57_P_2, | |
43234a1e L |
2318 | EVEX_W_0F58_P_0, |
2319 | EVEX_W_0F58_P_1, | |
2320 | EVEX_W_0F58_P_2, | |
2321 | EVEX_W_0F58_P_3, | |
2322 | EVEX_W_0F59_P_0, | |
2323 | EVEX_W_0F59_P_1, | |
2324 | EVEX_W_0F59_P_2, | |
2325 | EVEX_W_0F59_P_3, | |
2326 | EVEX_W_0F5A_P_0, | |
2327 | EVEX_W_0F5A_P_1, | |
2328 | EVEX_W_0F5A_P_2, | |
2329 | EVEX_W_0F5A_P_3, | |
2330 | EVEX_W_0F5B_P_0, | |
2331 | EVEX_W_0F5B_P_1, | |
2332 | EVEX_W_0F5B_P_2, | |
2333 | EVEX_W_0F5C_P_0, | |
2334 | EVEX_W_0F5C_P_1, | |
2335 | EVEX_W_0F5C_P_2, | |
2336 | EVEX_W_0F5C_P_3, | |
2337 | EVEX_W_0F5D_P_0, | |
2338 | EVEX_W_0F5D_P_1, | |
2339 | EVEX_W_0F5D_P_2, | |
2340 | EVEX_W_0F5D_P_3, | |
2341 | EVEX_W_0F5E_P_0, | |
2342 | EVEX_W_0F5E_P_1, | |
2343 | EVEX_W_0F5E_P_2, | |
2344 | EVEX_W_0F5E_P_3, | |
2345 | EVEX_W_0F5F_P_0, | |
2346 | EVEX_W_0F5F_P_1, | |
2347 | EVEX_W_0F5F_P_2, | |
2348 | EVEX_W_0F5F_P_3, | |
2349 | EVEX_W_0F62_P_2, | |
2350 | EVEX_W_0F66_P_2, | |
2351 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2352 | EVEX_W_0F6B_P_2, |
43234a1e L |
2353 | EVEX_W_0F6C_P_2, |
2354 | EVEX_W_0F6D_P_2, | |
2355 | EVEX_W_0F6E_P_2, | |
2356 | EVEX_W_0F6F_P_1, | |
2357 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2358 | EVEX_W_0F6F_P_3, |
43234a1e L |
2359 | EVEX_W_0F70_P_2, |
2360 | EVEX_W_0F72_R_2_P_2, | |
2361 | EVEX_W_0F72_R_6_P_2, | |
2362 | EVEX_W_0F73_R_2_P_2, | |
2363 | EVEX_W_0F73_R_6_P_2, | |
2364 | EVEX_W_0F76_P_2, | |
2365 | EVEX_W_0F78_P_0, | |
90a915bf | 2366 | EVEX_W_0F78_P_2, |
43234a1e | 2367 | EVEX_W_0F79_P_0, |
90a915bf | 2368 | EVEX_W_0F79_P_2, |
43234a1e | 2369 | EVEX_W_0F7A_P_1, |
90a915bf | 2370 | EVEX_W_0F7A_P_2, |
43234a1e L |
2371 | EVEX_W_0F7A_P_3, |
2372 | EVEX_W_0F7B_P_1, | |
90a915bf | 2373 | EVEX_W_0F7B_P_2, |
43234a1e L |
2374 | EVEX_W_0F7B_P_3, |
2375 | EVEX_W_0F7E_P_1, | |
2376 | EVEX_W_0F7E_P_2, | |
2377 | EVEX_W_0F7F_P_1, | |
2378 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2379 | EVEX_W_0F7F_P_3, |
43234a1e L |
2380 | EVEX_W_0FC2_P_0, |
2381 | EVEX_W_0FC2_P_1, | |
2382 | EVEX_W_0FC2_P_2, | |
2383 | EVEX_W_0FC2_P_3, | |
2384 | EVEX_W_0FC6_P_0, | |
2385 | EVEX_W_0FC6_P_2, | |
2386 | EVEX_W_0FD2_P_2, | |
2387 | EVEX_W_0FD3_P_2, | |
2388 | EVEX_W_0FD4_P_2, | |
2389 | EVEX_W_0FD6_P_2, | |
2390 | EVEX_W_0FE6_P_1, | |
2391 | EVEX_W_0FE6_P_2, | |
2392 | EVEX_W_0FE6_P_3, | |
2393 | EVEX_W_0FE7_P_2, | |
2394 | EVEX_W_0FF2_P_2, | |
2395 | EVEX_W_0FF3_P_2, | |
2396 | EVEX_W_0FF4_P_2, | |
2397 | EVEX_W_0FFA_P_2, | |
2398 | EVEX_W_0FFB_P_2, | |
2399 | EVEX_W_0FFE_P_2, | |
2400 | EVEX_W_0F380C_P_2, | |
2401 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2402 | EVEX_W_0F3810_P_1, |
2403 | EVEX_W_0F3810_P_2, | |
43234a1e | 2404 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2405 | EVEX_W_0F3811_P_2, |
43234a1e | 2406 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2407 | EVEX_W_0F3812_P_2, |
43234a1e L |
2408 | EVEX_W_0F3813_P_1, |
2409 | EVEX_W_0F3813_P_2, | |
2410 | EVEX_W_0F3814_P_1, | |
2411 | EVEX_W_0F3815_P_1, | |
2412 | EVEX_W_0F3818_P_2, | |
2413 | EVEX_W_0F3819_P_2, | |
2414 | EVEX_W_0F381A_P_2, | |
2415 | EVEX_W_0F381B_P_2, | |
2416 | EVEX_W_0F381E_P_2, | |
2417 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2418 | EVEX_W_0F3820_P_1, |
43234a1e L |
2419 | EVEX_W_0F3821_P_1, |
2420 | EVEX_W_0F3822_P_1, | |
2421 | EVEX_W_0F3823_P_1, | |
2422 | EVEX_W_0F3824_P_1, | |
2423 | EVEX_W_0F3825_P_1, | |
2424 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2425 | EVEX_W_0F3826_P_1, |
2426 | EVEX_W_0F3826_P_2, | |
2427 | EVEX_W_0F3828_P_1, | |
43234a1e | 2428 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2429 | EVEX_W_0F3829_P_1, |
43234a1e L |
2430 | EVEX_W_0F3829_P_2, |
2431 | EVEX_W_0F382A_P_1, | |
2432 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2433 | EVEX_W_0F382B_P_2, |
2434 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2435 | EVEX_W_0F3831_P_1, |
2436 | EVEX_W_0F3832_P_1, | |
2437 | EVEX_W_0F3833_P_1, | |
2438 | EVEX_W_0F3834_P_1, | |
2439 | EVEX_W_0F3835_P_1, | |
2440 | EVEX_W_0F3835_P_2, | |
2441 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2442 | EVEX_W_0F3838_P_1, |
2443 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2444 | EVEX_W_0F383A_P_1, |
2445 | EVEX_W_0F3840_P_2, | |
ee6872be | 2446 | EVEX_W_0F3854_P_2, |
620214f7 | 2447 | EVEX_W_0F3855_P_2, |
43234a1e L |
2448 | EVEX_W_0F3858_P_2, |
2449 | EVEX_W_0F3859_P_2, | |
2450 | EVEX_W_0F385A_P_2, | |
2451 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2452 | EVEX_W_0F3862_P_2, |
2453 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2454 | EVEX_W_0F3866_P_2, |
53467f57 IT |
2455 | EVEX_W_0F3870_P_2, |
2456 | EVEX_W_0F3871_P_2, | |
2457 | EVEX_W_0F3872_P_2, | |
2458 | EVEX_W_0F3873_P_2, | |
1ba585e8 IT |
2459 | EVEX_W_0F3875_P_2, |
2460 | EVEX_W_0F3878_P_2, | |
2461 | EVEX_W_0F3879_P_2, | |
2462 | EVEX_W_0F387A_P_2, | |
2463 | EVEX_W_0F387B_P_2, | |
2464 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2465 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2466 | EVEX_W_0F388D_P_2, |
43234a1e L |
2467 | EVEX_W_0F3891_P_2, |
2468 | EVEX_W_0F3893_P_2, | |
2469 | EVEX_W_0F38A1_P_2, | |
2470 | EVEX_W_0F38A3_P_2, | |
2471 | EVEX_W_0F38C7_R_1_P_2, | |
2472 | EVEX_W_0F38C7_R_2_P_2, | |
2473 | EVEX_W_0F38C7_R_5_P_2, | |
2474 | EVEX_W_0F38C7_R_6_P_2, | |
2475 | ||
2476 | EVEX_W_0F3A00_P_2, | |
2477 | EVEX_W_0F3A01_P_2, | |
2478 | EVEX_W_0F3A04_P_2, | |
2479 | EVEX_W_0F3A05_P_2, | |
2480 | EVEX_W_0F3A08_P_2, | |
2481 | EVEX_W_0F3A09_P_2, | |
2482 | EVEX_W_0F3A0A_P_2, | |
2483 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2484 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2485 | EVEX_W_0F3A18_P_2, |
2486 | EVEX_W_0F3A19_P_2, | |
2487 | EVEX_W_0F3A1A_P_2, | |
2488 | EVEX_W_0F3A1B_P_2, | |
2489 | EVEX_W_0F3A1D_P_2, | |
2490 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2491 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2492 | EVEX_W_0F3A23_P_2, |
2493 | EVEX_W_0F3A38_P_2, | |
2494 | EVEX_W_0F3A39_P_2, | |
2495 | EVEX_W_0F3A3A_P_2, | |
2496 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2497 | EVEX_W_0F3A3E_P_2, |
2498 | EVEX_W_0F3A3F_P_2, | |
2499 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2500 | EVEX_W_0F3A43_P_2, |
2501 | EVEX_W_0F3A50_P_2, | |
2502 | EVEX_W_0F3A51_P_2, | |
2503 | EVEX_W_0F3A56_P_2, | |
2504 | EVEX_W_0F3A57_P_2, | |
2505 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2506 | EVEX_W_0F3A67_P_2, |
2507 | EVEX_W_0F3A70_P_2, | |
2508 | EVEX_W_0F3A71_P_2, | |
2509 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2510 | EVEX_W_0F3A73_P_2, |
2511 | EVEX_W_0F3ACE_P_2, | |
2512 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2513 | }; |
2514 | ||
26ca5450 | 2515 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2516 | |
2517 | struct dis386 { | |
2da11e11 | 2518 | const char *name; |
ce518a5f L |
2519 | struct |
2520 | { | |
2521 | op_rtn rtn; | |
2522 | int bytemode; | |
2523 | } op[MAX_OPERANDS]; | |
bf890a93 | 2524 | unsigned int prefix_requirement; |
252b5132 RH |
2525 | }; |
2526 | ||
2527 | /* Upper case letters in the instruction names here are macros. | |
2528 | 'A' => print 'b' if no register operands or suffix_always is true | |
2529 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2530 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2531 | size prefix |
ed7841b3 | 2532 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2533 | suffix_always is true |
252b5132 | 2534 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2535 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2536 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2537 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2538 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2539 | for some of the macro letters) |
9306ca4a | 2540 | 'J' => print 'l' |
42903f7f | 2541 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2542 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2543 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2544 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2545 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2546 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2547 | or suffix_always is true. print 'q' if rex prefix is present. |
2548 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2549 | is true | |
a35ca55a | 2550 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2551 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2552 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2553 | prefix and behave as 'P' otherwise | |
2554 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2555 | prefix and behave as 'Q' otherwise | |
2556 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2557 | prefix and behave as 'S' otherwise | |
a35ca55a | 2558 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2559 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2560 | 'Y' unused. |
6dd5059a | 2561 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2562 | '!' => change condition from true to false or from false to true. |
98b528ac | 2563 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2564 | '^' => print 'w' or 'l' depending on operand size prefix or |
2565 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2566 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2567 | on operand size prefix. | |
07f5af7d L |
2568 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2569 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2570 | otherwise | |
98b528ac L |
2571 | |
2572 | 2 upper case letter macros: | |
04d824a4 JB |
2573 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2574 | operands and no broadcast. | |
2575 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2576 | register operands and no broadcast. | |
4b06377f L |
2577 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2578 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2579 | or suffix_always is true |
4b06377f L |
2580 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2581 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2582 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2583 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2584 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2585 | an operand size prefix, or suffix_always is true. print | |
2586 | 'q' if rex prefix is present. | |
52b15da3 | 2587 | |
6439fc28 AM |
2588 | Many of the above letters print nothing in Intel mode. See "putop" |
2589 | for the details. | |
52b15da3 | 2590 | |
6439fc28 | 2591 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2592 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2593 | |
6439fc28 | 2594 | static const struct dis386 dis386[] = { |
252b5132 | 2595 | /* 00 */ |
bf890a93 IT |
2596 | { "addB", { Ebh1, Gb }, 0 }, |
2597 | { "addS", { Evh1, Gv }, 0 }, | |
2598 | { "addB", { Gb, EbS }, 0 }, | |
2599 | { "addS", { Gv, EvS }, 0 }, | |
2600 | { "addB", { AL, Ib }, 0 }, | |
2601 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2602 | { X86_64_TABLE (X86_64_06) }, |
2603 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2604 | /* 08 */ |
bf890a93 IT |
2605 | { "orB", { Ebh1, Gb }, 0 }, |
2606 | { "orS", { Evh1, Gv }, 0 }, | |
2607 | { "orB", { Gb, EbS }, 0 }, | |
2608 | { "orS", { Gv, EvS }, 0 }, | |
2609 | { "orB", { AL, Ib }, 0 }, | |
2610 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2611 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2612 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2613 | /* 10 */ |
bf890a93 IT |
2614 | { "adcB", { Ebh1, Gb }, 0 }, |
2615 | { "adcS", { Evh1, Gv }, 0 }, | |
2616 | { "adcB", { Gb, EbS }, 0 }, | |
2617 | { "adcS", { Gv, EvS }, 0 }, | |
2618 | { "adcB", { AL, Ib }, 0 }, | |
2619 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2620 | { X86_64_TABLE (X86_64_16) }, |
2621 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2622 | /* 18 */ |
bf890a93 IT |
2623 | { "sbbB", { Ebh1, Gb }, 0 }, |
2624 | { "sbbS", { Evh1, Gv }, 0 }, | |
2625 | { "sbbB", { Gb, EbS }, 0 }, | |
2626 | { "sbbS", { Gv, EvS }, 0 }, | |
2627 | { "sbbB", { AL, Ib }, 0 }, | |
2628 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2629 | { X86_64_TABLE (X86_64_1E) }, |
2630 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2631 | /* 20 */ |
bf890a93 IT |
2632 | { "andB", { Ebh1, Gb }, 0 }, |
2633 | { "andS", { Evh1, Gv }, 0 }, | |
2634 | { "andB", { Gb, EbS }, 0 }, | |
2635 | { "andS", { Gv, EvS }, 0 }, | |
2636 | { "andB", { AL, Ib }, 0 }, | |
2637 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2638 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2639 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2640 | /* 28 */ |
bf890a93 IT |
2641 | { "subB", { Ebh1, Gb }, 0 }, |
2642 | { "subS", { Evh1, Gv }, 0 }, | |
2643 | { "subB", { Gb, EbS }, 0 }, | |
2644 | { "subS", { Gv, EvS }, 0 }, | |
2645 | { "subB", { AL, Ib }, 0 }, | |
2646 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2647 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2648 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2649 | /* 30 */ |
bf890a93 IT |
2650 | { "xorB", { Ebh1, Gb }, 0 }, |
2651 | { "xorS", { Evh1, Gv }, 0 }, | |
2652 | { "xorB", { Gb, EbS }, 0 }, | |
2653 | { "xorS", { Gv, EvS }, 0 }, | |
2654 | { "xorB", { AL, Ib }, 0 }, | |
2655 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2656 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2657 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2658 | /* 38 */ |
bf890a93 IT |
2659 | { "cmpB", { Eb, Gb }, 0 }, |
2660 | { "cmpS", { Ev, Gv }, 0 }, | |
2661 | { "cmpB", { Gb, EbS }, 0 }, | |
2662 | { "cmpS", { Gv, EvS }, 0 }, | |
2663 | { "cmpB", { AL, Ib }, 0 }, | |
2664 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2665 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2666 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2667 | /* 40 */ |
bf890a93 IT |
2668 | { "inc{S|}", { RMeAX }, 0 }, |
2669 | { "inc{S|}", { RMeCX }, 0 }, | |
2670 | { "inc{S|}", { RMeDX }, 0 }, | |
2671 | { "inc{S|}", { RMeBX }, 0 }, | |
2672 | { "inc{S|}", { RMeSP }, 0 }, | |
2673 | { "inc{S|}", { RMeBP }, 0 }, | |
2674 | { "inc{S|}", { RMeSI }, 0 }, | |
2675 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2676 | /* 48 */ |
bf890a93 IT |
2677 | { "dec{S|}", { RMeAX }, 0 }, |
2678 | { "dec{S|}", { RMeCX }, 0 }, | |
2679 | { "dec{S|}", { RMeDX }, 0 }, | |
2680 | { "dec{S|}", { RMeBX }, 0 }, | |
2681 | { "dec{S|}", { RMeSP }, 0 }, | |
2682 | { "dec{S|}", { RMeBP }, 0 }, | |
2683 | { "dec{S|}", { RMeSI }, 0 }, | |
2684 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2685 | /* 50 */ |
bf890a93 IT |
2686 | { "pushV", { RMrAX }, 0 }, |
2687 | { "pushV", { RMrCX }, 0 }, | |
2688 | { "pushV", { RMrDX }, 0 }, | |
2689 | { "pushV", { RMrBX }, 0 }, | |
2690 | { "pushV", { RMrSP }, 0 }, | |
2691 | { "pushV", { RMrBP }, 0 }, | |
2692 | { "pushV", { RMrSI }, 0 }, | |
2693 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2694 | /* 58 */ |
bf890a93 IT |
2695 | { "popV", { RMrAX }, 0 }, |
2696 | { "popV", { RMrCX }, 0 }, | |
2697 | { "popV", { RMrDX }, 0 }, | |
2698 | { "popV", { RMrBX }, 0 }, | |
2699 | { "popV", { RMrSP }, 0 }, | |
2700 | { "popV", { RMrBP }, 0 }, | |
2701 | { "popV", { RMrSI }, 0 }, | |
2702 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2703 | /* 60 */ |
4e7d34a6 L |
2704 | { X86_64_TABLE (X86_64_60) }, |
2705 | { X86_64_TABLE (X86_64_61) }, | |
2706 | { X86_64_TABLE (X86_64_62) }, | |
2707 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2708 | { Bad_Opcode }, /* seg fs */ |
2709 | { Bad_Opcode }, /* seg gs */ | |
2710 | { Bad_Opcode }, /* op size prefix */ | |
2711 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2712 | /* 68 */ |
bf890a93 IT |
2713 | { "pushT", { sIv }, 0 }, |
2714 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2715 | { "pushT", { sIbT }, 0 }, | |
2716 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2717 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2718 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2719 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2720 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2721 | /* 70 */ |
bf890a93 IT |
2722 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2723 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2724 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2725 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2726 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2727 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2728 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2729 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2730 | /* 78 */ |
bf890a93 IT |
2731 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2732 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2733 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2734 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2735 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2736 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2737 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2738 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2739 | /* 80 */ |
1ceb70f8 L |
2740 | { REG_TABLE (REG_80) }, |
2741 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2742 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2743 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2744 | { "testB", { Eb, Gb }, 0 }, |
2745 | { "testS", { Ev, Gv }, 0 }, | |
2746 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2747 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2748 | /* 88 */ |
bf890a93 IT |
2749 | { "movB", { Ebh3, Gb }, 0 }, |
2750 | { "movS", { Evh3, Gv }, 0 }, | |
2751 | { "movB", { Gb, EbS }, 0 }, | |
2752 | { "movS", { Gv, EvS }, 0 }, | |
2753 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2754 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2755 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2756 | { REG_TABLE (REG_8F) }, |
252b5132 | 2757 | /* 90 */ |
1ceb70f8 | 2758 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2759 | { "xchgS", { RMeCX, eAX }, 0 }, |
2760 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2761 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2762 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2763 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2764 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2765 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2766 | /* 98 */ |
bf890a93 IT |
2767 | { "cW{t|}R", { XX }, 0 }, |
2768 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2769 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2770 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2771 | { "pushfT", { XX }, 0 }, |
2772 | { "popfT", { XX }, 0 }, | |
2773 | { "sahf", { XX }, 0 }, | |
2774 | { "lahf", { XX }, 0 }, | |
252b5132 | 2775 | /* a0 */ |
bf890a93 IT |
2776 | { "mov%LB", { AL, Ob }, 0 }, |
2777 | { "mov%LS", { eAX, Ov }, 0 }, | |
2778 | { "mov%LB", { Ob, AL }, 0 }, | |
2779 | { "mov%LS", { Ov, eAX }, 0 }, | |
2780 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2781 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2782 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2783 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2784 | /* a8 */ |
bf890a93 IT |
2785 | { "testB", { AL, Ib }, 0 }, |
2786 | { "testS", { eAX, Iv }, 0 }, | |
2787 | { "stosB", { Ybr, AL }, 0 }, | |
2788 | { "stosS", { Yvr, eAX }, 0 }, | |
2789 | { "lodsB", { ALr, Xb }, 0 }, | |
2790 | { "lodsS", { eAXr, Xv }, 0 }, | |
2791 | { "scasB", { AL, Yb }, 0 }, | |
2792 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2793 | /* b0 */ |
bf890a93 IT |
2794 | { "movB", { RMAL, Ib }, 0 }, |
2795 | { "movB", { RMCL, Ib }, 0 }, | |
2796 | { "movB", { RMDL, Ib }, 0 }, | |
2797 | { "movB", { RMBL, Ib }, 0 }, | |
2798 | { "movB", { RMAH, Ib }, 0 }, | |
2799 | { "movB", { RMCH, Ib }, 0 }, | |
2800 | { "movB", { RMDH, Ib }, 0 }, | |
2801 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2802 | /* b8 */ |
bf890a93 IT |
2803 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2804 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2805 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2806 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2807 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2808 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2809 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2810 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2811 | /* c0 */ |
1ceb70f8 L |
2812 | { REG_TABLE (REG_C0) }, |
2813 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2814 | { "retT", { Iw, BND }, 0 }, |
2815 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2816 | { X86_64_TABLE (X86_64_C4) }, |
2817 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2818 | { REG_TABLE (REG_C6) }, |
2819 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2820 | /* c8 */ |
bf890a93 IT |
2821 | { "enterT", { Iw, Ib }, 0 }, |
2822 | { "leaveT", { XX }, 0 }, | |
2823 | { "Jret{|f}P", { Iw }, 0 }, | |
2824 | { "Jret{|f}P", { XX }, 0 }, | |
2825 | { "int3", { XX }, 0 }, | |
2826 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2827 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2828 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2829 | /* d0 */ |
1ceb70f8 L |
2830 | { REG_TABLE (REG_D0) }, |
2831 | { REG_TABLE (REG_D1) }, | |
2832 | { REG_TABLE (REG_D2) }, | |
2833 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2834 | { X86_64_TABLE (X86_64_D4) }, |
2835 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2836 | { Bad_Opcode }, |
bf890a93 | 2837 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2838 | /* d8 */ |
2839 | { FLOAT }, | |
2840 | { FLOAT }, | |
2841 | { FLOAT }, | |
2842 | { FLOAT }, | |
2843 | { FLOAT }, | |
2844 | { FLOAT }, | |
2845 | { FLOAT }, | |
2846 | { FLOAT }, | |
2847 | /* e0 */ | |
bf890a93 IT |
2848 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2849 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2850 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2851 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2852 | { "inB", { AL, Ib }, 0 }, | |
2853 | { "inG", { zAX, Ib }, 0 }, | |
2854 | { "outB", { Ib, AL }, 0 }, | |
2855 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2856 | /* e8 */ |
a72d2af2 L |
2857 | { X86_64_TABLE (X86_64_E8) }, |
2858 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2859 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2860 | { "jmp", { Jb, BND }, 0 }, |
2861 | { "inB", { AL, indirDX }, 0 }, | |
2862 | { "inG", { zAX, indirDX }, 0 }, | |
2863 | { "outB", { indirDX, AL }, 0 }, | |
2864 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2865 | /* f0 */ |
592d1631 | 2866 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2867 | { "icebp", { XX }, 0 }, |
592d1631 L |
2868 | { Bad_Opcode }, /* repne */ |
2869 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2870 | { "hlt", { XX }, 0 }, |
2871 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2872 | { REG_TABLE (REG_F6) }, |
2873 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2874 | /* f8 */ |
bf890a93 IT |
2875 | { "clc", { XX }, 0 }, |
2876 | { "stc", { XX }, 0 }, | |
2877 | { "cli", { XX }, 0 }, | |
2878 | { "sti", { XX }, 0 }, | |
2879 | { "cld", { XX }, 0 }, | |
2880 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2881 | { REG_TABLE (REG_FE) }, |
2882 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2883 | }; |
2884 | ||
6439fc28 | 2885 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2886 | /* 00 */ |
1ceb70f8 L |
2887 | { REG_TABLE (REG_0F00 ) }, |
2888 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2889 | { "larS", { Gv, Ew }, 0 }, |
2890 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2891 | { Bad_Opcode }, |
bf890a93 IT |
2892 | { "syscall", { XX }, 0 }, |
2893 | { "clts", { XX }, 0 }, | |
2894 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2895 | /* 08 */ |
bf890a93 | 2896 | { "invd", { XX }, 0 }, |
3233d7d0 | 2897 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2898 | { Bad_Opcode }, |
bf890a93 | 2899 | { "ud2", { XX }, 0 }, |
592d1631 | 2900 | { Bad_Opcode }, |
b5b1fc4f | 2901 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2902 | { "femms", { XX }, 0 }, |
2903 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2904 | /* 10 */ |
1ceb70f8 L |
2905 | { PREFIX_TABLE (PREFIX_0F10) }, |
2906 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2907 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2908 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2909 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2910 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2911 | { PREFIX_TABLE (PREFIX_0F16) }, |
2912 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2913 | /* 18 */ |
1ceb70f8 | 2914 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2915 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2916 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2917 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2918 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2919 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2920 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2921 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2922 | /* 20 */ |
bf890a93 IT |
2923 | { "movZ", { Rm, Cm }, 0 }, |
2924 | { "movZ", { Rm, Dm }, 0 }, | |
2925 | { "movZ", { Cm, Rm }, 0 }, | |
2926 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2927 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2928 | { Bad_Opcode }, |
1ceb70f8 | 2929 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2930 | { Bad_Opcode }, |
252b5132 | 2931 | /* 28 */ |
507bd325 L |
2932 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2933 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2934 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2935 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2936 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2937 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2938 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2939 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2940 | /* 30 */ |
bf890a93 IT |
2941 | { "wrmsr", { XX }, 0 }, |
2942 | { "rdtsc", { XX }, 0 }, | |
2943 | { "rdmsr", { XX }, 0 }, | |
2944 | { "rdpmc", { XX }, 0 }, | |
2945 | { "sysenter", { XX }, 0 }, | |
2946 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2947 | { Bad_Opcode }, |
bf890a93 | 2948 | { "getsec", { XX }, 0 }, |
252b5132 | 2949 | /* 38 */ |
507bd325 | 2950 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2951 | { Bad_Opcode }, |
507bd325 | 2952 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2953 | { Bad_Opcode }, |
2954 | { Bad_Opcode }, | |
2955 | { Bad_Opcode }, | |
2956 | { Bad_Opcode }, | |
2957 | { Bad_Opcode }, | |
252b5132 | 2958 | /* 40 */ |
bf890a93 IT |
2959 | { "cmovoS", { Gv, Ev }, 0 }, |
2960 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2961 | { "cmovbS", { Gv, Ev }, 0 }, | |
2962 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2963 | { "cmoveS", { Gv, Ev }, 0 }, | |
2964 | { "cmovneS", { Gv, Ev }, 0 }, | |
2965 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2966 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2967 | /* 48 */ |
bf890a93 IT |
2968 | { "cmovsS", { Gv, Ev }, 0 }, |
2969 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2970 | { "cmovpS", { Gv, Ev }, 0 }, | |
2971 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2972 | { "cmovlS", { Gv, Ev }, 0 }, | |
2973 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2974 | { "cmovleS", { Gv, Ev }, 0 }, | |
2975 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2976 | /* 50 */ |
75c135a8 | 2977 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2978 | { PREFIX_TABLE (PREFIX_0F51) }, |
2979 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2980 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2981 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2982 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2983 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2984 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2985 | /* 58 */ |
1ceb70f8 L |
2986 | { PREFIX_TABLE (PREFIX_0F58) }, |
2987 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2988 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2989 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2990 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2991 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2992 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2993 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2994 | /* 60 */ |
1ceb70f8 L |
2995 | { PREFIX_TABLE (PREFIX_0F60) }, |
2996 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2997 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2998 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2999 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
3000 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
3001 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
3002 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3003 | /* 68 */ |
507bd325 L |
3004 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
3005 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
3006 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
3007 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3008 | { PREFIX_TABLE (PREFIX_0F6C) }, |
3009 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 3010 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 3011 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 3012 | /* 70 */ |
1ceb70f8 L |
3013 | { PREFIX_TABLE (PREFIX_0F70) }, |
3014 | { REG_TABLE (REG_0F71) }, | |
3015 | { REG_TABLE (REG_0F72) }, | |
3016 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
3017 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
3018 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
3019 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
3020 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 3021 | /* 78 */ |
1ceb70f8 L |
3022 | { PREFIX_TABLE (PREFIX_0F78) }, |
3023 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 3024 | { Bad_Opcode }, |
592d1631 | 3025 | { Bad_Opcode }, |
1ceb70f8 L |
3026 | { PREFIX_TABLE (PREFIX_0F7C) }, |
3027 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
3028 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
3029 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 3030 | /* 80 */ |
bf890a93 IT |
3031 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
3032 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
3033 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
3034 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3035 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3036 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
3037 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3038 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3039 | /* 88 */ |
bf890a93 IT |
3040 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
3041 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
3042 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3043 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3044 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
3045 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3046 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
3047 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3048 | /* 90 */ |
bf890a93 IT |
3049 | { "seto", { Eb }, 0 }, |
3050 | { "setno", { Eb }, 0 }, | |
3051 | { "setb", { Eb }, 0 }, | |
3052 | { "setae", { Eb }, 0 }, | |
3053 | { "sete", { Eb }, 0 }, | |
3054 | { "setne", { Eb }, 0 }, | |
3055 | { "setbe", { Eb }, 0 }, | |
3056 | { "seta", { Eb }, 0 }, | |
252b5132 | 3057 | /* 98 */ |
bf890a93 IT |
3058 | { "sets", { Eb }, 0 }, |
3059 | { "setns", { Eb }, 0 }, | |
3060 | { "setp", { Eb }, 0 }, | |
3061 | { "setnp", { Eb }, 0 }, | |
3062 | { "setl", { Eb }, 0 }, | |
3063 | { "setge", { Eb }, 0 }, | |
3064 | { "setle", { Eb }, 0 }, | |
3065 | { "setg", { Eb }, 0 }, | |
252b5132 | 3066 | /* a0 */ |
bf890a93 IT |
3067 | { "pushT", { fs }, 0 }, |
3068 | { "popT", { fs }, 0 }, | |
3069 | { "cpuid", { XX }, 0 }, | |
3070 | { "btS", { Ev, Gv }, 0 }, | |
3071 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
3072 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
3073 | { REG_TABLE (REG_0FA6) }, |
3074 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 3075 | /* a8 */ |
bf890a93 IT |
3076 | { "pushT", { gs }, 0 }, |
3077 | { "popT", { gs }, 0 }, | |
3078 | { "rsm", { XX }, 0 }, | |
3079 | { "btsS", { Evh1, Gv }, 0 }, | |
3080 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3081 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3082 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3083 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3084 | /* b0 */ |
bf890a93 IT |
3085 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3086 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3087 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3088 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3089 | { MOD_TABLE (MOD_0FB4) }, |
3090 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3091 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3092 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3093 | /* b8 */ |
1ceb70f8 | 3094 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 3095 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 3096 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3097 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3098 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3099 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3100 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3101 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3102 | /* c0 */ |
bf890a93 IT |
3103 | { "xaddB", { Ebh1, Gb }, 0 }, |
3104 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3105 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3106 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3107 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3108 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3109 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3110 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3111 | /* c8 */ |
bf890a93 IT |
3112 | { "bswap", { RMeAX }, 0 }, |
3113 | { "bswap", { RMeCX }, 0 }, | |
3114 | { "bswap", { RMeDX }, 0 }, | |
3115 | { "bswap", { RMeBX }, 0 }, | |
3116 | { "bswap", { RMeSP }, 0 }, | |
3117 | { "bswap", { RMeBP }, 0 }, | |
3118 | { "bswap", { RMeSI }, 0 }, | |
3119 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3120 | /* d0 */ |
1ceb70f8 | 3121 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3122 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3123 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3124 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3125 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3126 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3127 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3128 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3129 | /* d8 */ |
507bd325 L |
3130 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3131 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3132 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3133 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3134 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3135 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3136 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3137 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3138 | /* e0 */ |
507bd325 L |
3139 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3140 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3141 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3142 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3143 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3144 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3145 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3146 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3147 | /* e8 */ |
507bd325 L |
3148 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3149 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3150 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3151 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3152 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3153 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3154 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3155 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3156 | /* f0 */ |
1ceb70f8 | 3157 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3158 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3159 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3160 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3161 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3162 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3163 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3164 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3165 | /* f8 */ |
507bd325 L |
3166 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3167 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3168 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3169 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3170 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3171 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3172 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 3173 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
3174 | }; |
3175 | ||
3176 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3177 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3178 | /* ------------------------------- */ | |
3179 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3180 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3181 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3182 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3183 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3184 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3185 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3186 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3187 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3188 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3189 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3190 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3191 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3192 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3193 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3194 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3195 | /* ------------------------------- */ | |
3196 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3197 | }; |
3198 | ||
3199 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3200 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3201 | /* ------------------------------- */ | |
252b5132 | 3202 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3203 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3204 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3205 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3206 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3207 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3208 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3209 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3210 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3211 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3212 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 3213 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 3214 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3215 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3216 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 3217 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
3218 | /* ------------------------------- */ |
3219 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3220 | }; | |
3221 | ||
252b5132 RH |
3222 | static char obuf[100]; |
3223 | static char *obufp; | |
ea397f5b | 3224 | static char *mnemonicendp; |
252b5132 RH |
3225 | static char scratchbuf[100]; |
3226 | static unsigned char *start_codep; | |
3227 | static unsigned char *insn_codep; | |
3228 | static unsigned char *codep; | |
285ca992 | 3229 | static unsigned char *end_codep; |
f16cd0d5 L |
3230 | static int last_lock_prefix; |
3231 | static int last_repz_prefix; | |
3232 | static int last_repnz_prefix; | |
3233 | static int last_data_prefix; | |
3234 | static int last_addr_prefix; | |
3235 | static int last_rex_prefix; | |
3236 | static int last_seg_prefix; | |
d9949a36 | 3237 | static int fwait_prefix; |
285ca992 L |
3238 | /* The active segment register prefix. */ |
3239 | static int active_seg_prefix; | |
f16cd0d5 L |
3240 | #define MAX_CODE_LENGTH 15 |
3241 | /* We can up to 14 prefixes since the maximum instruction length is | |
3242 | 15bytes. */ | |
3243 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3244 | static disassemble_info *the_info; |
7967e09e L |
3245 | static struct |
3246 | { | |
3247 | int mod; | |
7967e09e | 3248 | int reg; |
484c222e | 3249 | int rm; |
7967e09e L |
3250 | } |
3251 | modrm; | |
4bba6815 | 3252 | static unsigned char need_modrm; |
dfc8cf43 L |
3253 | static struct |
3254 | { | |
3255 | int scale; | |
3256 | int index; | |
3257 | int base; | |
3258 | } | |
3259 | sib; | |
c0f3af97 L |
3260 | static struct |
3261 | { | |
3262 | int register_specifier; | |
3263 | int length; | |
3264 | int prefix; | |
3265 | int w; | |
43234a1e L |
3266 | int evex; |
3267 | int r; | |
3268 | int v; | |
3269 | int mask_register_specifier; | |
3270 | int zeroing; | |
3271 | int ll; | |
3272 | int b; | |
c0f3af97 L |
3273 | } |
3274 | vex; | |
3275 | static unsigned char need_vex; | |
3276 | static unsigned char need_vex_reg; | |
dae39acc | 3277 | static unsigned char vex_w_done; |
252b5132 | 3278 | |
ea397f5b L |
3279 | struct op |
3280 | { | |
3281 | const char *name; | |
3282 | unsigned int len; | |
3283 | }; | |
3284 | ||
4bba6815 AM |
3285 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3286 | values are stale. Hitting this abort likely indicates that you | |
3287 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3288 | #define MODRM_CHECK if (!need_modrm) abort () | |
3289 | ||
d708bcba AM |
3290 | static const char **names64; |
3291 | static const char **names32; | |
3292 | static const char **names16; | |
3293 | static const char **names8; | |
3294 | static const char **names8rex; | |
3295 | static const char **names_seg; | |
db51cc60 L |
3296 | static const char *index64; |
3297 | static const char *index32; | |
d708bcba | 3298 | static const char **index16; |
7e8b059b | 3299 | static const char **names_bnd; |
d708bcba AM |
3300 | |
3301 | static const char *intel_names64[] = { | |
3302 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3303 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3304 | }; | |
3305 | static const char *intel_names32[] = { | |
3306 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3307 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3308 | }; | |
3309 | static const char *intel_names16[] = { | |
3310 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3311 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3312 | }; | |
3313 | static const char *intel_names8[] = { | |
3314 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3315 | }; | |
3316 | static const char *intel_names8rex[] = { | |
3317 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3318 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3319 | }; | |
3320 | static const char *intel_names_seg[] = { | |
3321 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3322 | }; | |
db51cc60 L |
3323 | static const char *intel_index64 = "riz"; |
3324 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3325 | static const char *intel_index16[] = { |
3326 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3327 | }; | |
3328 | ||
3329 | static const char *att_names64[] = { | |
3330 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3331 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3332 | }; | |
d708bcba AM |
3333 | static const char *att_names32[] = { |
3334 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3335 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3336 | }; |
d708bcba AM |
3337 | static const char *att_names16[] = { |
3338 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3339 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3340 | }; |
d708bcba AM |
3341 | static const char *att_names8[] = { |
3342 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3343 | }; |
d708bcba AM |
3344 | static const char *att_names8rex[] = { |
3345 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3346 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3347 | }; | |
d708bcba AM |
3348 | static const char *att_names_seg[] = { |
3349 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3350 | }; |
db51cc60 L |
3351 | static const char *att_index64 = "%riz"; |
3352 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3353 | static const char *att_index16[] = { |
3354 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3355 | }; |
3356 | ||
b9733481 L |
3357 | static const char **names_mm; |
3358 | static const char *intel_names_mm[] = { | |
3359 | "mm0", "mm1", "mm2", "mm3", | |
3360 | "mm4", "mm5", "mm6", "mm7" | |
3361 | }; | |
3362 | static const char *att_names_mm[] = { | |
3363 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3364 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3365 | }; | |
3366 | ||
7e8b059b L |
3367 | static const char *intel_names_bnd[] = { |
3368 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3369 | }; | |
3370 | ||
3371 | static const char *att_names_bnd[] = { | |
3372 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3373 | }; | |
3374 | ||
b9733481 L |
3375 | static const char **names_xmm; |
3376 | static const char *intel_names_xmm[] = { | |
3377 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3378 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3379 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3380 | "xmm12", "xmm13", "xmm14", "xmm15", |
3381 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3382 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3383 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3384 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3385 | }; |
3386 | static const char *att_names_xmm[] = { | |
3387 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3388 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3389 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3390 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3391 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3392 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3393 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3394 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3395 | }; |
3396 | ||
3397 | static const char **names_ymm; | |
3398 | static const char *intel_names_ymm[] = { | |
3399 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3400 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3401 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3402 | "ymm12", "ymm13", "ymm14", "ymm15", |
3403 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3404 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3405 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3406 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3407 | }; |
3408 | static const char *att_names_ymm[] = { | |
3409 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3410 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3411 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3412 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3413 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3414 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3415 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3416 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3417 | }; | |
3418 | ||
3419 | static const char **names_zmm; | |
3420 | static const char *intel_names_zmm[] = { | |
3421 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3422 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3423 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3424 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3425 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3426 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3427 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3428 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3429 | }; | |
3430 | static const char *att_names_zmm[] = { | |
3431 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3432 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3433 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3434 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3435 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3436 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3437 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3438 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3439 | }; | |
3440 | ||
3441 | static const char **names_mask; | |
3442 | static const char *intel_names_mask[] = { | |
3443 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3444 | }; | |
3445 | static const char *att_names_mask[] = { | |
3446 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3447 | }; | |
3448 | ||
3449 | static const char *names_rounding[] = | |
3450 | { | |
3451 | "{rn-sae}", | |
3452 | "{rd-sae}", | |
3453 | "{ru-sae}", | |
3454 | "{rz-sae}" | |
b9733481 L |
3455 | }; |
3456 | ||
1ceb70f8 L |
3457 | static const struct dis386 reg_table[][8] = { |
3458 | /* REG_80 */ | |
252b5132 | 3459 | { |
bf890a93 IT |
3460 | { "addA", { Ebh1, Ib }, 0 }, |
3461 | { "orA", { Ebh1, Ib }, 0 }, | |
3462 | { "adcA", { Ebh1, Ib }, 0 }, | |
3463 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3464 | { "andA", { Ebh1, Ib }, 0 }, | |
3465 | { "subA", { Ebh1, Ib }, 0 }, | |
3466 | { "xorA", { Ebh1, Ib }, 0 }, | |
3467 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3468 | }, |
1ceb70f8 | 3469 | /* REG_81 */ |
252b5132 | 3470 | { |
bf890a93 IT |
3471 | { "addQ", { Evh1, Iv }, 0 }, |
3472 | { "orQ", { Evh1, Iv }, 0 }, | |
3473 | { "adcQ", { Evh1, Iv }, 0 }, | |
3474 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3475 | { "andQ", { Evh1, Iv }, 0 }, | |
3476 | { "subQ", { Evh1, Iv }, 0 }, | |
3477 | { "xorQ", { Evh1, Iv }, 0 }, | |
3478 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3479 | }, |
7148c369 | 3480 | /* REG_83 */ |
252b5132 | 3481 | { |
bf890a93 IT |
3482 | { "addQ", { Evh1, sIb }, 0 }, |
3483 | { "orQ", { Evh1, sIb }, 0 }, | |
3484 | { "adcQ", { Evh1, sIb }, 0 }, | |
3485 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3486 | { "andQ", { Evh1, sIb }, 0 }, | |
3487 | { "subQ", { Evh1, sIb }, 0 }, | |
3488 | { "xorQ", { Evh1, sIb }, 0 }, | |
3489 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3490 | }, |
1ceb70f8 | 3491 | /* REG_8F */ |
4e7d34a6 | 3492 | { |
bf890a93 | 3493 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3494 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3495 | { Bad_Opcode }, |
3496 | { Bad_Opcode }, | |
3497 | { Bad_Opcode }, | |
f88c9eb0 | 3498 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3499 | }, |
1ceb70f8 | 3500 | /* REG_C0 */ |
252b5132 | 3501 | { |
bf890a93 IT |
3502 | { "rolA", { Eb, Ib }, 0 }, |
3503 | { "rorA", { Eb, Ib }, 0 }, | |
3504 | { "rclA", { Eb, Ib }, 0 }, | |
3505 | { "rcrA", { Eb, Ib }, 0 }, | |
3506 | { "shlA", { Eb, Ib }, 0 }, | |
3507 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3508 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3509 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3510 | }, |
1ceb70f8 | 3511 | /* REG_C1 */ |
252b5132 | 3512 | { |
bf890a93 IT |
3513 | { "rolQ", { Ev, Ib }, 0 }, |
3514 | { "rorQ", { Ev, Ib }, 0 }, | |
3515 | { "rclQ", { Ev, Ib }, 0 }, | |
3516 | { "rcrQ", { Ev, Ib }, 0 }, | |
3517 | { "shlQ", { Ev, Ib }, 0 }, | |
3518 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3519 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3520 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3521 | }, |
1ceb70f8 | 3522 | /* REG_C6 */ |
4e7d34a6 | 3523 | { |
bf890a93 | 3524 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3525 | { Bad_Opcode }, |
3526 | { Bad_Opcode }, | |
3527 | { Bad_Opcode }, | |
3528 | { Bad_Opcode }, | |
3529 | { Bad_Opcode }, | |
3530 | { Bad_Opcode }, | |
3531 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3532 | }, |
1ceb70f8 | 3533 | /* REG_C7 */ |
4e7d34a6 | 3534 | { |
bf890a93 | 3535 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3536 | { Bad_Opcode }, |
3537 | { Bad_Opcode }, | |
3538 | { Bad_Opcode }, | |
3539 | { Bad_Opcode }, | |
3540 | { Bad_Opcode }, | |
3541 | { Bad_Opcode }, | |
3542 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3543 | }, |
1ceb70f8 | 3544 | /* REG_D0 */ |
252b5132 | 3545 | { |
bf890a93 IT |
3546 | { "rolA", { Eb, I1 }, 0 }, |
3547 | { "rorA", { Eb, I1 }, 0 }, | |
3548 | { "rclA", { Eb, I1 }, 0 }, | |
3549 | { "rcrA", { Eb, I1 }, 0 }, | |
3550 | { "shlA", { Eb, I1 }, 0 }, | |
3551 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3552 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3553 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3554 | }, |
1ceb70f8 | 3555 | /* REG_D1 */ |
252b5132 | 3556 | { |
bf890a93 IT |
3557 | { "rolQ", { Ev, I1 }, 0 }, |
3558 | { "rorQ", { Ev, I1 }, 0 }, | |
3559 | { "rclQ", { Ev, I1 }, 0 }, | |
3560 | { "rcrQ", { Ev, I1 }, 0 }, | |
3561 | { "shlQ", { Ev, I1 }, 0 }, | |
3562 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3563 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3564 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3565 | }, |
1ceb70f8 | 3566 | /* REG_D2 */ |
252b5132 | 3567 | { |
bf890a93 IT |
3568 | { "rolA", { Eb, CL }, 0 }, |
3569 | { "rorA", { Eb, CL }, 0 }, | |
3570 | { "rclA", { Eb, CL }, 0 }, | |
3571 | { "rcrA", { Eb, CL }, 0 }, | |
3572 | { "shlA", { Eb, CL }, 0 }, | |
3573 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3574 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3575 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3576 | }, |
1ceb70f8 | 3577 | /* REG_D3 */ |
252b5132 | 3578 | { |
bf890a93 IT |
3579 | { "rolQ", { Ev, CL }, 0 }, |
3580 | { "rorQ", { Ev, CL }, 0 }, | |
3581 | { "rclQ", { Ev, CL }, 0 }, | |
3582 | { "rcrQ", { Ev, CL }, 0 }, | |
3583 | { "shlQ", { Ev, CL }, 0 }, | |
3584 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3585 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3586 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3587 | }, |
1ceb70f8 | 3588 | /* REG_F6 */ |
252b5132 | 3589 | { |
bf890a93 | 3590 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3591 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3592 | { "notA", { Ebh1 }, 0 }, |
3593 | { "negA", { Ebh1 }, 0 }, | |
3594 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3595 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3596 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3597 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3598 | }, |
1ceb70f8 | 3599 | /* REG_F7 */ |
252b5132 | 3600 | { |
bf890a93 | 3601 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3602 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3603 | { "notQ", { Evh1 }, 0 }, |
3604 | { "negQ", { Evh1 }, 0 }, | |
3605 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3606 | { "imulQ", { Ev }, 0 }, | |
3607 | { "divQ", { Ev }, 0 }, | |
3608 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3609 | }, |
1ceb70f8 | 3610 | /* REG_FE */ |
252b5132 | 3611 | { |
bf890a93 IT |
3612 | { "incA", { Ebh1 }, 0 }, |
3613 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3614 | }, |
1ceb70f8 | 3615 | /* REG_FF */ |
252b5132 | 3616 | { |
bf890a93 IT |
3617 | { "incQ", { Evh1 }, 0 }, |
3618 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3619 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3620 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3621 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3622 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3623 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3624 | { Bad_Opcode }, |
252b5132 | 3625 | }, |
1ceb70f8 | 3626 | /* REG_0F00 */ |
252b5132 | 3627 | { |
bf890a93 IT |
3628 | { "sldtD", { Sv }, 0 }, |
3629 | { "strD", { Sv }, 0 }, | |
3630 | { "lldt", { Ew }, 0 }, | |
3631 | { "ltr", { Ew }, 0 }, | |
3632 | { "verr", { Ew }, 0 }, | |
3633 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3634 | { Bad_Opcode }, |
3635 | { Bad_Opcode }, | |
252b5132 | 3636 | }, |
1ceb70f8 | 3637 | /* REG_0F01 */ |
252b5132 | 3638 | { |
1ceb70f8 L |
3639 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3640 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3641 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3642 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3643 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3644 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3645 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3646 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3647 | }, |
b5b1fc4f | 3648 | /* REG_0F0D */ |
252b5132 | 3649 | { |
bf890a93 IT |
3650 | { "prefetch", { Mb }, 0 }, |
3651 | { "prefetchw", { Mb }, 0 }, | |
3652 | { "prefetchwt1", { Mb }, 0 }, | |
3653 | { "prefetch", { Mb }, 0 }, | |
3654 | { "prefetch", { Mb }, 0 }, | |
3655 | { "prefetch", { Mb }, 0 }, | |
3656 | { "prefetch", { Mb }, 0 }, | |
3657 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3658 | }, |
1ceb70f8 | 3659 | /* REG_0F18 */ |
252b5132 | 3660 | { |
1ceb70f8 L |
3661 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3662 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3663 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3664 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3665 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3666 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3667 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3668 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3669 | }, |
c48935d7 IT |
3670 | /* REG_0F1C_MOD_0 */ |
3671 | { | |
3672 | { "cldemote", { Mb }, 0 }, | |
3673 | { "nopQ", { Ev }, 0 }, | |
3674 | { "nopQ", { Ev }, 0 }, | |
3675 | { "nopQ", { Ev }, 0 }, | |
3676 | { "nopQ", { Ev }, 0 }, | |
3677 | { "nopQ", { Ev }, 0 }, | |
3678 | { "nopQ", { Ev }, 0 }, | |
3679 | { "nopQ", { Ev }, 0 }, | |
3680 | }, | |
603555e5 L |
3681 | /* REG_0F1E_MOD_3 */ |
3682 | { | |
3683 | { "nopQ", { Ev }, 0 }, | |
3684 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3685 | { "nopQ", { Ev }, 0 }, | |
3686 | { "nopQ", { Ev }, 0 }, | |
3687 | { "nopQ", { Ev }, 0 }, | |
3688 | { "nopQ", { Ev }, 0 }, | |
3689 | { "nopQ", { Ev }, 0 }, | |
3690 | { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, | |
3691 | }, | |
1ceb70f8 | 3692 | /* REG_0F71 */ |
a6bd098c | 3693 | { |
592d1631 L |
3694 | { Bad_Opcode }, |
3695 | { Bad_Opcode }, | |
1ceb70f8 | 3696 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3697 | { Bad_Opcode }, |
1ceb70f8 | 3698 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3699 | { Bad_Opcode }, |
1ceb70f8 | 3700 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3701 | }, |
1ceb70f8 | 3702 | /* REG_0F72 */ |
a6bd098c | 3703 | { |
592d1631 L |
3704 | { Bad_Opcode }, |
3705 | { Bad_Opcode }, | |
1ceb70f8 | 3706 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3707 | { Bad_Opcode }, |
1ceb70f8 | 3708 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3709 | { Bad_Opcode }, |
1ceb70f8 | 3710 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3711 | }, |
1ceb70f8 | 3712 | /* REG_0F73 */ |
252b5132 | 3713 | { |
592d1631 L |
3714 | { Bad_Opcode }, |
3715 | { Bad_Opcode }, | |
1ceb70f8 L |
3716 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3717 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3718 | { Bad_Opcode }, |
3719 | { Bad_Opcode }, | |
1ceb70f8 L |
3720 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3721 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3722 | }, |
1ceb70f8 | 3723 | /* REG_0FA6 */ |
252b5132 | 3724 | { |
bf890a93 IT |
3725 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3726 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3727 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3728 | }, |
1ceb70f8 | 3729 | /* REG_0FA7 */ |
4e7d34a6 | 3730 | { |
bf890a93 IT |
3731 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3732 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3733 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3734 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3735 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3736 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3737 | }, |
1ceb70f8 | 3738 | /* REG_0FAE */ |
4e7d34a6 | 3739 | { |
1ceb70f8 L |
3740 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3741 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3742 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3743 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3744 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3745 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3746 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3747 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3748 | }, |
1ceb70f8 | 3749 | /* REG_0FBA */ |
252b5132 | 3750 | { |
592d1631 L |
3751 | { Bad_Opcode }, |
3752 | { Bad_Opcode }, | |
3753 | { Bad_Opcode }, | |
3754 | { Bad_Opcode }, | |
bf890a93 IT |
3755 | { "btQ", { Ev, Ib }, 0 }, |
3756 | { "btsQ", { Evh1, Ib }, 0 }, | |
3757 | { "btrQ", { Evh1, Ib }, 0 }, | |
3758 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3759 | }, |
1ceb70f8 | 3760 | /* REG_0FC7 */ |
c608c12e | 3761 | { |
592d1631 | 3762 | { Bad_Opcode }, |
bf890a93 | 3763 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3764 | { Bad_Opcode }, |
963f3586 IT |
3765 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3766 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3767 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3768 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3769 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3770 | }, |
592a252b | 3771 | /* REG_VEX_0F71 */ |
c0f3af97 | 3772 | { |
592d1631 L |
3773 | { Bad_Opcode }, |
3774 | { Bad_Opcode }, | |
592a252b | 3775 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3776 | { Bad_Opcode }, |
592a252b | 3777 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3778 | { Bad_Opcode }, |
592a252b | 3779 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3780 | }, |
592a252b | 3781 | /* REG_VEX_0F72 */ |
c0f3af97 | 3782 | { |
592d1631 L |
3783 | { Bad_Opcode }, |
3784 | { Bad_Opcode }, | |
592a252b | 3785 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3786 | { Bad_Opcode }, |
592a252b | 3787 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3788 | { Bad_Opcode }, |
592a252b | 3789 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3790 | }, |
592a252b | 3791 | /* REG_VEX_0F73 */ |
c0f3af97 | 3792 | { |
592d1631 L |
3793 | { Bad_Opcode }, |
3794 | { Bad_Opcode }, | |
592a252b L |
3795 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3796 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3797 | { Bad_Opcode }, |
3798 | { Bad_Opcode }, | |
592a252b L |
3799 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3800 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3801 | }, |
592a252b | 3802 | /* REG_VEX_0FAE */ |
c0f3af97 | 3803 | { |
592d1631 L |
3804 | { Bad_Opcode }, |
3805 | { Bad_Opcode }, | |
592a252b L |
3806 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3807 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3808 | }, |
f12dc422 L |
3809 | /* REG_VEX_0F38F3 */ |
3810 | { | |
3811 | { Bad_Opcode }, | |
3812 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3813 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3814 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3815 | }, | |
f88c9eb0 SP |
3816 | /* REG_XOP_LWPCB */ |
3817 | { | |
bf890a93 IT |
3818 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3819 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3820 | }, |
3821 | /* REG_XOP_LWP */ | |
3822 | { | |
bf890a93 IT |
3823 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3824 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3825 | }, |
2a2a0f38 QN |
3826 | /* REG_XOP_TBM_01 */ |
3827 | { | |
3828 | { Bad_Opcode }, | |
bf890a93 IT |
3829 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3830 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3831 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3832 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3833 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3834 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3835 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3836 | }, |
3837 | /* REG_XOP_TBM_02 */ | |
3838 | { | |
3839 | { Bad_Opcode }, | |
bf890a93 | 3840 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3841 | { Bad_Opcode }, |
3842 | { Bad_Opcode }, | |
3843 | { Bad_Opcode }, | |
3844 | { Bad_Opcode }, | |
bf890a93 | 3845 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3846 | }, |
43234a1e L |
3847 | #define NEED_REG_TABLE |
3848 | #include "i386-dis-evex.h" | |
3849 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3850 | }; |
3851 | ||
1ceb70f8 L |
3852 | static const struct dis386 prefix_table[][4] = { |
3853 | /* PREFIX_90 */ | |
252b5132 | 3854 | { |
bf890a93 IT |
3855 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3856 | { "pause", { XX }, 0 }, | |
3857 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3858 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3859 | }, |
4e7d34a6 | 3860 | |
603555e5 L |
3861 | /* PREFIX_MOD_0_0F01_REG_5 */ |
3862 | { | |
3863 | { Bad_Opcode }, | |
3864 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3865 | }, | |
3866 | ||
2234eee6 | 3867 | /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ |
603555e5 L |
3868 | { |
3869 | { Bad_Opcode }, | |
2234eee6 | 3870 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3871 | }, |
3872 | ||
3873 | /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ | |
3874 | { | |
3875 | { Bad_Opcode }, | |
c2f76402 | 3876 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3877 | }, |
3878 | ||
3233d7d0 IT |
3879 | /* PREFIX_0F09 */ |
3880 | { | |
3881 | { "wbinvd", { XX }, 0 }, | |
3882 | { "wbnoinvd", { XX }, 0 }, | |
3883 | }, | |
3884 | ||
1ceb70f8 | 3885 | /* PREFIX_0F10 */ |
cc0ec051 | 3886 | { |
507bd325 L |
3887 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3888 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3889 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3890 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3891 | }, |
4e7d34a6 | 3892 | |
1ceb70f8 | 3893 | /* PREFIX_0F11 */ |
30d1c836 | 3894 | { |
507bd325 L |
3895 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3896 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3897 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3898 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3899 | }, |
252b5132 | 3900 | |
1ceb70f8 | 3901 | /* PREFIX_0F12 */ |
c608c12e | 3902 | { |
1ceb70f8 | 3903 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3904 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3905 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3906 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3907 | }, |
4e7d34a6 | 3908 | |
1ceb70f8 | 3909 | /* PREFIX_0F16 */ |
c608c12e | 3910 | { |
1ceb70f8 | 3911 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3912 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3913 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3914 | }, |
4e7d34a6 | 3915 | |
7e8b059b L |
3916 | /* PREFIX_0F1A */ |
3917 | { | |
3918 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3919 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3920 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3921 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3922 | }, |
3923 | ||
3924 | /* PREFIX_0F1B */ | |
3925 | { | |
3926 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3927 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3928 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3929 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3930 | }, |
3931 | ||
c48935d7 IT |
3932 | /* PREFIX_0F1C */ |
3933 | { | |
3934 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3935 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3936 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3937 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3938 | }, | |
3939 | ||
603555e5 L |
3940 | /* PREFIX_0F1E */ |
3941 | { | |
3942 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3943 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3944 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3945 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3946 | }, | |
3947 | ||
1ceb70f8 | 3948 | /* PREFIX_0F2A */ |
c608c12e | 3949 | { |
507bd325 L |
3950 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3951 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3952 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3953 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3954 | }, |
4e7d34a6 | 3955 | |
1ceb70f8 | 3956 | /* PREFIX_0F2B */ |
c608c12e | 3957 | { |
75c135a8 L |
3958 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3959 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3960 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3961 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3962 | }, |
4e7d34a6 | 3963 | |
1ceb70f8 | 3964 | /* PREFIX_0F2C */ |
c608c12e | 3965 | { |
507bd325 | 3966 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3967 | { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3968 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3969 | { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3970 | }, |
4e7d34a6 | 3971 | |
1ceb70f8 | 3972 | /* PREFIX_0F2D */ |
c608c12e | 3973 | { |
507bd325 | 3974 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3975 | { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3976 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3977 | { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3978 | }, |
4e7d34a6 | 3979 | |
1ceb70f8 | 3980 | /* PREFIX_0F2E */ |
c608c12e | 3981 | { |
bf890a93 | 3982 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3983 | { Bad_Opcode }, |
bf890a93 | 3984 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3985 | }, |
4e7d34a6 | 3986 | |
1ceb70f8 | 3987 | /* PREFIX_0F2F */ |
c608c12e | 3988 | { |
bf890a93 | 3989 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3990 | { Bad_Opcode }, |
bf890a93 | 3991 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3992 | }, |
4e7d34a6 | 3993 | |
1ceb70f8 | 3994 | /* PREFIX_0F51 */ |
c608c12e | 3995 | { |
507bd325 L |
3996 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3997 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3998 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3999 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 4000 | }, |
4e7d34a6 | 4001 | |
1ceb70f8 | 4002 | /* PREFIX_0F52 */ |
c608c12e | 4003 | { |
507bd325 L |
4004 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
4005 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 4006 | }, |
4e7d34a6 | 4007 | |
1ceb70f8 | 4008 | /* PREFIX_0F53 */ |
c608c12e | 4009 | { |
507bd325 L |
4010 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
4011 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 4012 | }, |
4e7d34a6 | 4013 | |
1ceb70f8 | 4014 | /* PREFIX_0F58 */ |
c608c12e | 4015 | { |
507bd325 L |
4016 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
4017 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
4018 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
4019 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 4020 | }, |
4e7d34a6 | 4021 | |
1ceb70f8 | 4022 | /* PREFIX_0F59 */ |
c608c12e | 4023 | { |
507bd325 L |
4024 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
4025 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
4026 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
4027 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4028 | }, |
4e7d34a6 | 4029 | |
1ceb70f8 | 4030 | /* PREFIX_0F5A */ |
041bd2e0 | 4031 | { |
507bd325 L |
4032 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
4033 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
4034 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
4035 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4036 | }, |
4e7d34a6 | 4037 | |
1ceb70f8 | 4038 | /* PREFIX_0F5B */ |
041bd2e0 | 4039 | { |
507bd325 L |
4040 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
4041 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4042 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 4043 | }, |
4e7d34a6 | 4044 | |
1ceb70f8 | 4045 | /* PREFIX_0F5C */ |
041bd2e0 | 4046 | { |
507bd325 L |
4047 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
4048 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
4049 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
4050 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4051 | }, |
4e7d34a6 | 4052 | |
1ceb70f8 | 4053 | /* PREFIX_0F5D */ |
041bd2e0 | 4054 | { |
507bd325 L |
4055 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
4056 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
4057 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
4058 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4059 | }, |
4e7d34a6 | 4060 | |
1ceb70f8 | 4061 | /* PREFIX_0F5E */ |
041bd2e0 | 4062 | { |
507bd325 L |
4063 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
4064 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
4065 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
4066 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4067 | }, |
4e7d34a6 | 4068 | |
1ceb70f8 | 4069 | /* PREFIX_0F5F */ |
041bd2e0 | 4070 | { |
507bd325 L |
4071 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
4072 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
4073 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
4074 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4075 | }, |
4e7d34a6 | 4076 | |
1ceb70f8 | 4077 | /* PREFIX_0F60 */ |
041bd2e0 | 4078 | { |
507bd325 | 4079 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4080 | { Bad_Opcode }, |
507bd325 | 4081 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4082 | }, |
4e7d34a6 | 4083 | |
1ceb70f8 | 4084 | /* PREFIX_0F61 */ |
041bd2e0 | 4085 | { |
507bd325 | 4086 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4087 | { Bad_Opcode }, |
507bd325 | 4088 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4089 | }, |
4e7d34a6 | 4090 | |
1ceb70f8 | 4091 | /* PREFIX_0F62 */ |
041bd2e0 | 4092 | { |
507bd325 | 4093 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4094 | { Bad_Opcode }, |
507bd325 | 4095 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4096 | }, |
4e7d34a6 | 4097 | |
1ceb70f8 | 4098 | /* PREFIX_0F6C */ |
041bd2e0 | 4099 | { |
592d1631 L |
4100 | { Bad_Opcode }, |
4101 | { Bad_Opcode }, | |
507bd325 | 4102 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 4103 | }, |
4e7d34a6 | 4104 | |
1ceb70f8 | 4105 | /* PREFIX_0F6D */ |
0f17484f | 4106 | { |
592d1631 L |
4107 | { Bad_Opcode }, |
4108 | { Bad_Opcode }, | |
507bd325 | 4109 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 4110 | }, |
4e7d34a6 | 4111 | |
1ceb70f8 | 4112 | /* PREFIX_0F6F */ |
ca164297 | 4113 | { |
507bd325 L |
4114 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
4115 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
4116 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4117 | }, |
4e7d34a6 | 4118 | |
1ceb70f8 | 4119 | /* PREFIX_0F70 */ |
4e7d34a6 | 4120 | { |
507bd325 L |
4121 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
4122 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4123 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
4124 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4125 | }, |
4126 | ||
92fddf8e L |
4127 | /* PREFIX_0F73_REG_3 */ |
4128 | { | |
592d1631 L |
4129 | { Bad_Opcode }, |
4130 | { Bad_Opcode }, | |
bf890a93 | 4131 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
4132 | }, |
4133 | ||
4134 | /* PREFIX_0F73_REG_7 */ | |
4135 | { | |
592d1631 L |
4136 | { Bad_Opcode }, |
4137 | { Bad_Opcode }, | |
bf890a93 | 4138 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
4139 | }, |
4140 | ||
1ceb70f8 | 4141 | /* PREFIX_0F78 */ |
4e7d34a6 | 4142 | { |
bf890a93 | 4143 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4144 | { Bad_Opcode }, |
bf890a93 IT |
4145 | {"extrq", { XS, Ib, Ib }, 0 }, |
4146 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4147 | }, |
4148 | ||
1ceb70f8 | 4149 | /* PREFIX_0F79 */ |
4e7d34a6 | 4150 | { |
bf890a93 | 4151 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4152 | { Bad_Opcode }, |
bf890a93 IT |
4153 | {"extrq", { XM, XS }, 0 }, |
4154 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4155 | }, |
4156 | ||
1ceb70f8 | 4157 | /* PREFIX_0F7C */ |
ca164297 | 4158 | { |
592d1631 L |
4159 | { Bad_Opcode }, |
4160 | { Bad_Opcode }, | |
507bd325 L |
4161 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4162 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4163 | }, |
4e7d34a6 | 4164 | |
1ceb70f8 | 4165 | /* PREFIX_0F7D */ |
ca164297 | 4166 | { |
592d1631 L |
4167 | { Bad_Opcode }, |
4168 | { Bad_Opcode }, | |
507bd325 L |
4169 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4170 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4171 | }, |
4e7d34a6 | 4172 | |
1ceb70f8 | 4173 | /* PREFIX_0F7E */ |
ca164297 | 4174 | { |
507bd325 L |
4175 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4176 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4177 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4178 | }, |
4e7d34a6 | 4179 | |
1ceb70f8 | 4180 | /* PREFIX_0F7F */ |
ca164297 | 4181 | { |
507bd325 L |
4182 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4183 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4184 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4185 | }, |
4e7d34a6 | 4186 | |
c7b8aa3a L |
4187 | /* PREFIX_0FAE_REG_0 */ |
4188 | { | |
4189 | { Bad_Opcode }, | |
bf890a93 | 4190 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4191 | }, |
4192 | ||
4193 | /* PREFIX_0FAE_REG_1 */ | |
4194 | { | |
4195 | { Bad_Opcode }, | |
bf890a93 | 4196 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4197 | }, |
4198 | ||
4199 | /* PREFIX_0FAE_REG_2 */ | |
4200 | { | |
4201 | { Bad_Opcode }, | |
bf890a93 | 4202 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4203 | }, |
4204 | ||
4205 | /* PREFIX_0FAE_REG_3 */ | |
4206 | { | |
4207 | { Bad_Opcode }, | |
bf890a93 | 4208 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4209 | }, |
4210 | ||
6b40c462 L |
4211 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
4212 | { | |
4213 | { "xsave", { FXSAVE }, 0 }, | |
4214 | { "ptwrite%LQ", { Edq }, 0 }, | |
4215 | }, | |
4216 | ||
4217 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
4218 | { | |
4219 | { Bad_Opcode }, | |
4220 | { "ptwrite%LQ", { Edq }, 0 }, | |
4221 | }, | |
4222 | ||
603555e5 L |
4223 | /* PREFIX_MOD_0_0FAE_REG_5 */ |
4224 | { | |
4225 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
4226 | }, |
4227 | ||
4228 | /* PREFIX_MOD_3_0FAE_REG_5 */ | |
4229 | { | |
4230 | { "lfence", { Skip_MODRM }, 0 }, | |
4231 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4232 | }, |
4233 | ||
de89d0a3 | 4234 | /* PREFIX_MOD_0_0FAE_REG_6 */ |
c5e7287a | 4235 | { |
603555e5 L |
4236 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4237 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4238 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4239 | }, |
4240 | ||
de89d0a3 IT |
4241 | /* PREFIX_MOD_1_0FAE_REG_6 */ |
4242 | { | |
4243 | { RM_TABLE (RM_0FAE_REG_6) }, | |
4244 | { "umonitor", { Eva }, PREFIX_OPCODE }, | |
ae1d3843 L |
4245 | { "tpause", { Edq }, PREFIX_OPCODE }, |
4246 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
4247 | }, |
4248 | ||
963f3586 IT |
4249 | /* PREFIX_0FAE_REG_7 */ |
4250 | { | |
bf890a93 | 4251 | { "clflush", { Mb }, 0 }, |
963f3586 | 4252 | { Bad_Opcode }, |
bf890a93 | 4253 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4254 | }, |
4255 | ||
1ceb70f8 | 4256 | /* PREFIX_0FB8 */ |
ca164297 | 4257 | { |
592d1631 | 4258 | { Bad_Opcode }, |
bf890a93 | 4259 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4260 | }, |
4e7d34a6 | 4261 | |
f12dc422 L |
4262 | /* PREFIX_0FBC */ |
4263 | { | |
bf890a93 IT |
4264 | { "bsfS", { Gv, Ev }, 0 }, |
4265 | { "tzcntS", { Gv, Ev }, 0 }, | |
4266 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4267 | }, |
4268 | ||
1ceb70f8 | 4269 | /* PREFIX_0FBD */ |
050dfa73 | 4270 | { |
bf890a93 IT |
4271 | { "bsrS", { Gv, Ev }, 0 }, |
4272 | { "lzcntS", { Gv, Ev }, 0 }, | |
4273 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4274 | }, |
4275 | ||
1ceb70f8 | 4276 | /* PREFIX_0FC2 */ |
050dfa73 | 4277 | { |
507bd325 L |
4278 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4279 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4280 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4281 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4282 | }, |
246c51aa | 4283 | |
a8484f96 | 4284 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4285 | { |
a8484f96 | 4286 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4287 | }, |
4288 | ||
f24bcbaa | 4289 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4290 | { |
bf890a93 IT |
4291 | { "vmptrld",{ Mq }, 0 }, |
4292 | { "vmxon", { Mq }, 0 }, | |
4293 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4294 | }, |
4295 | ||
f24bcbaa L |
4296 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4297 | { | |
4298 | { "rdrand", { Ev }, 0 }, | |
4299 | { Bad_Opcode }, | |
4300 | { "rdrand", { Ev }, 0 } | |
4301 | }, | |
4302 | ||
4303 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4304 | { | |
4305 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4306 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4307 | { "rdseed", { Ev }, 0 }, |
4308 | }, | |
4309 | ||
1ceb70f8 | 4310 | /* PREFIX_0FD0 */ |
050dfa73 | 4311 | { |
592d1631 L |
4312 | { Bad_Opcode }, |
4313 | { Bad_Opcode }, | |
bf890a93 IT |
4314 | { "addsubpd", { XM, EXx }, 0 }, |
4315 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4316 | }, |
050dfa73 | 4317 | |
1ceb70f8 | 4318 | /* PREFIX_0FD6 */ |
050dfa73 | 4319 | { |
592d1631 | 4320 | { Bad_Opcode }, |
bf890a93 IT |
4321 | { "movq2dq",{ XM, MS }, 0 }, |
4322 | { "movq", { EXqS, XM }, 0 }, | |
4323 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4324 | }, |
4325 | ||
1ceb70f8 | 4326 | /* PREFIX_0FE6 */ |
7918206c | 4327 | { |
592d1631 | 4328 | { Bad_Opcode }, |
507bd325 L |
4329 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4330 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4331 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4332 | }, |
8b38ad71 | 4333 | |
1ceb70f8 | 4334 | /* PREFIX_0FE7 */ |
8b38ad71 | 4335 | { |
507bd325 | 4336 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4337 | { Bad_Opcode }, |
75c135a8 | 4338 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4339 | }, |
4340 | ||
1ceb70f8 | 4341 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4342 | { |
592d1631 L |
4343 | { Bad_Opcode }, |
4344 | { Bad_Opcode }, | |
4345 | { Bad_Opcode }, | |
1ceb70f8 | 4346 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4347 | }, |
4348 | ||
1ceb70f8 | 4349 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4350 | { |
507bd325 | 4351 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4352 | { Bad_Opcode }, |
507bd325 | 4353 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4354 | }, |
42903f7f | 4355 | |
1ceb70f8 | 4356 | /* PREFIX_0F3810 */ |
42903f7f | 4357 | { |
592d1631 L |
4358 | { Bad_Opcode }, |
4359 | { Bad_Opcode }, | |
507bd325 | 4360 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4361 | }, |
4362 | ||
1ceb70f8 | 4363 | /* PREFIX_0F3814 */ |
42903f7f | 4364 | { |
592d1631 L |
4365 | { Bad_Opcode }, |
4366 | { Bad_Opcode }, | |
507bd325 | 4367 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4368 | }, |
4369 | ||
1ceb70f8 | 4370 | /* PREFIX_0F3815 */ |
42903f7f | 4371 | { |
592d1631 L |
4372 | { Bad_Opcode }, |
4373 | { Bad_Opcode }, | |
507bd325 | 4374 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4375 | }, |
4376 | ||
1ceb70f8 | 4377 | /* PREFIX_0F3817 */ |
42903f7f | 4378 | { |
592d1631 L |
4379 | { Bad_Opcode }, |
4380 | { Bad_Opcode }, | |
507bd325 | 4381 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4382 | }, |
4383 | ||
1ceb70f8 | 4384 | /* PREFIX_0F3820 */ |
42903f7f | 4385 | { |
592d1631 L |
4386 | { Bad_Opcode }, |
4387 | { Bad_Opcode }, | |
507bd325 | 4388 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4389 | }, |
4390 | ||
1ceb70f8 | 4391 | /* PREFIX_0F3821 */ |
42903f7f | 4392 | { |
592d1631 L |
4393 | { Bad_Opcode }, |
4394 | { Bad_Opcode }, | |
507bd325 | 4395 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4396 | }, |
4397 | ||
1ceb70f8 | 4398 | /* PREFIX_0F3822 */ |
42903f7f | 4399 | { |
592d1631 L |
4400 | { Bad_Opcode }, |
4401 | { Bad_Opcode }, | |
507bd325 | 4402 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4403 | }, |
4404 | ||
1ceb70f8 | 4405 | /* PREFIX_0F3823 */ |
42903f7f | 4406 | { |
592d1631 L |
4407 | { Bad_Opcode }, |
4408 | { Bad_Opcode }, | |
507bd325 | 4409 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4410 | }, |
4411 | ||
1ceb70f8 | 4412 | /* PREFIX_0F3824 */ |
42903f7f | 4413 | { |
592d1631 L |
4414 | { Bad_Opcode }, |
4415 | { Bad_Opcode }, | |
507bd325 | 4416 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4417 | }, |
4418 | ||
1ceb70f8 | 4419 | /* PREFIX_0F3825 */ |
42903f7f | 4420 | { |
592d1631 L |
4421 | { Bad_Opcode }, |
4422 | { Bad_Opcode }, | |
507bd325 | 4423 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4424 | }, |
4425 | ||
1ceb70f8 | 4426 | /* PREFIX_0F3828 */ |
42903f7f | 4427 | { |
592d1631 L |
4428 | { Bad_Opcode }, |
4429 | { Bad_Opcode }, | |
507bd325 | 4430 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4431 | }, |
4432 | ||
1ceb70f8 | 4433 | /* PREFIX_0F3829 */ |
42903f7f | 4434 | { |
592d1631 L |
4435 | { Bad_Opcode }, |
4436 | { Bad_Opcode }, | |
507bd325 | 4437 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4438 | }, |
4439 | ||
1ceb70f8 | 4440 | /* PREFIX_0F382A */ |
42903f7f | 4441 | { |
592d1631 L |
4442 | { Bad_Opcode }, |
4443 | { Bad_Opcode }, | |
75c135a8 | 4444 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4445 | }, |
4446 | ||
1ceb70f8 | 4447 | /* PREFIX_0F382B */ |
42903f7f | 4448 | { |
592d1631 L |
4449 | { Bad_Opcode }, |
4450 | { Bad_Opcode }, | |
507bd325 | 4451 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4452 | }, |
4453 | ||
1ceb70f8 | 4454 | /* PREFIX_0F3830 */ |
42903f7f | 4455 | { |
592d1631 L |
4456 | { Bad_Opcode }, |
4457 | { Bad_Opcode }, | |
507bd325 | 4458 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4459 | }, |
4460 | ||
1ceb70f8 | 4461 | /* PREFIX_0F3831 */ |
42903f7f | 4462 | { |
592d1631 L |
4463 | { Bad_Opcode }, |
4464 | { Bad_Opcode }, | |
507bd325 | 4465 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4466 | }, |
4467 | ||
1ceb70f8 | 4468 | /* PREFIX_0F3832 */ |
42903f7f | 4469 | { |
592d1631 L |
4470 | { Bad_Opcode }, |
4471 | { Bad_Opcode }, | |
507bd325 | 4472 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4473 | }, |
4474 | ||
1ceb70f8 | 4475 | /* PREFIX_0F3833 */ |
42903f7f | 4476 | { |
592d1631 L |
4477 | { Bad_Opcode }, |
4478 | { Bad_Opcode }, | |
507bd325 | 4479 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4480 | }, |
4481 | ||
1ceb70f8 | 4482 | /* PREFIX_0F3834 */ |
42903f7f | 4483 | { |
592d1631 L |
4484 | { Bad_Opcode }, |
4485 | { Bad_Opcode }, | |
507bd325 | 4486 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4487 | }, |
4488 | ||
1ceb70f8 | 4489 | /* PREFIX_0F3835 */ |
42903f7f | 4490 | { |
592d1631 L |
4491 | { Bad_Opcode }, |
4492 | { Bad_Opcode }, | |
507bd325 | 4493 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4494 | }, |
4495 | ||
1ceb70f8 | 4496 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4497 | { |
592d1631 L |
4498 | { Bad_Opcode }, |
4499 | { Bad_Opcode }, | |
507bd325 | 4500 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4501 | }, |
4502 | ||
1ceb70f8 | 4503 | /* PREFIX_0F3838 */ |
42903f7f | 4504 | { |
592d1631 L |
4505 | { Bad_Opcode }, |
4506 | { Bad_Opcode }, | |
507bd325 | 4507 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4508 | }, |
4509 | ||
1ceb70f8 | 4510 | /* PREFIX_0F3839 */ |
42903f7f | 4511 | { |
592d1631 L |
4512 | { Bad_Opcode }, |
4513 | { Bad_Opcode }, | |
507bd325 | 4514 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4515 | }, |
4516 | ||
1ceb70f8 | 4517 | /* PREFIX_0F383A */ |
42903f7f | 4518 | { |
592d1631 L |
4519 | { Bad_Opcode }, |
4520 | { Bad_Opcode }, | |
507bd325 | 4521 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4522 | }, |
4523 | ||
1ceb70f8 | 4524 | /* PREFIX_0F383B */ |
42903f7f | 4525 | { |
592d1631 L |
4526 | { Bad_Opcode }, |
4527 | { Bad_Opcode }, | |
507bd325 | 4528 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4529 | }, |
4530 | ||
1ceb70f8 | 4531 | /* PREFIX_0F383C */ |
42903f7f | 4532 | { |
592d1631 L |
4533 | { Bad_Opcode }, |
4534 | { Bad_Opcode }, | |
507bd325 | 4535 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4536 | }, |
4537 | ||
1ceb70f8 | 4538 | /* PREFIX_0F383D */ |
42903f7f | 4539 | { |
592d1631 L |
4540 | { Bad_Opcode }, |
4541 | { Bad_Opcode }, | |
507bd325 | 4542 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4543 | }, |
4544 | ||
1ceb70f8 | 4545 | /* PREFIX_0F383E */ |
42903f7f | 4546 | { |
592d1631 L |
4547 | { Bad_Opcode }, |
4548 | { Bad_Opcode }, | |
507bd325 | 4549 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4550 | }, |
4551 | ||
1ceb70f8 | 4552 | /* PREFIX_0F383F */ |
42903f7f | 4553 | { |
592d1631 L |
4554 | { Bad_Opcode }, |
4555 | { Bad_Opcode }, | |
507bd325 | 4556 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4557 | }, |
4558 | ||
1ceb70f8 | 4559 | /* PREFIX_0F3840 */ |
42903f7f | 4560 | { |
592d1631 L |
4561 | { Bad_Opcode }, |
4562 | { Bad_Opcode }, | |
507bd325 | 4563 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4564 | }, |
4565 | ||
1ceb70f8 | 4566 | /* PREFIX_0F3841 */ |
42903f7f | 4567 | { |
592d1631 L |
4568 | { Bad_Opcode }, |
4569 | { Bad_Opcode }, | |
507bd325 | 4570 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4571 | }, |
4572 | ||
f1f8f695 L |
4573 | /* PREFIX_0F3880 */ |
4574 | { | |
592d1631 L |
4575 | { Bad_Opcode }, |
4576 | { Bad_Opcode }, | |
507bd325 | 4577 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4578 | }, |
4579 | ||
4580 | /* PREFIX_0F3881 */ | |
4581 | { | |
592d1631 L |
4582 | { Bad_Opcode }, |
4583 | { Bad_Opcode }, | |
507bd325 | 4584 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4585 | }, |
4586 | ||
6c30d220 L |
4587 | /* PREFIX_0F3882 */ |
4588 | { | |
4589 | { Bad_Opcode }, | |
4590 | { Bad_Opcode }, | |
507bd325 | 4591 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4592 | }, |
4593 | ||
a0046408 L |
4594 | /* PREFIX_0F38C8 */ |
4595 | { | |
507bd325 | 4596 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4597 | }, |
4598 | ||
4599 | /* PREFIX_0F38C9 */ | |
4600 | { | |
507bd325 | 4601 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4602 | }, |
4603 | ||
4604 | /* PREFIX_0F38CA */ | |
4605 | { | |
507bd325 | 4606 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4607 | }, |
4608 | ||
4609 | /* PREFIX_0F38CB */ | |
4610 | { | |
507bd325 | 4611 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4612 | }, |
4613 | ||
4614 | /* PREFIX_0F38CC */ | |
4615 | { | |
507bd325 | 4616 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4617 | }, |
4618 | ||
4619 | /* PREFIX_0F38CD */ | |
4620 | { | |
507bd325 | 4621 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4622 | }, |
4623 | ||
48521003 IT |
4624 | /* PREFIX_0F38CF */ |
4625 | { | |
4626 | { Bad_Opcode }, | |
4627 | { Bad_Opcode }, | |
4628 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4629 | }, | |
4630 | ||
c0f3af97 L |
4631 | /* PREFIX_0F38DB */ |
4632 | { | |
592d1631 L |
4633 | { Bad_Opcode }, |
4634 | { Bad_Opcode }, | |
507bd325 | 4635 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4636 | }, |
4637 | ||
4638 | /* PREFIX_0F38DC */ | |
4639 | { | |
592d1631 L |
4640 | { Bad_Opcode }, |
4641 | { Bad_Opcode }, | |
507bd325 | 4642 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4643 | }, |
4644 | ||
4645 | /* PREFIX_0F38DD */ | |
4646 | { | |
592d1631 L |
4647 | { Bad_Opcode }, |
4648 | { Bad_Opcode }, | |
507bd325 | 4649 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4650 | }, |
4651 | ||
4652 | /* PREFIX_0F38DE */ | |
4653 | { | |
592d1631 L |
4654 | { Bad_Opcode }, |
4655 | { Bad_Opcode }, | |
507bd325 | 4656 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4657 | }, |
4658 | ||
4659 | /* PREFIX_0F38DF */ | |
4660 | { | |
592d1631 L |
4661 | { Bad_Opcode }, |
4662 | { Bad_Opcode }, | |
507bd325 | 4663 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4664 | }, |
4665 | ||
1ceb70f8 | 4666 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4667 | { |
507bd325 | 4668 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4669 | { Bad_Opcode }, |
507bd325 L |
4670 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4671 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4672 | }, |
4673 | ||
1ceb70f8 | 4674 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4675 | { |
507bd325 | 4676 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4677 | { Bad_Opcode }, |
507bd325 L |
4678 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4679 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4680 | }, |
4681 | ||
603555e5 | 4682 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4683 | { |
4684 | { Bad_Opcode }, | |
603555e5 L |
4685 | { Bad_Opcode }, |
4686 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4687 | }, | |
4688 | ||
4689 | /* PREFIX_0F38F6 */ | |
4690 | { | |
4691 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4692 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4693 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4694 | { Bad_Opcode }, |
4695 | }, | |
4696 | ||
c0a30a9f L |
4697 | /* PREFIX_0F38F8 */ |
4698 | { | |
4699 | { Bad_Opcode }, | |
4700 | { Bad_Opcode }, | |
4701 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, | |
4702 | }, | |
4703 | ||
4704 | /* PREFIX_0F38F9 */ | |
4705 | { | |
4706 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4707 | }, | |
4708 | ||
1ceb70f8 | 4709 | /* PREFIX_0F3A08 */ |
42903f7f | 4710 | { |
592d1631 L |
4711 | { Bad_Opcode }, |
4712 | { Bad_Opcode }, | |
507bd325 | 4713 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4714 | }, |
4715 | ||
1ceb70f8 | 4716 | /* PREFIX_0F3A09 */ |
42903f7f | 4717 | { |
592d1631 L |
4718 | { Bad_Opcode }, |
4719 | { Bad_Opcode }, | |
507bd325 | 4720 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4721 | }, |
4722 | ||
1ceb70f8 | 4723 | /* PREFIX_0F3A0A */ |
42903f7f | 4724 | { |
592d1631 L |
4725 | { Bad_Opcode }, |
4726 | { Bad_Opcode }, | |
507bd325 | 4727 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4728 | }, |
4729 | ||
1ceb70f8 | 4730 | /* PREFIX_0F3A0B */ |
42903f7f | 4731 | { |
592d1631 L |
4732 | { Bad_Opcode }, |
4733 | { Bad_Opcode }, | |
507bd325 | 4734 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4735 | }, |
4736 | ||
1ceb70f8 | 4737 | /* PREFIX_0F3A0C */ |
42903f7f | 4738 | { |
592d1631 L |
4739 | { Bad_Opcode }, |
4740 | { Bad_Opcode }, | |
507bd325 | 4741 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4742 | }, |
4743 | ||
1ceb70f8 | 4744 | /* PREFIX_0F3A0D */ |
42903f7f | 4745 | { |
592d1631 L |
4746 | { Bad_Opcode }, |
4747 | { Bad_Opcode }, | |
507bd325 | 4748 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4749 | }, |
4750 | ||
1ceb70f8 | 4751 | /* PREFIX_0F3A0E */ |
42903f7f | 4752 | { |
592d1631 L |
4753 | { Bad_Opcode }, |
4754 | { Bad_Opcode }, | |
507bd325 | 4755 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4756 | }, |
4757 | ||
1ceb70f8 | 4758 | /* PREFIX_0F3A14 */ |
42903f7f | 4759 | { |
592d1631 L |
4760 | { Bad_Opcode }, |
4761 | { Bad_Opcode }, | |
507bd325 | 4762 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4763 | }, |
4764 | ||
1ceb70f8 | 4765 | /* PREFIX_0F3A15 */ |
42903f7f | 4766 | { |
592d1631 L |
4767 | { Bad_Opcode }, |
4768 | { Bad_Opcode }, | |
507bd325 | 4769 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4770 | }, |
4771 | ||
1ceb70f8 | 4772 | /* PREFIX_0F3A16 */ |
42903f7f | 4773 | { |
592d1631 L |
4774 | { Bad_Opcode }, |
4775 | { Bad_Opcode }, | |
507bd325 | 4776 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4777 | }, |
4778 | ||
1ceb70f8 | 4779 | /* PREFIX_0F3A17 */ |
42903f7f | 4780 | { |
592d1631 L |
4781 | { Bad_Opcode }, |
4782 | { Bad_Opcode }, | |
507bd325 | 4783 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4784 | }, |
4785 | ||
1ceb70f8 | 4786 | /* PREFIX_0F3A20 */ |
42903f7f | 4787 | { |
592d1631 L |
4788 | { Bad_Opcode }, |
4789 | { Bad_Opcode }, | |
507bd325 | 4790 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4791 | }, |
4792 | ||
1ceb70f8 | 4793 | /* PREFIX_0F3A21 */ |
42903f7f | 4794 | { |
592d1631 L |
4795 | { Bad_Opcode }, |
4796 | { Bad_Opcode }, | |
507bd325 | 4797 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4798 | }, |
4799 | ||
1ceb70f8 | 4800 | /* PREFIX_0F3A22 */ |
42903f7f | 4801 | { |
592d1631 L |
4802 | { Bad_Opcode }, |
4803 | { Bad_Opcode }, | |
507bd325 | 4804 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4805 | }, |
4806 | ||
1ceb70f8 | 4807 | /* PREFIX_0F3A40 */ |
42903f7f | 4808 | { |
592d1631 L |
4809 | { Bad_Opcode }, |
4810 | { Bad_Opcode }, | |
507bd325 | 4811 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4812 | }, |
4813 | ||
1ceb70f8 | 4814 | /* PREFIX_0F3A41 */ |
42903f7f | 4815 | { |
592d1631 L |
4816 | { Bad_Opcode }, |
4817 | { Bad_Opcode }, | |
507bd325 | 4818 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4819 | }, |
4820 | ||
1ceb70f8 | 4821 | /* PREFIX_0F3A42 */ |
42903f7f | 4822 | { |
592d1631 L |
4823 | { Bad_Opcode }, |
4824 | { Bad_Opcode }, | |
507bd325 | 4825 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4826 | }, |
381d071f | 4827 | |
c0f3af97 L |
4828 | /* PREFIX_0F3A44 */ |
4829 | { | |
592d1631 L |
4830 | { Bad_Opcode }, |
4831 | { Bad_Opcode }, | |
507bd325 | 4832 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4833 | }, |
4834 | ||
1ceb70f8 | 4835 | /* PREFIX_0F3A60 */ |
381d071f | 4836 | { |
592d1631 L |
4837 | { Bad_Opcode }, |
4838 | { Bad_Opcode }, | |
15c7c1d8 | 4839 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4840 | }, |
4841 | ||
1ceb70f8 | 4842 | /* PREFIX_0F3A61 */ |
381d071f | 4843 | { |
592d1631 L |
4844 | { Bad_Opcode }, |
4845 | { Bad_Opcode }, | |
15c7c1d8 | 4846 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4847 | }, |
4848 | ||
1ceb70f8 | 4849 | /* PREFIX_0F3A62 */ |
381d071f | 4850 | { |
592d1631 L |
4851 | { Bad_Opcode }, |
4852 | { Bad_Opcode }, | |
507bd325 | 4853 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4854 | }, |
4855 | ||
1ceb70f8 | 4856 | /* PREFIX_0F3A63 */ |
381d071f | 4857 | { |
592d1631 L |
4858 | { Bad_Opcode }, |
4859 | { Bad_Opcode }, | |
507bd325 | 4860 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4861 | }, |
09a2c6cf | 4862 | |
a0046408 L |
4863 | /* PREFIX_0F3ACC */ |
4864 | { | |
507bd325 | 4865 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4866 | }, |
4867 | ||
48521003 IT |
4868 | /* PREFIX_0F3ACE */ |
4869 | { | |
4870 | { Bad_Opcode }, | |
4871 | { Bad_Opcode }, | |
4872 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4873 | }, | |
4874 | ||
4875 | /* PREFIX_0F3ACF */ | |
4876 | { | |
4877 | { Bad_Opcode }, | |
4878 | { Bad_Opcode }, | |
4879 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4880 | }, | |
4881 | ||
c0f3af97 | 4882 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4883 | { |
592d1631 L |
4884 | { Bad_Opcode }, |
4885 | { Bad_Opcode }, | |
507bd325 | 4886 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4887 | }, |
4888 | ||
592a252b | 4889 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4890 | { |
592a252b L |
4891 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4892 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4893 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4894 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4895 | }, |
4896 | ||
592a252b | 4897 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4898 | { |
592a252b L |
4899 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4900 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4901 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4902 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4903 | }, |
4904 | ||
592a252b | 4905 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4906 | { |
592a252b L |
4907 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4908 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4909 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4910 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4911 | }, |
4912 | ||
592a252b | 4913 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4914 | { |
592a252b L |
4915 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4916 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4917 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4918 | }, |
7c52e0e8 | 4919 | |
592a252b | 4920 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4921 | { |
592d1631 | 4922 | { Bad_Opcode }, |
592a252b | 4923 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4924 | { Bad_Opcode }, |
592a252b | 4925 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4926 | }, |
7c52e0e8 | 4927 | |
592a252b | 4928 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4929 | { |
592d1631 | 4930 | { Bad_Opcode }, |
592a252b | 4931 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4932 | { Bad_Opcode }, |
592a252b | 4933 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4934 | }, |
7c52e0e8 | 4935 | |
592a252b | 4936 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4937 | { |
592d1631 | 4938 | { Bad_Opcode }, |
592a252b | 4939 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4940 | { Bad_Opcode }, |
592a252b | 4941 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4942 | }, |
4943 | ||
592a252b | 4944 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4945 | { |
592a252b | 4946 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4947 | { Bad_Opcode }, |
592a252b | 4948 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4949 | }, |
4950 | ||
592a252b | 4951 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4952 | { |
592a252b | 4953 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4954 | { Bad_Opcode }, |
592a252b | 4955 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4956 | }, |
4957 | ||
43234a1e L |
4958 | /* PREFIX_VEX_0F41 */ |
4959 | { | |
4960 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4961 | { Bad_Opcode }, |
4962 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4963 | }, |
4964 | ||
4965 | /* PREFIX_VEX_0F42 */ | |
4966 | { | |
4967 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4968 | { Bad_Opcode }, |
4969 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4970 | }, |
4971 | ||
4972 | /* PREFIX_VEX_0F44 */ | |
4973 | { | |
4974 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4975 | { Bad_Opcode }, |
4976 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4977 | }, |
4978 | ||
4979 | /* PREFIX_VEX_0F45 */ | |
4980 | { | |
4981 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4982 | { Bad_Opcode }, |
4983 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4984 | }, |
4985 | ||
4986 | /* PREFIX_VEX_0F46 */ | |
4987 | { | |
4988 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4989 | { Bad_Opcode }, |
4990 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4991 | }, |
4992 | ||
4993 | /* PREFIX_VEX_0F47 */ | |
4994 | { | |
4995 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4996 | { Bad_Opcode }, |
4997 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4998 | }, |
4999 | ||
1ba585e8 | 5000 | /* PREFIX_VEX_0F4A */ |
43234a1e | 5001 | { |
1ba585e8 | 5002 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 5003 | { Bad_Opcode }, |
1ba585e8 IT |
5004 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
5005 | }, | |
5006 | ||
5007 | /* PREFIX_VEX_0F4B */ | |
5008 | { | |
5009 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
5010 | { Bad_Opcode }, |
5011 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
5012 | }, | |
5013 | ||
592a252b | 5014 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 5015 | { |
592a252b L |
5016 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
5017 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
5018 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
5019 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
5020 | }, |
5021 | ||
592a252b | 5022 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 5023 | { |
592a252b L |
5024 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
5025 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
5026 | }, |
5027 | ||
592a252b | 5028 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 5029 | { |
592a252b L |
5030 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
5031 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
5032 | }, |
5033 | ||
592a252b | 5034 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 5035 | { |
592a252b L |
5036 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
5037 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
5038 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
5039 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
5040 | }, |
5041 | ||
592a252b | 5042 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 5043 | { |
592a252b L |
5044 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
5045 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
5046 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
5047 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
5048 | }, |
5049 | ||
592a252b | 5050 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 5051 | { |
592a252b L |
5052 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
5053 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 5054 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 5055 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
5056 | }, |
5057 | ||
592a252b | 5058 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 5059 | { |
592a252b L |
5060 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
5061 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
5062 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
5063 | }, |
5064 | ||
592a252b | 5065 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 5066 | { |
592a252b L |
5067 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
5068 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
5069 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
5070 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 5074 | { |
592a252b L |
5075 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
5076 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
5077 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
5078 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
5079 | }, |
5080 | ||
592a252b | 5081 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 5082 | { |
592a252b L |
5083 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
5084 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
5085 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
5086 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
5087 | }, |
5088 | ||
592a252b | 5089 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 5090 | { |
592a252b L |
5091 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
5092 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
5093 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
5094 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
5095 | }, |
5096 | ||
592a252b | 5097 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 5098 | { |
592d1631 L |
5099 | { Bad_Opcode }, |
5100 | { Bad_Opcode }, | |
6c30d220 | 5101 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
5102 | }, |
5103 | ||
592a252b | 5104 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 5105 | { |
592d1631 L |
5106 | { Bad_Opcode }, |
5107 | { Bad_Opcode }, | |
6c30d220 | 5108 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
5109 | }, |
5110 | ||
592a252b | 5111 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 5112 | { |
592d1631 L |
5113 | { Bad_Opcode }, |
5114 | { Bad_Opcode }, | |
6c30d220 | 5115 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
5116 | }, |
5117 | ||
592a252b | 5118 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 5119 | { |
592d1631 L |
5120 | { Bad_Opcode }, |
5121 | { Bad_Opcode }, | |
6c30d220 | 5122 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
5123 | }, |
5124 | ||
592a252b | 5125 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 5126 | { |
592d1631 L |
5127 | { Bad_Opcode }, |
5128 | { Bad_Opcode }, | |
6c30d220 | 5129 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
5130 | }, |
5131 | ||
592a252b | 5132 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 5133 | { |
592d1631 L |
5134 | { Bad_Opcode }, |
5135 | { Bad_Opcode }, | |
6c30d220 | 5136 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
5137 | }, |
5138 | ||
592a252b | 5139 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 5140 | { |
592d1631 L |
5141 | { Bad_Opcode }, |
5142 | { Bad_Opcode }, | |
6c30d220 | 5143 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 5144 | }, |
6439fc28 | 5145 | |
592a252b | 5146 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 5147 | { |
592d1631 L |
5148 | { Bad_Opcode }, |
5149 | { Bad_Opcode }, | |
6c30d220 | 5150 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
5151 | }, |
5152 | ||
592a252b | 5153 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 5154 | { |
592d1631 L |
5155 | { Bad_Opcode }, |
5156 | { Bad_Opcode }, | |
6c30d220 | 5157 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
5158 | }, |
5159 | ||
592a252b | 5160 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 5161 | { |
592d1631 L |
5162 | { Bad_Opcode }, |
5163 | { Bad_Opcode }, | |
6c30d220 | 5164 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
5165 | }, |
5166 | ||
592a252b | 5167 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 5168 | { |
592d1631 L |
5169 | { Bad_Opcode }, |
5170 | { Bad_Opcode }, | |
6c30d220 | 5171 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
5172 | }, |
5173 | ||
592a252b | 5174 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 5175 | { |
592d1631 L |
5176 | { Bad_Opcode }, |
5177 | { Bad_Opcode }, | |
6c30d220 | 5178 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
5179 | }, |
5180 | ||
592a252b | 5181 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 5182 | { |
592d1631 L |
5183 | { Bad_Opcode }, |
5184 | { Bad_Opcode }, | |
6c30d220 | 5185 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
5186 | }, |
5187 | ||
592a252b | 5188 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 5189 | { |
592d1631 L |
5190 | { Bad_Opcode }, |
5191 | { Bad_Opcode }, | |
6c30d220 | 5192 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
5193 | }, |
5194 | ||
592a252b | 5195 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 5196 | { |
592d1631 L |
5197 | { Bad_Opcode }, |
5198 | { Bad_Opcode }, | |
592a252b | 5199 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
5200 | }, |
5201 | ||
592a252b | 5202 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 5203 | { |
592d1631 | 5204 | { Bad_Opcode }, |
592a252b L |
5205 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5206 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5207 | }, |
5208 | ||
592a252b | 5209 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5210 | { |
592d1631 | 5211 | { Bad_Opcode }, |
6c30d220 L |
5212 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5213 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5214 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5215 | }, |
5216 | ||
592a252b | 5217 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5218 | { |
592d1631 L |
5219 | { Bad_Opcode }, |
5220 | { Bad_Opcode }, | |
6c30d220 | 5221 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5222 | }, |
5223 | ||
592a252b | 5224 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5225 | { |
592d1631 L |
5226 | { Bad_Opcode }, |
5227 | { Bad_Opcode }, | |
6c30d220 | 5228 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5229 | }, |
5230 | ||
592a252b | 5231 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5232 | { |
592d1631 L |
5233 | { Bad_Opcode }, |
5234 | { Bad_Opcode }, | |
6c30d220 | 5235 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5236 | }, |
5237 | ||
592a252b | 5238 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5239 | { |
592d1631 L |
5240 | { Bad_Opcode }, |
5241 | { Bad_Opcode }, | |
6c30d220 | 5242 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5243 | }, |
5244 | ||
592a252b | 5245 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5246 | { |
592d1631 L |
5247 | { Bad_Opcode }, |
5248 | { Bad_Opcode }, | |
6c30d220 | 5249 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5250 | }, |
5251 | ||
592a252b | 5252 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5253 | { |
592d1631 L |
5254 | { Bad_Opcode }, |
5255 | { Bad_Opcode }, | |
6c30d220 | 5256 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5257 | }, |
5258 | ||
592a252b | 5259 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5260 | { |
592d1631 L |
5261 | { Bad_Opcode }, |
5262 | { Bad_Opcode }, | |
6c30d220 | 5263 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5264 | }, |
5265 | ||
592a252b | 5266 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5267 | { |
592d1631 L |
5268 | { Bad_Opcode }, |
5269 | { Bad_Opcode }, | |
6c30d220 | 5270 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5271 | }, |
5272 | ||
592a252b | 5273 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5274 | { |
592d1631 L |
5275 | { Bad_Opcode }, |
5276 | { Bad_Opcode }, | |
6c30d220 | 5277 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5278 | }, |
5279 | ||
592a252b | 5280 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5281 | { |
592d1631 L |
5282 | { Bad_Opcode }, |
5283 | { Bad_Opcode }, | |
6c30d220 | 5284 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5285 | }, |
5286 | ||
592a252b | 5287 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5288 | { |
592d1631 L |
5289 | { Bad_Opcode }, |
5290 | { Bad_Opcode }, | |
6c30d220 | 5291 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5292 | }, |
5293 | ||
592a252b | 5294 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5295 | { |
592d1631 L |
5296 | { Bad_Opcode }, |
5297 | { Bad_Opcode }, | |
6c30d220 | 5298 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5299 | }, |
5300 | ||
592a252b | 5301 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5302 | { |
592d1631 L |
5303 | { Bad_Opcode }, |
5304 | { Bad_Opcode }, | |
6c30d220 | 5305 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5306 | }, |
5307 | ||
592a252b | 5308 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5309 | { |
592a252b | 5310 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5311 | }, |
5312 | ||
592a252b | 5313 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5314 | { |
592d1631 L |
5315 | { Bad_Opcode }, |
5316 | { Bad_Opcode }, | |
592a252b L |
5317 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5318 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5319 | }, |
5320 | ||
592a252b | 5321 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5322 | { |
592d1631 L |
5323 | { Bad_Opcode }, |
5324 | { Bad_Opcode }, | |
592a252b L |
5325 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5326 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5327 | }, |
5328 | ||
592a252b | 5329 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5330 | { |
592d1631 | 5331 | { Bad_Opcode }, |
592a252b L |
5332 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5333 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5334 | }, |
5335 | ||
592a252b | 5336 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5337 | { |
592d1631 | 5338 | { Bad_Opcode }, |
592a252b L |
5339 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5340 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5341 | }, |
5342 | ||
43234a1e L |
5343 | /* PREFIX_VEX_0F90 */ |
5344 | { | |
5345 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5346 | { Bad_Opcode }, |
5347 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5348 | }, |
5349 | ||
5350 | /* PREFIX_VEX_0F91 */ | |
5351 | { | |
5352 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5353 | { Bad_Opcode }, |
5354 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5355 | }, |
5356 | ||
5357 | /* PREFIX_VEX_0F92 */ | |
5358 | { | |
5359 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5360 | { Bad_Opcode }, |
90a915bf | 5361 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5362 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5363 | }, |
5364 | ||
5365 | /* PREFIX_VEX_0F93 */ | |
5366 | { | |
5367 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5368 | { Bad_Opcode }, |
90a915bf | 5369 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5370 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5371 | }, |
5372 | ||
5373 | /* PREFIX_VEX_0F98 */ | |
5374 | { | |
5375 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5376 | { Bad_Opcode }, |
5377 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5378 | }, | |
5379 | ||
5380 | /* PREFIX_VEX_0F99 */ | |
5381 | { | |
5382 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5383 | { Bad_Opcode }, | |
5384 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5388 | { |
592a252b L |
5389 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5390 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5391 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5392 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5393 | }, |
5394 | ||
592a252b | 5395 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5396 | { |
592d1631 L |
5397 | { Bad_Opcode }, |
5398 | { Bad_Opcode }, | |
592a252b | 5399 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5400 | }, |
5401 | ||
592a252b | 5402 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5403 | { |
592d1631 L |
5404 | { Bad_Opcode }, |
5405 | { Bad_Opcode }, | |
592a252b | 5406 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5407 | }, |
5408 | ||
592a252b | 5409 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5410 | { |
592d1631 L |
5411 | { Bad_Opcode }, |
5412 | { Bad_Opcode }, | |
592a252b L |
5413 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5414 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5415 | }, |
5416 | ||
592a252b | 5417 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5418 | { |
592d1631 L |
5419 | { Bad_Opcode }, |
5420 | { Bad_Opcode }, | |
6c30d220 | 5421 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5422 | }, |
5423 | ||
592a252b | 5424 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5425 | { |
592d1631 L |
5426 | { Bad_Opcode }, |
5427 | { Bad_Opcode }, | |
6c30d220 | 5428 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5429 | }, |
5430 | ||
592a252b | 5431 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5432 | { |
592d1631 L |
5433 | { Bad_Opcode }, |
5434 | { Bad_Opcode }, | |
6c30d220 | 5435 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5436 | }, |
5437 | ||
592a252b | 5438 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5439 | { |
592d1631 L |
5440 | { Bad_Opcode }, |
5441 | { Bad_Opcode }, | |
6c30d220 | 5442 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5443 | }, |
5444 | ||
592a252b | 5445 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5446 | { |
592d1631 L |
5447 | { Bad_Opcode }, |
5448 | { Bad_Opcode }, | |
6c30d220 | 5449 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5450 | }, |
5451 | ||
592a252b | 5452 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5453 | { |
592d1631 L |
5454 | { Bad_Opcode }, |
5455 | { Bad_Opcode }, | |
592a252b | 5456 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5457 | }, |
5458 | ||
592a252b | 5459 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5460 | { |
592d1631 L |
5461 | { Bad_Opcode }, |
5462 | { Bad_Opcode }, | |
592a252b | 5463 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5464 | }, |
5465 | ||
592a252b | 5466 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5467 | { |
592d1631 L |
5468 | { Bad_Opcode }, |
5469 | { Bad_Opcode }, | |
6c30d220 | 5470 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5471 | }, |
5472 | ||
592a252b | 5473 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5474 | { |
592d1631 L |
5475 | { Bad_Opcode }, |
5476 | { Bad_Opcode }, | |
6c30d220 | 5477 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5478 | }, |
5479 | ||
592a252b | 5480 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5481 | { |
592d1631 L |
5482 | { Bad_Opcode }, |
5483 | { Bad_Opcode }, | |
6c30d220 | 5484 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5485 | }, |
5486 | ||
592a252b | 5487 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5488 | { |
592d1631 L |
5489 | { Bad_Opcode }, |
5490 | { Bad_Opcode }, | |
6c30d220 | 5491 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5492 | }, |
5493 | ||
592a252b | 5494 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5495 | { |
592d1631 L |
5496 | { Bad_Opcode }, |
5497 | { Bad_Opcode }, | |
6c30d220 | 5498 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5499 | }, |
5500 | ||
592a252b | 5501 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5502 | { |
592d1631 L |
5503 | { Bad_Opcode }, |
5504 | { Bad_Opcode }, | |
6c30d220 | 5505 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5506 | }, |
5507 | ||
592a252b | 5508 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5509 | { |
592d1631 L |
5510 | { Bad_Opcode }, |
5511 | { Bad_Opcode }, | |
6c30d220 | 5512 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5513 | }, |
5514 | ||
592a252b | 5515 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5516 | { |
592d1631 L |
5517 | { Bad_Opcode }, |
5518 | { Bad_Opcode }, | |
6c30d220 | 5519 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5520 | }, |
5521 | ||
592a252b | 5522 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5523 | { |
592d1631 L |
5524 | { Bad_Opcode }, |
5525 | { Bad_Opcode }, | |
6c30d220 | 5526 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5527 | }, |
5528 | ||
592a252b | 5529 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5530 | { |
592d1631 L |
5531 | { Bad_Opcode }, |
5532 | { Bad_Opcode }, | |
6c30d220 | 5533 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5534 | }, |
5535 | ||
592a252b | 5536 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5537 | { |
592d1631 L |
5538 | { Bad_Opcode }, |
5539 | { Bad_Opcode }, | |
6c30d220 | 5540 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5541 | }, |
5542 | ||
592a252b | 5543 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5544 | { |
592d1631 L |
5545 | { Bad_Opcode }, |
5546 | { Bad_Opcode }, | |
6c30d220 | 5547 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5548 | }, |
5549 | ||
592a252b | 5550 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5551 | { |
592d1631 L |
5552 | { Bad_Opcode }, |
5553 | { Bad_Opcode }, | |
6c30d220 | 5554 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5555 | }, |
5556 | ||
592a252b | 5557 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5558 | { |
592d1631 L |
5559 | { Bad_Opcode }, |
5560 | { Bad_Opcode }, | |
6c30d220 | 5561 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5562 | }, |
5563 | ||
592a252b | 5564 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5565 | { |
592d1631 | 5566 | { Bad_Opcode }, |
592a252b L |
5567 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5568 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5569 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5570 | }, |
5571 | ||
592a252b | 5572 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5573 | { |
592d1631 L |
5574 | { Bad_Opcode }, |
5575 | { Bad_Opcode }, | |
592a252b | 5576 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5577 | }, |
5578 | ||
592a252b | 5579 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5580 | { |
592d1631 L |
5581 | { Bad_Opcode }, |
5582 | { Bad_Opcode }, | |
6c30d220 | 5583 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5584 | }, |
5585 | ||
592a252b | 5586 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5587 | { |
592d1631 L |
5588 | { Bad_Opcode }, |
5589 | { Bad_Opcode }, | |
6c30d220 | 5590 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5591 | }, |
5592 | ||
592a252b | 5593 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5594 | { |
592d1631 L |
5595 | { Bad_Opcode }, |
5596 | { Bad_Opcode }, | |
6c30d220 | 5597 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5598 | }, |
5599 | ||
592a252b | 5600 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5601 | { |
592d1631 L |
5602 | { Bad_Opcode }, |
5603 | { Bad_Opcode }, | |
6c30d220 | 5604 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5605 | }, |
5606 | ||
592a252b | 5607 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5608 | { |
592d1631 L |
5609 | { Bad_Opcode }, |
5610 | { Bad_Opcode }, | |
6c30d220 | 5611 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5612 | }, |
5613 | ||
592a252b | 5614 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5615 | { |
592d1631 L |
5616 | { Bad_Opcode }, |
5617 | { Bad_Opcode }, | |
6c30d220 | 5618 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5619 | }, |
5620 | ||
592a252b | 5621 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5622 | { |
592d1631 L |
5623 | { Bad_Opcode }, |
5624 | { Bad_Opcode }, | |
6c30d220 | 5625 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5626 | }, |
5627 | ||
592a252b | 5628 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5629 | { |
592d1631 L |
5630 | { Bad_Opcode }, |
5631 | { Bad_Opcode }, | |
6c30d220 | 5632 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5633 | }, |
5634 | ||
592a252b | 5635 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5636 | { |
592d1631 L |
5637 | { Bad_Opcode }, |
5638 | { Bad_Opcode }, | |
5639 | { Bad_Opcode }, | |
592a252b | 5640 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5641 | }, |
5642 | ||
592a252b | 5643 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5644 | { |
592d1631 L |
5645 | { Bad_Opcode }, |
5646 | { Bad_Opcode }, | |
6c30d220 | 5647 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5648 | }, |
5649 | ||
592a252b | 5650 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5651 | { |
592d1631 L |
5652 | { Bad_Opcode }, |
5653 | { Bad_Opcode }, | |
6c30d220 | 5654 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5655 | }, |
5656 | ||
592a252b | 5657 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5658 | { |
592d1631 L |
5659 | { Bad_Opcode }, |
5660 | { Bad_Opcode }, | |
6c30d220 | 5661 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5662 | }, |
5663 | ||
592a252b | 5664 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5665 | { |
592d1631 L |
5666 | { Bad_Opcode }, |
5667 | { Bad_Opcode }, | |
6c30d220 | 5668 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5669 | }, |
5670 | ||
592a252b | 5671 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5672 | { |
592d1631 L |
5673 | { Bad_Opcode }, |
5674 | { Bad_Opcode }, | |
6c30d220 | 5675 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5676 | }, |
5677 | ||
592a252b | 5678 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5679 | { |
592d1631 L |
5680 | { Bad_Opcode }, |
5681 | { Bad_Opcode }, | |
6c30d220 | 5682 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5683 | }, |
5684 | ||
592a252b | 5685 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5686 | { |
592d1631 L |
5687 | { Bad_Opcode }, |
5688 | { Bad_Opcode }, | |
592a252b | 5689 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5690 | }, |
5691 | ||
592a252b | 5692 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5693 | { |
592d1631 L |
5694 | { Bad_Opcode }, |
5695 | { Bad_Opcode }, | |
6c30d220 | 5696 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5697 | }, |
5698 | ||
592a252b | 5699 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5700 | { |
592d1631 L |
5701 | { Bad_Opcode }, |
5702 | { Bad_Opcode }, | |
6c30d220 | 5703 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5704 | }, |
5705 | ||
592a252b | 5706 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5707 | { |
592d1631 L |
5708 | { Bad_Opcode }, |
5709 | { Bad_Opcode }, | |
6c30d220 | 5710 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5711 | }, |
5712 | ||
592a252b | 5713 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5714 | { |
592d1631 L |
5715 | { Bad_Opcode }, |
5716 | { Bad_Opcode }, | |
6c30d220 | 5717 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5718 | }, |
5719 | ||
592a252b | 5720 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5721 | { |
592d1631 L |
5722 | { Bad_Opcode }, |
5723 | { Bad_Opcode }, | |
6c30d220 | 5724 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5725 | }, |
5726 | ||
592a252b | 5727 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5728 | { |
592d1631 L |
5729 | { Bad_Opcode }, |
5730 | { Bad_Opcode }, | |
6c30d220 | 5731 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5732 | }, |
5733 | ||
592a252b | 5734 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5735 | { |
592d1631 L |
5736 | { Bad_Opcode }, |
5737 | { Bad_Opcode }, | |
6c30d220 | 5738 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5739 | }, |
5740 | ||
592a252b | 5741 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5742 | { |
592d1631 L |
5743 | { Bad_Opcode }, |
5744 | { Bad_Opcode }, | |
6c30d220 | 5745 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5746 | }, |
5747 | ||
592a252b | 5748 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5749 | { |
592d1631 L |
5750 | { Bad_Opcode }, |
5751 | { Bad_Opcode }, | |
6c30d220 | 5752 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5753 | }, |
5754 | ||
592a252b | 5755 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5756 | { |
592d1631 L |
5757 | { Bad_Opcode }, |
5758 | { Bad_Opcode }, | |
6c30d220 | 5759 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5760 | }, |
5761 | ||
592a252b | 5762 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5763 | { |
592d1631 L |
5764 | { Bad_Opcode }, |
5765 | { Bad_Opcode }, | |
6c30d220 | 5766 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5767 | }, |
5768 | ||
592a252b | 5769 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5770 | { |
592d1631 L |
5771 | { Bad_Opcode }, |
5772 | { Bad_Opcode }, | |
6c30d220 | 5773 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5774 | }, |
5775 | ||
592a252b | 5776 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5777 | { |
592d1631 L |
5778 | { Bad_Opcode }, |
5779 | { Bad_Opcode }, | |
6c30d220 | 5780 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5781 | }, |
5782 | ||
592a252b | 5783 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5784 | { |
592d1631 L |
5785 | { Bad_Opcode }, |
5786 | { Bad_Opcode }, | |
6c30d220 | 5787 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5788 | }, |
5789 | ||
592a252b | 5790 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5791 | { |
592d1631 L |
5792 | { Bad_Opcode }, |
5793 | { Bad_Opcode }, | |
6c30d220 | 5794 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5795 | }, |
5796 | ||
592a252b | 5797 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5798 | { |
592d1631 L |
5799 | { Bad_Opcode }, |
5800 | { Bad_Opcode }, | |
6c30d220 | 5801 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5802 | }, |
5803 | ||
592a252b | 5804 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5805 | { |
592d1631 L |
5806 | { Bad_Opcode }, |
5807 | { Bad_Opcode }, | |
6c30d220 | 5808 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5809 | }, |
5810 | ||
592a252b | 5811 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5812 | { |
592d1631 L |
5813 | { Bad_Opcode }, |
5814 | { Bad_Opcode }, | |
6c30d220 | 5815 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5816 | }, |
5817 | ||
592a252b | 5818 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5819 | { |
592d1631 L |
5820 | { Bad_Opcode }, |
5821 | { Bad_Opcode }, | |
6c30d220 | 5822 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5823 | }, |
5824 | ||
592a252b | 5825 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5826 | { |
592d1631 L |
5827 | { Bad_Opcode }, |
5828 | { Bad_Opcode }, | |
592a252b | 5829 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5830 | }, |
5831 | ||
592a252b | 5832 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5833 | { |
592d1631 L |
5834 | { Bad_Opcode }, |
5835 | { Bad_Opcode }, | |
592a252b | 5836 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5837 | }, |
5838 | ||
592a252b | 5839 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5840 | { |
592d1631 L |
5841 | { Bad_Opcode }, |
5842 | { Bad_Opcode }, | |
592a252b | 5843 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5844 | }, |
5845 | ||
592a252b | 5846 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5847 | { |
592d1631 L |
5848 | { Bad_Opcode }, |
5849 | { Bad_Opcode }, | |
592a252b | 5850 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5851 | }, |
5852 | ||
592a252b | 5853 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5854 | { |
5855 | { Bad_Opcode }, | |
5856 | { Bad_Opcode }, | |
bf890a93 | 5857 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5858 | }, |
5859 | ||
6c30d220 L |
5860 | /* PREFIX_VEX_0F3816 */ |
5861 | { | |
5862 | { Bad_Opcode }, | |
5863 | { Bad_Opcode }, | |
5864 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5865 | }, | |
5866 | ||
592a252b | 5867 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5868 | { |
592d1631 L |
5869 | { Bad_Opcode }, |
5870 | { Bad_Opcode }, | |
592a252b | 5871 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5872 | }, |
5873 | ||
592a252b | 5874 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5875 | { |
592d1631 L |
5876 | { Bad_Opcode }, |
5877 | { Bad_Opcode }, | |
6c30d220 | 5878 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5879 | }, |
5880 | ||
592a252b | 5881 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5882 | { |
592d1631 L |
5883 | { Bad_Opcode }, |
5884 | { Bad_Opcode }, | |
6c30d220 | 5885 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5886 | }, |
5887 | ||
592a252b | 5888 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5889 | { |
592d1631 L |
5890 | { Bad_Opcode }, |
5891 | { Bad_Opcode }, | |
592a252b | 5892 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5893 | }, |
5894 | ||
592a252b | 5895 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5896 | { |
592d1631 L |
5897 | { Bad_Opcode }, |
5898 | { Bad_Opcode }, | |
6c30d220 | 5899 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5900 | }, |
5901 | ||
592a252b | 5902 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5903 | { |
592d1631 L |
5904 | { Bad_Opcode }, |
5905 | { Bad_Opcode }, | |
6c30d220 | 5906 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5907 | }, |
5908 | ||
592a252b | 5909 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5910 | { |
592d1631 L |
5911 | { Bad_Opcode }, |
5912 | { Bad_Opcode }, | |
6c30d220 | 5913 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5914 | }, |
5915 | ||
592a252b | 5916 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5917 | { |
592d1631 L |
5918 | { Bad_Opcode }, |
5919 | { Bad_Opcode }, | |
6c30d220 | 5920 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5921 | }, |
5922 | ||
592a252b | 5923 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5924 | { |
592d1631 L |
5925 | { Bad_Opcode }, |
5926 | { Bad_Opcode }, | |
6c30d220 | 5927 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5928 | }, |
5929 | ||
592a252b | 5930 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5931 | { |
592d1631 L |
5932 | { Bad_Opcode }, |
5933 | { Bad_Opcode }, | |
6c30d220 | 5934 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5935 | }, |
5936 | ||
592a252b | 5937 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5938 | { |
592d1631 L |
5939 | { Bad_Opcode }, |
5940 | { Bad_Opcode }, | |
6c30d220 | 5941 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5942 | }, |
5943 | ||
592a252b | 5944 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5945 | { |
592d1631 L |
5946 | { Bad_Opcode }, |
5947 | { Bad_Opcode }, | |
6c30d220 | 5948 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5949 | }, |
5950 | ||
592a252b | 5951 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5952 | { |
592d1631 L |
5953 | { Bad_Opcode }, |
5954 | { Bad_Opcode }, | |
6c30d220 | 5955 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5956 | }, |
5957 | ||
592a252b | 5958 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5959 | { |
592d1631 L |
5960 | { Bad_Opcode }, |
5961 | { Bad_Opcode }, | |
6c30d220 | 5962 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5963 | }, |
5964 | ||
592a252b | 5965 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5966 | { |
592d1631 L |
5967 | { Bad_Opcode }, |
5968 | { Bad_Opcode }, | |
6c30d220 | 5969 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5970 | }, |
5971 | ||
592a252b | 5972 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5973 | { |
592d1631 L |
5974 | { Bad_Opcode }, |
5975 | { Bad_Opcode }, | |
592a252b | 5976 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5977 | }, |
5978 | ||
592a252b | 5979 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5980 | { |
592d1631 L |
5981 | { Bad_Opcode }, |
5982 | { Bad_Opcode }, | |
6c30d220 | 5983 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5984 | }, |
5985 | ||
592a252b | 5986 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5987 | { |
592d1631 L |
5988 | { Bad_Opcode }, |
5989 | { Bad_Opcode }, | |
592a252b | 5990 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5991 | }, |
5992 | ||
592a252b | 5993 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5994 | { |
592d1631 L |
5995 | { Bad_Opcode }, |
5996 | { Bad_Opcode }, | |
592a252b | 5997 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5998 | }, |
5999 | ||
592a252b | 6000 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 6001 | { |
592d1631 L |
6002 | { Bad_Opcode }, |
6003 | { Bad_Opcode }, | |
592a252b | 6004 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
6005 | }, |
6006 | ||
592a252b | 6007 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 6008 | { |
592d1631 L |
6009 | { Bad_Opcode }, |
6010 | { Bad_Opcode }, | |
592a252b | 6011 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
6012 | }, |
6013 | ||
592a252b | 6014 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 6015 | { |
592d1631 L |
6016 | { Bad_Opcode }, |
6017 | { Bad_Opcode }, | |
6c30d220 | 6018 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
6019 | }, |
6020 | ||
592a252b | 6021 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 6022 | { |
592d1631 L |
6023 | { Bad_Opcode }, |
6024 | { Bad_Opcode }, | |
6c30d220 | 6025 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
6026 | }, |
6027 | ||
592a252b | 6028 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 6029 | { |
592d1631 L |
6030 | { Bad_Opcode }, |
6031 | { Bad_Opcode }, | |
6c30d220 | 6032 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
6033 | }, |
6034 | ||
592a252b | 6035 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 6036 | { |
592d1631 L |
6037 | { Bad_Opcode }, |
6038 | { Bad_Opcode }, | |
6c30d220 | 6039 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
6040 | }, |
6041 | ||
592a252b | 6042 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 6043 | { |
592d1631 L |
6044 | { Bad_Opcode }, |
6045 | { Bad_Opcode }, | |
6c30d220 | 6046 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
6047 | }, |
6048 | ||
592a252b | 6049 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 6050 | { |
592d1631 L |
6051 | { Bad_Opcode }, |
6052 | { Bad_Opcode }, | |
6c30d220 L |
6053 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
6054 | }, | |
6055 | ||
6056 | /* PREFIX_VEX_0F3836 */ | |
6057 | { | |
6058 | { Bad_Opcode }, | |
6059 | { Bad_Opcode }, | |
6060 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
6061 | }, |
6062 | ||
592a252b | 6063 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 6064 | { |
592d1631 L |
6065 | { Bad_Opcode }, |
6066 | { Bad_Opcode }, | |
6c30d220 | 6067 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
6068 | }, |
6069 | ||
592a252b | 6070 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 6071 | { |
592d1631 L |
6072 | { Bad_Opcode }, |
6073 | { Bad_Opcode }, | |
6c30d220 | 6074 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
6075 | }, |
6076 | ||
592a252b | 6077 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 6078 | { |
592d1631 L |
6079 | { Bad_Opcode }, |
6080 | { Bad_Opcode }, | |
6c30d220 | 6081 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
6082 | }, |
6083 | ||
592a252b | 6084 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 6085 | { |
592d1631 L |
6086 | { Bad_Opcode }, |
6087 | { Bad_Opcode }, | |
6c30d220 | 6088 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
6089 | }, |
6090 | ||
592a252b | 6091 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 6092 | { |
592d1631 L |
6093 | { Bad_Opcode }, |
6094 | { Bad_Opcode }, | |
6c30d220 | 6095 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
6096 | }, |
6097 | ||
592a252b | 6098 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 6099 | { |
592d1631 L |
6100 | { Bad_Opcode }, |
6101 | { Bad_Opcode }, | |
6c30d220 | 6102 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
6103 | }, |
6104 | ||
592a252b | 6105 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 6106 | { |
592d1631 L |
6107 | { Bad_Opcode }, |
6108 | { Bad_Opcode }, | |
6c30d220 | 6109 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
6110 | }, |
6111 | ||
592a252b | 6112 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 6113 | { |
592d1631 L |
6114 | { Bad_Opcode }, |
6115 | { Bad_Opcode }, | |
6c30d220 | 6116 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
6117 | }, |
6118 | ||
592a252b | 6119 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 6120 | { |
592d1631 L |
6121 | { Bad_Opcode }, |
6122 | { Bad_Opcode }, | |
6c30d220 | 6123 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
6124 | }, |
6125 | ||
592a252b | 6126 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 6127 | { |
592d1631 L |
6128 | { Bad_Opcode }, |
6129 | { Bad_Opcode }, | |
6c30d220 | 6130 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
6131 | }, |
6132 | ||
592a252b | 6133 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 6134 | { |
592d1631 L |
6135 | { Bad_Opcode }, |
6136 | { Bad_Opcode }, | |
592a252b | 6137 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
6138 | }, |
6139 | ||
6c30d220 L |
6140 | /* PREFIX_VEX_0F3845 */ |
6141 | { | |
6142 | { Bad_Opcode }, | |
6143 | { Bad_Opcode }, | |
bf890a93 | 6144 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6145 | }, |
6146 | ||
6147 | /* PREFIX_VEX_0F3846 */ | |
6148 | { | |
6149 | { Bad_Opcode }, | |
6150 | { Bad_Opcode }, | |
6151 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
6152 | }, | |
6153 | ||
6154 | /* PREFIX_VEX_0F3847 */ | |
6155 | { | |
6156 | { Bad_Opcode }, | |
6157 | { Bad_Opcode }, | |
bf890a93 | 6158 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6159 | }, |
6160 | ||
6161 | /* PREFIX_VEX_0F3858 */ | |
6162 | { | |
6163 | { Bad_Opcode }, | |
6164 | { Bad_Opcode }, | |
6165 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
6166 | }, | |
6167 | ||
6168 | /* PREFIX_VEX_0F3859 */ | |
6169 | { | |
6170 | { Bad_Opcode }, | |
6171 | { Bad_Opcode }, | |
6172 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
6173 | }, | |
6174 | ||
6175 | /* PREFIX_VEX_0F385A */ | |
6176 | { | |
6177 | { Bad_Opcode }, | |
6178 | { Bad_Opcode }, | |
6179 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
6180 | }, | |
6181 | ||
6182 | /* PREFIX_VEX_0F3878 */ | |
6183 | { | |
6184 | { Bad_Opcode }, | |
6185 | { Bad_Opcode }, | |
6186 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
6187 | }, | |
6188 | ||
6189 | /* PREFIX_VEX_0F3879 */ | |
6190 | { | |
6191 | { Bad_Opcode }, | |
6192 | { Bad_Opcode }, | |
6193 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
6194 | }, | |
6195 | ||
6196 | /* PREFIX_VEX_0F388C */ | |
6197 | { | |
6198 | { Bad_Opcode }, | |
6199 | { Bad_Opcode }, | |
f7002f42 | 6200 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6201 | }, |
6202 | ||
6203 | /* PREFIX_VEX_0F388E */ | |
6204 | { | |
6205 | { Bad_Opcode }, | |
6206 | { Bad_Opcode }, | |
f7002f42 | 6207 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6208 | }, |
6209 | ||
6210 | /* PREFIX_VEX_0F3890 */ | |
6211 | { | |
6212 | { Bad_Opcode }, | |
6213 | { Bad_Opcode }, | |
bf890a93 | 6214 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6215 | }, |
6216 | ||
6217 | /* PREFIX_VEX_0F3891 */ | |
6218 | { | |
6219 | { Bad_Opcode }, | |
6220 | { Bad_Opcode }, | |
bf890a93 | 6221 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6222 | }, |
6223 | ||
6224 | /* PREFIX_VEX_0F3892 */ | |
6225 | { | |
6226 | { Bad_Opcode }, | |
6227 | { Bad_Opcode }, | |
bf890a93 | 6228 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6229 | }, |
6230 | ||
6231 | /* PREFIX_VEX_0F3893 */ | |
6232 | { | |
6233 | { Bad_Opcode }, | |
6234 | { Bad_Opcode }, | |
bf890a93 | 6235 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6236 | }, |
6237 | ||
592a252b | 6238 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6239 | { |
592d1631 L |
6240 | { Bad_Opcode }, |
6241 | { Bad_Opcode }, | |
bf890a93 | 6242 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6243 | }, |
6244 | ||
592a252b | 6245 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6246 | { |
592d1631 L |
6247 | { Bad_Opcode }, |
6248 | { Bad_Opcode }, | |
bf890a93 | 6249 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6250 | }, |
6251 | ||
592a252b | 6252 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6253 | { |
592d1631 L |
6254 | { Bad_Opcode }, |
6255 | { Bad_Opcode }, | |
bf890a93 | 6256 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6257 | }, |
6258 | ||
592a252b | 6259 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6260 | { |
592d1631 L |
6261 | { Bad_Opcode }, |
6262 | { Bad_Opcode }, | |
bf890a93 | 6263 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6264 | }, |
6265 | ||
592a252b | 6266 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6267 | { |
592d1631 L |
6268 | { Bad_Opcode }, |
6269 | { Bad_Opcode }, | |
bf890a93 | 6270 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6271 | }, |
6272 | ||
592a252b | 6273 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6274 | { |
592d1631 L |
6275 | { Bad_Opcode }, |
6276 | { Bad_Opcode }, | |
bf890a93 | 6277 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6278 | }, |
6279 | ||
592a252b | 6280 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6281 | { |
592d1631 L |
6282 | { Bad_Opcode }, |
6283 | { Bad_Opcode }, | |
bf890a93 | 6284 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6285 | }, |
6286 | ||
592a252b | 6287 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6288 | { |
592d1631 L |
6289 | { Bad_Opcode }, |
6290 | { Bad_Opcode }, | |
bf890a93 | 6291 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6292 | }, |
6293 | ||
592a252b | 6294 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6295 | { |
592d1631 L |
6296 | { Bad_Opcode }, |
6297 | { Bad_Opcode }, | |
bf890a93 | 6298 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6299 | }, |
6300 | ||
592a252b | 6301 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6302 | { |
592d1631 L |
6303 | { Bad_Opcode }, |
6304 | { Bad_Opcode }, | |
bf890a93 | 6305 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6306 | }, |
6307 | ||
592a252b | 6308 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6309 | { |
592d1631 L |
6310 | { Bad_Opcode }, |
6311 | { Bad_Opcode }, | |
bf890a93 | 6312 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6313 | { Bad_Opcode }, |
c0f3af97 L |
6314 | }, |
6315 | ||
592a252b | 6316 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6317 | { |
592d1631 L |
6318 | { Bad_Opcode }, |
6319 | { Bad_Opcode }, | |
bf890a93 | 6320 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6321 | }, |
6322 | ||
592a252b | 6323 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6324 | { |
592d1631 L |
6325 | { Bad_Opcode }, |
6326 | { Bad_Opcode }, | |
bf890a93 | 6327 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6328 | }, |
6329 | ||
592a252b | 6330 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6331 | { |
592d1631 L |
6332 | { Bad_Opcode }, |
6333 | { Bad_Opcode }, | |
bf890a93 | 6334 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6335 | }, |
6336 | ||
592a252b | 6337 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6338 | { |
592d1631 L |
6339 | { Bad_Opcode }, |
6340 | { Bad_Opcode }, | |
bf890a93 | 6341 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6342 | }, |
6343 | ||
592a252b | 6344 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6345 | { |
592d1631 L |
6346 | { Bad_Opcode }, |
6347 | { Bad_Opcode }, | |
bf890a93 | 6348 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6349 | }, |
6350 | ||
592a252b | 6351 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6352 | { |
592d1631 L |
6353 | { Bad_Opcode }, |
6354 | { Bad_Opcode }, | |
bf890a93 | 6355 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6356 | }, |
6357 | ||
592a252b | 6358 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6359 | { |
592d1631 L |
6360 | { Bad_Opcode }, |
6361 | { Bad_Opcode }, | |
bf890a93 | 6362 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6363 | }, |
6364 | ||
592a252b | 6365 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6366 | { |
592d1631 L |
6367 | { Bad_Opcode }, |
6368 | { Bad_Opcode }, | |
bf890a93 | 6369 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6370 | }, |
6371 | ||
592a252b | 6372 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6373 | { |
592d1631 L |
6374 | { Bad_Opcode }, |
6375 | { Bad_Opcode }, | |
bf890a93 | 6376 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6377 | }, |
6378 | ||
592a252b | 6379 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6380 | { |
592d1631 L |
6381 | { Bad_Opcode }, |
6382 | { Bad_Opcode }, | |
bf890a93 | 6383 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6384 | }, |
6385 | ||
592a252b | 6386 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6387 | { |
592d1631 L |
6388 | { Bad_Opcode }, |
6389 | { Bad_Opcode }, | |
bf890a93 | 6390 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6391 | }, |
6392 | ||
592a252b | 6393 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6394 | { |
592d1631 L |
6395 | { Bad_Opcode }, |
6396 | { Bad_Opcode }, | |
bf890a93 | 6397 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6398 | }, |
6399 | ||
592a252b | 6400 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6401 | { |
592d1631 L |
6402 | { Bad_Opcode }, |
6403 | { Bad_Opcode }, | |
bf890a93 | 6404 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6405 | }, |
6406 | ||
592a252b | 6407 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6408 | { |
592d1631 L |
6409 | { Bad_Opcode }, |
6410 | { Bad_Opcode }, | |
bf890a93 | 6411 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6412 | }, |
6413 | ||
592a252b | 6414 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6415 | { |
592d1631 L |
6416 | { Bad_Opcode }, |
6417 | { Bad_Opcode }, | |
bf890a93 | 6418 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6419 | }, |
6420 | ||
592a252b | 6421 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6422 | { |
592d1631 L |
6423 | { Bad_Opcode }, |
6424 | { Bad_Opcode }, | |
bf890a93 | 6425 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6426 | }, |
6427 | ||
592a252b | 6428 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6429 | { |
592d1631 L |
6430 | { Bad_Opcode }, |
6431 | { Bad_Opcode }, | |
bf890a93 | 6432 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6433 | }, |
6434 | ||
592a252b | 6435 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6436 | { |
592d1631 L |
6437 | { Bad_Opcode }, |
6438 | { Bad_Opcode }, | |
bf890a93 | 6439 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6440 | }, |
6441 | ||
592a252b | 6442 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6443 | { |
592d1631 L |
6444 | { Bad_Opcode }, |
6445 | { Bad_Opcode }, | |
bf890a93 | 6446 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6447 | }, |
6448 | ||
48521003 IT |
6449 | /* PREFIX_VEX_0F38CF */ |
6450 | { | |
6451 | { Bad_Opcode }, | |
6452 | { Bad_Opcode }, | |
6453 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6454 | }, | |
6455 | ||
592a252b | 6456 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6457 | { |
592d1631 L |
6458 | { Bad_Opcode }, |
6459 | { Bad_Opcode }, | |
592a252b | 6460 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6461 | }, |
6462 | ||
592a252b | 6463 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6464 | { |
592d1631 L |
6465 | { Bad_Opcode }, |
6466 | { Bad_Opcode }, | |
8dcf1fad | 6467 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6468 | }, |
6469 | ||
592a252b | 6470 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6471 | { |
592d1631 L |
6472 | { Bad_Opcode }, |
6473 | { Bad_Opcode }, | |
8dcf1fad | 6474 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6475 | }, |
6476 | ||
592a252b | 6477 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6478 | { |
592d1631 L |
6479 | { Bad_Opcode }, |
6480 | { Bad_Opcode }, | |
8dcf1fad | 6481 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6482 | }, |
6483 | ||
592a252b | 6484 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6485 | { |
592d1631 L |
6486 | { Bad_Opcode }, |
6487 | { Bad_Opcode }, | |
8dcf1fad | 6488 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6489 | }, |
6490 | ||
f12dc422 L |
6491 | /* PREFIX_VEX_0F38F2 */ |
6492 | { | |
6493 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6494 | }, | |
6495 | ||
6496 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6497 | { | |
6498 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6499 | }, | |
6500 | ||
6501 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6502 | { | |
6503 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6504 | }, | |
6505 | ||
6506 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6507 | { | |
6508 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6509 | }, | |
6510 | ||
6c30d220 L |
6511 | /* PREFIX_VEX_0F38F5 */ |
6512 | { | |
6513 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6514 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6515 | { Bad_Opcode }, | |
6516 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6517 | }, | |
6518 | ||
6519 | /* PREFIX_VEX_0F38F6 */ | |
6520 | { | |
6521 | { Bad_Opcode }, | |
6522 | { Bad_Opcode }, | |
6523 | { Bad_Opcode }, | |
6524 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6525 | }, | |
6526 | ||
f12dc422 L |
6527 | /* PREFIX_VEX_0F38F7 */ |
6528 | { | |
6529 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6530 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6531 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6532 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6533 | }, | |
6534 | ||
6535 | /* PREFIX_VEX_0F3A00 */ | |
6536 | { | |
6537 | { Bad_Opcode }, | |
6538 | { Bad_Opcode }, | |
6539 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6540 | }, | |
6541 | ||
6542 | /* PREFIX_VEX_0F3A01 */ | |
6543 | { | |
6544 | { Bad_Opcode }, | |
6545 | { Bad_Opcode }, | |
6546 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6547 | }, | |
6548 | ||
6549 | /* PREFIX_VEX_0F3A02 */ | |
6550 | { | |
6551 | { Bad_Opcode }, | |
6552 | { Bad_Opcode }, | |
6553 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6554 | }, |
6555 | ||
592a252b | 6556 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6557 | { |
592d1631 L |
6558 | { Bad_Opcode }, |
6559 | { Bad_Opcode }, | |
592a252b | 6560 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6561 | }, |
6562 | ||
592a252b | 6563 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6564 | { |
592d1631 L |
6565 | { Bad_Opcode }, |
6566 | { Bad_Opcode }, | |
592a252b | 6567 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6568 | }, |
6569 | ||
592a252b | 6570 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6571 | { |
592d1631 L |
6572 | { Bad_Opcode }, |
6573 | { Bad_Opcode }, | |
592a252b | 6574 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6575 | }, |
6576 | ||
592a252b | 6577 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6578 | { |
592d1631 L |
6579 | { Bad_Opcode }, |
6580 | { Bad_Opcode }, | |
592a252b | 6581 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6582 | }, |
6583 | ||
592a252b | 6584 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6585 | { |
592d1631 L |
6586 | { Bad_Opcode }, |
6587 | { Bad_Opcode }, | |
592a252b | 6588 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6589 | }, |
6590 | ||
592a252b | 6591 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6592 | { |
592d1631 L |
6593 | { Bad_Opcode }, |
6594 | { Bad_Opcode }, | |
592a252b | 6595 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6596 | }, |
6597 | ||
592a252b | 6598 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6599 | { |
592d1631 L |
6600 | { Bad_Opcode }, |
6601 | { Bad_Opcode }, | |
592a252b | 6602 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6603 | }, |
6604 | ||
592a252b | 6605 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6606 | { |
592d1631 L |
6607 | { Bad_Opcode }, |
6608 | { Bad_Opcode }, | |
592a252b | 6609 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6610 | }, |
6611 | ||
592a252b | 6612 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6613 | { |
592d1631 L |
6614 | { Bad_Opcode }, |
6615 | { Bad_Opcode }, | |
592a252b | 6616 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6617 | }, |
6618 | ||
592a252b | 6619 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6620 | { |
592d1631 L |
6621 | { Bad_Opcode }, |
6622 | { Bad_Opcode }, | |
6c30d220 | 6623 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6624 | }, |
6625 | ||
592a252b | 6626 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6627 | { |
592d1631 L |
6628 | { Bad_Opcode }, |
6629 | { Bad_Opcode }, | |
6c30d220 | 6630 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6631 | }, |
6632 | ||
592a252b | 6633 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6634 | { |
592d1631 L |
6635 | { Bad_Opcode }, |
6636 | { Bad_Opcode }, | |
592a252b | 6637 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6638 | }, |
6639 | ||
592a252b | 6640 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6641 | { |
592d1631 L |
6642 | { Bad_Opcode }, |
6643 | { Bad_Opcode }, | |
592a252b | 6644 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6645 | }, |
6646 | ||
592a252b | 6647 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6648 | { |
592d1631 L |
6649 | { Bad_Opcode }, |
6650 | { Bad_Opcode }, | |
592a252b | 6651 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6652 | }, |
6653 | ||
592a252b | 6654 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6655 | { |
592d1631 L |
6656 | { Bad_Opcode }, |
6657 | { Bad_Opcode }, | |
592a252b | 6658 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6659 | }, |
6660 | ||
592a252b | 6661 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6662 | { |
592d1631 L |
6663 | { Bad_Opcode }, |
6664 | { Bad_Opcode }, | |
592a252b | 6665 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6666 | }, |
6667 | ||
592a252b | 6668 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6669 | { |
592d1631 L |
6670 | { Bad_Opcode }, |
6671 | { Bad_Opcode }, | |
592a252b | 6672 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6673 | }, |
6674 | ||
592a252b | 6675 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6676 | { |
6677 | { Bad_Opcode }, | |
6678 | { Bad_Opcode }, | |
bf890a93 | 6679 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6680 | }, |
6681 | ||
592a252b | 6682 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6683 | { |
592d1631 L |
6684 | { Bad_Opcode }, |
6685 | { Bad_Opcode }, | |
592a252b | 6686 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6687 | }, |
6688 | ||
592a252b | 6689 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6690 | { |
592d1631 L |
6691 | { Bad_Opcode }, |
6692 | { Bad_Opcode }, | |
592a252b | 6693 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6694 | }, |
6695 | ||
592a252b | 6696 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6697 | { |
592d1631 L |
6698 | { Bad_Opcode }, |
6699 | { Bad_Opcode }, | |
592a252b | 6700 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6701 | }, |
6702 | ||
43234a1e L |
6703 | /* PREFIX_VEX_0F3A30 */ |
6704 | { | |
6705 | { Bad_Opcode }, | |
6706 | { Bad_Opcode }, | |
6707 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6708 | }, | |
6709 | ||
1ba585e8 IT |
6710 | /* PREFIX_VEX_0F3A31 */ |
6711 | { | |
6712 | { Bad_Opcode }, | |
6713 | { Bad_Opcode }, | |
6714 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6715 | }, | |
6716 | ||
43234a1e L |
6717 | /* PREFIX_VEX_0F3A32 */ |
6718 | { | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
6721 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6722 | }, | |
6723 | ||
1ba585e8 IT |
6724 | /* PREFIX_VEX_0F3A33 */ |
6725 | { | |
6726 | { Bad_Opcode }, | |
6727 | { Bad_Opcode }, | |
6728 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6729 | }, | |
6730 | ||
6c30d220 L |
6731 | /* PREFIX_VEX_0F3A38 */ |
6732 | { | |
6733 | { Bad_Opcode }, | |
6734 | { Bad_Opcode }, | |
6735 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6736 | }, | |
6737 | ||
6738 | /* PREFIX_VEX_0F3A39 */ | |
6739 | { | |
6740 | { Bad_Opcode }, | |
6741 | { Bad_Opcode }, | |
6742 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6743 | }, | |
6744 | ||
592a252b | 6745 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6746 | { |
592d1631 L |
6747 | { Bad_Opcode }, |
6748 | { Bad_Opcode }, | |
592a252b | 6749 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6750 | }, |
6751 | ||
592a252b | 6752 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6753 | { |
592d1631 L |
6754 | { Bad_Opcode }, |
6755 | { Bad_Opcode }, | |
592a252b | 6756 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6757 | }, |
6758 | ||
592a252b | 6759 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6760 | { |
592d1631 L |
6761 | { Bad_Opcode }, |
6762 | { Bad_Opcode }, | |
6c30d220 | 6763 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6764 | }, |
6765 | ||
592a252b | 6766 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6767 | { |
592d1631 L |
6768 | { Bad_Opcode }, |
6769 | { Bad_Opcode }, | |
ff1982d5 | 6770 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6771 | }, |
6772 | ||
6c30d220 L |
6773 | /* PREFIX_VEX_0F3A46 */ |
6774 | { | |
6775 | { Bad_Opcode }, | |
6776 | { Bad_Opcode }, | |
6777 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6778 | }, | |
6779 | ||
592a252b | 6780 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6781 | { |
6782 | { Bad_Opcode }, | |
6783 | { Bad_Opcode }, | |
592a252b | 6784 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6785 | }, |
6786 | ||
592a252b | 6787 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6788 | { |
6789 | { Bad_Opcode }, | |
6790 | { Bad_Opcode }, | |
592a252b | 6791 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6792 | }, |
6793 | ||
592a252b | 6794 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6795 | { |
592d1631 L |
6796 | { Bad_Opcode }, |
6797 | { Bad_Opcode }, | |
592a252b | 6798 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6799 | }, |
6800 | ||
592a252b | 6801 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6802 | { |
592d1631 L |
6803 | { Bad_Opcode }, |
6804 | { Bad_Opcode }, | |
592a252b | 6805 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6806 | }, |
6807 | ||
592a252b | 6808 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6809 | { |
592d1631 L |
6810 | { Bad_Opcode }, |
6811 | { Bad_Opcode }, | |
6c30d220 | 6812 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6813 | }, |
6814 | ||
592a252b | 6815 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6816 | { |
592d1631 L |
6817 | { Bad_Opcode }, |
6818 | { Bad_Opcode }, | |
3a2430e0 | 6819 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6820 | }, |
6821 | ||
592a252b | 6822 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6823 | { |
592d1631 L |
6824 | { Bad_Opcode }, |
6825 | { Bad_Opcode }, | |
3a2430e0 | 6826 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6827 | }, |
6828 | ||
592a252b | 6829 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6830 | { |
592d1631 L |
6831 | { Bad_Opcode }, |
6832 | { Bad_Opcode }, | |
3a2430e0 | 6833 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6834 | }, |
6835 | ||
592a252b | 6836 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6837 | { |
592d1631 L |
6838 | { Bad_Opcode }, |
6839 | { Bad_Opcode }, | |
3a2430e0 | 6840 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6841 | }, |
6842 | ||
592a252b | 6843 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6844 | { |
592d1631 L |
6845 | { Bad_Opcode }, |
6846 | { Bad_Opcode }, | |
592a252b | 6847 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6848 | { Bad_Opcode }, |
c0f3af97 L |
6849 | }, |
6850 | ||
592a252b | 6851 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6852 | { |
592d1631 L |
6853 | { Bad_Opcode }, |
6854 | { Bad_Opcode }, | |
592a252b | 6855 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6856 | }, |
6857 | ||
592a252b | 6858 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6859 | { |
592d1631 L |
6860 | { Bad_Opcode }, |
6861 | { Bad_Opcode }, | |
592a252b | 6862 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6863 | }, |
6864 | ||
592a252b | 6865 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6866 | { |
592d1631 L |
6867 | { Bad_Opcode }, |
6868 | { Bad_Opcode }, | |
592a252b | 6869 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6870 | }, |
a5ff0eb2 | 6871 | |
592a252b | 6872 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6873 | { |
592d1631 L |
6874 | { Bad_Opcode }, |
6875 | { Bad_Opcode }, | |
3a2430e0 | 6876 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6877 | }, |
6878 | ||
592a252b | 6879 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6880 | { |
592d1631 L |
6881 | { Bad_Opcode }, |
6882 | { Bad_Opcode }, | |
3a2430e0 | 6883 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6884 | }, |
6885 | ||
592a252b | 6886 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6887 | { |
592d1631 L |
6888 | { Bad_Opcode }, |
6889 | { Bad_Opcode }, | |
592a252b | 6890 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6891 | }, |
6892 | ||
592a252b | 6893 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6894 | { |
592d1631 L |
6895 | { Bad_Opcode }, |
6896 | { Bad_Opcode }, | |
592a252b | 6897 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6898 | }, |
6899 | ||
592a252b | 6900 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6901 | { |
592d1631 L |
6902 | { Bad_Opcode }, |
6903 | { Bad_Opcode }, | |
3a2430e0 | 6904 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6905 | }, |
6906 | ||
592a252b | 6907 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6908 | { |
592d1631 L |
6909 | { Bad_Opcode }, |
6910 | { Bad_Opcode }, | |
3a2430e0 | 6911 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6912 | }, |
6913 | ||
592a252b | 6914 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6915 | { |
592d1631 L |
6916 | { Bad_Opcode }, |
6917 | { Bad_Opcode }, | |
592a252b | 6918 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6919 | }, |
6920 | ||
592a252b | 6921 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6922 | { |
592d1631 L |
6923 | { Bad_Opcode }, |
6924 | { Bad_Opcode }, | |
592a252b | 6925 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6926 | }, |
6927 | ||
592a252b | 6928 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6929 | { |
592d1631 L |
6930 | { Bad_Opcode }, |
6931 | { Bad_Opcode }, | |
3a2430e0 | 6932 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6933 | }, |
6934 | ||
592a252b | 6935 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6936 | { |
592d1631 L |
6937 | { Bad_Opcode }, |
6938 | { Bad_Opcode }, | |
3a2430e0 | 6939 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6940 | }, |
6941 | ||
592a252b | 6942 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6943 | { |
592d1631 L |
6944 | { Bad_Opcode }, |
6945 | { Bad_Opcode }, | |
592a252b | 6946 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6947 | }, |
6948 | ||
592a252b | 6949 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6950 | { |
592d1631 L |
6951 | { Bad_Opcode }, |
6952 | { Bad_Opcode }, | |
592a252b | 6953 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6954 | }, |
6955 | ||
592a252b | 6956 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6957 | { |
592d1631 L |
6958 | { Bad_Opcode }, |
6959 | { Bad_Opcode }, | |
3a2430e0 | 6960 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6961 | { Bad_Opcode }, |
922d8de8 DR |
6962 | }, |
6963 | ||
592a252b | 6964 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6965 | { |
592d1631 L |
6966 | { Bad_Opcode }, |
6967 | { Bad_Opcode }, | |
3a2430e0 | 6968 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6969 | }, |
6970 | ||
592a252b | 6971 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6972 | { |
592d1631 L |
6973 | { Bad_Opcode }, |
6974 | { Bad_Opcode }, | |
592a252b | 6975 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6976 | }, |
6977 | ||
592a252b | 6978 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6979 | { |
592d1631 L |
6980 | { Bad_Opcode }, |
6981 | { Bad_Opcode }, | |
592a252b | 6982 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6983 | }, |
6984 | ||
48521003 IT |
6985 | /* PREFIX_VEX_0F3ACE */ |
6986 | { | |
6987 | { Bad_Opcode }, | |
6988 | { Bad_Opcode }, | |
6989 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6990 | }, | |
6991 | ||
6992 | /* PREFIX_VEX_0F3ACF */ | |
6993 | { | |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
6996 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6997 | }, | |
6998 | ||
592a252b | 6999 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 7000 | { |
592d1631 L |
7001 | { Bad_Opcode }, |
7002 | { Bad_Opcode }, | |
592a252b | 7003 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 7004 | }, |
6c30d220 L |
7005 | |
7006 | /* PREFIX_VEX_0F3AF0 */ | |
7007 | { | |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
7012 | }, | |
43234a1e L |
7013 | |
7014 | #define NEED_PREFIX_TABLE | |
7015 | #include "i386-dis-evex.h" | |
7016 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
7017 | }; |
7018 | ||
7019 | static const struct dis386 x86_64_table[][2] = { | |
7020 | /* X86_64_06 */ | |
7021 | { | |
bf890a93 | 7022 | { "pushP", { es }, 0 }, |
c0f3af97 L |
7023 | }, |
7024 | ||
7025 | /* X86_64_07 */ | |
7026 | { | |
bf890a93 | 7027 | { "popP", { es }, 0 }, |
c0f3af97 L |
7028 | }, |
7029 | ||
7030 | /* X86_64_0D */ | |
7031 | { | |
bf890a93 | 7032 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
7033 | }, |
7034 | ||
7035 | /* X86_64_16 */ | |
7036 | { | |
bf890a93 | 7037 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
7038 | }, |
7039 | ||
7040 | /* X86_64_17 */ | |
7041 | { | |
bf890a93 | 7042 | { "popP", { ss }, 0 }, |
c0f3af97 L |
7043 | }, |
7044 | ||
7045 | /* X86_64_1E */ | |
7046 | { | |
bf890a93 | 7047 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
7048 | }, |
7049 | ||
7050 | /* X86_64_1F */ | |
7051 | { | |
bf890a93 | 7052 | { "popP", { ds }, 0 }, |
c0f3af97 L |
7053 | }, |
7054 | ||
7055 | /* X86_64_27 */ | |
7056 | { | |
bf890a93 | 7057 | { "daa", { XX }, 0 }, |
c0f3af97 L |
7058 | }, |
7059 | ||
7060 | /* X86_64_2F */ | |
7061 | { | |
bf890a93 | 7062 | { "das", { XX }, 0 }, |
c0f3af97 L |
7063 | }, |
7064 | ||
7065 | /* X86_64_37 */ | |
7066 | { | |
bf890a93 | 7067 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
7068 | }, |
7069 | ||
7070 | /* X86_64_3F */ | |
7071 | { | |
bf890a93 | 7072 | { "aas", { XX }, 0 }, |
c0f3af97 L |
7073 | }, |
7074 | ||
7075 | /* X86_64_60 */ | |
7076 | { | |
bf890a93 | 7077 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
7078 | }, |
7079 | ||
7080 | /* X86_64_61 */ | |
7081 | { | |
bf890a93 | 7082 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
7083 | }, |
7084 | ||
7085 | /* X86_64_62 */ | |
7086 | { | |
7087 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 7088 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
7089 | }, |
7090 | ||
7091 | /* X86_64_63 */ | |
7092 | { | |
bf890a93 IT |
7093 | { "arpl", { Ew, Gw }, 0 }, |
7094 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
7095 | }, |
7096 | ||
7097 | /* X86_64_6D */ | |
7098 | { | |
bf890a93 IT |
7099 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
7100 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
7101 | }, |
7102 | ||
7103 | /* X86_64_6F */ | |
7104 | { | |
bf890a93 IT |
7105 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
7106 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
7107 | }, |
7108 | ||
d039fef3 | 7109 | /* X86_64_82 */ |
8b89fe14 | 7110 | { |
de194d85 | 7111 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 7112 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
7113 | }, |
7114 | ||
c0f3af97 L |
7115 | /* X86_64_9A */ |
7116 | { | |
bf890a93 | 7117 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
7118 | }, |
7119 | ||
7120 | /* X86_64_C4 */ | |
7121 | { | |
7122 | { MOD_TABLE (MOD_C4_32BIT) }, | |
7123 | { VEX_C4_TABLE (VEX_0F) }, | |
7124 | }, | |
7125 | ||
7126 | /* X86_64_C5 */ | |
7127 | { | |
7128 | { MOD_TABLE (MOD_C5_32BIT) }, | |
7129 | { VEX_C5_TABLE (VEX_0F) }, | |
7130 | }, | |
7131 | ||
7132 | /* X86_64_CE */ | |
7133 | { | |
bf890a93 | 7134 | { "into", { XX }, 0 }, |
c0f3af97 L |
7135 | }, |
7136 | ||
7137 | /* X86_64_D4 */ | |
7138 | { | |
bf890a93 | 7139 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
7140 | }, |
7141 | ||
7142 | /* X86_64_D5 */ | |
7143 | { | |
bf890a93 | 7144 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
7145 | }, |
7146 | ||
a72d2af2 L |
7147 | /* X86_64_E8 */ |
7148 | { | |
7149 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 7150 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
7151 | }, |
7152 | ||
7153 | /* X86_64_E9 */ | |
7154 | { | |
7155 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 7156 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
7157 | }, |
7158 | ||
c0f3af97 L |
7159 | /* X86_64_EA */ |
7160 | { | |
bf890a93 | 7161 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
7162 | }, |
7163 | ||
7164 | /* X86_64_0F01_REG_0 */ | |
7165 | { | |
bf890a93 IT |
7166 | { "sgdt{Q|IQ}", { M }, 0 }, |
7167 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
7168 | }, |
7169 | ||
7170 | /* X86_64_0F01_REG_1 */ | |
7171 | { | |
bf890a93 IT |
7172 | { "sidt{Q|IQ}", { M }, 0 }, |
7173 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
7174 | }, |
7175 | ||
7176 | /* X86_64_0F01_REG_2 */ | |
7177 | { | |
bf890a93 IT |
7178 | { "lgdt{Q|Q}", { M }, 0 }, |
7179 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
7180 | }, |
7181 | ||
7182 | /* X86_64_0F01_REG_3 */ | |
7183 | { | |
bf890a93 IT |
7184 | { "lidt{Q|Q}", { M }, 0 }, |
7185 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
7186 | }, |
7187 | }; | |
7188 | ||
7189 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
7190 | |
7191 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
7192 | { |
7193 | /* 00 */ | |
507bd325 L |
7194 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
7195 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
7196 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
7197 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
7198 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
7199 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
7200 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
7201 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 7202 | /* 08 */ |
507bd325 L |
7203 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7204 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7205 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7206 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7207 | { Bad_Opcode }, |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
f88c9eb0 SP |
7211 | /* 10 */ |
7212 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7213 | { Bad_Opcode }, |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
f88c9eb0 SP |
7216 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7217 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7218 | { Bad_Opcode }, |
f88c9eb0 SP |
7219 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7220 | /* 18 */ | |
592d1631 L |
7221 | { Bad_Opcode }, |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
507bd325 L |
7225 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7226 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7227 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7228 | { Bad_Opcode }, |
f88c9eb0 SP |
7229 | /* 20 */ |
7230 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7231 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7232 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7233 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7234 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7235 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7236 | { Bad_Opcode }, |
7237 | { Bad_Opcode }, | |
f88c9eb0 SP |
7238 | /* 28 */ |
7239 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7240 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7241 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7242 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7243 | { Bad_Opcode }, |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
f88c9eb0 SP |
7247 | /* 30 */ |
7248 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7249 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7250 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7251 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7252 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7253 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7254 | { Bad_Opcode }, |
f88c9eb0 SP |
7255 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7256 | /* 38 */ | |
7257 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7258 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7259 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7260 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7261 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7263 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7264 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7265 | /* 40 */ | |
7266 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7267 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7268 | { Bad_Opcode }, |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
f88c9eb0 | 7274 | /* 48 */ |
592d1631 L |
7275 | { Bad_Opcode }, |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
f88c9eb0 | 7283 | /* 50 */ |
592d1631 L |
7284 | { Bad_Opcode }, |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
f88c9eb0 | 7292 | /* 58 */ |
592d1631 L |
7293 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
f88c9eb0 | 7301 | /* 60 */ |
592d1631 L |
7302 | { Bad_Opcode }, |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
f88c9eb0 | 7310 | /* 68 */ |
592d1631 L |
7311 | { Bad_Opcode }, |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
f88c9eb0 | 7319 | /* 70 */ |
592d1631 L |
7320 | { Bad_Opcode }, |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
f88c9eb0 | 7328 | /* 78 */ |
592d1631 L |
7329 | { Bad_Opcode }, |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
f88c9eb0 SP |
7337 | /* 80 */ |
7338 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7339 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7340 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7341 | { Bad_Opcode }, |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
f88c9eb0 | 7346 | /* 88 */ |
592d1631 L |
7347 | { Bad_Opcode }, |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
f88c9eb0 | 7355 | /* 90 */ |
592d1631 L |
7356 | { Bad_Opcode }, |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
f88c9eb0 | 7364 | /* 98 */ |
592d1631 L |
7365 | { Bad_Opcode }, |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
f88c9eb0 | 7373 | /* a0 */ |
592d1631 L |
7374 | { Bad_Opcode }, |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
f88c9eb0 | 7382 | /* a8 */ |
592d1631 L |
7383 | { Bad_Opcode }, |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
f88c9eb0 | 7391 | /* b0 */ |
592d1631 L |
7392 | { Bad_Opcode }, |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
f88c9eb0 | 7400 | /* b8 */ |
592d1631 L |
7401 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
f88c9eb0 | 7409 | /* c0 */ |
592d1631 L |
7410 | { Bad_Opcode }, |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
f88c9eb0 | 7418 | /* c8 */ |
a0046408 L |
7419 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7420 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7421 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7422 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7423 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7424 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7425 | { Bad_Opcode }, |
48521003 | 7426 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7427 | /* d0 */ |
592d1631 L |
7428 | { Bad_Opcode }, |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
f88c9eb0 | 7436 | /* d8 */ |
592d1631 L |
7437 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
f88c9eb0 SP |
7440 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7441 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7442 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7443 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7444 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7445 | /* e0 */ | |
592d1631 L |
7446 | { Bad_Opcode }, |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
f88c9eb0 | 7454 | /* e8 */ |
592d1631 L |
7455 | { Bad_Opcode }, |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
f88c9eb0 SP |
7463 | /* f0 */ |
7464 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7465 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7466 | { Bad_Opcode }, |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
603555e5 | 7469 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7470 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7471 | { Bad_Opcode }, |
f88c9eb0 | 7472 | /* f8 */ |
c0a30a9f L |
7473 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7474 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7475 | { Bad_Opcode }, |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
f88c9eb0 SP |
7481 | }, |
7482 | /* THREE_BYTE_0F3A */ | |
7483 | { | |
7484 | /* 00 */ | |
592d1631 L |
7485 | { Bad_Opcode }, |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
f88c9eb0 SP |
7493 | /* 08 */ |
7494 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7495 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7496 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7497 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7498 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7499 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7500 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7501 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7502 | /* 10 */ |
592d1631 L |
7503 | { Bad_Opcode }, |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
f88c9eb0 SP |
7507 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7508 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7509 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7510 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7511 | /* 18 */ | |
592d1631 L |
7512 | { Bad_Opcode }, |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
f88c9eb0 SP |
7520 | /* 20 */ |
7521 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7522 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7523 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7524 | { Bad_Opcode }, |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
f88c9eb0 | 7529 | /* 28 */ |
592d1631 L |
7530 | { Bad_Opcode }, |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
f88c9eb0 | 7538 | /* 30 */ |
592d1631 L |
7539 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
f88c9eb0 | 7547 | /* 38 */ |
592d1631 L |
7548 | { Bad_Opcode }, |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
f88c9eb0 SP |
7556 | /* 40 */ |
7557 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7558 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7559 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7560 | { Bad_Opcode }, |
f88c9eb0 | 7561 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7562 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
f88c9eb0 | 7565 | /* 48 */ |
592d1631 L |
7566 | { Bad_Opcode }, |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
f88c9eb0 | 7574 | /* 50 */ |
592d1631 L |
7575 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
f88c9eb0 | 7583 | /* 58 */ |
592d1631 L |
7584 | { Bad_Opcode }, |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
f88c9eb0 SP |
7592 | /* 60 */ |
7593 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7594 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7595 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7596 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7597 | { Bad_Opcode }, |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
f88c9eb0 | 7601 | /* 68 */ |
592d1631 L |
7602 | { Bad_Opcode }, |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
f88c9eb0 | 7610 | /* 70 */ |
592d1631 L |
7611 | { Bad_Opcode }, |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
f88c9eb0 | 7619 | /* 78 */ |
592d1631 L |
7620 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
f88c9eb0 | 7628 | /* 80 */ |
592d1631 L |
7629 | { Bad_Opcode }, |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
f88c9eb0 | 7637 | /* 88 */ |
592d1631 L |
7638 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
f88c9eb0 | 7646 | /* 90 */ |
592d1631 L |
7647 | { Bad_Opcode }, |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
f88c9eb0 | 7655 | /* 98 */ |
592d1631 L |
7656 | { Bad_Opcode }, |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
f88c9eb0 | 7664 | /* a0 */ |
592d1631 L |
7665 | { Bad_Opcode }, |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
f88c9eb0 | 7673 | /* a8 */ |
592d1631 L |
7674 | { Bad_Opcode }, |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
f88c9eb0 | 7682 | /* b0 */ |
592d1631 L |
7683 | { Bad_Opcode }, |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
f88c9eb0 | 7691 | /* b8 */ |
592d1631 L |
7692 | { Bad_Opcode }, |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
f88c9eb0 | 7700 | /* c0 */ |
592d1631 L |
7701 | { Bad_Opcode }, |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
f88c9eb0 | 7709 | /* c8 */ |
592d1631 L |
7710 | { Bad_Opcode }, |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
a0046408 | 7714 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7715 | { Bad_Opcode }, |
48521003 IT |
7716 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7717 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7718 | /* d0 */ |
592d1631 L |
7719 | { Bad_Opcode }, |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
f88c9eb0 | 7727 | /* d8 */ |
592d1631 L |
7728 | { Bad_Opcode }, |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
f88c9eb0 SP |
7735 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7736 | /* e0 */ | |
592d1631 L |
7737 | { Bad_Opcode }, |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
592d1631 L |
7742 | { Bad_Opcode }, |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
85f10a01 | 7745 | /* e8 */ |
592d1631 L |
7746 | { Bad_Opcode }, |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
85f10a01 | 7754 | /* f0 */ |
592d1631 L |
7755 | { Bad_Opcode }, |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
85f10a01 | 7763 | /* f8 */ |
592d1631 L |
7764 | { Bad_Opcode }, |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
85f10a01 | 7772 | }, |
f88c9eb0 SP |
7773 | }; |
7774 | ||
7775 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7776 | /* XOP_08 */ |
85f10a01 MM |
7777 | { |
7778 | /* 00 */ | |
592d1631 L |
7779 | { Bad_Opcode }, |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
85f10a01 | 7787 | /* 08 */ |
592d1631 L |
7788 | { Bad_Opcode }, |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
85f10a01 | 7796 | /* 10 */ |
3929df09 | 7797 | { Bad_Opcode }, |
592d1631 L |
7798 | { Bad_Opcode }, |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
85f10a01 | 7805 | /* 18 */ |
592d1631 L |
7806 | { Bad_Opcode }, |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
85f10a01 | 7814 | /* 20 */ |
592d1631 L |
7815 | { Bad_Opcode }, |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
85f10a01 | 7823 | /* 28 */ |
592d1631 L |
7824 | { Bad_Opcode }, |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
c0f3af97 | 7832 | /* 30 */ |
592d1631 L |
7833 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
c0f3af97 | 7841 | /* 38 */ |
592d1631 L |
7842 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
c0f3af97 | 7850 | /* 40 */ |
592d1631 L |
7851 | { Bad_Opcode }, |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
85f10a01 | 7859 | /* 48 */ |
592d1631 L |
7860 | { Bad_Opcode }, |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
c0f3af97 | 7868 | /* 50 */ |
592d1631 L |
7869 | { Bad_Opcode }, |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
85f10a01 | 7877 | /* 58 */ |
592d1631 L |
7878 | { Bad_Opcode }, |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
c1e679ec | 7886 | /* 60 */ |
592d1631 L |
7887 | { Bad_Opcode }, |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
c0f3af97 | 7895 | /* 68 */ |
592d1631 L |
7896 | { Bad_Opcode }, |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
85f10a01 | 7904 | /* 70 */ |
592d1631 L |
7905 | { Bad_Opcode }, |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
85f10a01 | 7913 | /* 78 */ |
592d1631 L |
7914 | { Bad_Opcode }, |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
85f10a01 | 7922 | /* 80 */ |
592d1631 L |
7923 | { Bad_Opcode }, |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
3a2430e0 JB |
7928 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7929 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7930 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7931 | /* 88 */ |
592d1631 L |
7932 | { Bad_Opcode }, |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
3a2430e0 JB |
7938 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7939 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7940 | /* 90 */ |
592d1631 L |
7941 | { Bad_Opcode }, |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
3a2430e0 JB |
7946 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7947 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7948 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7949 | /* 98 */ |
592d1631 L |
7950 | { Bad_Opcode }, |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
3a2430e0 JB |
7956 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7957 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7958 | /* a0 */ |
592d1631 L |
7959 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, | |
3a2430e0 JB |
7961 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7962 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7963 | { Bad_Opcode }, |
7964 | { Bad_Opcode }, | |
3a2430e0 | 7965 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7966 | { Bad_Opcode }, |
5dd85c99 | 7967 | /* a8 */ |
592d1631 L |
7968 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
5dd85c99 | 7976 | /* b0 */ |
592d1631 L |
7977 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
3a2430e0 | 7983 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7984 | { Bad_Opcode }, |
5dd85c99 | 7985 | /* b8 */ |
592d1631 L |
7986 | { Bad_Opcode }, |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
5dd85c99 | 7994 | /* c0 */ |
bf890a93 IT |
7995 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7996 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7997 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7998 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7999 | { Bad_Opcode }, |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
5dd85c99 | 8003 | /* c8 */ |
592d1631 L |
8004 | { Bad_Opcode }, |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
ff688e1f L |
8008 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
8009 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
8010 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
8011 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 8012 | /* d0 */ |
592d1631 L |
8013 | { Bad_Opcode }, |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
5dd85c99 | 8021 | /* d8 */ |
592d1631 L |
8022 | { Bad_Opcode }, |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
5dd85c99 | 8030 | /* e0 */ |
592d1631 L |
8031 | { Bad_Opcode }, |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
5dd85c99 | 8039 | /* e8 */ |
592d1631 L |
8040 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
ff688e1f L |
8044 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
8045 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
8046 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
8047 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 8048 | /* f0 */ |
592d1631 L |
8049 | { Bad_Opcode }, |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
5dd85c99 | 8057 | /* f8 */ |
592d1631 L |
8058 | { Bad_Opcode }, |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
5dd85c99 SP |
8066 | }, |
8067 | /* XOP_09 */ | |
8068 | { | |
8069 | /* 00 */ | |
592d1631 | 8070 | { Bad_Opcode }, |
2a2a0f38 QN |
8071 | { REG_TABLE (REG_XOP_TBM_01) }, |
8072 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8073 | { Bad_Opcode }, |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
5dd85c99 | 8078 | /* 08 */ |
592d1631 L |
8079 | { Bad_Opcode }, |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
5dd85c99 | 8087 | /* 10 */ |
592d1631 L |
8088 | { Bad_Opcode }, |
8089 | { Bad_Opcode }, | |
5dd85c99 | 8090 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8091 | { Bad_Opcode }, |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
5dd85c99 | 8096 | /* 18 */ |
592d1631 L |
8097 | { Bad_Opcode }, |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
5dd85c99 | 8105 | /* 20 */ |
592d1631 L |
8106 | { Bad_Opcode }, |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
5dd85c99 | 8114 | /* 28 */ |
592d1631 L |
8115 | { Bad_Opcode }, |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
5dd85c99 | 8123 | /* 30 */ |
592d1631 L |
8124 | { Bad_Opcode }, |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
5dd85c99 | 8132 | /* 38 */ |
592d1631 L |
8133 | { Bad_Opcode }, |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
5dd85c99 | 8141 | /* 40 */ |
592d1631 L |
8142 | { Bad_Opcode }, |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
5dd85c99 | 8150 | /* 48 */ |
592d1631 L |
8151 | { Bad_Opcode }, |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
5dd85c99 | 8159 | /* 50 */ |
592d1631 L |
8160 | { Bad_Opcode }, |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
5dd85c99 | 8168 | /* 58 */ |
592d1631 L |
8169 | { Bad_Opcode }, |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
5dd85c99 | 8177 | /* 60 */ |
592d1631 L |
8178 | { Bad_Opcode }, |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
5dd85c99 | 8186 | /* 68 */ |
592d1631 L |
8187 | { Bad_Opcode }, |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
5dd85c99 | 8195 | /* 70 */ |
592d1631 L |
8196 | { Bad_Opcode }, |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
5dd85c99 | 8204 | /* 78 */ |
592d1631 L |
8205 | { Bad_Opcode }, |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
5dd85c99 | 8213 | /* 80 */ |
592a252b L |
8214 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8215 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8216 | { "vfrczss", { XM, EXd }, 0 }, |
8217 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8218 | { Bad_Opcode }, |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
5dd85c99 | 8222 | /* 88 */ |
592d1631 L |
8223 | { Bad_Opcode }, |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
5dd85c99 | 8231 | /* 90 */ |
bf890a93 IT |
8232 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8233 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8234 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8235 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8236 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8237 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8238 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8239 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8240 | /* 98 */ |
bf890a93 IT |
8241 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8242 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8243 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8244 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8245 | { Bad_Opcode }, |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
5dd85c99 | 8249 | /* a0 */ |
592d1631 L |
8250 | { Bad_Opcode }, |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
5dd85c99 | 8258 | /* a8 */ |
592d1631 L |
8259 | { Bad_Opcode }, |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
5dd85c99 | 8267 | /* b0 */ |
592d1631 L |
8268 | { Bad_Opcode }, |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
5dd85c99 | 8276 | /* b8 */ |
592d1631 L |
8277 | { Bad_Opcode }, |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
5dd85c99 | 8285 | /* c0 */ |
592d1631 | 8286 | { Bad_Opcode }, |
bf890a93 IT |
8287 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8288 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8289 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8290 | { Bad_Opcode }, |
8291 | { Bad_Opcode }, | |
bf890a93 IT |
8292 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8293 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8294 | /* c8 */ |
592d1631 L |
8295 | { Bad_Opcode }, |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
bf890a93 | 8298 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8299 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
5dd85c99 | 8303 | /* d0 */ |
592d1631 | 8304 | { Bad_Opcode }, |
bf890a93 IT |
8305 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8306 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8307 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8308 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, | |
bf890a93 IT |
8310 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8311 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8312 | /* d8 */ |
592d1631 L |
8313 | { Bad_Opcode }, |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
bf890a93 | 8316 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8317 | { Bad_Opcode }, |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
5dd85c99 | 8321 | /* e0 */ |
592d1631 | 8322 | { Bad_Opcode }, |
bf890a93 IT |
8323 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8324 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8325 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8326 | { Bad_Opcode }, |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
4e7d34a6 | 8330 | /* e8 */ |
592d1631 L |
8331 | { Bad_Opcode }, |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
4e7d34a6 | 8339 | /* f0 */ |
592d1631 L |
8340 | { Bad_Opcode }, |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
4e7d34a6 | 8348 | /* f8 */ |
592d1631 L |
8349 | { Bad_Opcode }, |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
4e7d34a6 | 8357 | }, |
f88c9eb0 | 8358 | /* XOP_0A */ |
4e7d34a6 L |
8359 | { |
8360 | /* 00 */ | |
592d1631 L |
8361 | { Bad_Opcode }, |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
4e7d34a6 | 8369 | /* 08 */ |
592d1631 L |
8370 | { Bad_Opcode }, |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
4e7d34a6 | 8378 | /* 10 */ |
bf890a93 | 8379 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8380 | { Bad_Opcode }, |
f88c9eb0 | 8381 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8382 | { Bad_Opcode }, |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
4e7d34a6 | 8387 | /* 18 */ |
592d1631 L |
8388 | { Bad_Opcode }, |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
4e7d34a6 | 8396 | /* 20 */ |
592d1631 L |
8397 | { Bad_Opcode }, |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
4e7d34a6 | 8405 | /* 28 */ |
592d1631 L |
8406 | { Bad_Opcode }, |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
4e7d34a6 | 8414 | /* 30 */ |
592d1631 L |
8415 | { Bad_Opcode }, |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
c0f3af97 | 8423 | /* 38 */ |
592d1631 L |
8424 | { Bad_Opcode }, |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
c0f3af97 | 8432 | /* 40 */ |
592d1631 L |
8433 | { Bad_Opcode }, |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
c1e679ec | 8441 | /* 48 */ |
592d1631 L |
8442 | { Bad_Opcode }, |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
c1e679ec | 8450 | /* 50 */ |
592d1631 L |
8451 | { Bad_Opcode }, |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
4e7d34a6 | 8459 | /* 58 */ |
592d1631 L |
8460 | { Bad_Opcode }, |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
4e7d34a6 | 8468 | /* 60 */ |
592d1631 L |
8469 | { Bad_Opcode }, |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
4e7d34a6 | 8477 | /* 68 */ |
592d1631 L |
8478 | { Bad_Opcode }, |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
4e7d34a6 | 8486 | /* 70 */ |
592d1631 L |
8487 | { Bad_Opcode }, |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
4e7d34a6 | 8495 | /* 78 */ |
592d1631 L |
8496 | { Bad_Opcode }, |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
4e7d34a6 | 8504 | /* 80 */ |
592d1631 L |
8505 | { Bad_Opcode }, |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
4e7d34a6 | 8513 | /* 88 */ |
592d1631 L |
8514 | { Bad_Opcode }, |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
4e7d34a6 | 8522 | /* 90 */ |
592d1631 L |
8523 | { Bad_Opcode }, |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
4e7d34a6 | 8531 | /* 98 */ |
592d1631 L |
8532 | { Bad_Opcode }, |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
4e7d34a6 | 8540 | /* a0 */ |
592d1631 L |
8541 | { Bad_Opcode }, |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
8546 | { Bad_Opcode }, | |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
4e7d34a6 | 8549 | /* a8 */ |
592d1631 L |
8550 | { Bad_Opcode }, |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
d5d7db8e | 8558 | /* b0 */ |
592d1631 L |
8559 | { Bad_Opcode }, |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
85f10a01 | 8567 | /* b8 */ |
592d1631 L |
8568 | { Bad_Opcode }, |
8569 | { Bad_Opcode }, | |
8570 | { Bad_Opcode }, | |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
85f10a01 | 8576 | /* c0 */ |
592d1631 L |
8577 | { Bad_Opcode }, |
8578 | { Bad_Opcode }, | |
8579 | { Bad_Opcode }, | |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
85f10a01 | 8585 | /* c8 */ |
592d1631 L |
8586 | { Bad_Opcode }, |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
85f10a01 | 8594 | /* d0 */ |
592d1631 L |
8595 | { Bad_Opcode }, |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
85f10a01 | 8603 | /* d8 */ |
592d1631 L |
8604 | { Bad_Opcode }, |
8605 | { Bad_Opcode }, | |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
85f10a01 | 8612 | /* e0 */ |
592d1631 L |
8613 | { Bad_Opcode }, |
8614 | { Bad_Opcode }, | |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
85f10a01 | 8621 | /* e8 */ |
592d1631 L |
8622 | { Bad_Opcode }, |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
85f10a01 | 8630 | /* f0 */ |
592d1631 L |
8631 | { Bad_Opcode }, |
8632 | { Bad_Opcode }, | |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
85f10a01 | 8639 | /* f8 */ |
592d1631 L |
8640 | { Bad_Opcode }, |
8641 | { Bad_Opcode }, | |
8642 | { Bad_Opcode }, | |
8643 | { Bad_Opcode }, | |
8644 | { Bad_Opcode }, | |
8645 | { Bad_Opcode }, | |
8646 | { Bad_Opcode }, | |
8647 | { Bad_Opcode }, | |
85f10a01 | 8648 | }, |
c0f3af97 L |
8649 | }; |
8650 | ||
8651 | static const struct dis386 vex_table[][256] = { | |
8652 | /* VEX_0F */ | |
85f10a01 MM |
8653 | { |
8654 | /* 00 */ | |
592d1631 L |
8655 | { Bad_Opcode }, |
8656 | { Bad_Opcode }, | |
8657 | { Bad_Opcode }, | |
8658 | { Bad_Opcode }, | |
8659 | { Bad_Opcode }, | |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
85f10a01 | 8663 | /* 08 */ |
592d1631 L |
8664 | { Bad_Opcode }, |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
8667 | { Bad_Opcode }, | |
8668 | { Bad_Opcode }, | |
8669 | { Bad_Opcode }, | |
8670 | { Bad_Opcode }, | |
8671 | { Bad_Opcode }, | |
c0f3af97 | 8672 | /* 10 */ |
592a252b L |
8673 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8674 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8676 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8677 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8678 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8679 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8680 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8681 | /* 18 */ |
592d1631 L |
8682 | { Bad_Opcode }, |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
8689 | { Bad_Opcode }, | |
c0f3af97 | 8690 | /* 20 */ |
592d1631 L |
8691 | { Bad_Opcode }, |
8692 | { Bad_Opcode }, | |
8693 | { Bad_Opcode }, | |
8694 | { Bad_Opcode }, | |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
c0f3af97 | 8699 | /* 28 */ |
592a252b L |
8700 | { VEX_W_TABLE (VEX_W_0F28) }, |
8701 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8703 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8704 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8706 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8708 | /* 30 */ |
592d1631 L |
8709 | { Bad_Opcode }, |
8710 | { Bad_Opcode }, | |
8711 | { Bad_Opcode }, | |
8712 | { Bad_Opcode }, | |
8713 | { Bad_Opcode }, | |
8714 | { Bad_Opcode }, | |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
4e7d34a6 | 8717 | /* 38 */ |
592d1631 L |
8718 | { Bad_Opcode }, |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
8721 | { Bad_Opcode }, | |
8722 | { Bad_Opcode }, | |
8723 | { Bad_Opcode }, | |
8724 | { Bad_Opcode }, | |
8725 | { Bad_Opcode }, | |
d5d7db8e | 8726 | /* 40 */ |
592d1631 | 8727 | { Bad_Opcode }, |
43234a1e L |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8730 | { Bad_Opcode }, |
43234a1e L |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8735 | /* 48 */ |
592d1631 L |
8736 | { Bad_Opcode }, |
8737 | { Bad_Opcode }, | |
1ba585e8 | 8738 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8739 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8740 | { Bad_Opcode }, |
8741 | { Bad_Opcode }, | |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
d5d7db8e | 8744 | /* 50 */ |
592a252b L |
8745 | { MOD_TABLE (MOD_VEX_0F50) }, |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8749 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8750 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8751 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8752 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8753 | /* 58 */ |
592a252b L |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8762 | /* 60 */ |
592a252b L |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8771 | /* 68 */ |
592a252b L |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8780 | /* 70 */ |
592a252b L |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8782 | { REG_TABLE (REG_VEX_0F71) }, | |
8783 | { REG_TABLE (REG_VEX_0F72) }, | |
8784 | { REG_TABLE (REG_VEX_0F73) }, | |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8789 | /* 78 */ |
592d1631 L |
8790 | { Bad_Opcode }, |
8791 | { Bad_Opcode }, | |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
592a252b L |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8798 | /* 80 */ |
592d1631 L |
8799 | { Bad_Opcode }, |
8800 | { Bad_Opcode }, | |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
c0f3af97 | 8807 | /* 88 */ |
592d1631 L |
8808 | { Bad_Opcode }, |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
c0f3af97 | 8816 | /* 90 */ |
43234a1e L |
8817 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8818 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8819 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8821 | { Bad_Opcode }, |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
c0f3af97 | 8825 | /* 98 */ |
43234a1e | 8826 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8827 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8828 | { Bad_Opcode }, |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
c0f3af97 | 8834 | /* a0 */ |
592d1631 L |
8835 | { Bad_Opcode }, |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
c0f3af97 | 8843 | /* a8 */ |
592d1631 L |
8844 | { Bad_Opcode }, |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
592a252b | 8850 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8851 | { Bad_Opcode }, |
c0f3af97 | 8852 | /* b0 */ |
592d1631 L |
8853 | { Bad_Opcode }, |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
c0f3af97 | 8861 | /* b8 */ |
592d1631 L |
8862 | { Bad_Opcode }, |
8863 | { Bad_Opcode }, | |
8864 | { Bad_Opcode }, | |
8865 | { Bad_Opcode }, | |
8866 | { Bad_Opcode }, | |
8867 | { Bad_Opcode }, | |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
c0f3af97 | 8870 | /* c0 */ |
592d1631 L |
8871 | { Bad_Opcode }, |
8872 | { Bad_Opcode }, | |
592a252b | 8873 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8874 | { Bad_Opcode }, |
592a252b L |
8875 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8876 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8877 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8878 | { Bad_Opcode }, |
c0f3af97 | 8879 | /* c8 */ |
592d1631 L |
8880 | { Bad_Opcode }, |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
8886 | { Bad_Opcode }, | |
8887 | { Bad_Opcode }, | |
c0f3af97 | 8888 | /* d0 */ |
592a252b L |
8889 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8890 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8895 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8896 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8897 | /* d8 */ |
592a252b L |
8898 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8899 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8900 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8906 | /* e0 */ |
592a252b L |
8907 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8908 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8913 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8915 | /* e8 */ |
592a252b L |
8916 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8917 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8922 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8923 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8924 | /* f0 */ |
592a252b L |
8925 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8926 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8927 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8928 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8929 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8930 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8931 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8932 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8933 | /* f8 */ |
592a252b L |
8934 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8935 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8936 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8937 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8938 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8940 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8941 | { Bad_Opcode }, |
c0f3af97 L |
8942 | }, |
8943 | /* VEX_0F38 */ | |
8944 | { | |
8945 | /* 00 */ | |
592a252b L |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8949 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8954 | /* 08 */ |
592a252b L |
8955 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8956 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8958 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8959 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8960 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8961 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8963 | /* 10 */ |
592d1631 L |
8964 | { Bad_Opcode }, |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
592a252b | 8967 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8968 | { Bad_Opcode }, |
8969 | { Bad_Opcode }, | |
6c30d220 | 8970 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8971 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8972 | /* 18 */ |
592a252b L |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8976 | { Bad_Opcode }, |
592a252b L |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8980 | { Bad_Opcode }, |
c0f3af97 | 8981 | /* 20 */ |
592a252b L |
8982 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8983 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8984 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8985 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8988 | { Bad_Opcode }, |
8989 | { Bad_Opcode }, | |
c0f3af97 | 8990 | /* 28 */ |
592a252b L |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8999 | /* 30 */ |
592a252b L |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 9006 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 9007 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 9008 | /* 38 */ |
592a252b L |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 9017 | /* 40 */ |
592a252b L |
9018 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
9020 | { Bad_Opcode }, |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
6c30d220 L |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 9026 | /* 48 */ |
592d1631 L |
9027 | { Bad_Opcode }, |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
c0f3af97 | 9035 | /* 50 */ |
592d1631 L |
9036 | { Bad_Opcode }, |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
c0f3af97 | 9044 | /* 58 */ |
6c30d220 L |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
9048 | { Bad_Opcode }, |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
c0f3af97 | 9053 | /* 60 */ |
592d1631 L |
9054 | { Bad_Opcode }, |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
c0f3af97 | 9062 | /* 68 */ |
592d1631 L |
9063 | { Bad_Opcode }, |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
c0f3af97 | 9071 | /* 70 */ |
592d1631 L |
9072 | { Bad_Opcode }, |
9073 | { Bad_Opcode }, | |
9074 | { Bad_Opcode }, | |
9075 | { Bad_Opcode }, | |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
c0f3af97 | 9080 | /* 78 */ |
6c30d220 L |
9081 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9082 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9083 | { Bad_Opcode }, |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
c0f3af97 | 9089 | /* 80 */ |
592d1631 L |
9090 | { Bad_Opcode }, |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
9094 | { Bad_Opcode }, | |
9095 | { Bad_Opcode }, | |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
c0f3af97 | 9098 | /* 88 */ |
592d1631 L |
9099 | { Bad_Opcode }, |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
6c30d220 | 9103 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9104 | { Bad_Opcode }, |
6c30d220 | 9105 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9106 | { Bad_Opcode }, |
c0f3af97 | 9107 | /* 90 */ |
6c30d220 L |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9112 | { Bad_Opcode }, |
9113 | { Bad_Opcode }, | |
592a252b L |
9114 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9115 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9116 | /* 98 */ |
592a252b L |
9117 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9118 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9119 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9120 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9121 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9122 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9123 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9125 | /* a0 */ |
592d1631 L |
9126 | { Bad_Opcode }, |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
9129 | { Bad_Opcode }, | |
9130 | { Bad_Opcode }, | |
9131 | { Bad_Opcode }, | |
592a252b L |
9132 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9133 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9134 | /* a8 */ |
592a252b L |
9135 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9136 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9137 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9138 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9139 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9141 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9142 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9143 | /* b0 */ |
592d1631 L |
9144 | { Bad_Opcode }, |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
592a252b L |
9150 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9151 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9152 | /* b8 */ |
592a252b L |
9153 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9154 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9155 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9156 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9160 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9161 | /* c0 */ |
592d1631 L |
9162 | { Bad_Opcode }, |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
c0f3af97 | 9170 | /* c8 */ |
592d1631 L |
9171 | { Bad_Opcode }, |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
48521003 | 9178 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 9179 | /* d0 */ |
592d1631 L |
9180 | { Bad_Opcode }, |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
c0f3af97 | 9188 | /* d8 */ |
592d1631 L |
9189 | { Bad_Opcode }, |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
592a252b L |
9192 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9196 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9197 | /* e0 */ |
592d1631 L |
9198 | { Bad_Opcode }, |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
c0f3af97 | 9206 | /* e8 */ |
592d1631 L |
9207 | { Bad_Opcode }, |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
9213 | { Bad_Opcode }, | |
9214 | { Bad_Opcode }, | |
c0f3af97 | 9215 | /* f0 */ |
592d1631 L |
9216 | { Bad_Opcode }, |
9217 | { Bad_Opcode }, | |
f12dc422 L |
9218 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9219 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9220 | { Bad_Opcode }, |
6c30d220 L |
9221 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9222 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9223 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9224 | /* f8 */ |
592d1631 L |
9225 | { Bad_Opcode }, |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
c0f3af97 L |
9233 | }, |
9234 | /* VEX_0F3A */ | |
9235 | { | |
9236 | /* 00 */ | |
6c30d220 L |
9237 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9238 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9239 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9240 | { Bad_Opcode }, |
592a252b L |
9241 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9242 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9243 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9244 | { Bad_Opcode }, |
c0f3af97 | 9245 | /* 08 */ |
592a252b L |
9246 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9247 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9248 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9249 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9250 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9251 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9252 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9253 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9254 | /* 10 */ |
592d1631 L |
9255 | { Bad_Opcode }, |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
592a252b L |
9259 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9260 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9261 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9262 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9263 | /* 18 */ |
592a252b L |
9264 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9265 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9266 | { Bad_Opcode }, |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
592a252b | 9269 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9270 | { Bad_Opcode }, |
9271 | { Bad_Opcode }, | |
c0f3af97 | 9272 | /* 20 */ |
592a252b L |
9273 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9274 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9275 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9276 | { Bad_Opcode }, |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
c0f3af97 | 9281 | /* 28 */ |
592d1631 L |
9282 | { Bad_Opcode }, |
9283 | { Bad_Opcode }, | |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
c0f3af97 | 9290 | /* 30 */ |
43234a1e | 9291 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9292 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9293 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9294 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9295 | { Bad_Opcode }, |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
c0f3af97 | 9299 | /* 38 */ |
6c30d220 L |
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9301 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9302 | { Bad_Opcode }, |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
9306 | { Bad_Opcode }, | |
9307 | { Bad_Opcode }, | |
c0f3af97 | 9308 | /* 40 */ |
592a252b L |
9309 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9310 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9311 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9312 | { Bad_Opcode }, |
592a252b | 9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9314 | { Bad_Opcode }, |
6c30d220 | 9315 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9316 | { Bad_Opcode }, |
c0f3af97 | 9317 | /* 48 */ |
592a252b L |
9318 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9319 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9320 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9321 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9322 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9323 | { Bad_Opcode }, |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
c0f3af97 | 9326 | /* 50 */ |
592d1631 L |
9327 | { Bad_Opcode }, |
9328 | { Bad_Opcode }, | |
9329 | { Bad_Opcode }, | |
9330 | { Bad_Opcode }, | |
9331 | { Bad_Opcode }, | |
9332 | { Bad_Opcode }, | |
9333 | { Bad_Opcode }, | |
9334 | { Bad_Opcode }, | |
c0f3af97 | 9335 | /* 58 */ |
592d1631 L |
9336 | { Bad_Opcode }, |
9337 | { Bad_Opcode }, | |
9338 | { Bad_Opcode }, | |
9339 | { Bad_Opcode }, | |
592a252b L |
9340 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9341 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9342 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9343 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9344 | /* 60 */ |
592a252b L |
9345 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9346 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9347 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9348 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9349 | { Bad_Opcode }, |
9350 | { Bad_Opcode }, | |
9351 | { Bad_Opcode }, | |
9352 | { Bad_Opcode }, | |
c0f3af97 | 9353 | /* 68 */ |
592a252b L |
9354 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9355 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9356 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9357 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9358 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9359 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9360 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9361 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9362 | /* 70 */ |
592d1631 L |
9363 | { Bad_Opcode }, |
9364 | { Bad_Opcode }, | |
9365 | { Bad_Opcode }, | |
9366 | { Bad_Opcode }, | |
9367 | { Bad_Opcode }, | |
9368 | { Bad_Opcode }, | |
9369 | { Bad_Opcode }, | |
9370 | { Bad_Opcode }, | |
c0f3af97 | 9371 | /* 78 */ |
592a252b L |
9372 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9373 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9374 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9375 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9376 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9377 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9378 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9379 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9380 | /* 80 */ |
592d1631 L |
9381 | { Bad_Opcode }, |
9382 | { Bad_Opcode }, | |
9383 | { Bad_Opcode }, | |
9384 | { Bad_Opcode }, | |
9385 | { Bad_Opcode }, | |
9386 | { Bad_Opcode }, | |
9387 | { Bad_Opcode }, | |
9388 | { Bad_Opcode }, | |
c0f3af97 | 9389 | /* 88 */ |
592d1631 L |
9390 | { Bad_Opcode }, |
9391 | { Bad_Opcode }, | |
9392 | { Bad_Opcode }, | |
9393 | { Bad_Opcode }, | |
9394 | { Bad_Opcode }, | |
9395 | { Bad_Opcode }, | |
9396 | { Bad_Opcode }, | |
9397 | { Bad_Opcode }, | |
c0f3af97 | 9398 | /* 90 */ |
592d1631 L |
9399 | { Bad_Opcode }, |
9400 | { Bad_Opcode }, | |
9401 | { Bad_Opcode }, | |
9402 | { Bad_Opcode }, | |
9403 | { Bad_Opcode }, | |
9404 | { Bad_Opcode }, | |
9405 | { Bad_Opcode }, | |
9406 | { Bad_Opcode }, | |
c0f3af97 | 9407 | /* 98 */ |
592d1631 L |
9408 | { Bad_Opcode }, |
9409 | { Bad_Opcode }, | |
9410 | { Bad_Opcode }, | |
9411 | { Bad_Opcode }, | |
9412 | { Bad_Opcode }, | |
9413 | { Bad_Opcode }, | |
9414 | { Bad_Opcode }, | |
9415 | { Bad_Opcode }, | |
c0f3af97 | 9416 | /* a0 */ |
592d1631 L |
9417 | { Bad_Opcode }, |
9418 | { Bad_Opcode }, | |
9419 | { Bad_Opcode }, | |
9420 | { Bad_Opcode }, | |
9421 | { Bad_Opcode }, | |
9422 | { Bad_Opcode }, | |
9423 | { Bad_Opcode }, | |
9424 | { Bad_Opcode }, | |
c0f3af97 | 9425 | /* a8 */ |
592d1631 L |
9426 | { Bad_Opcode }, |
9427 | { Bad_Opcode }, | |
9428 | { Bad_Opcode }, | |
9429 | { Bad_Opcode }, | |
9430 | { Bad_Opcode }, | |
9431 | { Bad_Opcode }, | |
9432 | { Bad_Opcode }, | |
9433 | { Bad_Opcode }, | |
c0f3af97 | 9434 | /* b0 */ |
592d1631 L |
9435 | { Bad_Opcode }, |
9436 | { Bad_Opcode }, | |
9437 | { Bad_Opcode }, | |
9438 | { Bad_Opcode }, | |
9439 | { Bad_Opcode }, | |
9440 | { Bad_Opcode }, | |
9441 | { Bad_Opcode }, | |
9442 | { Bad_Opcode }, | |
c0f3af97 | 9443 | /* b8 */ |
592d1631 L |
9444 | { Bad_Opcode }, |
9445 | { Bad_Opcode }, | |
9446 | { Bad_Opcode }, | |
9447 | { Bad_Opcode }, | |
9448 | { Bad_Opcode }, | |
9449 | { Bad_Opcode }, | |
9450 | { Bad_Opcode }, | |
9451 | { Bad_Opcode }, | |
c0f3af97 | 9452 | /* c0 */ |
592d1631 L |
9453 | { Bad_Opcode }, |
9454 | { Bad_Opcode }, | |
9455 | { Bad_Opcode }, | |
9456 | { Bad_Opcode }, | |
9457 | { Bad_Opcode }, | |
9458 | { Bad_Opcode }, | |
9459 | { Bad_Opcode }, | |
9460 | { Bad_Opcode }, | |
c0f3af97 | 9461 | /* c8 */ |
592d1631 L |
9462 | { Bad_Opcode }, |
9463 | { Bad_Opcode }, | |
9464 | { Bad_Opcode }, | |
9465 | { Bad_Opcode }, | |
9466 | { Bad_Opcode }, | |
9467 | { Bad_Opcode }, | |
48521003 IT |
9468 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9469 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9470 | /* d0 */ |
592d1631 L |
9471 | { Bad_Opcode }, |
9472 | { Bad_Opcode }, | |
9473 | { Bad_Opcode }, | |
9474 | { Bad_Opcode }, | |
9475 | { Bad_Opcode }, | |
9476 | { Bad_Opcode }, | |
9477 | { Bad_Opcode }, | |
9478 | { Bad_Opcode }, | |
c0f3af97 | 9479 | /* d8 */ |
592d1631 L |
9480 | { Bad_Opcode }, |
9481 | { Bad_Opcode }, | |
9482 | { Bad_Opcode }, | |
9483 | { Bad_Opcode }, | |
9484 | { Bad_Opcode }, | |
9485 | { Bad_Opcode }, | |
9486 | { Bad_Opcode }, | |
592a252b | 9487 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9488 | /* e0 */ |
592d1631 L |
9489 | { Bad_Opcode }, |
9490 | { Bad_Opcode }, | |
9491 | { Bad_Opcode }, | |
9492 | { Bad_Opcode }, | |
9493 | { Bad_Opcode }, | |
9494 | { Bad_Opcode }, | |
9495 | { Bad_Opcode }, | |
9496 | { Bad_Opcode }, | |
c0f3af97 | 9497 | /* e8 */ |
592d1631 L |
9498 | { Bad_Opcode }, |
9499 | { Bad_Opcode }, | |
9500 | { Bad_Opcode }, | |
9501 | { Bad_Opcode }, | |
9502 | { Bad_Opcode }, | |
9503 | { Bad_Opcode }, | |
9504 | { Bad_Opcode }, | |
9505 | { Bad_Opcode }, | |
c0f3af97 | 9506 | /* f0 */ |
6c30d220 | 9507 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9508 | { Bad_Opcode }, |
9509 | { Bad_Opcode }, | |
9510 | { Bad_Opcode }, | |
9511 | { Bad_Opcode }, | |
9512 | { Bad_Opcode }, | |
9513 | { Bad_Opcode }, | |
9514 | { Bad_Opcode }, | |
c0f3af97 | 9515 | /* f8 */ |
592d1631 L |
9516 | { Bad_Opcode }, |
9517 | { Bad_Opcode }, | |
9518 | { Bad_Opcode }, | |
9519 | { Bad_Opcode }, | |
9520 | { Bad_Opcode }, | |
9521 | { Bad_Opcode }, | |
9522 | { Bad_Opcode }, | |
9523 | { Bad_Opcode }, | |
c0f3af97 L |
9524 | }, |
9525 | }; | |
9526 | ||
43234a1e L |
9527 | #define NEED_OPCODE_TABLE |
9528 | #include "i386-dis-evex.h" | |
9529 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9530 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9531 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9532 | { |
592a252b L |
9533 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9534 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9535 | }, |
9536 | ||
592a252b | 9537 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9538 | { |
592a252b L |
9539 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9540 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9541 | }, |
9542 | ||
592a252b | 9543 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9544 | { |
592a252b L |
9545 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9546 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9547 | }, |
9548 | ||
592a252b | 9549 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9550 | { |
592a252b L |
9551 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9552 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9553 | }, |
9554 | ||
592a252b | 9555 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9556 | { |
592a252b | 9557 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9558 | }, |
9559 | ||
592a252b | 9560 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9561 | { |
592a252b | 9562 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9563 | }, |
9564 | ||
592a252b | 9565 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9566 | { |
592a252b | 9567 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9568 | }, |
9569 | ||
592a252b | 9570 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9571 | { |
592a252b | 9572 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9573 | }, |
9574 | ||
592a252b | 9575 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9576 | { |
592a252b | 9577 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9578 | }, |
9579 | ||
592a252b | 9580 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9581 | { |
592a252b | 9582 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9583 | }, |
9584 | ||
592a252b | 9585 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9586 | { |
592a252b | 9587 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9588 | }, |
9589 | ||
592a252b | 9590 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9591 | { |
592a252b | 9592 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9593 | }, |
9594 | ||
592a252b | 9595 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9596 | { |
bf890a93 IT |
9597 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9598 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9599 | }, |
9600 | ||
592a252b | 9601 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9602 | { |
bf890a93 IT |
9603 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9604 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9605 | }, |
9606 | ||
592a252b | 9607 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9608 | { |
9646c87b JB |
9609 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, |
9610 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9611 | }, |
9612 | ||
592a252b | 9613 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9614 | { |
9646c87b JB |
9615 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, |
9616 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9617 | }, |
9618 | ||
592a252b | 9619 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9620 | { |
9646c87b JB |
9621 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, |
9622 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9623 | }, |
9624 | ||
592a252b | 9625 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9626 | { |
9646c87b JB |
9627 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, |
9628 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9629 | }, |
9630 | ||
592a252b | 9631 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9632 | { |
592a252b L |
9633 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9634 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9635 | }, |
9636 | ||
592a252b | 9637 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9638 | { |
592a252b L |
9639 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9640 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9641 | }, |
9642 | ||
592a252b | 9643 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9644 | { |
592a252b L |
9645 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9646 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9647 | }, |
9648 | ||
592a252b | 9649 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9650 | { |
592a252b L |
9651 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9652 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9653 | }, |
9654 | ||
43234a1e L |
9655 | /* VEX_LEN_0F41_P_0 */ |
9656 | { | |
9657 | { Bad_Opcode }, | |
9658 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9659 | }, | |
1ba585e8 IT |
9660 | /* VEX_LEN_0F41_P_2 */ |
9661 | { | |
9662 | { Bad_Opcode }, | |
9663 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9664 | }, | |
43234a1e L |
9665 | /* VEX_LEN_0F42_P_0 */ |
9666 | { | |
9667 | { Bad_Opcode }, | |
9668 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9669 | }, | |
1ba585e8 IT |
9670 | /* VEX_LEN_0F42_P_2 */ |
9671 | { | |
9672 | { Bad_Opcode }, | |
9673 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9674 | }, | |
43234a1e L |
9675 | /* VEX_LEN_0F44_P_0 */ |
9676 | { | |
9677 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9678 | }, | |
1ba585e8 IT |
9679 | /* VEX_LEN_0F44_P_2 */ |
9680 | { | |
9681 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9682 | }, | |
43234a1e L |
9683 | /* VEX_LEN_0F45_P_0 */ |
9684 | { | |
9685 | { Bad_Opcode }, | |
9686 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9687 | }, | |
1ba585e8 IT |
9688 | /* VEX_LEN_0F45_P_2 */ |
9689 | { | |
9690 | { Bad_Opcode }, | |
9691 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9692 | }, | |
43234a1e L |
9693 | /* VEX_LEN_0F46_P_0 */ |
9694 | { | |
9695 | { Bad_Opcode }, | |
9696 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9697 | }, | |
1ba585e8 IT |
9698 | /* VEX_LEN_0F46_P_2 */ |
9699 | { | |
9700 | { Bad_Opcode }, | |
9701 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9702 | }, | |
43234a1e L |
9703 | /* VEX_LEN_0F47_P_0 */ |
9704 | { | |
9705 | { Bad_Opcode }, | |
9706 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9707 | }, | |
1ba585e8 IT |
9708 | /* VEX_LEN_0F47_P_2 */ |
9709 | { | |
9710 | { Bad_Opcode }, | |
9711 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9712 | }, | |
9713 | /* VEX_LEN_0F4A_P_0 */ | |
9714 | { | |
9715 | { Bad_Opcode }, | |
9716 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9717 | }, | |
9718 | /* VEX_LEN_0F4A_P_2 */ | |
9719 | { | |
9720 | { Bad_Opcode }, | |
9721 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9722 | }, | |
9723 | /* VEX_LEN_0F4B_P_0 */ | |
9724 | { | |
9725 | { Bad_Opcode }, | |
9726 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9727 | }, | |
43234a1e L |
9728 | /* VEX_LEN_0F4B_P_2 */ |
9729 | { | |
9730 | { Bad_Opcode }, | |
9731 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9732 | }, | |
9733 | ||
592a252b | 9734 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9735 | { |
592a252b L |
9736 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9737 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9738 | }, |
9739 | ||
592a252b | 9740 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9741 | { |
592a252b L |
9742 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9743 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9744 | }, |
9745 | ||
592a252b | 9746 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9747 | { |
592a252b L |
9748 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9749 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9750 | }, |
9751 | ||
592a252b | 9752 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9753 | { |
592a252b L |
9754 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9755 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9756 | }, |
9757 | ||
592a252b | 9758 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9759 | { |
592a252b L |
9760 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9761 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9762 | }, |
9763 | ||
592a252b | 9764 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9765 | { |
592a252b L |
9766 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9767 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9768 | }, |
9769 | ||
592a252b | 9770 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9771 | { |
592a252b L |
9772 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9773 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9774 | }, |
9775 | ||
592a252b | 9776 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9777 | { |
592a252b L |
9778 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9779 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9780 | }, |
9781 | ||
592a252b | 9782 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9783 | { |
592a252b L |
9784 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9785 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9786 | }, |
9787 | ||
592a252b | 9788 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9789 | { |
592a252b L |
9790 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9791 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9792 | }, |
9793 | ||
592a252b | 9794 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9795 | { |
592a252b L |
9796 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9797 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9798 | }, |
9799 | ||
592a252b | 9800 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9801 | { |
592a252b L |
9802 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9803 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9804 | }, |
9805 | ||
592a252b | 9806 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9807 | { |
592a252b L |
9808 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9809 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9810 | }, |
9811 | ||
592a252b | 9812 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9813 | { |
592a252b L |
9814 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9815 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9816 | }, |
9817 | ||
592a252b | 9818 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9819 | { |
592a252b L |
9820 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9821 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9822 | }, |
9823 | ||
592a252b | 9824 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9825 | { |
592a252b L |
9826 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9827 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9828 | }, |
9829 | ||
592a252b | 9830 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9831 | { |
592a252b L |
9832 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9833 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9834 | }, |
9835 | ||
592a252b | 9836 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9837 | { |
592a252b L |
9838 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9839 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9840 | }, |
9841 | ||
592a252b | 9842 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9843 | { |
bf890a93 IT |
9844 | { "vmovK", { XMScalar, Edq }, 0 }, |
9845 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9846 | }, |
9847 | ||
592a252b | 9848 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9849 | { |
592a252b | 9850 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
c0f3af97 L |
9851 | }, |
9852 | ||
592a252b | 9853 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9854 | { |
bf890a93 IT |
9855 | { "vmovK", { Edq, XMScalar }, 0 }, |
9856 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9857 | }, |
9858 | ||
43234a1e L |
9859 | /* VEX_LEN_0F90_P_0 */ |
9860 | { | |
9861 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9862 | }, | |
9863 | ||
1ba585e8 IT |
9864 | /* VEX_LEN_0F90_P_2 */ |
9865 | { | |
9866 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9867 | }, | |
9868 | ||
43234a1e L |
9869 | /* VEX_LEN_0F91_P_0 */ |
9870 | { | |
9871 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9872 | }, | |
9873 | ||
1ba585e8 IT |
9874 | /* VEX_LEN_0F91_P_2 */ |
9875 | { | |
9876 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9877 | }, | |
9878 | ||
43234a1e L |
9879 | /* VEX_LEN_0F92_P_0 */ |
9880 | { | |
9881 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9882 | }, | |
9883 | ||
90a915bf IT |
9884 | /* VEX_LEN_0F92_P_2 */ |
9885 | { | |
9886 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9887 | }, | |
9888 | ||
1ba585e8 IT |
9889 | /* VEX_LEN_0F92_P_3 */ |
9890 | { | |
9891 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9892 | }, | |
9893 | ||
43234a1e L |
9894 | /* VEX_LEN_0F93_P_0 */ |
9895 | { | |
9896 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9897 | }, | |
9898 | ||
90a915bf IT |
9899 | /* VEX_LEN_0F93_P_2 */ |
9900 | { | |
9901 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9902 | }, | |
9903 | ||
1ba585e8 IT |
9904 | /* VEX_LEN_0F93_P_3 */ |
9905 | { | |
9906 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9907 | }, | |
9908 | ||
43234a1e L |
9909 | /* VEX_LEN_0F98_P_0 */ |
9910 | { | |
9911 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9912 | }, | |
9913 | ||
1ba585e8 IT |
9914 | /* VEX_LEN_0F98_P_2 */ |
9915 | { | |
9916 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9917 | }, | |
9918 | ||
9919 | /* VEX_LEN_0F99_P_0 */ | |
9920 | { | |
9921 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9922 | }, | |
9923 | ||
9924 | /* VEX_LEN_0F99_P_2 */ | |
9925 | { | |
9926 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9927 | }, | |
9928 | ||
6c30d220 | 9929 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9930 | { |
6c30d220 | 9931 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9932 | }, |
9933 | ||
6c30d220 | 9934 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9935 | { |
6c30d220 | 9936 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9937 | }, |
9938 | ||
6c30d220 | 9939 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9940 | { |
6c30d220 L |
9941 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9942 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9943 | }, |
9944 | ||
6c30d220 | 9945 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9946 | { |
6c30d220 L |
9947 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9948 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9949 | }, |
9950 | ||
6c30d220 | 9951 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9952 | { |
6c30d220 | 9953 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9954 | }, |
9955 | ||
6c30d220 | 9956 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9957 | { |
6c30d220 | 9958 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9959 | }, |
9960 | ||
6c30d220 | 9961 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9962 | { |
6c30d220 | 9963 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
c0f3af97 L |
9964 | }, |
9965 | ||
6c30d220 | 9966 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9967 | { |
6c30d220 | 9968 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9969 | }, |
9970 | ||
6c30d220 | 9971 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9972 | { |
6c30d220 L |
9973 | { Bad_Opcode }, |
9974 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9975 | }, |
9976 | ||
6c30d220 | 9977 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9978 | { |
6c30d220 L |
9979 | { Bad_Opcode }, |
9980 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9981 | }, |
9982 | ||
6c30d220 | 9983 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9984 | { |
6c30d220 L |
9985 | { Bad_Opcode }, |
9986 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9987 | }, |
9988 | ||
6c30d220 | 9989 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9990 | { |
6c30d220 L |
9991 | { Bad_Opcode }, |
9992 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9993 | }, |
9994 | ||
592a252b | 9995 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9996 | { |
592a252b | 9997 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9998 | }, |
9999 | ||
6c30d220 L |
10000 | /* VEX_LEN_0F385A_P_2_M_0 */ |
10001 | { | |
10002 | { Bad_Opcode }, | |
10003 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
10004 | }, | |
10005 | ||
592a252b | 10006 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 10007 | { |
592a252b | 10008 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
10009 | }, |
10010 | ||
f12dc422 L |
10011 | /* VEX_LEN_0F38F2_P_0 */ |
10012 | { | |
bf890a93 | 10013 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
10014 | }, |
10015 | ||
10016 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
10017 | { | |
bf890a93 | 10018 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10019 | }, |
10020 | ||
10021 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
10022 | { | |
bf890a93 | 10023 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10024 | }, |
10025 | ||
10026 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
10027 | { | |
bf890a93 | 10028 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10029 | }, |
10030 | ||
6c30d220 L |
10031 | /* VEX_LEN_0F38F5_P_0 */ |
10032 | { | |
bf890a93 | 10033 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10034 | }, |
10035 | ||
10036 | /* VEX_LEN_0F38F5_P_1 */ | |
10037 | { | |
bf890a93 | 10038 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10039 | }, |
10040 | ||
10041 | /* VEX_LEN_0F38F5_P_3 */ | |
10042 | { | |
bf890a93 | 10043 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10044 | }, |
10045 | ||
10046 | /* VEX_LEN_0F38F6_P_3 */ | |
10047 | { | |
bf890a93 | 10048 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10049 | }, |
10050 | ||
f12dc422 L |
10051 | /* VEX_LEN_0F38F7_P_0 */ |
10052 | { | |
bf890a93 | 10053 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
10054 | }, |
10055 | ||
6c30d220 L |
10056 | /* VEX_LEN_0F38F7_P_1 */ |
10057 | { | |
bf890a93 | 10058 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10059 | }, |
10060 | ||
10061 | /* VEX_LEN_0F38F7_P_2 */ | |
10062 | { | |
bf890a93 | 10063 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10064 | }, |
10065 | ||
10066 | /* VEX_LEN_0F38F7_P_3 */ | |
10067 | { | |
bf890a93 | 10068 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10069 | }, |
10070 | ||
10071 | /* VEX_LEN_0F3A00_P_2 */ | |
10072 | { | |
10073 | { Bad_Opcode }, | |
10074 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10075 | }, | |
10076 | ||
10077 | /* VEX_LEN_0F3A01_P_2 */ | |
10078 | { | |
10079 | { Bad_Opcode }, | |
10080 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10081 | }, | |
10082 | ||
592a252b | 10083 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10084 | { |
592d1631 | 10085 | { Bad_Opcode }, |
592a252b | 10086 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10087 | }, |
10088 | ||
592a252b | 10089 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10090 | { |
592a252b L |
10091 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10092 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10093 | }, |
10094 | ||
592a252b | 10095 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10096 | { |
592a252b L |
10097 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10098 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10099 | }, |
10100 | ||
592a252b | 10101 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10102 | { |
592a252b | 10103 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10104 | }, |
10105 | ||
592a252b | 10106 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10107 | { |
592a252b | 10108 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10109 | }, |
10110 | ||
592a252b | 10111 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 10112 | { |
bf890a93 | 10113 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
10114 | }, |
10115 | ||
592a252b | 10116 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 10117 | { |
bf890a93 | 10118 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
10119 | }, |
10120 | ||
592a252b | 10121 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10122 | { |
592d1631 | 10123 | { Bad_Opcode }, |
592a252b | 10124 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10125 | }, |
10126 | ||
592a252b | 10127 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10128 | { |
592d1631 | 10129 | { Bad_Opcode }, |
592a252b | 10130 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10131 | }, |
10132 | ||
592a252b | 10133 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10134 | { |
592a252b | 10135 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10136 | }, |
10137 | ||
592a252b | 10138 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10139 | { |
592a252b | 10140 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10141 | }, |
10142 | ||
592a252b | 10143 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10144 | { |
bf890a93 | 10145 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10146 | }, |
10147 | ||
43234a1e L |
10148 | /* VEX_LEN_0F3A30_P_2 */ |
10149 | { | |
10150 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10151 | }, | |
10152 | ||
1ba585e8 IT |
10153 | /* VEX_LEN_0F3A31_P_2 */ |
10154 | { | |
10155 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10156 | }, | |
10157 | ||
43234a1e L |
10158 | /* VEX_LEN_0F3A32_P_2 */ |
10159 | { | |
10160 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10161 | }, | |
10162 | ||
1ba585e8 IT |
10163 | /* VEX_LEN_0F3A33_P_2 */ |
10164 | { | |
10165 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10166 | }, | |
10167 | ||
6c30d220 | 10168 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10169 | { |
6c30d220 L |
10170 | { Bad_Opcode }, |
10171 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10172 | }, |
10173 | ||
6c30d220 | 10174 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10175 | { |
6c30d220 L |
10176 | { Bad_Opcode }, |
10177 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10178 | }, | |
10179 | ||
10180 | /* VEX_LEN_0F3A41_P_2 */ | |
10181 | { | |
10182 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10183 | }, |
10184 | ||
6c30d220 | 10185 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10186 | { |
6c30d220 L |
10187 | { Bad_Opcode }, |
10188 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10189 | }, |
10190 | ||
592a252b | 10191 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10192 | { |
15c7c1d8 | 10193 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10194 | }, |
10195 | ||
592a252b | 10196 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10197 | { |
15c7c1d8 | 10198 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10199 | }, |
10200 | ||
592a252b | 10201 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10202 | { |
592a252b | 10203 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10204 | }, |
10205 | ||
592a252b | 10206 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10207 | { |
592a252b | 10208 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10209 | }, |
10210 | ||
592a252b | 10211 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10212 | { |
3a2430e0 | 10213 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10214 | }, |
10215 | ||
592a252b | 10216 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10217 | { |
3a2430e0 | 10218 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10219 | }, |
10220 | ||
592a252b | 10221 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10222 | { |
3a2430e0 | 10223 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10224 | }, |
10225 | ||
592a252b | 10226 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10227 | { |
3a2430e0 | 10228 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10229 | }, |
10230 | ||
592a252b | 10231 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10232 | { |
3a2430e0 | 10233 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10234 | }, |
10235 | ||
592a252b | 10236 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10237 | { |
3a2430e0 | 10238 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10239 | }, |
10240 | ||
592a252b | 10241 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10242 | { |
3a2430e0 | 10243 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10244 | }, |
10245 | ||
592a252b | 10246 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10247 | { |
3a2430e0 | 10248 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10249 | }, |
10250 | ||
592a252b | 10251 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10252 | { |
592a252b | 10253 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10254 | }, |
4c807e72 | 10255 | |
6c30d220 L |
10256 | /* VEX_LEN_0F3AF0_P_3 */ |
10257 | { | |
bf890a93 | 10258 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10259 | }, |
10260 | ||
ff688e1f L |
10261 | /* VEX_LEN_0FXOP_08_CC */ |
10262 | { | |
be92cb14 | 10263 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10264 | }, |
10265 | ||
10266 | /* VEX_LEN_0FXOP_08_CD */ | |
10267 | { | |
be92cb14 | 10268 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10269 | }, |
10270 | ||
10271 | /* VEX_LEN_0FXOP_08_CE */ | |
10272 | { | |
be92cb14 | 10273 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10274 | }, |
10275 | ||
10276 | /* VEX_LEN_0FXOP_08_CF */ | |
10277 | { | |
be92cb14 | 10278 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10279 | }, |
10280 | ||
10281 | /* VEX_LEN_0FXOP_08_EC */ | |
10282 | { | |
be92cb14 | 10283 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10284 | }, |
10285 | ||
10286 | /* VEX_LEN_0FXOP_08_ED */ | |
10287 | { | |
be92cb14 | 10288 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10289 | }, |
10290 | ||
10291 | /* VEX_LEN_0FXOP_08_EE */ | |
10292 | { | |
be92cb14 | 10293 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10294 | }, |
10295 | ||
10296 | /* VEX_LEN_0FXOP_08_EF */ | |
10297 | { | |
be92cb14 | 10298 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10299 | }, |
10300 | ||
592a252b | 10301 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10302 | { |
bf890a93 IT |
10303 | { "vfrczps", { XM, EXxmm }, 0 }, |
10304 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10305 | }, |
4c807e72 | 10306 | |
592a252b | 10307 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10308 | { |
bf890a93 IT |
10309 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10310 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10311 | }, |
331d2d0d L |
10312 | }; |
10313 | ||
9e30b8e0 | 10314 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10315 | { |
592a252b | 10316 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10317 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10318 | }, |
10319 | { | |
592a252b | 10320 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10321 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10322 | }, |
10323 | { | |
592a252b | 10324 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10325 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10326 | }, |
10327 | { | |
592a252b | 10328 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10329 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10330 | }, |
10331 | { | |
592a252b | 10332 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10333 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10334 | }, |
10335 | { | |
592a252b | 10336 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10337 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10338 | }, |
10339 | { | |
592a252b | 10340 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10341 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10342 | }, |
10343 | { | |
592a252b | 10344 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10345 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10346 | }, |
10347 | { | |
592a252b | 10348 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10349 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10350 | }, |
10351 | { | |
592a252b | 10352 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10353 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10354 | }, |
10355 | { | |
592a252b | 10356 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10357 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10358 | }, |
10359 | { | |
592a252b | 10360 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10361 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10362 | }, |
10363 | { | |
592a252b | 10364 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10365 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10366 | }, |
10367 | { | |
592a252b | 10368 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10369 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10370 | }, |
10371 | { | |
592a252b | 10372 | /* VEX_W_0F14 */ |
bf890a93 | 10373 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10374 | }, |
10375 | { | |
592a252b | 10376 | /* VEX_W_0F15 */ |
bf890a93 | 10377 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10378 | }, |
10379 | { | |
592a252b | 10380 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10381 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10382 | }, |
10383 | { | |
592a252b | 10384 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10385 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10386 | }, |
10387 | { | |
592a252b | 10388 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10389 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10390 | }, |
10391 | { | |
592a252b | 10392 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10393 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10394 | }, |
10395 | { | |
592a252b | 10396 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10397 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10398 | }, |
10399 | { | |
592a252b | 10400 | /* VEX_W_0F28 */ |
bf890a93 | 10401 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10402 | }, |
10403 | { | |
592a252b | 10404 | /* VEX_W_0F29 */ |
bf890a93 | 10405 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10406 | }, |
10407 | { | |
592a252b | 10408 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10409 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10410 | }, |
10411 | { | |
592a252b | 10412 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10413 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10414 | }, |
10415 | { | |
592a252b | 10416 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10417 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10418 | }, |
10419 | { | |
592a252b | 10420 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10421 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10422 | }, |
10423 | { | |
592a252b | 10424 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10425 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10426 | }, |
43234a1e L |
10427 | { |
10428 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10429 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10430 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10431 | }, |
10432 | { | |
10433 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10434 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10435 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10436 | }, |
10437 | { | |
10438 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10439 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10440 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10441 | }, |
10442 | { | |
10443 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10444 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10445 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10446 | }, |
10447 | { | |
10448 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10449 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10450 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10451 | }, |
10452 | { | |
10453 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10454 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10455 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10456 | }, |
10457 | { | |
10458 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10459 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10460 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10461 | }, |
10462 | { | |
10463 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10464 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10465 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10466 | }, |
10467 | { | |
10468 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10469 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10470 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10471 | }, |
10472 | { | |
10473 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10474 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10475 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10476 | }, |
10477 | { | |
10478 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10479 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10480 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10481 | }, |
10482 | { | |
10483 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10484 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10485 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10486 | }, |
10487 | { | |
10488 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10489 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10490 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10491 | }, |
10492 | { | |
10493 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10494 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10495 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10496 | }, |
10497 | { | |
10498 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10499 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10500 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10501 | }, |
10502 | { | |
10503 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10504 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10505 | }, |
9e30b8e0 | 10506 | { |
592a252b | 10507 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10508 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10509 | }, |
10510 | { | |
592a252b | 10511 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10512 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10513 | }, |
10514 | { | |
592a252b | 10515 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10516 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10517 | }, |
10518 | { | |
592a252b | 10519 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10520 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10521 | }, |
10522 | { | |
592a252b | 10523 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10524 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10525 | }, |
10526 | { | |
592a252b | 10527 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10528 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10529 | }, |
10530 | { | |
592a252b | 10531 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10532 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10533 | }, |
10534 | { | |
592a252b | 10535 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10536 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10537 | }, |
10538 | { | |
592a252b | 10539 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10540 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10541 | }, |
10542 | { | |
592a252b | 10543 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10544 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10545 | }, |
10546 | { | |
592a252b | 10547 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10548 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10549 | }, |
10550 | { | |
592a252b | 10551 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10552 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10553 | }, |
10554 | { | |
592a252b | 10555 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10556 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10557 | }, |
10558 | { | |
592a252b | 10559 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10560 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10561 | }, |
10562 | { | |
592a252b | 10563 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10564 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10565 | }, |
10566 | { | |
592a252b | 10567 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10568 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10569 | }, |
10570 | { | |
592a252b | 10571 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10572 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10573 | }, |
10574 | { | |
592a252b | 10575 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10576 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10577 | }, |
10578 | { | |
592a252b | 10579 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10580 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10581 | }, |
10582 | { | |
592a252b | 10583 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10584 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10585 | }, |
10586 | { | |
592a252b | 10587 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10588 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10589 | }, |
10590 | { | |
592a252b | 10591 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10592 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10593 | }, |
10594 | { | |
592a252b | 10595 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10596 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10597 | }, |
10598 | { | |
592a252b | 10599 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10600 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10601 | }, |
10602 | { | |
592a252b | 10603 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10604 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10605 | }, |
10606 | { | |
592a252b | 10607 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10608 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10609 | }, |
10610 | { | |
592a252b | 10611 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10612 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10613 | }, |
10614 | { | |
592a252b | 10615 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10616 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10617 | }, |
10618 | { | |
592a252b | 10619 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10620 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10621 | }, |
10622 | { | |
592a252b | 10623 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10624 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10625 | }, |
10626 | { | |
592a252b | 10627 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10628 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10629 | }, |
10630 | { | |
592a252b | 10631 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10632 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10633 | }, |
10634 | { | |
592a252b | 10635 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10636 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10637 | }, |
10638 | { | |
592a252b | 10639 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10640 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10641 | }, |
10642 | { | |
592a252b | 10643 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10644 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10645 | }, |
10646 | { | |
592a252b | 10647 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10648 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10649 | }, |
10650 | { | |
592a252b | 10651 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10652 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10653 | }, |
10654 | { | |
592a252b | 10655 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10656 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10657 | }, |
10658 | { | |
592a252b | 10659 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10660 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10661 | }, |
10662 | { | |
592a252b | 10663 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10664 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10665 | }, |
10666 | { | |
592a252b | 10667 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10668 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10669 | }, |
10670 | { | |
592a252b | 10671 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10672 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10673 | }, |
10674 | { | |
592a252b | 10675 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10676 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10677 | }, |
10678 | { | |
592a252b | 10679 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10680 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10681 | }, |
10682 | { | |
592a252b | 10683 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10684 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10685 | }, |
10686 | { | |
592a252b | 10687 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10688 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10689 | }, |
10690 | { | |
592a252b | 10691 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10692 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10693 | }, |
10694 | { | |
592a252b | 10695 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10696 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10697 | }, |
10698 | { | |
592a252b | 10699 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10700 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10701 | }, |
10702 | { | |
592a252b | 10703 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10704 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10705 | }, |
10706 | { | |
592a252b | 10707 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10708 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10709 | }, |
10710 | { | |
592a252b | 10711 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10712 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10713 | }, |
10714 | { | |
592a252b | 10715 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10716 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10717 | }, |
10718 | { | |
592a252b | 10719 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10720 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10721 | }, |
10722 | { | |
592a252b | 10723 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10724 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10725 | }, |
10726 | { | |
592a252b | 10727 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10728 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10729 | }, |
10730 | { | |
592a252b | 10731 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10732 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10733 | }, |
10734 | { | |
592a252b | 10735 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10736 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10737 | }, |
10738 | { | |
592a252b | 10739 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10740 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10741 | }, |
10742 | { | |
592a252b | 10743 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10744 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10745 | }, |
10746 | { | |
592a252b | 10747 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10748 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10749 | }, |
10750 | { | |
592a252b | 10751 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10752 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10753 | }, |
10754 | { | |
592a252b | 10755 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10756 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10757 | }, |
10758 | { | |
592a252b | 10759 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10760 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10761 | }, |
10762 | { | |
592a252b | 10763 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10764 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10765 | }, |
10766 | { | |
592a252b | 10767 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10768 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10769 | }, |
10770 | { | |
592a252b | 10771 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10772 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10773 | }, |
10774 | { | |
592a252b | 10775 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10776 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10777 | }, |
10778 | { | |
592a252b | 10779 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10780 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10781 | }, |
10782 | { | |
592a252b | 10783 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10784 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10785 | }, |
10786 | { | |
592a252b | 10787 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10788 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10789 | }, |
10790 | { | |
592a252b | 10791 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10792 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10793 | }, |
10794 | { | |
592a252b | 10795 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10796 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10797 | }, |
10798 | { | |
592a252b | 10799 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10800 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10801 | }, |
10802 | { | |
592a252b | 10803 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10804 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10805 | }, |
10806 | { | |
592a252b | 10807 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10808 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10809 | }, |
10810 | { | |
592a252b | 10811 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10812 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10813 | }, |
10814 | { | |
592a252b | 10815 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10816 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10817 | }, |
10818 | { | |
592a252b | 10819 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10820 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10821 | }, |
43234a1e L |
10822 | { |
10823 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10824 | { "kmovw", { MaskG, MaskE }, 0 }, |
10825 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10826 | }, |
10827 | { | |
10828 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10829 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10830 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10831 | }, |
10832 | { | |
10833 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10834 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10835 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10836 | }, |
10837 | { | |
10838 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10839 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10840 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10841 | }, |
10842 | { | |
10843 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10844 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10845 | }, |
90a915bf IT |
10846 | { |
10847 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10848 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10849 | }, |
1ba585e8 IT |
10850 | { |
10851 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10852 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10853 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10854 | }, |
43234a1e L |
10855 | { |
10856 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10857 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10858 | }, |
90a915bf IT |
10859 | { |
10860 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10861 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10862 | }, |
1ba585e8 IT |
10863 | { |
10864 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10865 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10866 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10867 | }, |
43234a1e L |
10868 | { |
10869 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10870 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10871 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10872 | }, |
10873 | { | |
10874 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10875 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10876 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10877 | }, |
10878 | { | |
10879 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10880 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10881 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10882 | }, |
10883 | { | |
10884 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10885 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10886 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10887 | }, |
9e30b8e0 | 10888 | { |
592a252b | 10889 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10890 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10891 | }, |
10892 | { | |
592a252b | 10893 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10894 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10895 | }, |
10896 | { | |
592a252b | 10897 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10898 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10899 | }, |
10900 | { | |
592a252b | 10901 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10902 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10903 | }, |
10904 | { | |
592a252b | 10905 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10906 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10907 | }, |
10908 | { | |
592a252b | 10909 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10910 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10911 | }, |
10912 | { | |
592a252b | 10913 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 10914 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
10915 | }, |
10916 | { | |
592a252b | 10917 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 10918 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
10919 | }, |
10920 | { | |
592a252b | 10921 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 10922 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10923 | }, |
10924 | { | |
592a252b | 10925 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 10926 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10927 | }, |
10928 | { | |
592a252b | 10929 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 10930 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10931 | }, |
10932 | { | |
592a252b | 10933 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 10934 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10935 | }, |
10936 | { | |
592a252b | 10937 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 10938 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10939 | }, |
10940 | { | |
592a252b | 10941 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 10942 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10943 | }, |
10944 | { | |
592a252b | 10945 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 10946 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10947 | }, |
10948 | { | |
592a252b | 10949 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 10950 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
10951 | }, |
10952 | { | |
592a252b | 10953 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 10954 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10955 | }, |
10956 | { | |
592a252b | 10957 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 10958 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10959 | }, |
10960 | { | |
592a252b | 10961 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 10962 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10963 | }, |
10964 | { | |
592a252b | 10965 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 10966 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10967 | }, |
10968 | { | |
592a252b | 10969 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 10970 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10971 | }, |
10972 | { | |
592a252b | 10973 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 10974 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10975 | }, |
10976 | { | |
592a252b | 10977 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 10978 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10979 | }, |
10980 | { | |
592a252b | 10981 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 10982 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10983 | }, |
10984 | { | |
592a252b | 10985 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 10986 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10987 | }, |
10988 | { | |
592a252b | 10989 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 10990 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10991 | }, |
10992 | { | |
592a252b | 10993 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 10994 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10995 | }, |
10996 | { | |
592a252b | 10997 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 10998 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10999 | }, |
11000 | { | |
592a252b | 11001 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 11002 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11003 | }, |
11004 | { | |
592a252b | 11005 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 11006 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11007 | }, |
11008 | { | |
592a252b | 11009 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 11010 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11011 | }, |
11012 | { | |
592a252b | 11013 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 11014 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11015 | }, |
11016 | { | |
592a252b | 11017 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 11018 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11019 | }, |
11020 | { | |
592a252b | 11021 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 11022 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11023 | }, |
11024 | { | |
592a252b | 11025 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 11026 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
11027 | }, |
11028 | { | |
592a252b | 11029 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 11030 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11031 | }, |
11032 | { | |
592a252b | 11033 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 11034 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11035 | }, |
11036 | { | |
592a252b | 11037 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 11038 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11039 | }, |
11040 | { | |
592a252b | 11041 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 11042 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11043 | }, |
11044 | { | |
592a252b | 11045 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 11046 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11047 | }, |
11048 | { | |
592a252b | 11049 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 11050 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11051 | }, |
11052 | { | |
592a252b | 11053 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 11054 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11055 | }, |
11056 | { | |
592a252b | 11057 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 11058 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11059 | }, |
11060 | { | |
592a252b | 11061 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 11062 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
11063 | }, |
11064 | { | |
592a252b | 11065 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 11066 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11067 | }, |
11068 | { | |
592a252b | 11069 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 11070 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11071 | }, |
11072 | { | |
592a252b | 11073 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 11074 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11075 | }, |
11076 | { | |
592a252b | 11077 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 11078 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11079 | }, |
11080 | { | |
592a252b | 11081 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 11082 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11083 | }, |
11084 | { | |
592a252b | 11085 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 11086 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11087 | }, |
11088 | { | |
592a252b | 11089 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 11090 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
11091 | }, |
11092 | { | |
592a252b | 11093 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 11094 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11095 | }, |
11096 | { | |
592a252b | 11097 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 11098 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11099 | }, |
11100 | { | |
592a252b | 11101 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 11102 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11103 | }, |
11104 | { | |
592a252b | 11105 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 11106 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11107 | }, |
11108 | { | |
592a252b | 11109 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 11110 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11111 | }, |
11112 | { | |
592a252b | 11113 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 11114 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11115 | }, |
11116 | { | |
592a252b | 11117 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 11118 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11119 | }, |
11120 | { | |
592a252b | 11121 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 11122 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11123 | }, |
11124 | { | |
592a252b | 11125 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11126 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11127 | }, |
11128 | { | |
592a252b | 11129 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11130 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11131 | }, |
11132 | { | |
592a252b | 11133 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11134 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11135 | }, |
11136 | { | |
592a252b | 11137 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11138 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11139 | }, |
11140 | { | |
592a252b | 11141 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11142 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11143 | }, |
11144 | { | |
592a252b | 11145 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11146 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11147 | }, |
11148 | { | |
592a252b | 11149 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11150 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11151 | }, |
11152 | { | |
592a252b | 11153 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11154 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11155 | }, |
11156 | { | |
592a252b | 11157 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11158 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11159 | }, |
11160 | { | |
592a252b | 11161 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11162 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11163 | }, |
11164 | { | |
592a252b | 11165 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11166 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11167 | }, |
11168 | { | |
592a252b | 11169 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11170 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11171 | }, |
11172 | { | |
592a252b | 11173 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11174 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11175 | }, |
11176 | { | |
592a252b | 11177 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11178 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11179 | }, |
11180 | { | |
592a252b | 11181 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11182 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11183 | }, |
6c30d220 L |
11184 | { |
11185 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11186 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11187 | }, |
9e30b8e0 | 11188 | { |
592a252b | 11189 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11190 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11191 | }, |
bcf2684f | 11192 | { |
6c30d220 | 11193 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11194 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11195 | }, |
9e30b8e0 | 11196 | { |
6c30d220 | 11197 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11198 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11199 | }, |
11200 | { | |
592a252b | 11201 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11202 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11203 | }, |
11204 | { | |
592a252b | 11205 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11206 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11207 | }, |
11208 | { | |
592a252b | 11209 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11210 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11211 | }, |
11212 | { | |
592a252b | 11213 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11214 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11215 | }, |
11216 | { | |
592a252b | 11217 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11218 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11219 | }, |
11220 | { | |
592a252b | 11221 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11222 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11223 | }, |
11224 | { | |
592a252b | 11225 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11226 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11227 | }, |
11228 | { | |
592a252b | 11229 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11230 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11231 | }, |
11232 | { | |
592a252b | 11233 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11234 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11235 | }, |
11236 | { | |
592a252b | 11237 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11238 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11239 | }, |
11240 | { | |
592a252b | 11241 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11242 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11243 | }, |
11244 | { | |
592a252b | 11245 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11246 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11247 | }, |
11248 | { | |
592a252b | 11249 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11250 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11251 | }, |
11252 | { | |
592a252b | 11253 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11254 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11255 | }, |
53aa04a0 | 11256 | { |
592a252b | 11257 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11258 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11259 | }, |
11260 | { | |
592a252b | 11261 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11262 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11263 | }, |
11264 | { | |
592a252b | 11265 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11266 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11267 | }, |
11268 | { | |
592a252b | 11269 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11270 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11271 | }, |
9e30b8e0 | 11272 | { |
592a252b | 11273 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11274 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11275 | }, |
11276 | { | |
592a252b | 11277 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11278 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11279 | }, |
11280 | { | |
592a252b | 11281 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11282 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11283 | }, |
11284 | { | |
592a252b | 11285 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11286 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11287 | }, |
11288 | { | |
592a252b | 11289 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11290 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11291 | }, |
11292 | { | |
592a252b | 11293 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11294 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11295 | }, |
11296 | { | |
11297 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11298 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11299 | }, |
11300 | { | |
592a252b | 11301 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11302 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11303 | }, |
11304 | { | |
592a252b | 11305 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11306 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11307 | }, |
11308 | { | |
592a252b | 11309 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11310 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11311 | }, |
11312 | { | |
592a252b | 11313 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11314 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11315 | }, |
11316 | { | |
592a252b | 11317 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11318 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11319 | }, |
11320 | { | |
592a252b | 11321 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11322 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11323 | }, |
11324 | { | |
592a252b | 11325 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11326 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11327 | }, |
11328 | { | |
592a252b | 11329 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11330 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11331 | }, |
11332 | { | |
592a252b | 11333 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11334 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11335 | }, |
11336 | { | |
592a252b | 11337 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11338 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11339 | }, |
11340 | { | |
592a252b | 11341 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11342 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11343 | }, |
6c30d220 L |
11344 | { |
11345 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11346 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11347 | }, |
11348 | { | |
11349 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11350 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11351 | }, |
11352 | { | |
11353 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11354 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11355 | }, |
11356 | { | |
11357 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11358 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11359 | }, |
11360 | { | |
11361 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11362 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11363 | }, |
11364 | { | |
11365 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11366 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11367 | }, |
48521003 IT |
11368 | { |
11369 | /* VEX_W_0F38CF_P_2 */ | |
11370 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
11371 | }, | |
9e30b8e0 | 11372 | { |
592a252b | 11373 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11374 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 | 11375 | }, |
6c30d220 L |
11376 | { |
11377 | /* VEX_W_0F3A00_P_2 */ | |
11378 | { Bad_Opcode }, | |
bf890a93 | 11379 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11380 | }, |
11381 | { | |
11382 | /* VEX_W_0F3A01_P_2 */ | |
11383 | { Bad_Opcode }, | |
bf890a93 | 11384 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11385 | }, |
11386 | { | |
11387 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11388 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11389 | }, |
9e30b8e0 | 11390 | { |
592a252b | 11391 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11392 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11393 | }, |
11394 | { | |
592a252b | 11395 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11396 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11397 | }, |
11398 | { | |
592a252b | 11399 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11400 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11401 | }, |
11402 | { | |
592a252b | 11403 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11404 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11405 | }, |
11406 | { | |
592a252b | 11407 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11408 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11409 | }, |
11410 | { | |
592a252b | 11411 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11412 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11413 | }, |
11414 | { | |
592a252b | 11415 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11416 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11417 | }, |
11418 | { | |
592a252b | 11419 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11420 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11421 | }, |
11422 | { | |
592a252b | 11423 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11424 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11425 | }, |
11426 | { | |
592a252b | 11427 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11428 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11429 | }, |
11430 | { | |
592a252b | 11431 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11432 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11433 | }, |
11434 | { | |
592a252b | 11435 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11436 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11437 | }, |
11438 | { | |
592a252b | 11439 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11440 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11441 | }, |
11442 | { | |
592a252b | 11443 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11444 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11445 | }, |
11446 | { | |
592a252b | 11447 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11448 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11449 | }, |
11450 | { | |
592a252b | 11451 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11452 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11453 | }, |
11454 | { | |
592a252b | 11455 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11456 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11457 | }, |
43234a1e | 11458 | { |
1ba585e8 | 11459 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11460 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11461 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11462 | }, |
11463 | { | |
1ba585e8 | 11464 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11465 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11466 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11467 | }, |
11468 | { | |
11469 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11470 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11471 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11472 | }, |
1ba585e8 IT |
11473 | { |
11474 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11475 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11476 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11477 | }, |
6c30d220 L |
11478 | { |
11479 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11480 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11481 | }, |
11482 | { | |
11483 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11484 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11485 | }, |
9e30b8e0 | 11486 | { |
592a252b | 11487 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11488 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11489 | }, |
11490 | { | |
592a252b | 11491 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11492 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11493 | }, |
11494 | { | |
592a252b | 11495 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11496 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 | 11497 | }, |
6c30d220 L |
11498 | { |
11499 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11500 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11501 | }, |
a683cc34 | 11502 | { |
592a252b | 11503 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11504 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11505 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11506 | }, |
11507 | { | |
592a252b | 11508 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11509 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11510 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11511 | }, |
9e30b8e0 | 11512 | { |
592a252b | 11513 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11514 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11515 | }, |
11516 | { | |
592a252b | 11517 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11518 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11519 | }, |
11520 | { | |
592a252b | 11521 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11522 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 11523 | }, |
9e30b8e0 | 11524 | { |
592a252b | 11525 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11526 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11527 | }, |
11528 | { | |
592a252b | 11529 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11530 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11531 | }, |
48521003 IT |
11532 | { |
11533 | /* VEX_W_0F3ACE_P_2 */ | |
11534 | { Bad_Opcode }, | |
11535 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
11536 | }, | |
11537 | { | |
11538 | /* VEX_W_0F3ACF_P_2 */ | |
11539 | { Bad_Opcode }, | |
11540 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
11541 | }, | |
9e30b8e0 | 11542 | { |
592a252b | 11543 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11544 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11545 | }, |
43234a1e L |
11546 | #define NEED_VEX_W_TABLE |
11547 | #include "i386-dis-evex.h" | |
11548 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11549 | }; |
11550 | ||
11551 | static const struct dis386 mod_table[][2] = { | |
11552 | { | |
11553 | /* MOD_8D */ | |
bf890a93 | 11554 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11555 | }, |
42164a71 L |
11556 | { |
11557 | /* MOD_C6_REG_7 */ | |
11558 | { Bad_Opcode }, | |
11559 | { RM_TABLE (RM_C6_REG_7) }, | |
11560 | }, | |
11561 | { | |
11562 | /* MOD_C7_REG_7 */ | |
11563 | { Bad_Opcode }, | |
11564 | { RM_TABLE (RM_C7_REG_7) }, | |
11565 | }, | |
4a357820 MZ |
11566 | { |
11567 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11568 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11569 | }, |
11570 | { | |
11571 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11572 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11573 | }, |
9e30b8e0 L |
11574 | { |
11575 | /* MOD_0F01_REG_0 */ | |
11576 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11577 | { RM_TABLE (RM_0F01_REG_0) }, | |
11578 | }, | |
11579 | { | |
11580 | /* MOD_0F01_REG_1 */ | |
11581 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11582 | { RM_TABLE (RM_0F01_REG_1) }, | |
11583 | }, | |
11584 | { | |
11585 | /* MOD_0F01_REG_2 */ | |
11586 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11587 | { RM_TABLE (RM_0F01_REG_2) }, | |
11588 | }, | |
11589 | { | |
11590 | /* MOD_0F01_REG_3 */ | |
11591 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11592 | { RM_TABLE (RM_0F01_REG_3) }, | |
11593 | }, | |
8eab4136 L |
11594 | { |
11595 | /* MOD_0F01_REG_5 */ | |
603555e5 | 11596 | { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, |
8eab4136 L |
11597 | { RM_TABLE (RM_0F01_REG_5) }, |
11598 | }, | |
9e30b8e0 L |
11599 | { |
11600 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11601 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11602 | { RM_TABLE (RM_0F01_REG_7) }, |
11603 | }, | |
11604 | { | |
11605 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11606 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11607 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11608 | }, |
11609 | { | |
11610 | /* MOD_0F13 */ | |
507bd325 | 11611 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11612 | }, |
11613 | { | |
11614 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11615 | { "movhps", { XM, EXq }, 0 }, |
11616 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11617 | }, |
11618 | { | |
11619 | /* MOD_0F17 */ | |
507bd325 | 11620 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11621 | }, |
11622 | { | |
11623 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11624 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11625 | }, |
11626 | { | |
11627 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11628 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11629 | }, |
11630 | { | |
11631 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11632 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11633 | }, |
11634 | { | |
11635 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11636 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11637 | }, |
d7189fa5 RM |
11638 | { |
11639 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11640 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11641 | }, |
11642 | { | |
11643 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11644 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11645 | }, |
11646 | { | |
11647 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11648 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11649 | }, |
11650 | { | |
11651 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11652 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11653 | }, |
7e8b059b L |
11654 | { |
11655 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 11656 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 11657 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
11658 | }, |
11659 | { | |
11660 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 11661 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 11662 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
11663 | }, |
11664 | { | |
11665 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 11666 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 11667 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 11668 | }, |
c48935d7 IT |
11669 | { |
11670 | /* MOD_0F1C_PREFIX_0 */ | |
11671 | { REG_TABLE (REG_0F1C_MOD_0) }, | |
11672 | { "nopQ", { Ev }, 0 }, | |
11673 | }, | |
603555e5 L |
11674 | { |
11675 | /* MOD_0F1E_PREFIX_1 */ | |
11676 | { "nopQ", { Ev }, 0 }, | |
11677 | { REG_TABLE (REG_0F1E_MOD_3) }, | |
11678 | }, | |
b844680a | 11679 | { |
92fddf8e | 11680 | /* MOD_0F24 */ |
7bb15c6f | 11681 | { Bad_Opcode }, |
bf890a93 | 11682 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11683 | }, |
11684 | { | |
92fddf8e | 11685 | /* MOD_0F26 */ |
592d1631 | 11686 | { Bad_Opcode }, |
bf890a93 | 11687 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11688 | }, |
75c135a8 L |
11689 | { |
11690 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11691 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11692 | }, |
11693 | { | |
11694 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11695 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11696 | }, |
11697 | { | |
11698 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11699 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11700 | }, |
11701 | { | |
11702 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11703 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11704 | }, |
11705 | { | |
11706 | /* MOD_0F51 */ | |
592d1631 | 11707 | { Bad_Opcode }, |
507bd325 | 11708 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11709 | }, |
b844680a | 11710 | { |
1ceb70f8 | 11711 | /* MOD_0F71_REG_2 */ |
592d1631 | 11712 | { Bad_Opcode }, |
bf890a93 | 11713 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11714 | }, |
11715 | { | |
1ceb70f8 | 11716 | /* MOD_0F71_REG_4 */ |
592d1631 | 11717 | { Bad_Opcode }, |
bf890a93 | 11718 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11719 | }, |
11720 | { | |
1ceb70f8 | 11721 | /* MOD_0F71_REG_6 */ |
592d1631 | 11722 | { Bad_Opcode }, |
bf890a93 | 11723 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11724 | }, |
11725 | { | |
1ceb70f8 | 11726 | /* MOD_0F72_REG_2 */ |
592d1631 | 11727 | { Bad_Opcode }, |
bf890a93 | 11728 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11729 | }, |
11730 | { | |
1ceb70f8 | 11731 | /* MOD_0F72_REG_4 */ |
592d1631 | 11732 | { Bad_Opcode }, |
bf890a93 | 11733 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11734 | }, |
11735 | { | |
1ceb70f8 | 11736 | /* MOD_0F72_REG_6 */ |
592d1631 | 11737 | { Bad_Opcode }, |
bf890a93 | 11738 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11739 | }, |
11740 | { | |
1ceb70f8 | 11741 | /* MOD_0F73_REG_2 */ |
592d1631 | 11742 | { Bad_Opcode }, |
bf890a93 | 11743 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11744 | }, |
11745 | { | |
1ceb70f8 | 11746 | /* MOD_0F73_REG_3 */ |
592d1631 | 11747 | { Bad_Opcode }, |
c0f3af97 L |
11748 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11749 | }, | |
11750 | { | |
11751 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11752 | { Bad_Opcode }, |
bf890a93 | 11753 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11754 | }, |
11755 | { | |
11756 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11757 | { Bad_Opcode }, |
c0f3af97 L |
11758 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11759 | }, | |
11760 | { | |
11761 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11762 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11763 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11764 | }, |
11765 | { | |
11766 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11767 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11768 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11769 | }, |
11770 | { | |
11771 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11772 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11773 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11774 | }, |
11775 | { | |
11776 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11777 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11778 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11779 | }, |
11780 | { | |
11781 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
11782 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
11783 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
11784 | }, |
11785 | { | |
11786 | /* MOD_0FAE_REG_5 */ | |
603555e5 | 11787 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, |
2234eee6 | 11788 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, |
c0f3af97 L |
11789 | }, |
11790 | { | |
11791 | /* MOD_0FAE_REG_6 */ | |
de89d0a3 IT |
11792 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, |
11793 | { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, | |
c0f3af97 L |
11794 | }, |
11795 | { | |
11796 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11797 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11798 | { RM_TABLE (RM_0FAE_REG_7) }, |
11799 | }, | |
11800 | { | |
11801 | /* MOD_0FB2 */ | |
bf890a93 | 11802 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11803 | }, |
11804 | { | |
11805 | /* MOD_0FB4 */ | |
bf890a93 | 11806 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11807 | }, |
11808 | { | |
11809 | /* MOD_0FB5 */ | |
bf890a93 | 11810 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11811 | }, |
a8484f96 L |
11812 | { |
11813 | /* MOD_0FC3 */ | |
11814 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11815 | }, | |
963f3586 IT |
11816 | { |
11817 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11818 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11819 | }, |
11820 | { | |
11821 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11822 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11823 | }, |
11824 | { | |
11825 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11826 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11827 | }, |
c0f3af97 L |
11828 | { |
11829 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11830 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11831 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11832 | }, |
11833 | { | |
11834 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11835 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11836 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11837 | }, |
11838 | { | |
11839 | /* MOD_0FD7 */ | |
592d1631 | 11840 | { Bad_Opcode }, |
bf890a93 | 11841 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11842 | }, |
11843 | { | |
11844 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11845 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11846 | }, |
11847 | { | |
11848 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11849 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11850 | }, |
11851 | { | |
11852 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11853 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 11854 | }, |
603555e5 L |
11855 | { |
11856 | /* MOD_0F38F5_PREFIX_2 */ | |
11857 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11858 | }, | |
11859 | { | |
11860 | /* MOD_0F38F6_PREFIX_0 */ | |
11861 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11862 | }, | |
c0a30a9f L |
11863 | { |
11864 | /* MOD_0F38F8_PREFIX_2 */ | |
11865 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
11866 | }, | |
11867 | { | |
11868 | /* MOD_0F38F9_PREFIX_0 */ | |
11869 | { "movdiri", { Em, Gv }, PREFIX_OPCODE }, | |
11870 | }, | |
c0f3af97 L |
11871 | { |
11872 | /* MOD_62_32BIT */ | |
bf890a93 | 11873 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11874 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11875 | }, |
11876 | { | |
11877 | /* MOD_C4_32BIT */ | |
bf890a93 | 11878 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11879 | { VEX_C4_TABLE (VEX_0F) }, |
11880 | }, | |
11881 | { | |
11882 | /* MOD_C5_32BIT */ | |
bf890a93 | 11883 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11884 | { VEX_C5_TABLE (VEX_0F) }, |
11885 | }, | |
11886 | { | |
592a252b L |
11887 | /* MOD_VEX_0F12_PREFIX_0 */ |
11888 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11889 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11890 | }, |
11891 | { | |
592a252b L |
11892 | /* MOD_VEX_0F13 */ |
11893 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11894 | }, |
11895 | { | |
592a252b L |
11896 | /* MOD_VEX_0F16_PREFIX_0 */ |
11897 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11898 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11899 | }, |
11900 | { | |
592a252b L |
11901 | /* MOD_VEX_0F17 */ |
11902 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11903 | }, |
11904 | { | |
592a252b L |
11905 | /* MOD_VEX_0F2B */ |
11906 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11907 | }, |
ab4e4ed5 AF |
11908 | { |
11909 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11910 | { Bad_Opcode }, | |
11911 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11912 | }, | |
11913 | { | |
11914 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11915 | { Bad_Opcode }, | |
11916 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11917 | }, | |
11918 | { | |
11919 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11920 | { Bad_Opcode }, | |
11921 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11922 | }, | |
11923 | { | |
11924 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11925 | { Bad_Opcode }, | |
11926 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11927 | }, | |
11928 | { | |
11929 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11930 | { Bad_Opcode }, | |
11931 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11932 | }, | |
11933 | { | |
11934 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11935 | { Bad_Opcode }, | |
11936 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11937 | }, | |
11938 | { | |
11939 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11940 | { Bad_Opcode }, | |
11941 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11942 | }, | |
11943 | { | |
11944 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11945 | { Bad_Opcode }, | |
11946 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11947 | }, | |
11948 | { | |
11949 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11950 | { Bad_Opcode }, | |
11951 | { "knotw", { MaskG, MaskR }, 0 }, | |
11952 | }, | |
11953 | { | |
11954 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11955 | { Bad_Opcode }, | |
11956 | { "knotq", { MaskG, MaskR }, 0 }, | |
11957 | }, | |
11958 | { | |
11959 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11960 | { Bad_Opcode }, | |
11961 | { "knotb", { MaskG, MaskR }, 0 }, | |
11962 | }, | |
11963 | { | |
11964 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11965 | { Bad_Opcode }, | |
11966 | { "knotd", { MaskG, MaskR }, 0 }, | |
11967 | }, | |
11968 | { | |
11969 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11970 | { Bad_Opcode }, | |
11971 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11972 | }, | |
11973 | { | |
11974 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11975 | { Bad_Opcode }, | |
11976 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11977 | }, | |
11978 | { | |
11979 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11980 | { Bad_Opcode }, | |
11981 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11982 | }, | |
11983 | { | |
11984 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11985 | { Bad_Opcode }, | |
11986 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11987 | }, | |
11988 | { | |
11989 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11990 | { Bad_Opcode }, | |
11991 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11992 | }, | |
11993 | { | |
11994 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11995 | { Bad_Opcode }, | |
11996 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11997 | }, | |
11998 | { | |
11999 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
12000 | { Bad_Opcode }, | |
12001 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
12002 | }, | |
12003 | { | |
12004 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
12005 | { Bad_Opcode }, | |
12006 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
12007 | }, | |
12008 | { | |
12009 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
12010 | { Bad_Opcode }, | |
12011 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
12012 | }, | |
12013 | { | |
12014 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
12015 | { Bad_Opcode }, | |
12016 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
12017 | }, | |
12018 | { | |
12019 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
12020 | { Bad_Opcode }, | |
12021 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
12022 | }, | |
12023 | { | |
12024 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
12025 | { Bad_Opcode }, | |
12026 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
12027 | }, | |
12028 | { | |
12029 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
12030 | { Bad_Opcode }, | |
12031 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
12032 | }, | |
12033 | { | |
12034 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
12035 | { Bad_Opcode }, | |
12036 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
12037 | }, | |
12038 | { | |
12039 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
12040 | { Bad_Opcode }, | |
12041 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
12042 | }, | |
12043 | { | |
12044 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
12045 | { Bad_Opcode }, | |
12046 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
12047 | }, | |
12048 | { | |
12049 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
12050 | { Bad_Opcode }, | |
12051 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
12052 | }, | |
12053 | { | |
12054 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
12055 | { Bad_Opcode }, | |
12056 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
12057 | }, | |
12058 | { | |
12059 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
12060 | { Bad_Opcode }, | |
12061 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
12062 | }, | |
c0f3af97 | 12063 | { |
592a252b | 12064 | /* MOD_VEX_0F50 */ |
592d1631 | 12065 | { Bad_Opcode }, |
592a252b | 12066 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
12067 | }, |
12068 | { | |
592a252b | 12069 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 12070 | { Bad_Opcode }, |
592a252b | 12071 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
12072 | }, |
12073 | { | |
592a252b | 12074 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 12075 | { Bad_Opcode }, |
592a252b | 12076 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
12077 | }, |
12078 | { | |
592a252b | 12079 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 12080 | { Bad_Opcode }, |
592a252b | 12081 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
12082 | }, |
12083 | { | |
592a252b | 12084 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 12085 | { Bad_Opcode }, |
592a252b | 12086 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 12087 | }, |
d8faab4e | 12088 | { |
592a252b | 12089 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 12090 | { Bad_Opcode }, |
592a252b | 12091 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
12092 | }, |
12093 | { | |
592a252b | 12094 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 12095 | { Bad_Opcode }, |
592a252b | 12096 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 12097 | }, |
876d4bfa | 12098 | { |
592a252b | 12099 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 12100 | { Bad_Opcode }, |
592a252b | 12101 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
12102 | }, |
12103 | { | |
592a252b | 12104 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 12105 | { Bad_Opcode }, |
592a252b | 12106 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
12107 | }, |
12108 | { | |
592a252b | 12109 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 12110 | { Bad_Opcode }, |
592a252b | 12111 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
12112 | }, |
12113 | { | |
592a252b | 12114 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 12115 | { Bad_Opcode }, |
592a252b | 12116 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 12117 | }, |
ab4e4ed5 AF |
12118 | { |
12119 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12120 | { "kmovw", { Ew, MaskG }, 0 }, | |
12121 | { Bad_Opcode }, | |
12122 | }, | |
12123 | { | |
12124 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12125 | { "kmovq", { Eq, MaskG }, 0 }, | |
12126 | { Bad_Opcode }, | |
12127 | }, | |
12128 | { | |
12129 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12130 | { "kmovb", { Eb, MaskG }, 0 }, | |
12131 | { Bad_Opcode }, | |
12132 | }, | |
12133 | { | |
12134 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12135 | { "kmovd", { Ed, MaskG }, 0 }, | |
12136 | { Bad_Opcode }, | |
12137 | }, | |
12138 | { | |
12139 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
12140 | { Bad_Opcode }, | |
12141 | { "kmovw", { MaskG, Rdq }, 0 }, | |
12142 | }, | |
12143 | { | |
12144 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
12145 | { Bad_Opcode }, | |
12146 | { "kmovb", { MaskG, Rdq }, 0 }, | |
12147 | }, | |
12148 | { | |
12149 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
12150 | { Bad_Opcode }, | |
12151 | { "kmovd", { MaskG, Rdq }, 0 }, | |
12152 | }, | |
12153 | { | |
12154 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
12155 | { Bad_Opcode }, | |
12156 | { "kmovq", { MaskG, Rdq }, 0 }, | |
12157 | }, | |
12158 | { | |
12159 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
12160 | { Bad_Opcode }, | |
12161 | { "kmovw", { Gdq, MaskR }, 0 }, | |
12162 | }, | |
12163 | { | |
12164 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
12165 | { Bad_Opcode }, | |
12166 | { "kmovb", { Gdq, MaskR }, 0 }, | |
12167 | }, | |
12168 | { | |
12169 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
12170 | { Bad_Opcode }, | |
12171 | { "kmovd", { Gdq, MaskR }, 0 }, | |
12172 | }, | |
12173 | { | |
12174 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
12175 | { Bad_Opcode }, | |
12176 | { "kmovq", { Gdq, MaskR }, 0 }, | |
12177 | }, | |
12178 | { | |
12179 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
12180 | { Bad_Opcode }, | |
12181 | { "kortestw", { MaskG, MaskR }, 0 }, | |
12182 | }, | |
12183 | { | |
12184 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
12185 | { Bad_Opcode }, | |
12186 | { "kortestq", { MaskG, MaskR }, 0 }, | |
12187 | }, | |
12188 | { | |
12189 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
12190 | { Bad_Opcode }, | |
12191 | { "kortestb", { MaskG, MaskR }, 0 }, | |
12192 | }, | |
12193 | { | |
12194 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
12195 | { Bad_Opcode }, | |
12196 | { "kortestd", { MaskG, MaskR }, 0 }, | |
12197 | }, | |
12198 | { | |
12199 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
12200 | { Bad_Opcode }, | |
12201 | { "ktestw", { MaskG, MaskR }, 0 }, | |
12202 | }, | |
12203 | { | |
12204 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
12205 | { Bad_Opcode }, | |
12206 | { "ktestq", { MaskG, MaskR }, 0 }, | |
12207 | }, | |
12208 | { | |
12209 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
12210 | { Bad_Opcode }, | |
12211 | { "ktestb", { MaskG, MaskR }, 0 }, | |
12212 | }, | |
12213 | { | |
12214 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12215 | { Bad_Opcode }, | |
12216 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12217 | }, | |
876d4bfa | 12218 | { |
592a252b L |
12219 | /* MOD_VEX_0FAE_REG_2 */ |
12220 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12221 | }, |
bbedc832 | 12222 | { |
592a252b L |
12223 | /* MOD_VEX_0FAE_REG_3 */ |
12224 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12225 | }, |
144c41d9 | 12226 | { |
592a252b | 12227 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12228 | { Bad_Opcode }, |
6c30d220 | 12229 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12230 | }, |
1afd85e3 | 12231 | { |
592a252b L |
12232 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12233 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12234 | }, |
12235 | { | |
592a252b L |
12236 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12237 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12238 | }, |
75c135a8 | 12239 | { |
592a252b L |
12240 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12241 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12242 | }, |
1afd85e3 | 12243 | { |
592a252b | 12244 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12245 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12246 | }, |
75c135a8 | 12247 | { |
592a252b L |
12248 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12249 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12250 | }, |
1afd85e3 | 12251 | { |
592a252b L |
12252 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12253 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12254 | }, |
12255 | { | |
592a252b L |
12256 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12257 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12258 | }, |
12259 | { | |
592a252b L |
12260 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12261 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12262 | }, |
6c30d220 L |
12263 | { |
12264 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12265 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12266 | }, | |
12267 | { | |
12268 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12269 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12270 | }, |
12271 | { | |
12272 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12273 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12274 | }, |
ab4e4ed5 AF |
12275 | { |
12276 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12277 | { Bad_Opcode }, | |
12278 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12279 | }, | |
12280 | { | |
12281 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12282 | { Bad_Opcode }, | |
12283 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12284 | }, | |
12285 | { | |
12286 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12287 | { Bad_Opcode }, | |
12288 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12289 | }, | |
12290 | { | |
12291 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12292 | { Bad_Opcode }, | |
12293 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12294 | }, | |
12295 | { | |
12296 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12297 | { Bad_Opcode }, | |
12298 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12299 | }, | |
12300 | { | |
12301 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12302 | { Bad_Opcode }, | |
12303 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12304 | }, | |
12305 | { | |
12306 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12307 | { Bad_Opcode }, | |
12308 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12309 | }, | |
12310 | { | |
12311 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12312 | { Bad_Opcode }, | |
12313 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12314 | }, | |
43234a1e L |
12315 | #define NEED_MOD_TABLE |
12316 | #include "i386-dis-evex.h" | |
12317 | #undef NEED_MOD_TABLE | |
b844680a L |
12318 | }; |
12319 | ||
1ceb70f8 | 12320 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12321 | { |
12322 | /* RM_C6_REG_7 */ | |
bf890a93 | 12323 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12324 | }, |
12325 | { | |
12326 | /* RM_C7_REG_7 */ | |
bf890a93 | 12327 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12328 | }, |
b844680a | 12329 | { |
1ceb70f8 | 12330 | /* RM_0F01_REG_0 */ |
592d1631 | 12331 | { Bad_Opcode }, |
bf890a93 IT |
12332 | { "vmcall", { Skip_MODRM }, 0 }, |
12333 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12334 | { "vmresume", { Skip_MODRM }, 0 }, | |
12335 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 12336 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
12337 | }, |
12338 | { | |
1ceb70f8 | 12339 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12340 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12341 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12342 | { "clac", { Skip_MODRM }, 0 }, | |
12343 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12344 | { Bad_Opcode }, |
12345 | { Bad_Opcode }, | |
12346 | { Bad_Opcode }, | |
bf890a93 | 12347 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12348 | }, |
475a2301 L |
12349 | { |
12350 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12351 | { "xgetbv", { Skip_MODRM }, 0 }, |
12352 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12353 | { Bad_Opcode }, |
12354 | { Bad_Opcode }, | |
bf890a93 IT |
12355 | { "vmfunc", { Skip_MODRM }, 0 }, |
12356 | { "xend", { Skip_MODRM }, 0 }, | |
12357 | { "xtest", { Skip_MODRM }, 0 }, | |
12358 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12359 | }, |
b844680a | 12360 | { |
1ceb70f8 | 12361 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12362 | { "vmrun", { Skip_MODRM }, 0 }, |
12363 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12364 | { "vmload", { Skip_MODRM }, 0 }, | |
12365 | { "vmsave", { Skip_MODRM }, 0 }, | |
12366 | { "stgi", { Skip_MODRM }, 0 }, | |
12367 | { "clgi", { Skip_MODRM }, 0 }, | |
12368 | { "skinit", { Skip_MODRM }, 0 }, | |
12369 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12370 | }, |
8eab4136 L |
12371 | { |
12372 | /* RM_0F01_REG_5 */ | |
2234eee6 | 12373 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, |
8eab4136 | 12374 | { Bad_Opcode }, |
603555e5 | 12375 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, |
8eab4136 L |
12376 | { Bad_Opcode }, |
12377 | { Bad_Opcode }, | |
12378 | { Bad_Opcode }, | |
12379 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12380 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12381 | }, | |
4e7d34a6 | 12382 | { |
1ceb70f8 | 12383 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12384 | { "swapgs", { Skip_MODRM }, 0 }, |
12385 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12386 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12387 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12388 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a | 12389 | }, |
603555e5 L |
12390 | { |
12391 | /* RM_0F1E_MOD_3_REG_7 */ | |
12392 | { "nopQ", { Ev }, 0 }, | |
12393 | { "nopQ", { Ev }, 0 }, | |
12394 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
12395 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
12396 | { "nopQ", { Ev }, 0 }, | |
12397 | { "nopQ", { Ev }, 0 }, | |
12398 | { "nopQ", { Ev }, 0 }, | |
12399 | { "nopQ", { Ev }, 0 }, | |
12400 | }, | |
b844680a | 12401 | { |
1ceb70f8 | 12402 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12403 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12404 | }, |
bbedc832 | 12405 | { |
1ceb70f8 | 12406 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
12407 | { "sfence", { Skip_MODRM }, 0 }, |
12408 | ||
144c41d9 | 12409 | }, |
b844680a L |
12410 | }; |
12411 | ||
c608c12e AM |
12412 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12413 | ||
f16cd0d5 L |
12414 | /* We use the high bit to indicate different name for the same |
12415 | prefix. */ | |
f16cd0d5 | 12416 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12417 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12418 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12419 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 12420 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
12421 | |
12422 | static int | |
26ca5450 | 12423 | ckprefix (void) |
252b5132 | 12424 | { |
f16cd0d5 | 12425 | int newrex, i, length; |
52b15da3 | 12426 | rex = 0; |
c0f3af97 | 12427 | rex_ignored = 0; |
252b5132 | 12428 | prefixes = 0; |
7d421014 | 12429 | used_prefixes = 0; |
52b15da3 | 12430 | rex_used = 0; |
f16cd0d5 L |
12431 | last_lock_prefix = -1; |
12432 | last_repz_prefix = -1; | |
12433 | last_repnz_prefix = -1; | |
12434 | last_data_prefix = -1; | |
12435 | last_addr_prefix = -1; | |
12436 | last_rex_prefix = -1; | |
12437 | last_seg_prefix = -1; | |
d9949a36 | 12438 | fwait_prefix = -1; |
285ca992 | 12439 | active_seg_prefix = 0; |
f310f33d L |
12440 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12441 | all_prefixes[i] = 0; | |
12442 | i = 0; | |
f16cd0d5 L |
12443 | length = 0; |
12444 | /* The maximum instruction length is 15bytes. */ | |
12445 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12446 | { |
12447 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12448 | newrex = 0; |
252b5132 RH |
12449 | switch (*codep) |
12450 | { | |
52b15da3 JH |
12451 | /* REX prefixes family. */ |
12452 | case 0x40: | |
12453 | case 0x41: | |
12454 | case 0x42: | |
12455 | case 0x43: | |
12456 | case 0x44: | |
12457 | case 0x45: | |
12458 | case 0x46: | |
12459 | case 0x47: | |
12460 | case 0x48: | |
12461 | case 0x49: | |
12462 | case 0x4a: | |
12463 | case 0x4b: | |
12464 | case 0x4c: | |
12465 | case 0x4d: | |
12466 | case 0x4e: | |
12467 | case 0x4f: | |
f16cd0d5 L |
12468 | if (address_mode == mode_64bit) |
12469 | newrex = *codep; | |
12470 | else | |
12471 | return 1; | |
12472 | last_rex_prefix = i; | |
52b15da3 | 12473 | break; |
252b5132 RH |
12474 | case 0xf3: |
12475 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12476 | last_repz_prefix = i; |
252b5132 RH |
12477 | break; |
12478 | case 0xf2: | |
12479 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12480 | last_repnz_prefix = i; |
252b5132 RH |
12481 | break; |
12482 | case 0xf0: | |
12483 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12484 | last_lock_prefix = i; |
252b5132 RH |
12485 | break; |
12486 | case 0x2e: | |
12487 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12488 | last_seg_prefix = i; |
285ca992 | 12489 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12490 | break; |
12491 | case 0x36: | |
12492 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12493 | last_seg_prefix = i; |
285ca992 | 12494 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12495 | break; |
12496 | case 0x3e: | |
12497 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12498 | last_seg_prefix = i; |
285ca992 | 12499 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12500 | break; |
12501 | case 0x26: | |
12502 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12503 | last_seg_prefix = i; |
285ca992 | 12504 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12505 | break; |
12506 | case 0x64: | |
12507 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12508 | last_seg_prefix = i; |
285ca992 | 12509 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12510 | break; |
12511 | case 0x65: | |
12512 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12513 | last_seg_prefix = i; |
285ca992 | 12514 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12515 | break; |
12516 | case 0x66: | |
12517 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12518 | last_data_prefix = i; |
252b5132 RH |
12519 | break; |
12520 | case 0x67: | |
12521 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12522 | last_addr_prefix = i; |
252b5132 | 12523 | break; |
5076851f | 12524 | case FWAIT_OPCODE: |
252b5132 RH |
12525 | /* fwait is really an instruction. If there are prefixes |
12526 | before the fwait, they belong to the fwait, *not* to the | |
12527 | following instruction. */ | |
d9949a36 | 12528 | fwait_prefix = i; |
3e7d61b2 | 12529 | if (prefixes || rex) |
252b5132 RH |
12530 | { |
12531 | prefixes |= PREFIX_FWAIT; | |
12532 | codep++; | |
6c067bbb RM |
12533 | /* This ensures that the previous REX prefixes are noticed |
12534 | as unused prefixes, as in the return case below. */ | |
12535 | rex_used = rex; | |
f16cd0d5 | 12536 | return 1; |
252b5132 RH |
12537 | } |
12538 | prefixes = PREFIX_FWAIT; | |
12539 | break; | |
12540 | default: | |
f16cd0d5 | 12541 | return 1; |
252b5132 | 12542 | } |
52b15da3 JH |
12543 | /* Rex is ignored when followed by another prefix. */ |
12544 | if (rex) | |
12545 | { | |
3e7d61b2 | 12546 | rex_used = rex; |
f16cd0d5 | 12547 | return 1; |
52b15da3 | 12548 | } |
f16cd0d5 | 12549 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 12550 | all_prefixes[i++] = *codep; |
52b15da3 | 12551 | rex = newrex; |
252b5132 | 12552 | codep++; |
f16cd0d5 L |
12553 | length++; |
12554 | } | |
12555 | return 0; | |
12556 | } | |
12557 | ||
7d421014 ILT |
12558 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12559 | prefix byte. */ | |
12560 | ||
12561 | static const char * | |
26ca5450 | 12562 | prefix_name (int pref, int sizeflag) |
7d421014 | 12563 | { |
0003779b L |
12564 | static const char *rexes [16] = |
12565 | { | |
12566 | "rex", /* 0x40 */ | |
12567 | "rex.B", /* 0x41 */ | |
12568 | "rex.X", /* 0x42 */ | |
12569 | "rex.XB", /* 0x43 */ | |
12570 | "rex.R", /* 0x44 */ | |
12571 | "rex.RB", /* 0x45 */ | |
12572 | "rex.RX", /* 0x46 */ | |
12573 | "rex.RXB", /* 0x47 */ | |
12574 | "rex.W", /* 0x48 */ | |
12575 | "rex.WB", /* 0x49 */ | |
12576 | "rex.WX", /* 0x4a */ | |
12577 | "rex.WXB", /* 0x4b */ | |
12578 | "rex.WR", /* 0x4c */ | |
12579 | "rex.WRB", /* 0x4d */ | |
12580 | "rex.WRX", /* 0x4e */ | |
12581 | "rex.WRXB", /* 0x4f */ | |
12582 | }; | |
12583 | ||
7d421014 ILT |
12584 | switch (pref) |
12585 | { | |
52b15da3 JH |
12586 | /* REX prefixes family. */ |
12587 | case 0x40: | |
52b15da3 | 12588 | case 0x41: |
52b15da3 | 12589 | case 0x42: |
52b15da3 | 12590 | case 0x43: |
52b15da3 | 12591 | case 0x44: |
52b15da3 | 12592 | case 0x45: |
52b15da3 | 12593 | case 0x46: |
52b15da3 | 12594 | case 0x47: |
52b15da3 | 12595 | case 0x48: |
52b15da3 | 12596 | case 0x49: |
52b15da3 | 12597 | case 0x4a: |
52b15da3 | 12598 | case 0x4b: |
52b15da3 | 12599 | case 0x4c: |
52b15da3 | 12600 | case 0x4d: |
52b15da3 | 12601 | case 0x4e: |
52b15da3 | 12602 | case 0x4f: |
0003779b | 12603 | return rexes [pref - 0x40]; |
7d421014 ILT |
12604 | case 0xf3: |
12605 | return "repz"; | |
12606 | case 0xf2: | |
12607 | return "repnz"; | |
12608 | case 0xf0: | |
12609 | return "lock"; | |
12610 | case 0x2e: | |
12611 | return "cs"; | |
12612 | case 0x36: | |
12613 | return "ss"; | |
12614 | case 0x3e: | |
12615 | return "ds"; | |
12616 | case 0x26: | |
12617 | return "es"; | |
12618 | case 0x64: | |
12619 | return "fs"; | |
12620 | case 0x65: | |
12621 | return "gs"; | |
12622 | case 0x66: | |
12623 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12624 | case 0x67: | |
cb712a9e | 12625 | if (address_mode == mode_64bit) |
db6eb5be | 12626 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12627 | else |
2888cb7a | 12628 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12629 | case FWAIT_OPCODE: |
12630 | return "fwait"; | |
f16cd0d5 L |
12631 | case REP_PREFIX: |
12632 | return "rep"; | |
42164a71 L |
12633 | case XACQUIRE_PREFIX: |
12634 | return "xacquire"; | |
12635 | case XRELEASE_PREFIX: | |
12636 | return "xrelease"; | |
7e8b059b L |
12637 | case BND_PREFIX: |
12638 | return "bnd"; | |
04ef582a L |
12639 | case NOTRACK_PREFIX: |
12640 | return "notrack"; | |
7d421014 ILT |
12641 | default: |
12642 | return NULL; | |
12643 | } | |
12644 | } | |
12645 | ||
ce518a5f L |
12646 | static char op_out[MAX_OPERANDS][100]; |
12647 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12648 | static int two_source_ops; |
ce518a5f L |
12649 | static bfd_vma op_address[MAX_OPERANDS]; |
12650 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12651 | static bfd_vma start_pc; |
ce518a5f | 12652 | |
252b5132 RH |
12653 | /* |
12654 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12655 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12656 | * section of the "Virtual 8086 Mode" chapter.) | |
12657 | * 'pc' should be the address of this instruction, it will | |
12658 | * be used to print the target address if this is a relative jump or call | |
12659 | * The function returns the length of this instruction in bytes. | |
12660 | */ | |
12661 | ||
252b5132 | 12662 | static char intel_syntax; |
9d141669 | 12663 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12664 | static char open_char; |
12665 | static char close_char; | |
12666 | static char separator_char; | |
12667 | static char scale_char; | |
12668 | ||
5db04b09 L |
12669 | enum x86_64_isa |
12670 | { | |
12671 | amd64 = 0, | |
12672 | intel64 | |
12673 | }; | |
12674 | ||
12675 | static enum x86_64_isa isa64; | |
12676 | ||
e396998b AM |
12677 | /* Here for backwards compatibility. When gdb stops using |
12678 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12679 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12680 | int |
26ca5450 | 12681 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12682 | { |
12683 | intel_syntax = 0; | |
e396998b AM |
12684 | |
12685 | return print_insn (pc, info); | |
252b5132 RH |
12686 | } |
12687 | ||
12688 | int | |
26ca5450 | 12689 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12690 | { |
12691 | intel_syntax = 1; | |
e396998b AM |
12692 | |
12693 | return print_insn (pc, info); | |
252b5132 RH |
12694 | } |
12695 | ||
e396998b | 12696 | int |
26ca5450 | 12697 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12698 | { |
12699 | intel_syntax = -1; | |
12700 | ||
12701 | return print_insn (pc, info); | |
12702 | } | |
12703 | ||
f59a29b9 L |
12704 | void |
12705 | print_i386_disassembler_options (FILE *stream) | |
12706 | { | |
12707 | fprintf (stream, _("\n\ | |
12708 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12709 | with the -M switch (multiple options should be separated by commas):\n")); | |
12710 | ||
12711 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12712 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12713 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12714 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12715 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12716 | fprintf (stream, _(" att-mnemonic\n" |
12717 | " Display instruction in AT&T mnemonic\n")); | |
12718 | fprintf (stream, _(" intel-mnemonic\n" | |
12719 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12720 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12721 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12722 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12723 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12724 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12725 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12726 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12727 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12728 | } |
12729 | ||
592d1631 | 12730 | /* Bad opcode. */ |
bf890a93 | 12731 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12732 | |
b844680a L |
12733 | /* Get a pointer to struct dis386 with a valid name. */ |
12734 | ||
12735 | static const struct dis386 * | |
8bb15339 | 12736 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12737 | { |
91d6fa6a | 12738 | int vindex, vex_table_index; |
b844680a L |
12739 | |
12740 | if (dp->name != NULL) | |
12741 | return dp; | |
12742 | ||
12743 | switch (dp->op[0].bytemode) | |
12744 | { | |
1ceb70f8 L |
12745 | case USE_REG_TABLE: |
12746 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12747 | break; | |
12748 | ||
12749 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12750 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12751 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12752 | break; |
12753 | ||
12754 | case USE_RM_TABLE: | |
12755 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12756 | break; |
12757 | ||
4e7d34a6 | 12758 | case USE_PREFIX_TABLE: |
c0f3af97 | 12759 | if (need_vex) |
b844680a | 12760 | { |
c0f3af97 L |
12761 | /* The prefix in VEX is implicit. */ |
12762 | switch (vex.prefix) | |
12763 | { | |
12764 | case 0: | |
91d6fa6a | 12765 | vindex = 0; |
c0f3af97 L |
12766 | break; |
12767 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12768 | vindex = 1; |
c0f3af97 L |
12769 | break; |
12770 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12771 | vindex = 2; |
c0f3af97 L |
12772 | break; |
12773 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12774 | vindex = 3; |
c0f3af97 L |
12775 | break; |
12776 | default: | |
12777 | abort (); | |
12778 | break; | |
12779 | } | |
b844680a | 12780 | } |
7bb15c6f | 12781 | else |
b844680a | 12782 | { |
285ca992 L |
12783 | int last_prefix = -1; |
12784 | int prefix = 0; | |
91d6fa6a | 12785 | vindex = 0; |
285ca992 L |
12786 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12787 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12788 | last one wins. */ | |
12789 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12790 | { |
285ca992 | 12791 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12792 | { |
285ca992 L |
12793 | vindex = 1; |
12794 | prefix = PREFIX_REPZ; | |
12795 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12796 | } |
12797 | else | |
b844680a | 12798 | { |
285ca992 L |
12799 | vindex = 3; |
12800 | prefix = PREFIX_REPNZ; | |
12801 | last_prefix = last_repnz_prefix; | |
b844680a | 12802 | } |
285ca992 | 12803 | |
507bd325 L |
12804 | /* Check if prefix should be ignored. */ |
12805 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12806 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12807 | & prefix) != 0) | |
285ca992 L |
12808 | vindex = 0; |
12809 | } | |
12810 | ||
12811 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12812 | { | |
12813 | vindex = 2; | |
12814 | prefix = PREFIX_DATA; | |
12815 | last_prefix = last_data_prefix; | |
12816 | } | |
12817 | ||
12818 | if (vindex != 0) | |
12819 | { | |
12820 | used_prefixes |= prefix; | |
12821 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12822 | } |
12823 | } | |
91d6fa6a | 12824 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12825 | break; |
12826 | ||
4e7d34a6 | 12827 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12828 | vindex = address_mode == mode_64bit ? 1 : 0; |
12829 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12830 | break; |
12831 | ||
4e7d34a6 | 12832 | case USE_3BYTE_TABLE: |
8bb15339 | 12833 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12834 | vindex = *codep++; |
12835 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12836 | end_codep = codep; |
8bb15339 L |
12837 | modrm.mod = (*codep >> 6) & 3; |
12838 | modrm.reg = (*codep >> 3) & 7; | |
12839 | modrm.rm = *codep & 7; | |
12840 | break; | |
12841 | ||
c0f3af97 L |
12842 | case USE_VEX_LEN_TABLE: |
12843 | if (!need_vex) | |
12844 | abort (); | |
12845 | ||
12846 | switch (vex.length) | |
12847 | { | |
12848 | case 128: | |
91d6fa6a | 12849 | vindex = 0; |
c0f3af97 L |
12850 | break; |
12851 | case 256: | |
91d6fa6a | 12852 | vindex = 1; |
c0f3af97 L |
12853 | break; |
12854 | default: | |
12855 | abort (); | |
12856 | break; | |
12857 | } | |
12858 | ||
91d6fa6a | 12859 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12860 | break; |
12861 | ||
f88c9eb0 SP |
12862 | case USE_XOP_8F_TABLE: |
12863 | FETCH_DATA (info, codep + 3); | |
12864 | /* All bits in the REX prefix are ignored. */ | |
12865 | rex_ignored = rex; | |
12866 | rex = ~(*codep >> 5) & 0x7; | |
12867 | ||
12868 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12869 | switch ((*codep & 0x1f)) | |
12870 | { | |
12871 | default: | |
f07af43e L |
12872 | dp = &bad_opcode; |
12873 | return dp; | |
5dd85c99 SP |
12874 | case 0x8: |
12875 | vex_table_index = XOP_08; | |
12876 | break; | |
f88c9eb0 SP |
12877 | case 0x9: |
12878 | vex_table_index = XOP_09; | |
12879 | break; | |
12880 | case 0xa: | |
12881 | vex_table_index = XOP_0A; | |
12882 | break; | |
12883 | } | |
12884 | codep++; | |
12885 | vex.w = *codep & 0x80; | |
12886 | if (vex.w && address_mode == mode_64bit) | |
12887 | rex |= REX_W; | |
12888 | ||
12889 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12890 | if (address_mode != mode_64bit) |
f07af43e | 12891 | { |
abfcb414 AP |
12892 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12893 | rex &= ~REX_B; | |
f07af43e | 12894 | } |
f88c9eb0 SP |
12895 | |
12896 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12897 | switch ((*codep & 0x3)) | |
12898 | { | |
12899 | case 0: | |
f88c9eb0 SP |
12900 | break; |
12901 | case 1: | |
12902 | vex.prefix = DATA_PREFIX_OPCODE; | |
12903 | break; | |
12904 | case 2: | |
12905 | vex.prefix = REPE_PREFIX_OPCODE; | |
12906 | break; | |
12907 | case 3: | |
12908 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12909 | break; | |
12910 | } | |
12911 | need_vex = 1; | |
12912 | need_vex_reg = 1; | |
12913 | codep++; | |
91d6fa6a NC |
12914 | vindex = *codep++; |
12915 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12916 | |
285ca992 | 12917 | end_codep = codep; |
c48244a5 SP |
12918 | FETCH_DATA (info, codep + 1); |
12919 | modrm.mod = (*codep >> 6) & 3; | |
12920 | modrm.reg = (*codep >> 3) & 7; | |
12921 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12922 | break; |
12923 | ||
c0f3af97 | 12924 | case USE_VEX_C4_TABLE: |
43234a1e | 12925 | /* VEX prefix. */ |
c0f3af97 L |
12926 | FETCH_DATA (info, codep + 3); |
12927 | /* All bits in the REX prefix are ignored. */ | |
12928 | rex_ignored = rex; | |
12929 | rex = ~(*codep >> 5) & 0x7; | |
12930 | switch ((*codep & 0x1f)) | |
12931 | { | |
12932 | default: | |
f07af43e L |
12933 | dp = &bad_opcode; |
12934 | return dp; | |
c0f3af97 | 12935 | case 0x1: |
f88c9eb0 | 12936 | vex_table_index = VEX_0F; |
c0f3af97 L |
12937 | break; |
12938 | case 0x2: | |
f88c9eb0 | 12939 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12940 | break; |
12941 | case 0x3: | |
f88c9eb0 | 12942 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12943 | break; |
12944 | } | |
12945 | codep++; | |
12946 | vex.w = *codep & 0x80; | |
9889cbb1 | 12947 | if (address_mode == mode_64bit) |
f07af43e | 12948 | { |
9889cbb1 L |
12949 | if (vex.w) |
12950 | rex |= REX_W; | |
9889cbb1 L |
12951 | } |
12952 | else | |
12953 | { | |
12954 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12955 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 12956 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 12957 | rex = 0; |
f07af43e | 12958 | } |
5f847646 | 12959 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12960 | vex.length = (*codep & 0x4) ? 256 : 128; |
12961 | switch ((*codep & 0x3)) | |
12962 | { | |
12963 | case 0: | |
c0f3af97 L |
12964 | break; |
12965 | case 1: | |
12966 | vex.prefix = DATA_PREFIX_OPCODE; | |
12967 | break; | |
12968 | case 2: | |
12969 | vex.prefix = REPE_PREFIX_OPCODE; | |
12970 | break; | |
12971 | case 3: | |
12972 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12973 | break; | |
12974 | } | |
12975 | need_vex = 1; | |
12976 | need_vex_reg = 1; | |
12977 | codep++; | |
91d6fa6a NC |
12978 | vindex = *codep++; |
12979 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12980 | end_codep = codep; |
53c4d625 JB |
12981 | /* There is no MODRM byte for VEX0F 77. */ |
12982 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12983 | { |
12984 | FETCH_DATA (info, codep + 1); | |
12985 | modrm.mod = (*codep >> 6) & 3; | |
12986 | modrm.reg = (*codep >> 3) & 7; | |
12987 | modrm.rm = *codep & 7; | |
12988 | } | |
12989 | break; | |
12990 | ||
12991 | case USE_VEX_C5_TABLE: | |
43234a1e | 12992 | /* VEX prefix. */ |
c0f3af97 L |
12993 | FETCH_DATA (info, codep + 2); |
12994 | /* All bits in the REX prefix are ignored. */ | |
12995 | rex_ignored = rex; | |
12996 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12997 | ||
9889cbb1 L |
12998 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12999 | VEX.vvvv is 1. */ | |
c0f3af97 | 13000 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
13001 | vex.length = (*codep & 0x4) ? 256 : 128; |
13002 | switch ((*codep & 0x3)) | |
13003 | { | |
13004 | case 0: | |
c0f3af97 L |
13005 | break; |
13006 | case 1: | |
13007 | vex.prefix = DATA_PREFIX_OPCODE; | |
13008 | break; | |
13009 | case 2: | |
13010 | vex.prefix = REPE_PREFIX_OPCODE; | |
13011 | break; | |
13012 | case 3: | |
13013 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13014 | break; | |
13015 | } | |
13016 | need_vex = 1; | |
13017 | need_vex_reg = 1; | |
13018 | codep++; | |
91d6fa6a NC |
13019 | vindex = *codep++; |
13020 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 13021 | end_codep = codep; |
53c4d625 JB |
13022 | /* There is no MODRM byte for VEX 77. */ |
13023 | if (vindex != 0x77) | |
c0f3af97 L |
13024 | { |
13025 | FETCH_DATA (info, codep + 1); | |
13026 | modrm.mod = (*codep >> 6) & 3; | |
13027 | modrm.reg = (*codep >> 3) & 7; | |
13028 | modrm.rm = *codep & 7; | |
13029 | } | |
13030 | break; | |
13031 | ||
9e30b8e0 L |
13032 | case USE_VEX_W_TABLE: |
13033 | if (!need_vex) | |
13034 | abort (); | |
13035 | ||
13036 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
13037 | break; | |
13038 | ||
43234a1e L |
13039 | case USE_EVEX_TABLE: |
13040 | two_source_ops = 0; | |
13041 | /* EVEX prefix. */ | |
13042 | vex.evex = 1; | |
13043 | FETCH_DATA (info, codep + 4); | |
13044 | /* All bits in the REX prefix are ignored. */ | |
13045 | rex_ignored = rex; | |
13046 | /* The first byte after 0x62. */ | |
13047 | rex = ~(*codep >> 5) & 0x7; | |
13048 | vex.r = *codep & 0x10; | |
13049 | switch ((*codep & 0xf)) | |
13050 | { | |
13051 | default: | |
13052 | return &bad_opcode; | |
13053 | case 0x1: | |
13054 | vex_table_index = EVEX_0F; | |
13055 | break; | |
13056 | case 0x2: | |
13057 | vex_table_index = EVEX_0F38; | |
13058 | break; | |
13059 | case 0x3: | |
13060 | vex_table_index = EVEX_0F3A; | |
13061 | break; | |
13062 | } | |
13063 | ||
13064 | /* The second byte after 0x62. */ | |
13065 | codep++; | |
13066 | vex.w = *codep & 0x80; | |
13067 | if (vex.w && address_mode == mode_64bit) | |
13068 | rex |= REX_W; | |
13069 | ||
13070 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
13071 | |
13072 | /* The U bit. */ | |
13073 | if (!(*codep & 0x4)) | |
13074 | return &bad_opcode; | |
13075 | ||
13076 | switch ((*codep & 0x3)) | |
13077 | { | |
13078 | case 0: | |
43234a1e L |
13079 | break; |
13080 | case 1: | |
13081 | vex.prefix = DATA_PREFIX_OPCODE; | |
13082 | break; | |
13083 | case 2: | |
13084 | vex.prefix = REPE_PREFIX_OPCODE; | |
13085 | break; | |
13086 | case 3: | |
13087 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13088 | break; | |
13089 | } | |
13090 | ||
13091 | /* The third byte after 0x62. */ | |
13092 | codep++; | |
13093 | ||
13094 | /* Remember the static rounding bits. */ | |
13095 | vex.ll = (*codep >> 5) & 3; | |
13096 | vex.b = (*codep & 0x10) != 0; | |
13097 | ||
13098 | vex.v = *codep & 0x8; | |
13099 | vex.mask_register_specifier = *codep & 0x7; | |
13100 | vex.zeroing = *codep & 0x80; | |
13101 | ||
5f847646 JB |
13102 | if (address_mode != mode_64bit) |
13103 | { | |
13104 | /* In 16/32-bit mode silently ignore following bits. */ | |
13105 | rex &= ~REX_B; | |
13106 | vex.r = 1; | |
13107 | vex.v = 1; | |
13108 | } | |
13109 | ||
43234a1e L |
13110 | need_vex = 1; |
13111 | need_vex_reg = 1; | |
13112 | codep++; | |
13113 | vindex = *codep++; | |
13114 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 13115 | end_codep = codep; |
43234a1e L |
13116 | FETCH_DATA (info, codep + 1); |
13117 | modrm.mod = (*codep >> 6) & 3; | |
13118 | modrm.reg = (*codep >> 3) & 7; | |
13119 | modrm.rm = *codep & 7; | |
13120 | ||
13121 | /* Set vector length. */ | |
13122 | if (modrm.mod == 3 && vex.b) | |
13123 | vex.length = 512; | |
13124 | else | |
13125 | { | |
13126 | switch (vex.ll) | |
13127 | { | |
13128 | case 0x0: | |
13129 | vex.length = 128; | |
13130 | break; | |
13131 | case 0x1: | |
13132 | vex.length = 256; | |
13133 | break; | |
13134 | case 0x2: | |
13135 | vex.length = 512; | |
13136 | break; | |
13137 | default: | |
13138 | return &bad_opcode; | |
13139 | } | |
13140 | } | |
13141 | break; | |
13142 | ||
592d1631 L |
13143 | case 0: |
13144 | dp = &bad_opcode; | |
13145 | break; | |
13146 | ||
b844680a | 13147 | default: |
d34b5006 | 13148 | abort (); |
b844680a L |
13149 | } |
13150 | ||
13151 | if (dp->name != NULL) | |
13152 | return dp; | |
13153 | else | |
8bb15339 | 13154 | return get_valid_dis386 (dp, info); |
b844680a L |
13155 | } |
13156 | ||
dfc8cf43 | 13157 | static void |
55cf16e1 | 13158 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
13159 | { |
13160 | /* If modrm.mod == 3, operand must be register. */ | |
13161 | if (need_modrm | |
55cf16e1 | 13162 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
13163 | && modrm.mod != 3 |
13164 | && modrm.rm == 4) | |
13165 | { | |
13166 | FETCH_DATA (info, codep + 2); | |
13167 | sib.index = (codep [1] >> 3) & 7; | |
13168 | sib.scale = (codep [1] >> 6) & 3; | |
13169 | sib.base = codep [1] & 7; | |
13170 | } | |
13171 | } | |
13172 | ||
e396998b | 13173 | static int |
26ca5450 | 13174 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 13175 | { |
2da11e11 | 13176 | const struct dis386 *dp; |
252b5132 | 13177 | int i; |
ce518a5f | 13178 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 13179 | int needcomma; |
df18fdba | 13180 | int sizeflag, orig_sizeflag; |
e396998b | 13181 | const char *p; |
252b5132 | 13182 | struct dis_private priv; |
f16cd0d5 | 13183 | int prefix_length; |
252b5132 | 13184 | |
d7921315 L |
13185 | priv.orig_sizeflag = AFLAG | DFLAG; |
13186 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 13187 | address_mode = mode_32bit; |
2da11e11 | 13188 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
13189 | { |
13190 | address_mode = mode_16bit; | |
13191 | priv.orig_sizeflag = 0; | |
13192 | } | |
2da11e11 | 13193 | else |
d7921315 L |
13194 | address_mode = mode_64bit; |
13195 | ||
13196 | if (intel_syntax == (char) -1) | |
13197 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
13198 | |
13199 | for (p = info->disassembler_options; p != NULL; ) | |
13200 | { | |
5db04b09 L |
13201 | if (CONST_STRNEQ (p, "amd64")) |
13202 | isa64 = amd64; | |
13203 | else if (CONST_STRNEQ (p, "intel64")) | |
13204 | isa64 = intel64; | |
13205 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 13206 | { |
cb712a9e | 13207 | address_mode = mode_64bit; |
e396998b AM |
13208 | priv.orig_sizeflag = AFLAG | DFLAG; |
13209 | } | |
0112cd26 | 13210 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 13211 | { |
cb712a9e | 13212 | address_mode = mode_32bit; |
e396998b AM |
13213 | priv.orig_sizeflag = AFLAG | DFLAG; |
13214 | } | |
0112cd26 | 13215 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13216 | { |
cb712a9e | 13217 | address_mode = mode_16bit; |
e396998b AM |
13218 | priv.orig_sizeflag = 0; |
13219 | } | |
0112cd26 | 13220 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13221 | { |
13222 | intel_syntax = 1; | |
9d141669 L |
13223 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13224 | intel_mnemonic = 1; | |
e396998b | 13225 | } |
0112cd26 | 13226 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13227 | { |
13228 | intel_syntax = 0; | |
9d141669 L |
13229 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13230 | intel_mnemonic = 0; | |
e396998b | 13231 | } |
0112cd26 | 13232 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13233 | { |
f59a29b9 L |
13234 | if (address_mode == mode_64bit) |
13235 | { | |
13236 | if (p[4] == '3' && p[5] == '2') | |
13237 | priv.orig_sizeflag &= ~AFLAG; | |
13238 | else if (p[4] == '6' && p[5] == '4') | |
13239 | priv.orig_sizeflag |= AFLAG; | |
13240 | } | |
13241 | else | |
13242 | { | |
13243 | if (p[4] == '1' && p[5] == '6') | |
13244 | priv.orig_sizeflag &= ~AFLAG; | |
13245 | else if (p[4] == '3' && p[5] == '2') | |
13246 | priv.orig_sizeflag |= AFLAG; | |
13247 | } | |
e396998b | 13248 | } |
0112cd26 | 13249 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13250 | { |
13251 | if (p[4] == '1' && p[5] == '6') | |
13252 | priv.orig_sizeflag &= ~DFLAG; | |
13253 | else if (p[4] == '3' && p[5] == '2') | |
13254 | priv.orig_sizeflag |= DFLAG; | |
13255 | } | |
0112cd26 | 13256 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13257 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13258 | ||
13259 | p = strchr (p, ','); | |
13260 | if (p != NULL) | |
13261 | p++; | |
13262 | } | |
13263 | ||
c0f92bf9 L |
13264 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13265 | { | |
13266 | (*info->fprintf_func) (info->stream, | |
13267 | _("64-bit address is disabled")); | |
13268 | return -1; | |
13269 | } | |
13270 | ||
e396998b AM |
13271 | if (intel_syntax) |
13272 | { | |
13273 | names64 = intel_names64; | |
13274 | names32 = intel_names32; | |
13275 | names16 = intel_names16; | |
13276 | names8 = intel_names8; | |
13277 | names8rex = intel_names8rex; | |
13278 | names_seg = intel_names_seg; | |
b9733481 | 13279 | names_mm = intel_names_mm; |
7e8b059b | 13280 | names_bnd = intel_names_bnd; |
b9733481 L |
13281 | names_xmm = intel_names_xmm; |
13282 | names_ymm = intel_names_ymm; | |
43234a1e | 13283 | names_zmm = intel_names_zmm; |
db51cc60 L |
13284 | index64 = intel_index64; |
13285 | index32 = intel_index32; | |
43234a1e | 13286 | names_mask = intel_names_mask; |
e396998b AM |
13287 | index16 = intel_index16; |
13288 | open_char = '['; | |
13289 | close_char = ']'; | |
13290 | separator_char = '+'; | |
13291 | scale_char = '*'; | |
13292 | } | |
13293 | else | |
13294 | { | |
13295 | names64 = att_names64; | |
13296 | names32 = att_names32; | |
13297 | names16 = att_names16; | |
13298 | names8 = att_names8; | |
13299 | names8rex = att_names8rex; | |
13300 | names_seg = att_names_seg; | |
b9733481 | 13301 | names_mm = att_names_mm; |
7e8b059b | 13302 | names_bnd = att_names_bnd; |
b9733481 L |
13303 | names_xmm = att_names_xmm; |
13304 | names_ymm = att_names_ymm; | |
43234a1e | 13305 | names_zmm = att_names_zmm; |
db51cc60 L |
13306 | index64 = att_index64; |
13307 | index32 = att_index32; | |
43234a1e | 13308 | names_mask = att_names_mask; |
e396998b AM |
13309 | index16 = att_index16; |
13310 | open_char = '('; | |
13311 | close_char = ')'; | |
13312 | separator_char = ','; | |
13313 | scale_char = ','; | |
13314 | } | |
2da11e11 | 13315 | |
4fe53c98 | 13316 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13317 | puts most long word instructions on a single line. Use 8 bytes |
13318 | for Intel L1OM. */ | |
d7921315 | 13319 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13320 | info->bytes_per_line = 8; |
13321 | else | |
13322 | info->bytes_per_line = 7; | |
252b5132 | 13323 | |
26ca5450 | 13324 | info->private_data = &priv; |
252b5132 RH |
13325 | priv.max_fetched = priv.the_buffer; |
13326 | priv.insn_start = pc; | |
252b5132 RH |
13327 | |
13328 | obuf[0] = 0; | |
ce518a5f L |
13329 | for (i = 0; i < MAX_OPERANDS; ++i) |
13330 | { | |
13331 | op_out[i][0] = 0; | |
13332 | op_index[i] = -1; | |
13333 | } | |
252b5132 RH |
13334 | |
13335 | the_info = info; | |
13336 | start_pc = pc; | |
e396998b AM |
13337 | start_codep = priv.the_buffer; |
13338 | codep = priv.the_buffer; | |
252b5132 | 13339 | |
8df14d78 | 13340 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13341 | { |
7d421014 ILT |
13342 | const char *name; |
13343 | ||
5076851f | 13344 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13345 | means we have an incomplete instruction of some sort. Just |
13346 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13347 | if (codep > priv.the_buffer) | |
5076851f | 13348 | { |
e396998b | 13349 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13350 | if (name != NULL) |
13351 | (*info->fprintf_func) (info->stream, "%s", name); | |
13352 | else | |
5076851f | 13353 | { |
7d421014 ILT |
13354 | /* Just print the first byte as a .byte instruction. */ |
13355 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13356 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13357 | } |
5076851f | 13358 | |
7d421014 | 13359 | return 1; |
5076851f ILT |
13360 | } |
13361 | ||
13362 | return -1; | |
13363 | } | |
13364 | ||
52b15da3 | 13365 | obufp = obuf; |
f16cd0d5 L |
13366 | sizeflag = priv.orig_sizeflag; |
13367 | ||
13368 | if (!ckprefix () || rex_used) | |
13369 | { | |
13370 | /* Too many prefixes or unused REX prefixes. */ | |
13371 | for (i = 0; | |
f6dd4781 | 13372 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13373 | i++) |
de882298 | 13374 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13375 | i == 0 ? "" : " ", |
f16cd0d5 | 13376 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13377 | return i; |
f16cd0d5 | 13378 | } |
252b5132 RH |
13379 | |
13380 | insn_codep = codep; | |
13381 | ||
13382 | FETCH_DATA (info, codep + 1); | |
13383 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13384 | ||
3e7d61b2 | 13385 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13386 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13387 | { |
86a80a50 | 13388 | /* Handle prefixes before fwait. */ |
d9949a36 | 13389 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13390 | i++) |
13391 | (*info->fprintf_func) (info->stream, "%s ", | |
13392 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13393 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13394 | return i + 1; |
252b5132 RH |
13395 | } |
13396 | ||
252b5132 RH |
13397 | if (*codep == 0x0f) |
13398 | { | |
eec0f4ca | 13399 | unsigned char threebyte; |
5f40e14d JS |
13400 | |
13401 | codep++; | |
13402 | FETCH_DATA (info, codep + 1); | |
13403 | threebyte = *codep; | |
eec0f4ca | 13404 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13405 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13406 | codep++; |
252b5132 RH |
13407 | } |
13408 | else | |
13409 | { | |
6439fc28 | 13410 | dp = &dis386[*codep]; |
252b5132 | 13411 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13412 | codep++; |
252b5132 | 13413 | } |
246c51aa | 13414 | |
df18fdba L |
13415 | /* Save sizeflag for printing the extra prefixes later before updating |
13416 | it for mnemonic and operand processing. The prefix names depend | |
13417 | only on the address mode. */ | |
13418 | orig_sizeflag = sizeflag; | |
c608c12e | 13419 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13420 | sizeflag ^= AFLAG; |
b844680a | 13421 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13422 | sizeflag ^= DFLAG; |
3ffd33cf | 13423 | |
285ca992 | 13424 | end_codep = codep; |
8bb15339 | 13425 | if (need_modrm) |
252b5132 RH |
13426 | { |
13427 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13428 | modrm.mod = (*codep >> 6) & 3; |
13429 | modrm.reg = (*codep >> 3) & 7; | |
13430 | modrm.rm = *codep & 7; | |
252b5132 RH |
13431 | } |
13432 | ||
42d5f9c6 MS |
13433 | need_vex = 0; |
13434 | need_vex_reg = 0; | |
13435 | vex_w_done = 0; | |
caf0678c | 13436 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 13437 | |
ce518a5f | 13438 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13439 | { |
55cf16e1 | 13440 | get_sib (info, sizeflag); |
252b5132 RH |
13441 | dofloat (sizeflag); |
13442 | } | |
13443 | else | |
13444 | { | |
8bb15339 | 13445 | dp = get_valid_dis386 (dp, info); |
b844680a | 13446 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13447 | { |
55cf16e1 | 13448 | get_sib (info, sizeflag); |
ce518a5f L |
13449 | for (i = 0; i < MAX_OPERANDS; ++i) |
13450 | { | |
246c51aa | 13451 | obufp = op_out[i]; |
ce518a5f L |
13452 | op_ad = MAX_OPERANDS - 1 - i; |
13453 | if (dp->op[i].rtn) | |
13454 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13455 | /* For EVEX instruction after the last operand masking |
13456 | should be printed. */ | |
13457 | if (i == 0 && vex.evex) | |
13458 | { | |
13459 | /* Don't print {%k0}. */ | |
13460 | if (vex.mask_register_specifier) | |
13461 | { | |
13462 | oappend ("{"); | |
13463 | oappend (names_mask[vex.mask_register_specifier]); | |
13464 | oappend ("}"); | |
13465 | } | |
13466 | if (vex.zeroing) | |
13467 | oappend ("{z}"); | |
13468 | } | |
ce518a5f | 13469 | } |
6439fc28 | 13470 | } |
252b5132 RH |
13471 | } |
13472 | ||
d869730d | 13473 | /* Check if the REX prefix is used. */ |
e2e6193d | 13474 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13475 | all_prefixes[last_rex_prefix] = 0; |
13476 | ||
5e6718e4 | 13477 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13478 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13479 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13480 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13481 | all_prefixes[last_seg_prefix] = 0; |
13482 | ||
5e6718e4 | 13483 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13484 | if ((prefixes & PREFIX_ADDR) != 0 |
13485 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13486 | all_prefixes[last_addr_prefix] = 0; | |
13487 | ||
df18fdba L |
13488 | /* Check if the DATA prefix is used. */ |
13489 | if ((prefixes & PREFIX_DATA) != 0 | |
13490 | && (used_prefixes & PREFIX_DATA) != 0) | |
13491 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13492 | |
df18fdba | 13493 | /* Print the extra prefixes. */ |
f16cd0d5 | 13494 | prefix_length = 0; |
f310f33d | 13495 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13496 | if (all_prefixes[i]) |
13497 | { | |
13498 | const char *name; | |
df18fdba | 13499 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13500 | if (name == NULL) |
13501 | abort (); | |
13502 | prefix_length += strlen (name) + 1; | |
13503 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13504 | } | |
b844680a | 13505 | |
285ca992 L |
13506 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13507 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13508 | used by putop and MMX/SSE operand and may be overriden by the | |
13509 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13510 | separately. */ | |
3888916d | 13511 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13512 | && dp != &bad_opcode |
13513 | && (((prefixes | |
13514 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13515 | && (used_prefixes | |
13516 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13517 | || ((((prefixes | |
13518 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13519 | == PREFIX_DATA) | |
13520 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13521 | { | |
13522 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13523 | return end_codep - priv.the_buffer; | |
13524 | } | |
13525 | ||
f16cd0d5 L |
13526 | /* Check maximum code length. */ |
13527 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13528 | { | |
13529 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13530 | return MAX_CODE_LENGTH; | |
13531 | } | |
b844680a | 13532 | |
ea397f5b | 13533 | obufp = mnemonicendp; |
f16cd0d5 | 13534 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13535 | oappend (" "); |
13536 | oappend (" "); | |
13537 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13538 | ||
13539 | /* The enter and bound instructions are printed with operands in the same | |
13540 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13541 | if (intel_syntax || two_source_ops) |
252b5132 | 13542 | { |
185b1163 L |
13543 | bfd_vma riprel; |
13544 | ||
ce518a5f | 13545 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13546 | op_txt[i] = op_out[i]; |
246c51aa | 13547 | |
3a8547d2 JB |
13548 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13549 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13550 | { | |
13551 | op_txt[2] = op_out[3]; | |
13552 | op_txt[3] = op_out[2]; | |
13553 | } | |
13554 | ||
ce518a5f L |
13555 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13556 | { | |
6c067bbb RM |
13557 | op_ad = op_index[i]; |
13558 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13559 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13560 | riprel = op_riprel[i]; |
13561 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13562 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13563 | } |
252b5132 RH |
13564 | } |
13565 | else | |
13566 | { | |
ce518a5f | 13567 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13568 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13569 | } |
13570 | ||
ce518a5f L |
13571 | needcomma = 0; |
13572 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13573 | if (*op_txt[i]) | |
13574 | { | |
13575 | if (needcomma) | |
13576 | (*info->fprintf_func) (info->stream, ","); | |
13577 | if (op_index[i] != -1 && !op_riprel[i]) | |
13578 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13579 | else | |
13580 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13581 | needcomma = 1; | |
13582 | } | |
050dfa73 | 13583 | |
ce518a5f | 13584 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13585 | if (op_index[i] != -1 && op_riprel[i]) |
13586 | { | |
13587 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13588 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13589 | + op_address[op_index[i]]), info); |
185b1163 | 13590 | break; |
52b15da3 | 13591 | } |
e396998b | 13592 | return codep - priv.the_buffer; |
252b5132 RH |
13593 | } |
13594 | ||
6439fc28 | 13595 | static const char *float_mem[] = { |
252b5132 | 13596 | /* d8 */ |
7c52e0e8 L |
13597 | "fadd{s|}", |
13598 | "fmul{s|}", | |
13599 | "fcom{s|}", | |
13600 | "fcomp{s|}", | |
13601 | "fsub{s|}", | |
13602 | "fsubr{s|}", | |
13603 | "fdiv{s|}", | |
13604 | "fdivr{s|}", | |
db6eb5be | 13605 | /* d9 */ |
7c52e0e8 | 13606 | "fld{s|}", |
252b5132 | 13607 | "(bad)", |
7c52e0e8 L |
13608 | "fst{s|}", |
13609 | "fstp{s|}", | |
9306ca4a | 13610 | "fldenvIC", |
252b5132 | 13611 | "fldcw", |
9306ca4a | 13612 | "fNstenvIC", |
252b5132 RH |
13613 | "fNstcw", |
13614 | /* da */ | |
7c52e0e8 L |
13615 | "fiadd{l|}", |
13616 | "fimul{l|}", | |
13617 | "ficom{l|}", | |
13618 | "ficomp{l|}", | |
13619 | "fisub{l|}", | |
13620 | "fisubr{l|}", | |
13621 | "fidiv{l|}", | |
13622 | "fidivr{l|}", | |
252b5132 | 13623 | /* db */ |
7c52e0e8 L |
13624 | "fild{l|}", |
13625 | "fisttp{l|}", | |
13626 | "fist{l|}", | |
13627 | "fistp{l|}", | |
252b5132 | 13628 | "(bad)", |
6439fc28 | 13629 | "fld{t||t|}", |
252b5132 | 13630 | "(bad)", |
6439fc28 | 13631 | "fstp{t||t|}", |
252b5132 | 13632 | /* dc */ |
7c52e0e8 L |
13633 | "fadd{l|}", |
13634 | "fmul{l|}", | |
13635 | "fcom{l|}", | |
13636 | "fcomp{l|}", | |
13637 | "fsub{l|}", | |
13638 | "fsubr{l|}", | |
13639 | "fdiv{l|}", | |
13640 | "fdivr{l|}", | |
252b5132 | 13641 | /* dd */ |
7c52e0e8 L |
13642 | "fld{l|}", |
13643 | "fisttp{ll|}", | |
13644 | "fst{l||}", | |
13645 | "fstp{l|}", | |
9306ca4a | 13646 | "frstorIC", |
252b5132 | 13647 | "(bad)", |
9306ca4a | 13648 | "fNsaveIC", |
252b5132 RH |
13649 | "fNstsw", |
13650 | /* de */ | |
ac465521 JB |
13651 | "fiadd{s|}", |
13652 | "fimul{s|}", | |
13653 | "ficom{s|}", | |
13654 | "ficomp{s|}", | |
13655 | "fisub{s|}", | |
13656 | "fisubr{s|}", | |
13657 | "fidiv{s|}", | |
13658 | "fidivr{s|}", | |
252b5132 | 13659 | /* df */ |
ac465521 JB |
13660 | "fild{s|}", |
13661 | "fisttp{s|}", | |
13662 | "fist{s|}", | |
13663 | "fistp{s|}", | |
252b5132 | 13664 | "fbld", |
7c52e0e8 | 13665 | "fild{ll|}", |
252b5132 | 13666 | "fbstp", |
7c52e0e8 | 13667 | "fistp{ll|}", |
1d9f512f AM |
13668 | }; |
13669 | ||
13670 | static const unsigned char float_mem_mode[] = { | |
13671 | /* d8 */ | |
13672 | d_mode, | |
13673 | d_mode, | |
13674 | d_mode, | |
13675 | d_mode, | |
13676 | d_mode, | |
13677 | d_mode, | |
13678 | d_mode, | |
13679 | d_mode, | |
13680 | /* d9 */ | |
13681 | d_mode, | |
13682 | 0, | |
13683 | d_mode, | |
13684 | d_mode, | |
13685 | 0, | |
13686 | w_mode, | |
13687 | 0, | |
13688 | w_mode, | |
13689 | /* da */ | |
13690 | d_mode, | |
13691 | d_mode, | |
13692 | d_mode, | |
13693 | d_mode, | |
13694 | d_mode, | |
13695 | d_mode, | |
13696 | d_mode, | |
13697 | d_mode, | |
13698 | /* db */ | |
13699 | d_mode, | |
13700 | d_mode, | |
13701 | d_mode, | |
13702 | d_mode, | |
13703 | 0, | |
9306ca4a | 13704 | t_mode, |
1d9f512f | 13705 | 0, |
9306ca4a | 13706 | t_mode, |
1d9f512f AM |
13707 | /* dc */ |
13708 | q_mode, | |
13709 | q_mode, | |
13710 | q_mode, | |
13711 | q_mode, | |
13712 | q_mode, | |
13713 | q_mode, | |
13714 | q_mode, | |
13715 | q_mode, | |
13716 | /* dd */ | |
13717 | q_mode, | |
13718 | q_mode, | |
13719 | q_mode, | |
13720 | q_mode, | |
13721 | 0, | |
13722 | 0, | |
13723 | 0, | |
13724 | w_mode, | |
13725 | /* de */ | |
13726 | w_mode, | |
13727 | w_mode, | |
13728 | w_mode, | |
13729 | w_mode, | |
13730 | w_mode, | |
13731 | w_mode, | |
13732 | w_mode, | |
13733 | w_mode, | |
13734 | /* df */ | |
13735 | w_mode, | |
13736 | w_mode, | |
13737 | w_mode, | |
13738 | w_mode, | |
9306ca4a | 13739 | t_mode, |
1d9f512f | 13740 | q_mode, |
9306ca4a | 13741 | t_mode, |
1d9f512f | 13742 | q_mode |
252b5132 RH |
13743 | }; |
13744 | ||
ce518a5f L |
13745 | #define ST { OP_ST, 0 } |
13746 | #define STi { OP_STi, 0 } | |
252b5132 | 13747 | |
48c97fa1 L |
13748 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13749 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13750 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13751 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13752 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13753 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13754 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13755 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13756 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13757 | |
2da11e11 | 13758 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13759 | /* d8 */ |
13760 | { | |
bf890a93 IT |
13761 | { "fadd", { ST, STi }, 0 }, |
13762 | { "fmul", { ST, STi }, 0 }, | |
13763 | { "fcom", { STi }, 0 }, | |
13764 | { "fcomp", { STi }, 0 }, | |
13765 | { "fsub", { ST, STi }, 0 }, | |
13766 | { "fsubr", { ST, STi }, 0 }, | |
13767 | { "fdiv", { ST, STi }, 0 }, | |
13768 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13769 | }, |
13770 | /* d9 */ | |
13771 | { | |
bf890a93 IT |
13772 | { "fld", { STi }, 0 }, |
13773 | { "fxch", { STi }, 0 }, | |
252b5132 | 13774 | { FGRPd9_2 }, |
592d1631 | 13775 | { Bad_Opcode }, |
252b5132 RH |
13776 | { FGRPd9_4 }, |
13777 | { FGRPd9_5 }, | |
13778 | { FGRPd9_6 }, | |
13779 | { FGRPd9_7 }, | |
13780 | }, | |
13781 | /* da */ | |
13782 | { | |
bf890a93 IT |
13783 | { "fcmovb", { ST, STi }, 0 }, |
13784 | { "fcmove", { ST, STi }, 0 }, | |
13785 | { "fcmovbe",{ ST, STi }, 0 }, | |
13786 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13787 | { Bad_Opcode }, |
252b5132 | 13788 | { FGRPda_5 }, |
592d1631 L |
13789 | { Bad_Opcode }, |
13790 | { Bad_Opcode }, | |
252b5132 RH |
13791 | }, |
13792 | /* db */ | |
13793 | { | |
bf890a93 IT |
13794 | { "fcmovnb",{ ST, STi }, 0 }, |
13795 | { "fcmovne",{ ST, STi }, 0 }, | |
13796 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13797 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13798 | { FGRPdb_4 }, |
bf890a93 IT |
13799 | { "fucomi", { ST, STi }, 0 }, |
13800 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13801 | { Bad_Opcode }, |
252b5132 RH |
13802 | }, |
13803 | /* dc */ | |
13804 | { | |
bf890a93 IT |
13805 | { "fadd", { STi, ST }, 0 }, |
13806 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13807 | { Bad_Opcode }, |
13808 | { Bad_Opcode }, | |
d53e6b98 JB |
13809 | { "fsub{!M|r}", { STi, ST }, 0 }, |
13810 | { "fsub{M|}", { STi, ST }, 0 }, | |
13811 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
13812 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
13813 | }, |
13814 | /* dd */ | |
13815 | { | |
bf890a93 | 13816 | { "ffree", { STi }, 0 }, |
592d1631 | 13817 | { Bad_Opcode }, |
bf890a93 IT |
13818 | { "fst", { STi }, 0 }, |
13819 | { "fstp", { STi }, 0 }, | |
13820 | { "fucom", { STi }, 0 }, | |
13821 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13822 | { Bad_Opcode }, |
13823 | { Bad_Opcode }, | |
252b5132 RH |
13824 | }, |
13825 | /* de */ | |
13826 | { | |
bf890a93 IT |
13827 | { "faddp", { STi, ST }, 0 }, |
13828 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13829 | { Bad_Opcode }, |
252b5132 | 13830 | { FGRPde_3 }, |
d53e6b98 JB |
13831 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
13832 | { "fsub{M|}p", { STi, ST }, 0 }, | |
13833 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
13834 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
13835 | }, |
13836 | /* df */ | |
13837 | { | |
bf890a93 | 13838 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13839 | { Bad_Opcode }, |
13840 | { Bad_Opcode }, | |
13841 | { Bad_Opcode }, | |
252b5132 | 13842 | { FGRPdf_4 }, |
bf890a93 IT |
13843 | { "fucomip", { ST, STi }, 0 }, |
13844 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13845 | { Bad_Opcode }, |
252b5132 RH |
13846 | }, |
13847 | }; | |
13848 | ||
252b5132 | 13849 | static char *fgrps[][8] = { |
48c97fa1 L |
13850 | /* Bad opcode 0 */ |
13851 | { | |
13852 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13853 | }, | |
13854 | ||
13855 | /* d9_2 1 */ | |
252b5132 RH |
13856 | { |
13857 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13858 | }, | |
13859 | ||
48c97fa1 | 13860 | /* d9_4 2 */ |
252b5132 RH |
13861 | { |
13862 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13863 | }, | |
13864 | ||
48c97fa1 | 13865 | /* d9_5 3 */ |
252b5132 RH |
13866 | { |
13867 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13868 | }, | |
13869 | ||
48c97fa1 | 13870 | /* d9_6 4 */ |
252b5132 RH |
13871 | { |
13872 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13873 | }, | |
13874 | ||
48c97fa1 | 13875 | /* d9_7 5 */ |
252b5132 RH |
13876 | { |
13877 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13878 | }, | |
13879 | ||
48c97fa1 | 13880 | /* da_5 6 */ |
252b5132 RH |
13881 | { |
13882 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13883 | }, | |
13884 | ||
48c97fa1 | 13885 | /* db_4 7 */ |
252b5132 | 13886 | { |
309d3373 JB |
13887 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13888 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13889 | }, |
13890 | ||
48c97fa1 | 13891 | /* de_3 8 */ |
252b5132 RH |
13892 | { |
13893 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13894 | }, | |
13895 | ||
48c97fa1 | 13896 | /* df_4 9 */ |
252b5132 RH |
13897 | { |
13898 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13899 | }, | |
13900 | }; | |
13901 | ||
b6169b20 L |
13902 | static void |
13903 | swap_operand (void) | |
13904 | { | |
13905 | mnemonicendp[0] = '.'; | |
13906 | mnemonicendp[1] = 's'; | |
13907 | mnemonicendp += 2; | |
13908 | } | |
13909 | ||
b844680a L |
13910 | static void |
13911 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13912 | int sizeflag ATTRIBUTE_UNUSED) | |
13913 | { | |
13914 | /* Skip mod/rm byte. */ | |
13915 | MODRM_CHECK; | |
13916 | codep++; | |
13917 | } | |
13918 | ||
252b5132 | 13919 | static void |
26ca5450 | 13920 | dofloat (int sizeflag) |
252b5132 | 13921 | { |
2da11e11 | 13922 | const struct dis386 *dp; |
252b5132 RH |
13923 | unsigned char floatop; |
13924 | ||
13925 | floatop = codep[-1]; | |
13926 | ||
7967e09e | 13927 | if (modrm.mod != 3) |
252b5132 | 13928 | { |
7967e09e | 13929 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13930 | |
13931 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13932 | obufp = op_out[0]; |
6e50d963 | 13933 | op_ad = 2; |
1d9f512f | 13934 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13935 | return; |
13936 | } | |
6608db57 | 13937 | /* Skip mod/rm byte. */ |
4bba6815 | 13938 | MODRM_CHECK; |
252b5132 RH |
13939 | codep++; |
13940 | ||
7967e09e | 13941 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13942 | if (dp->name == NULL) |
13943 | { | |
7967e09e | 13944 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13945 | |
6608db57 | 13946 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13947 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13948 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13949 | } |
13950 | else | |
13951 | { | |
13952 | putop (dp->name, sizeflag); | |
13953 | ||
ce518a5f | 13954 | obufp = op_out[0]; |
6e50d963 | 13955 | op_ad = 2; |
ce518a5f L |
13956 | if (dp->op[0].rtn) |
13957 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13958 | |
ce518a5f | 13959 | obufp = op_out[1]; |
6e50d963 | 13960 | op_ad = 1; |
ce518a5f L |
13961 | if (dp->op[1].rtn) |
13962 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13963 | } |
13964 | } | |
13965 | ||
9ce09ba2 RM |
13966 | /* Like oappend (below), but S is a string starting with '%'. |
13967 | In Intel syntax, the '%' is elided. */ | |
13968 | static void | |
13969 | oappend_maybe_intel (const char *s) | |
13970 | { | |
13971 | oappend (s + intel_syntax); | |
13972 | } | |
13973 | ||
252b5132 | 13974 | static void |
26ca5450 | 13975 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13976 | { |
9ce09ba2 | 13977 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13978 | } |
13979 | ||
252b5132 | 13980 | static void |
26ca5450 | 13981 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13982 | { |
7967e09e | 13983 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13984 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13985 | } |
13986 | ||
6608db57 | 13987 | /* Capital letters in template are macros. */ |
6439fc28 | 13988 | static int |
d3ce72d0 | 13989 | putop (const char *in_template, int sizeflag) |
252b5132 | 13990 | { |
2da11e11 | 13991 | const char *p; |
9306ca4a | 13992 | int alt = 0; |
9d141669 | 13993 | int cond = 1; |
98b528ac L |
13994 | unsigned int l = 0, len = 1; |
13995 | char last[4]; | |
13996 | ||
13997 | #define SAVE_LAST(c) \ | |
13998 | if (l < len && l < sizeof (last)) \ | |
13999 | last[l++] = c; \ | |
14000 | else \ | |
14001 | abort (); | |
252b5132 | 14002 | |
d3ce72d0 | 14003 | for (p = in_template; *p; p++) |
252b5132 RH |
14004 | { |
14005 | switch (*p) | |
14006 | { | |
14007 | default: | |
14008 | *obufp++ = *p; | |
14009 | break; | |
98b528ac L |
14010 | case '%': |
14011 | len++; | |
14012 | break; | |
9d141669 L |
14013 | case '!': |
14014 | cond = 0; | |
14015 | break; | |
6439fc28 | 14016 | case '{': |
6439fc28 | 14017 | if (intel_syntax) |
6439fc28 AM |
14018 | { |
14019 | while (*++p != '|') | |
7c52e0e8 L |
14020 | if (*p == '}' || *p == '\0') |
14021 | abort (); | |
6439fc28 | 14022 | } |
9306ca4a JB |
14023 | /* Fall through. */ |
14024 | case 'I': | |
14025 | alt = 1; | |
14026 | continue; | |
6439fc28 AM |
14027 | case '|': |
14028 | while (*++p != '}') | |
14029 | { | |
14030 | if (*p == '\0') | |
14031 | abort (); | |
14032 | } | |
14033 | break; | |
14034 | case '}': | |
14035 | break; | |
252b5132 | 14036 | case 'A': |
db6eb5be AM |
14037 | if (intel_syntax) |
14038 | break; | |
7967e09e | 14039 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
14040 | *obufp++ = 'b'; |
14041 | break; | |
14042 | case 'B': | |
4b06377f L |
14043 | if (l == 0 && len == 1) |
14044 | { | |
14045 | case_B: | |
14046 | if (intel_syntax) | |
14047 | break; | |
14048 | if (sizeflag & SUFFIX_ALWAYS) | |
14049 | *obufp++ = 'b'; | |
14050 | } | |
14051 | else | |
14052 | { | |
14053 | if (l != 1 | |
14054 | || len != 2 | |
14055 | || last[0] != 'L') | |
14056 | { | |
14057 | SAVE_LAST (*p); | |
14058 | break; | |
14059 | } | |
14060 | ||
14061 | if (address_mode == mode_64bit | |
14062 | && !(prefixes & PREFIX_ADDR)) | |
14063 | { | |
14064 | *obufp++ = 'a'; | |
14065 | *obufp++ = 'b'; | |
14066 | *obufp++ = 's'; | |
14067 | } | |
14068 | ||
14069 | goto case_B; | |
14070 | } | |
252b5132 | 14071 | break; |
9306ca4a JB |
14072 | case 'C': |
14073 | if (intel_syntax && !alt) | |
14074 | break; | |
14075 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14076 | { | |
14077 | if (sizeflag & DFLAG) | |
14078 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14079 | else | |
14080 | *obufp++ = intel_syntax ? 'w' : 's'; | |
14081 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14082 | } | |
14083 | break; | |
ed7841b3 JB |
14084 | case 'D': |
14085 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
14086 | break; | |
161a04f6 | 14087 | USED_REX (REX_W); |
7967e09e | 14088 | if (modrm.mod == 3) |
ed7841b3 | 14089 | { |
161a04f6 | 14090 | if (rex & REX_W) |
ed7841b3 | 14091 | *obufp++ = 'q'; |
ed7841b3 | 14092 | else |
f16cd0d5 L |
14093 | { |
14094 | if (sizeflag & DFLAG) | |
14095 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14096 | else | |
14097 | *obufp++ = 'w'; | |
14098 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14099 | } | |
ed7841b3 JB |
14100 | } |
14101 | else | |
14102 | *obufp++ = 'w'; | |
14103 | break; | |
252b5132 | 14104 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 14105 | if (address_mode == mode_64bit) |
c1a64871 JH |
14106 | { |
14107 | if (sizeflag & AFLAG) | |
14108 | *obufp++ = 'r'; | |
14109 | else | |
14110 | *obufp++ = 'e'; | |
14111 | } | |
14112 | else | |
14113 | if (sizeflag & AFLAG) | |
14114 | *obufp++ = 'e'; | |
3ffd33cf AM |
14115 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14116 | break; | |
14117 | case 'F': | |
db6eb5be AM |
14118 | if (intel_syntax) |
14119 | break; | |
e396998b | 14120 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
14121 | { |
14122 | if (sizeflag & AFLAG) | |
cb712a9e | 14123 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 14124 | else |
cb712a9e | 14125 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
14126 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14127 | } | |
252b5132 | 14128 | break; |
52fd6d94 JB |
14129 | case 'G': |
14130 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
14131 | break; | |
161a04f6 | 14132 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14133 | *obufp++ = 'l'; |
14134 | else | |
14135 | *obufp++ = 'w'; | |
161a04f6 | 14136 | if (!(rex & REX_W)) |
52fd6d94 JB |
14137 | used_prefixes |= (prefixes & PREFIX_DATA); |
14138 | break; | |
5dd0794d | 14139 | case 'H': |
db6eb5be AM |
14140 | if (intel_syntax) |
14141 | break; | |
5dd0794d AM |
14142 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14143 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
14144 | { | |
14145 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
14146 | *obufp++ = ','; | |
14147 | *obufp++ = 'p'; | |
14148 | if (prefixes & PREFIX_DS) | |
14149 | *obufp++ = 't'; | |
14150 | else | |
14151 | *obufp++ = 'n'; | |
14152 | } | |
14153 | break; | |
9306ca4a JB |
14154 | case 'J': |
14155 | if (intel_syntax) | |
14156 | break; | |
14157 | *obufp++ = 'l'; | |
14158 | break; | |
42903f7f L |
14159 | case 'K': |
14160 | USED_REX (REX_W); | |
14161 | if (rex & REX_W) | |
14162 | *obufp++ = 'q'; | |
14163 | else | |
14164 | *obufp++ = 'd'; | |
14165 | break; | |
6dd5059a | 14166 | case 'Z': |
04d824a4 JB |
14167 | if (l != 0 || len != 1) |
14168 | { | |
14169 | if (l != 1 || len != 2 || last[0] != 'X') | |
14170 | { | |
14171 | SAVE_LAST (*p); | |
14172 | break; | |
14173 | } | |
14174 | if (!need_vex || !vex.evex) | |
14175 | abort (); | |
14176 | if (intel_syntax | |
14177 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
14178 | break; | |
14179 | switch (vex.length) | |
14180 | { | |
14181 | case 128: | |
14182 | *obufp++ = 'x'; | |
14183 | break; | |
14184 | case 256: | |
14185 | *obufp++ = 'y'; | |
14186 | break; | |
14187 | case 512: | |
14188 | *obufp++ = 'z'; | |
14189 | break; | |
14190 | default: | |
14191 | abort (); | |
14192 | } | |
14193 | break; | |
14194 | } | |
6dd5059a L |
14195 | if (intel_syntax) |
14196 | break; | |
14197 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
14198 | { | |
14199 | *obufp++ = 'q'; | |
14200 | break; | |
14201 | } | |
14202 | /* Fall through. */ | |
98b528ac | 14203 | goto case_L; |
252b5132 | 14204 | case 'L': |
98b528ac L |
14205 | if (l != 0 || len != 1) |
14206 | { | |
14207 | SAVE_LAST (*p); | |
14208 | break; | |
14209 | } | |
14210 | case_L: | |
db6eb5be AM |
14211 | if (intel_syntax) |
14212 | break; | |
252b5132 RH |
14213 | if (sizeflag & SUFFIX_ALWAYS) |
14214 | *obufp++ = 'l'; | |
252b5132 | 14215 | break; |
9d141669 L |
14216 | case 'M': |
14217 | if (intel_mnemonic != cond) | |
14218 | *obufp++ = 'r'; | |
14219 | break; | |
252b5132 RH |
14220 | case 'N': |
14221 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14222 | *obufp++ = 'n'; | |
7d421014 ILT |
14223 | else |
14224 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14225 | break; |
52b15da3 | 14226 | case 'O': |
161a04f6 L |
14227 | USED_REX (REX_W); |
14228 | if (rex & REX_W) | |
6439fc28 | 14229 | *obufp++ = 'o'; |
a35ca55a JB |
14230 | else if (intel_syntax && (sizeflag & DFLAG)) |
14231 | *obufp++ = 'q'; | |
52b15da3 JH |
14232 | else |
14233 | *obufp++ = 'd'; | |
161a04f6 | 14234 | if (!(rex & REX_W)) |
a35ca55a | 14235 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14236 | break; |
07f5af7d L |
14237 | case '&': |
14238 | if (!intel_syntax | |
14239 | && address_mode == mode_64bit | |
14240 | && isa64 == intel64) | |
14241 | { | |
14242 | *obufp++ = 'q'; | |
14243 | break; | |
14244 | } | |
14245 | /* Fall through. */ | |
6439fc28 | 14246 | case 'T': |
d9e3625e L |
14247 | if (!intel_syntax |
14248 | && address_mode == mode_64bit | |
7bb15c6f | 14249 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14250 | { |
14251 | *obufp++ = 'q'; | |
14252 | break; | |
14253 | } | |
6608db57 | 14254 | /* Fall through. */ |
4b4c407a | 14255 | goto case_P; |
252b5132 | 14256 | case 'P': |
4b4c407a | 14257 | if (l == 0 && len == 1) |
d9e3625e | 14258 | { |
4b4c407a L |
14259 | case_P: |
14260 | if (intel_syntax) | |
d9e3625e | 14261 | { |
4b4c407a L |
14262 | if ((rex & REX_W) == 0 |
14263 | && (prefixes & PREFIX_DATA)) | |
14264 | { | |
14265 | if ((sizeflag & DFLAG) == 0) | |
14266 | *obufp++ = 'w'; | |
14267 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14268 | } | |
14269 | break; | |
14270 | } | |
14271 | if ((prefixes & PREFIX_DATA) | |
14272 | || (rex & REX_W) | |
14273 | || (sizeflag & SUFFIX_ALWAYS)) | |
14274 | { | |
14275 | USED_REX (REX_W); | |
14276 | if (rex & REX_W) | |
14277 | *obufp++ = 'q'; | |
14278 | else | |
14279 | { | |
14280 | if (sizeflag & DFLAG) | |
14281 | *obufp++ = 'l'; | |
14282 | else | |
14283 | *obufp++ = 'w'; | |
14284 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14285 | } | |
d9e3625e | 14286 | } |
d9e3625e | 14287 | } |
4b4c407a | 14288 | else |
252b5132 | 14289 | { |
4b4c407a L |
14290 | if (l != 1 || len != 2 || last[0] != 'L') |
14291 | { | |
14292 | SAVE_LAST (*p); | |
14293 | break; | |
14294 | } | |
14295 | ||
14296 | if ((prefixes & PREFIX_DATA) | |
14297 | || (rex & REX_W) | |
14298 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14299 | { |
4b4c407a L |
14300 | USED_REX (REX_W); |
14301 | if (rex & REX_W) | |
14302 | *obufp++ = 'q'; | |
14303 | else | |
14304 | { | |
14305 | if (sizeflag & DFLAG) | |
14306 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14307 | else | |
14308 | *obufp++ = 'w'; | |
14309 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14310 | } | |
52b15da3 | 14311 | } |
252b5132 RH |
14312 | } |
14313 | break; | |
6439fc28 | 14314 | case 'U': |
db6eb5be AM |
14315 | if (intel_syntax) |
14316 | break; | |
7bb15c6f | 14317 | if (address_mode == mode_64bit |
6c067bbb | 14318 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14319 | { |
7967e09e | 14320 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14321 | *obufp++ = 'q'; |
6439fc28 AM |
14322 | break; |
14323 | } | |
6608db57 | 14324 | /* Fall through. */ |
98b528ac | 14325 | goto case_Q; |
252b5132 | 14326 | case 'Q': |
98b528ac | 14327 | if (l == 0 && len == 1) |
252b5132 | 14328 | { |
98b528ac L |
14329 | case_Q: |
14330 | if (intel_syntax && !alt) | |
14331 | break; | |
14332 | USED_REX (REX_W); | |
14333 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14334 | { |
98b528ac L |
14335 | if (rex & REX_W) |
14336 | *obufp++ = 'q'; | |
52b15da3 | 14337 | else |
98b528ac L |
14338 | { |
14339 | if (sizeflag & DFLAG) | |
14340 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14341 | else | |
14342 | *obufp++ = 'w'; | |
f16cd0d5 | 14343 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14344 | } |
52b15da3 | 14345 | } |
98b528ac L |
14346 | } |
14347 | else | |
14348 | { | |
14349 | if (l != 1 || len != 2 || last[0] != 'L') | |
14350 | { | |
14351 | SAVE_LAST (*p); | |
14352 | break; | |
14353 | } | |
14354 | if (intel_syntax | |
14355 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14356 | break; | |
14357 | if ((rex & REX_W)) | |
14358 | { | |
14359 | USED_REX (REX_W); | |
14360 | *obufp++ = 'q'; | |
14361 | } | |
14362 | else | |
14363 | *obufp++ = 'l'; | |
252b5132 RH |
14364 | } |
14365 | break; | |
14366 | case 'R': | |
161a04f6 L |
14367 | USED_REX (REX_W); |
14368 | if (rex & REX_W) | |
a35ca55a JB |
14369 | *obufp++ = 'q'; |
14370 | else if (sizeflag & DFLAG) | |
c608c12e | 14371 | { |
a35ca55a | 14372 | if (intel_syntax) |
c608c12e | 14373 | *obufp++ = 'd'; |
c608c12e | 14374 | else |
a35ca55a | 14375 | *obufp++ = 'l'; |
c608c12e | 14376 | } |
252b5132 | 14377 | else |
a35ca55a JB |
14378 | *obufp++ = 'w'; |
14379 | if (intel_syntax && !p[1] | |
161a04f6 | 14380 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14381 | *obufp++ = 'e'; |
161a04f6 | 14382 | if (!(rex & REX_W)) |
52b15da3 | 14383 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14384 | break; |
1a114b12 | 14385 | case 'V': |
4b06377f | 14386 | if (l == 0 && len == 1) |
1a114b12 | 14387 | { |
4b06377f L |
14388 | if (intel_syntax) |
14389 | break; | |
7bb15c6f | 14390 | if (address_mode == mode_64bit |
6c067bbb | 14391 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14392 | { |
14393 | if (sizeflag & SUFFIX_ALWAYS) | |
14394 | *obufp++ = 'q'; | |
14395 | break; | |
14396 | } | |
14397 | } | |
14398 | else | |
14399 | { | |
14400 | if (l != 1 | |
14401 | || len != 2 | |
14402 | || last[0] != 'L') | |
14403 | { | |
14404 | SAVE_LAST (*p); | |
14405 | break; | |
14406 | } | |
14407 | ||
14408 | if (rex & REX_W) | |
14409 | { | |
14410 | *obufp++ = 'a'; | |
14411 | *obufp++ = 'b'; | |
14412 | *obufp++ = 's'; | |
14413 | } | |
1a114b12 JB |
14414 | } |
14415 | /* Fall through. */ | |
4b06377f | 14416 | goto case_S; |
252b5132 | 14417 | case 'S': |
4b06377f | 14418 | if (l == 0 && len == 1) |
252b5132 | 14419 | { |
4b06377f L |
14420 | case_S: |
14421 | if (intel_syntax) | |
14422 | break; | |
14423 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14424 | { |
4b06377f L |
14425 | if (rex & REX_W) |
14426 | *obufp++ = 'q'; | |
52b15da3 | 14427 | else |
4b06377f L |
14428 | { |
14429 | if (sizeflag & DFLAG) | |
14430 | *obufp++ = 'l'; | |
14431 | else | |
14432 | *obufp++ = 'w'; | |
14433 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14434 | } | |
14435 | } | |
14436 | } | |
14437 | else | |
14438 | { | |
14439 | if (l != 1 | |
14440 | || len != 2 | |
14441 | || last[0] != 'L') | |
14442 | { | |
14443 | SAVE_LAST (*p); | |
14444 | break; | |
52b15da3 | 14445 | } |
4b06377f L |
14446 | |
14447 | if (address_mode == mode_64bit | |
14448 | && !(prefixes & PREFIX_ADDR)) | |
14449 | { | |
14450 | *obufp++ = 'a'; | |
14451 | *obufp++ = 'b'; | |
14452 | *obufp++ = 's'; | |
14453 | } | |
14454 | ||
14455 | goto case_S; | |
252b5132 | 14456 | } |
252b5132 | 14457 | break; |
041bd2e0 | 14458 | case 'X': |
c0f3af97 L |
14459 | if (l != 0 || len != 1) |
14460 | { | |
14461 | SAVE_LAST (*p); | |
14462 | break; | |
14463 | } | |
14464 | if (need_vex && vex.prefix) | |
14465 | { | |
14466 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14467 | *obufp++ = 'd'; | |
14468 | else | |
14469 | *obufp++ = 's'; | |
14470 | } | |
041bd2e0 | 14471 | else |
f16cd0d5 L |
14472 | { |
14473 | if (prefixes & PREFIX_DATA) | |
14474 | *obufp++ = 'd'; | |
14475 | else | |
14476 | *obufp++ = 's'; | |
14477 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14478 | } | |
041bd2e0 | 14479 | break; |
76f227a5 | 14480 | case 'Y': |
c0f3af97 | 14481 | if (l == 0 && len == 1) |
9646c87b | 14482 | abort (); |
c0f3af97 L |
14483 | else |
14484 | { | |
14485 | if (l != 1 || len != 2 || last[0] != 'X') | |
14486 | { | |
14487 | SAVE_LAST (*p); | |
14488 | break; | |
14489 | } | |
14490 | if (!need_vex) | |
14491 | abort (); | |
14492 | if (intel_syntax | |
04d824a4 | 14493 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14494 | break; |
14495 | switch (vex.length) | |
14496 | { | |
14497 | case 128: | |
14498 | *obufp++ = 'x'; | |
14499 | break; | |
14500 | case 256: | |
14501 | *obufp++ = 'y'; | |
14502 | break; | |
04d824a4 JB |
14503 | case 512: |
14504 | if (!vex.evex) | |
c0f3af97 | 14505 | default: |
04d824a4 | 14506 | abort (); |
c0f3af97 | 14507 | } |
76f227a5 JH |
14508 | } |
14509 | break; | |
252b5132 | 14510 | case 'W': |
0bfee649 | 14511 | if (l == 0 && len == 1) |
a35ca55a | 14512 | { |
0bfee649 L |
14513 | /* operand size flag for cwtl, cbtw */ |
14514 | USED_REX (REX_W); | |
14515 | if (rex & REX_W) | |
14516 | { | |
14517 | if (intel_syntax) | |
14518 | *obufp++ = 'd'; | |
14519 | else | |
14520 | *obufp++ = 'l'; | |
14521 | } | |
14522 | else if (sizeflag & DFLAG) | |
14523 | *obufp++ = 'w'; | |
a35ca55a | 14524 | else |
0bfee649 L |
14525 | *obufp++ = 'b'; |
14526 | if (!(rex & REX_W)) | |
14527 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14528 | } |
252b5132 | 14529 | else |
0bfee649 | 14530 | { |
6c30d220 L |
14531 | if (l != 1 |
14532 | || len != 2 | |
14533 | || (last[0] != 'X' | |
14534 | && last[0] != 'L')) | |
0bfee649 L |
14535 | { |
14536 | SAVE_LAST (*p); | |
14537 | break; | |
14538 | } | |
14539 | if (!need_vex) | |
14540 | abort (); | |
6c30d220 L |
14541 | if (last[0] == 'X') |
14542 | *obufp++ = vex.w ? 'd': 's'; | |
14543 | else | |
14544 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14545 | } |
252b5132 | 14546 | break; |
a72d2af2 L |
14547 | case '^': |
14548 | if (intel_syntax) | |
14549 | break; | |
14550 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14551 | { | |
14552 | if (sizeflag & DFLAG) | |
14553 | *obufp++ = 'l'; | |
14554 | else | |
14555 | *obufp++ = 'w'; | |
14556 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14557 | } | |
14558 | break; | |
5db04b09 L |
14559 | case '@': |
14560 | if (intel_syntax) | |
14561 | break; | |
14562 | if (address_mode == mode_64bit | |
14563 | && (isa64 == intel64 | |
14564 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14565 | *obufp++ = 'q'; | |
14566 | else if ((prefixes & PREFIX_DATA)) | |
14567 | { | |
14568 | if (!(sizeflag & DFLAG)) | |
14569 | *obufp++ = 'w'; | |
14570 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14571 | } | |
14572 | break; | |
252b5132 | 14573 | } |
9306ca4a | 14574 | alt = 0; |
252b5132 RH |
14575 | } |
14576 | *obufp = 0; | |
ea397f5b | 14577 | mnemonicendp = obufp; |
6439fc28 | 14578 | return 0; |
252b5132 RH |
14579 | } |
14580 | ||
14581 | static void | |
26ca5450 | 14582 | oappend (const char *s) |
252b5132 | 14583 | { |
ea397f5b | 14584 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14585 | } |
14586 | ||
14587 | static void | |
26ca5450 | 14588 | append_seg (void) |
252b5132 | 14589 | { |
285ca992 L |
14590 | /* Only print the active segment register. */ |
14591 | if (!active_seg_prefix) | |
14592 | return; | |
14593 | ||
14594 | used_prefixes |= active_seg_prefix; | |
14595 | switch (active_seg_prefix) | |
7d421014 | 14596 | { |
285ca992 | 14597 | case PREFIX_CS: |
9ce09ba2 | 14598 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14599 | break; |
14600 | case PREFIX_DS: | |
9ce09ba2 | 14601 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14602 | break; |
14603 | case PREFIX_SS: | |
9ce09ba2 | 14604 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14605 | break; |
14606 | case PREFIX_ES: | |
9ce09ba2 | 14607 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14608 | break; |
14609 | case PREFIX_FS: | |
9ce09ba2 | 14610 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14611 | break; |
14612 | case PREFIX_GS: | |
9ce09ba2 | 14613 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14614 | break; |
14615 | default: | |
14616 | break; | |
7d421014 | 14617 | } |
252b5132 RH |
14618 | } |
14619 | ||
14620 | static void | |
26ca5450 | 14621 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14622 | { |
14623 | if (!intel_syntax) | |
14624 | oappend ("*"); | |
14625 | OP_E (bytemode, sizeflag); | |
14626 | } | |
14627 | ||
52b15da3 | 14628 | static void |
26ca5450 | 14629 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14630 | { |
cb712a9e | 14631 | if (address_mode == mode_64bit) |
52b15da3 JH |
14632 | { |
14633 | if (hex) | |
14634 | { | |
14635 | char tmp[30]; | |
14636 | int i; | |
14637 | buf[0] = '0'; | |
14638 | buf[1] = 'x'; | |
14639 | sprintf_vma (tmp, disp); | |
6608db57 | 14640 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14641 | strcpy (buf + 2, tmp + i); |
14642 | } | |
14643 | else | |
14644 | { | |
14645 | bfd_signed_vma v = disp; | |
14646 | char tmp[30]; | |
14647 | int i; | |
14648 | if (v < 0) | |
14649 | { | |
14650 | *(buf++) = '-'; | |
14651 | v = -disp; | |
6608db57 | 14652 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14653 | if (v < 0) |
14654 | { | |
14655 | strcpy (buf, "9223372036854775808"); | |
14656 | return; | |
14657 | } | |
14658 | } | |
14659 | if (!v) | |
14660 | { | |
14661 | strcpy (buf, "0"); | |
14662 | return; | |
14663 | } | |
14664 | ||
14665 | i = 0; | |
14666 | tmp[29] = 0; | |
14667 | while (v) | |
14668 | { | |
6608db57 | 14669 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14670 | v /= 10; |
14671 | i++; | |
14672 | } | |
14673 | strcpy (buf, tmp + 29 - i); | |
14674 | } | |
14675 | } | |
14676 | else | |
14677 | { | |
14678 | if (hex) | |
14679 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14680 | else | |
14681 | sprintf (buf, "%d", (int) disp); | |
14682 | } | |
14683 | } | |
14684 | ||
5d669648 L |
14685 | /* Put DISP in BUF as signed hex number. */ |
14686 | ||
14687 | static void | |
14688 | print_displacement (char *buf, bfd_vma disp) | |
14689 | { | |
14690 | bfd_signed_vma val = disp; | |
14691 | char tmp[30]; | |
14692 | int i, j = 0; | |
14693 | ||
14694 | if (val < 0) | |
14695 | { | |
14696 | buf[j++] = '-'; | |
14697 | val = -disp; | |
14698 | ||
14699 | /* Check for possible overflow. */ | |
14700 | if (val < 0) | |
14701 | { | |
14702 | switch (address_mode) | |
14703 | { | |
14704 | case mode_64bit: | |
14705 | strcpy (buf + j, "0x8000000000000000"); | |
14706 | break; | |
14707 | case mode_32bit: | |
14708 | strcpy (buf + j, "0x80000000"); | |
14709 | break; | |
14710 | case mode_16bit: | |
14711 | strcpy (buf + j, "0x8000"); | |
14712 | break; | |
14713 | } | |
14714 | return; | |
14715 | } | |
14716 | } | |
14717 | ||
14718 | buf[j++] = '0'; | |
14719 | buf[j++] = 'x'; | |
14720 | ||
0af1713e | 14721 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14722 | for (i = 0; tmp[i] == '0'; i++) |
14723 | continue; | |
14724 | if (tmp[i] == '\0') | |
14725 | i--; | |
14726 | strcpy (buf + j, tmp + i); | |
14727 | } | |
14728 | ||
3f31e633 JB |
14729 | static void |
14730 | intel_operand_size (int bytemode, int sizeflag) | |
14731 | { | |
43234a1e L |
14732 | if (vex.evex |
14733 | && vex.b | |
14734 | && (bytemode == x_mode | |
14735 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14736 | { | |
14737 | if (vex.w) | |
14738 | oappend ("QWORD PTR "); | |
14739 | else | |
14740 | oappend ("DWORD PTR "); | |
14741 | return; | |
14742 | } | |
3f31e633 JB |
14743 | switch (bytemode) |
14744 | { | |
14745 | case b_mode: | |
b6169b20 | 14746 | case b_swap_mode: |
42903f7f | 14747 | case dqb_mode: |
1ba585e8 | 14748 | case db_mode: |
3f31e633 JB |
14749 | oappend ("BYTE PTR "); |
14750 | break; | |
14751 | case w_mode: | |
1ba585e8 | 14752 | case dw_mode: |
3f31e633 JB |
14753 | case dqw_mode: |
14754 | oappend ("WORD PTR "); | |
14755 | break; | |
07f5af7d L |
14756 | case indir_v_mode: |
14757 | if (address_mode == mode_64bit && isa64 == intel64) | |
14758 | { | |
14759 | oappend ("QWORD PTR "); | |
14760 | break; | |
14761 | } | |
1a0670f3 | 14762 | /* Fall through. */ |
1a114b12 | 14763 | case stack_v_mode: |
7bb15c6f | 14764 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14765 | { |
14766 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14767 | break; |
14768 | } | |
1a0670f3 | 14769 | /* Fall through. */ |
3f31e633 | 14770 | case v_mode: |
b6169b20 | 14771 | case v_swap_mode: |
3f31e633 | 14772 | case dq_mode: |
161a04f6 L |
14773 | USED_REX (REX_W); |
14774 | if (rex & REX_W) | |
3f31e633 | 14775 | oappend ("QWORD PTR "); |
3f31e633 | 14776 | else |
f16cd0d5 L |
14777 | { |
14778 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14779 | oappend ("DWORD PTR "); | |
14780 | else | |
14781 | oappend ("WORD PTR "); | |
14782 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14783 | } | |
3f31e633 | 14784 | break; |
52fd6d94 | 14785 | case z_mode: |
161a04f6 | 14786 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14787 | *obufp++ = 'D'; |
14788 | oappend ("WORD PTR "); | |
161a04f6 | 14789 | if (!(rex & REX_W)) |
52fd6d94 JB |
14790 | used_prefixes |= (prefixes & PREFIX_DATA); |
14791 | break; | |
34b772a6 JB |
14792 | case a_mode: |
14793 | if (sizeflag & DFLAG) | |
14794 | oappend ("QWORD PTR "); | |
14795 | else | |
14796 | oappend ("DWORD PTR "); | |
14797 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14798 | break; | |
3f31e633 | 14799 | case d_mode: |
539f890d L |
14800 | case d_scalar_mode: |
14801 | case d_scalar_swap_mode: | |
fa99fab2 | 14802 | case d_swap_mode: |
42903f7f | 14803 | case dqd_mode: |
3f31e633 JB |
14804 | oappend ("DWORD PTR "); |
14805 | break; | |
14806 | case q_mode: | |
539f890d L |
14807 | case q_scalar_mode: |
14808 | case q_scalar_swap_mode: | |
b6169b20 | 14809 | case q_swap_mode: |
3f31e633 JB |
14810 | oappend ("QWORD PTR "); |
14811 | break; | |
d20dee9e | 14812 | case dqa_mode: |
3f31e633 | 14813 | case m_mode: |
cb712a9e | 14814 | if (address_mode == mode_64bit) |
3f31e633 JB |
14815 | oappend ("QWORD PTR "); |
14816 | else | |
14817 | oappend ("DWORD PTR "); | |
14818 | break; | |
14819 | case f_mode: | |
14820 | if (sizeflag & DFLAG) | |
14821 | oappend ("FWORD PTR "); | |
14822 | else | |
14823 | oappend ("DWORD PTR "); | |
14824 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14825 | break; | |
14826 | case t_mode: | |
14827 | oappend ("TBYTE PTR "); | |
14828 | break; | |
14829 | case x_mode: | |
b6169b20 | 14830 | case x_swap_mode: |
43234a1e L |
14831 | case evex_x_gscat_mode: |
14832 | case evex_x_nobcst_mode: | |
53467f57 IT |
14833 | case b_scalar_mode: |
14834 | case w_scalar_mode: | |
c0f3af97 L |
14835 | if (need_vex) |
14836 | { | |
14837 | switch (vex.length) | |
14838 | { | |
14839 | case 128: | |
14840 | oappend ("XMMWORD PTR "); | |
14841 | break; | |
14842 | case 256: | |
14843 | oappend ("YMMWORD PTR "); | |
14844 | break; | |
43234a1e L |
14845 | case 512: |
14846 | oappend ("ZMMWORD PTR "); | |
14847 | break; | |
c0f3af97 L |
14848 | default: |
14849 | abort (); | |
14850 | } | |
14851 | } | |
14852 | else | |
14853 | oappend ("XMMWORD PTR "); | |
14854 | break; | |
14855 | case xmm_mode: | |
3f31e633 JB |
14856 | oappend ("XMMWORD PTR "); |
14857 | break; | |
43234a1e L |
14858 | case ymm_mode: |
14859 | oappend ("YMMWORD PTR "); | |
14860 | break; | |
c0f3af97 | 14861 | case xmmq_mode: |
43234a1e | 14862 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14863 | if (!need_vex) |
14864 | abort (); | |
14865 | ||
14866 | switch (vex.length) | |
14867 | { | |
14868 | case 128: | |
14869 | oappend ("QWORD PTR "); | |
14870 | break; | |
14871 | case 256: | |
14872 | oappend ("XMMWORD PTR "); | |
14873 | break; | |
43234a1e L |
14874 | case 512: |
14875 | oappend ("YMMWORD PTR "); | |
14876 | break; | |
c0f3af97 L |
14877 | default: |
14878 | abort (); | |
14879 | } | |
14880 | break; | |
6c30d220 L |
14881 | case xmm_mb_mode: |
14882 | if (!need_vex) | |
14883 | abort (); | |
14884 | ||
14885 | switch (vex.length) | |
14886 | { | |
14887 | case 128: | |
14888 | case 256: | |
43234a1e | 14889 | case 512: |
6c30d220 L |
14890 | oappend ("BYTE PTR "); |
14891 | break; | |
14892 | default: | |
14893 | abort (); | |
14894 | } | |
14895 | break; | |
14896 | case xmm_mw_mode: | |
14897 | if (!need_vex) | |
14898 | abort (); | |
14899 | ||
14900 | switch (vex.length) | |
14901 | { | |
14902 | case 128: | |
14903 | case 256: | |
43234a1e | 14904 | case 512: |
6c30d220 L |
14905 | oappend ("WORD PTR "); |
14906 | break; | |
14907 | default: | |
14908 | abort (); | |
14909 | } | |
14910 | break; | |
14911 | case xmm_md_mode: | |
14912 | if (!need_vex) | |
14913 | abort (); | |
14914 | ||
14915 | switch (vex.length) | |
14916 | { | |
14917 | case 128: | |
14918 | case 256: | |
43234a1e | 14919 | case 512: |
6c30d220 L |
14920 | oappend ("DWORD PTR "); |
14921 | break; | |
14922 | default: | |
14923 | abort (); | |
14924 | } | |
14925 | break; | |
14926 | case xmm_mq_mode: | |
14927 | if (!need_vex) | |
14928 | abort (); | |
14929 | ||
14930 | switch (vex.length) | |
14931 | { | |
14932 | case 128: | |
14933 | case 256: | |
43234a1e | 14934 | case 512: |
6c30d220 L |
14935 | oappend ("QWORD PTR "); |
14936 | break; | |
14937 | default: | |
14938 | abort (); | |
14939 | } | |
14940 | break; | |
14941 | case xmmdw_mode: | |
14942 | if (!need_vex) | |
14943 | abort (); | |
14944 | ||
14945 | switch (vex.length) | |
14946 | { | |
14947 | case 128: | |
14948 | oappend ("WORD PTR "); | |
14949 | break; | |
14950 | case 256: | |
14951 | oappend ("DWORD PTR "); | |
14952 | break; | |
43234a1e L |
14953 | case 512: |
14954 | oappend ("QWORD PTR "); | |
14955 | break; | |
6c30d220 L |
14956 | default: |
14957 | abort (); | |
14958 | } | |
14959 | break; | |
14960 | case xmmqd_mode: | |
14961 | if (!need_vex) | |
14962 | abort (); | |
14963 | ||
14964 | switch (vex.length) | |
14965 | { | |
14966 | case 128: | |
14967 | oappend ("DWORD PTR "); | |
14968 | break; | |
14969 | case 256: | |
14970 | oappend ("QWORD PTR "); | |
14971 | break; | |
43234a1e L |
14972 | case 512: |
14973 | oappend ("XMMWORD PTR "); | |
14974 | break; | |
6c30d220 L |
14975 | default: |
14976 | abort (); | |
14977 | } | |
14978 | break; | |
c0f3af97 L |
14979 | case ymmq_mode: |
14980 | if (!need_vex) | |
14981 | abort (); | |
14982 | ||
14983 | switch (vex.length) | |
14984 | { | |
14985 | case 128: | |
14986 | oappend ("QWORD PTR "); | |
14987 | break; | |
14988 | case 256: | |
14989 | oappend ("YMMWORD PTR "); | |
14990 | break; | |
43234a1e L |
14991 | case 512: |
14992 | oappend ("ZMMWORD PTR "); | |
14993 | break; | |
c0f3af97 L |
14994 | default: |
14995 | abort (); | |
14996 | } | |
14997 | break; | |
6c30d220 L |
14998 | case ymmxmm_mode: |
14999 | if (!need_vex) | |
15000 | abort (); | |
15001 | ||
15002 | switch (vex.length) | |
15003 | { | |
15004 | case 128: | |
15005 | case 256: | |
15006 | oappend ("XMMWORD PTR "); | |
15007 | break; | |
15008 | default: | |
15009 | abort (); | |
15010 | } | |
15011 | break; | |
fb9c77c7 L |
15012 | case o_mode: |
15013 | oappend ("OWORD PTR "); | |
15014 | break; | |
43234a1e | 15015 | case xmm_mdq_mode: |
0bfee649 | 15016 | case vex_w_dq_mode: |
1c480963 | 15017 | case vex_scalar_w_dq_mode: |
0bfee649 L |
15018 | if (!need_vex) |
15019 | abort (); | |
15020 | ||
15021 | if (vex.w) | |
15022 | oappend ("QWORD PTR "); | |
15023 | else | |
15024 | oappend ("DWORD PTR "); | |
15025 | break; | |
43234a1e L |
15026 | case vex_vsib_d_w_dq_mode: |
15027 | case vex_vsib_q_w_dq_mode: | |
15028 | if (!need_vex) | |
15029 | abort (); | |
15030 | ||
15031 | if (!vex.evex) | |
15032 | { | |
15033 | if (vex.w) | |
15034 | oappend ("QWORD PTR "); | |
15035 | else | |
15036 | oappend ("DWORD PTR "); | |
15037 | } | |
15038 | else | |
15039 | { | |
b28d1bda IT |
15040 | switch (vex.length) |
15041 | { | |
15042 | case 128: | |
15043 | oappend ("XMMWORD PTR "); | |
15044 | break; | |
15045 | case 256: | |
15046 | oappend ("YMMWORD PTR "); | |
15047 | break; | |
15048 | case 512: | |
15049 | oappend ("ZMMWORD PTR "); | |
15050 | break; | |
15051 | default: | |
15052 | abort (); | |
15053 | } | |
43234a1e L |
15054 | } |
15055 | break; | |
5fc35d96 IT |
15056 | case vex_vsib_q_w_d_mode: |
15057 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 15058 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
15059 | abort (); |
15060 | ||
b28d1bda IT |
15061 | switch (vex.length) |
15062 | { | |
15063 | case 128: | |
15064 | oappend ("QWORD PTR "); | |
15065 | break; | |
15066 | case 256: | |
15067 | oappend ("XMMWORD PTR "); | |
15068 | break; | |
15069 | case 512: | |
15070 | oappend ("YMMWORD PTR "); | |
15071 | break; | |
15072 | default: | |
15073 | abort (); | |
15074 | } | |
5fc35d96 IT |
15075 | |
15076 | break; | |
1ba585e8 IT |
15077 | case mask_bd_mode: |
15078 | if (!need_vex || vex.length != 128) | |
15079 | abort (); | |
15080 | if (vex.w) | |
15081 | oappend ("DWORD PTR "); | |
15082 | else | |
15083 | oappend ("BYTE PTR "); | |
15084 | break; | |
43234a1e L |
15085 | case mask_mode: |
15086 | if (!need_vex) | |
15087 | abort (); | |
1ba585e8 IT |
15088 | if (vex.w) |
15089 | oappend ("QWORD PTR "); | |
15090 | else | |
15091 | oappend ("WORD PTR "); | |
43234a1e | 15092 | break; |
6c75cc62 | 15093 | case v_bnd_mode: |
d276ec69 | 15094 | case v_bndmk_mode: |
3f31e633 JB |
15095 | default: |
15096 | break; | |
15097 | } | |
15098 | } | |
15099 | ||
252b5132 | 15100 | static void |
c0f3af97 | 15101 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 15102 | { |
c0f3af97 L |
15103 | int reg = modrm.rm; |
15104 | const char **names; | |
252b5132 | 15105 | |
c0f3af97 L |
15106 | USED_REX (REX_B); |
15107 | if ((rex & REX_B)) | |
15108 | reg += 8; | |
252b5132 | 15109 | |
b6169b20 | 15110 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 15111 | && (bytemode == b_swap_mode |
9f79e886 | 15112 | || bytemode == bnd_swap_mode |
60227d64 | 15113 | || bytemode == v_swap_mode)) |
b6169b20 L |
15114 | swap_operand (); |
15115 | ||
c0f3af97 | 15116 | switch (bytemode) |
252b5132 | 15117 | { |
c0f3af97 | 15118 | case b_mode: |
b6169b20 | 15119 | case b_swap_mode: |
c0f3af97 L |
15120 | USED_REX (0); |
15121 | if (rex) | |
15122 | names = names8rex; | |
15123 | else | |
15124 | names = names8; | |
15125 | break; | |
15126 | case w_mode: | |
15127 | names = names16; | |
15128 | break; | |
15129 | case d_mode: | |
1ba585e8 IT |
15130 | case dw_mode: |
15131 | case db_mode: | |
c0f3af97 L |
15132 | names = names32; |
15133 | break; | |
15134 | case q_mode: | |
15135 | names = names64; | |
15136 | break; | |
15137 | case m_mode: | |
6c75cc62 | 15138 | case v_bnd_mode: |
c0f3af97 L |
15139 | names = address_mode == mode_64bit ? names64 : names32; |
15140 | break; | |
7e8b059b | 15141 | case bnd_mode: |
9f79e886 | 15142 | case bnd_swap_mode: |
0d96e4df L |
15143 | if (reg > 0x3) |
15144 | { | |
15145 | oappend ("(bad)"); | |
15146 | return; | |
15147 | } | |
7e8b059b L |
15148 | names = names_bnd; |
15149 | break; | |
07f5af7d L |
15150 | case indir_v_mode: |
15151 | if (address_mode == mode_64bit && isa64 == intel64) | |
15152 | { | |
15153 | names = names64; | |
15154 | break; | |
15155 | } | |
1a0670f3 | 15156 | /* Fall through. */ |
c0f3af97 | 15157 | case stack_v_mode: |
7bb15c6f | 15158 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 15159 | { |
c0f3af97 | 15160 | names = names64; |
252b5132 | 15161 | break; |
252b5132 | 15162 | } |
c0f3af97 | 15163 | bytemode = v_mode; |
1a0670f3 | 15164 | /* Fall through. */ |
c0f3af97 | 15165 | case v_mode: |
b6169b20 | 15166 | case v_swap_mode: |
c0f3af97 L |
15167 | case dq_mode: |
15168 | case dqb_mode: | |
15169 | case dqd_mode: | |
15170 | case dqw_mode: | |
d20dee9e | 15171 | case dqa_mode: |
c0f3af97 L |
15172 | USED_REX (REX_W); |
15173 | if (rex & REX_W) | |
15174 | names = names64; | |
c0f3af97 | 15175 | else |
f16cd0d5 | 15176 | { |
7bb15c6f | 15177 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
15178 | || (bytemode != v_mode |
15179 | && bytemode != v_swap_mode)) | |
15180 | names = names32; | |
15181 | else | |
15182 | names = names16; | |
15183 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15184 | } | |
c0f3af97 | 15185 | break; |
de89d0a3 IT |
15186 | case va_mode: |
15187 | names = (address_mode == mode_64bit | |
15188 | ? names64 : names32); | |
15189 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
15190 | names = (address_mode == mode_16bit |
15191 | ? names16 : names); | |
de89d0a3 IT |
15192 | else |
15193 | { | |
15194 | /* Remove "addr16/addr32". */ | |
15195 | all_prefixes[last_addr_prefix] = 0; | |
15196 | names = (address_mode != mode_32bit | |
15197 | ? names32 : names16); | |
15198 | used_prefixes |= PREFIX_ADDR; | |
15199 | } | |
15200 | break; | |
1ba585e8 | 15201 | case mask_bd_mode: |
43234a1e | 15202 | case mask_mode: |
9889cbb1 L |
15203 | if (reg > 0x7) |
15204 | { | |
15205 | oappend ("(bad)"); | |
15206 | return; | |
15207 | } | |
43234a1e L |
15208 | names = names_mask; |
15209 | break; | |
c0f3af97 L |
15210 | case 0: |
15211 | return; | |
15212 | default: | |
15213 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
15214 | return; |
15215 | } | |
c0f3af97 L |
15216 | oappend (names[reg]); |
15217 | } | |
15218 | ||
15219 | static void | |
c1e679ec | 15220 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
15221 | { |
15222 | bfd_vma disp = 0; | |
15223 | int add = (rex & REX_B) ? 8 : 0; | |
15224 | int riprel = 0; | |
43234a1e L |
15225 | int shift; |
15226 | ||
15227 | if (vex.evex) | |
15228 | { | |
15229 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
15230 | if (vex.b | |
15231 | && bytemode != x_mode | |
90a915bf | 15232 | && bytemode != xmmq_mode |
43234a1e L |
15233 | && bytemode != evex_half_bcst_xmmq_mode) |
15234 | { | |
15235 | BadOp (); | |
15236 | return; | |
15237 | } | |
15238 | switch (bytemode) | |
15239 | { | |
1ba585e8 IT |
15240 | case dqw_mode: |
15241 | case dw_mode: | |
1ba585e8 IT |
15242 | shift = 1; |
15243 | break; | |
15244 | case dqb_mode: | |
15245 | case db_mode: | |
15246 | shift = 0; | |
15247 | break; | |
43234a1e | 15248 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15249 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15250 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15251 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15252 | case evex_x_gscat_mode: |
15253 | case xmm_mdq_mode: | |
15254 | shift = vex.w ? 3 : 2; | |
15255 | break; | |
43234a1e L |
15256 | case x_mode: |
15257 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15258 | case xmmq_mode: |
43234a1e L |
15259 | if (vex.b) |
15260 | { | |
15261 | shift = vex.w ? 3 : 2; | |
15262 | break; | |
15263 | } | |
1a0670f3 | 15264 | /* Fall through. */ |
43234a1e L |
15265 | case xmmqd_mode: |
15266 | case xmmdw_mode: | |
43234a1e L |
15267 | case ymmq_mode: |
15268 | case evex_x_nobcst_mode: | |
15269 | case x_swap_mode: | |
15270 | switch (vex.length) | |
15271 | { | |
15272 | case 128: | |
15273 | shift = 4; | |
15274 | break; | |
15275 | case 256: | |
15276 | shift = 5; | |
15277 | break; | |
15278 | case 512: | |
15279 | shift = 6; | |
15280 | break; | |
15281 | default: | |
15282 | abort (); | |
15283 | } | |
15284 | break; | |
15285 | case ymm_mode: | |
15286 | shift = 5; | |
15287 | break; | |
15288 | case xmm_mode: | |
15289 | shift = 4; | |
15290 | break; | |
15291 | case xmm_mq_mode: | |
15292 | case q_mode: | |
15293 | case q_scalar_mode: | |
15294 | case q_swap_mode: | |
15295 | case q_scalar_swap_mode: | |
15296 | shift = 3; | |
15297 | break; | |
15298 | case dqd_mode: | |
15299 | case xmm_md_mode: | |
15300 | case d_mode: | |
15301 | case d_scalar_mode: | |
15302 | case d_swap_mode: | |
15303 | case d_scalar_swap_mode: | |
15304 | shift = 2; | |
15305 | break; | |
5074ad8a | 15306 | case w_scalar_mode: |
43234a1e L |
15307 | case xmm_mw_mode: |
15308 | shift = 1; | |
15309 | break; | |
5074ad8a | 15310 | case b_scalar_mode: |
43234a1e L |
15311 | case xmm_mb_mode: |
15312 | shift = 0; | |
15313 | break; | |
d20dee9e L |
15314 | case dqa_mode: |
15315 | shift = address_mode == mode_64bit ? 3 : 2; | |
15316 | break; | |
43234a1e L |
15317 | default: |
15318 | abort (); | |
15319 | } | |
15320 | /* Make necessary corrections to shift for modes that need it. | |
15321 | For these modes we currently have shift 4, 5 or 6 depending on | |
15322 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15323 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15324 | xmmq_mode). In case of broadcast enabled the corrections | |
15325 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15326 | if (!vex.b |
15327 | && (bytemode == xmmq_mode | |
15328 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15329 | shift -= 1; |
15330 | else if (bytemode == xmmqd_mode) | |
15331 | shift -= 2; | |
15332 | else if (bytemode == xmmdw_mode) | |
15333 | shift -= 3; | |
b28d1bda IT |
15334 | else if (bytemode == ymmq_mode && vex.length == 128) |
15335 | shift -= 1; | |
43234a1e L |
15336 | } |
15337 | else | |
15338 | shift = 0; | |
252b5132 | 15339 | |
c0f3af97 | 15340 | USED_REX (REX_B); |
3f31e633 JB |
15341 | if (intel_syntax) |
15342 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15343 | append_seg (); |
15344 | ||
5d669648 | 15345 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15346 | { |
5d669648 L |
15347 | /* 32/64 bit address mode */ |
15348 | int havedisp; | |
252b5132 RH |
15349 | int havesib; |
15350 | int havebase; | |
0f7da397 | 15351 | int haveindex; |
20afcfb7 | 15352 | int needindex; |
1bc60e56 | 15353 | int needaddr32; |
82c18208 | 15354 | int base, rbase; |
91d6fa6a | 15355 | int vindex = 0; |
252b5132 | 15356 | int scale = 0; |
7e8b059b L |
15357 | int addr32flag = !((sizeflag & AFLAG) |
15358 | || bytemode == v_bnd_mode | |
d276ec69 | 15359 | || bytemode == v_bndmk_mode |
9f79e886 JB |
15360 | || bytemode == bnd_mode |
15361 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
15362 | const char **indexes64 = names64; |
15363 | const char **indexes32 = names32; | |
252b5132 RH |
15364 | |
15365 | havesib = 0; | |
15366 | havebase = 1; | |
0f7da397 | 15367 | haveindex = 0; |
7967e09e | 15368 | base = modrm.rm; |
252b5132 RH |
15369 | |
15370 | if (base == 4) | |
15371 | { | |
15372 | havesib = 1; | |
dfc8cf43 | 15373 | vindex = sib.index; |
161a04f6 L |
15374 | USED_REX (REX_X); |
15375 | if (rex & REX_X) | |
91d6fa6a | 15376 | vindex += 8; |
6c30d220 L |
15377 | switch (bytemode) |
15378 | { | |
15379 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15380 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15381 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15382 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15383 | if (!need_vex) |
15384 | abort (); | |
43234a1e L |
15385 | if (vex.evex) |
15386 | { | |
15387 | if (!vex.v) | |
15388 | vindex += 16; | |
15389 | } | |
6c30d220 L |
15390 | |
15391 | haveindex = 1; | |
15392 | switch (vex.length) | |
15393 | { | |
15394 | case 128: | |
7bb15c6f | 15395 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15396 | break; |
15397 | case 256: | |
5fc35d96 IT |
15398 | if (!vex.w |
15399 | || bytemode == vex_vsib_q_w_dq_mode | |
15400 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15401 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15402 | else |
7bb15c6f | 15403 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15404 | break; |
43234a1e | 15405 | case 512: |
5fc35d96 IT |
15406 | if (!vex.w |
15407 | || bytemode == vex_vsib_q_w_dq_mode | |
15408 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15409 | indexes64 = indexes32 = names_zmm; |
15410 | else | |
15411 | indexes64 = indexes32 = names_ymm; | |
15412 | break; | |
6c30d220 L |
15413 | default: |
15414 | abort (); | |
15415 | } | |
15416 | break; | |
15417 | default: | |
15418 | haveindex = vindex != 4; | |
15419 | break; | |
15420 | } | |
15421 | scale = sib.scale; | |
15422 | base = sib.base; | |
252b5132 RH |
15423 | codep++; |
15424 | } | |
82c18208 | 15425 | rbase = base + add; |
252b5132 | 15426 | |
7967e09e | 15427 | switch (modrm.mod) |
252b5132 RH |
15428 | { |
15429 | case 0: | |
82c18208 | 15430 | if (base == 5) |
252b5132 RH |
15431 | { |
15432 | havebase = 0; | |
cb712a9e | 15433 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15434 | riprel = 1; |
15435 | disp = get32s (); | |
d276ec69 JB |
15436 | if (riprel && bytemode == v_bndmk_mode) |
15437 | { | |
15438 | oappend ("(bad)"); | |
15439 | return; | |
15440 | } | |
252b5132 RH |
15441 | } |
15442 | break; | |
15443 | case 1: | |
15444 | FETCH_DATA (the_info, codep + 1); | |
15445 | disp = *codep++; | |
15446 | if ((disp & 0x80) != 0) | |
15447 | disp -= 0x100; | |
43234a1e L |
15448 | if (vex.evex && shift > 0) |
15449 | disp <<= shift; | |
252b5132 RH |
15450 | break; |
15451 | case 2: | |
52b15da3 | 15452 | disp = get32s (); |
252b5132 RH |
15453 | break; |
15454 | } | |
15455 | ||
1bc60e56 L |
15456 | needindex = 0; |
15457 | needaddr32 = 0; | |
15458 | if (havesib | |
15459 | && !havebase | |
15460 | && !haveindex | |
15461 | && address_mode != mode_16bit) | |
15462 | { | |
15463 | if (address_mode == mode_64bit) | |
15464 | { | |
15465 | /* Display eiz instead of addr32. */ | |
15466 | needindex = addr32flag; | |
15467 | needaddr32 = 1; | |
15468 | } | |
15469 | else | |
15470 | { | |
15471 | /* In 32-bit mode, we need index register to tell [offset] | |
15472 | from [eiz*1 + offset]. */ | |
15473 | needindex = 1; | |
15474 | } | |
15475 | } | |
15476 | ||
20afcfb7 L |
15477 | havedisp = (havebase |
15478 | || needindex | |
15479 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15480 | |
252b5132 | 15481 | if (!intel_syntax) |
82c18208 | 15482 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15483 | { |
5d669648 L |
15484 | if (havedisp || riprel) |
15485 | print_displacement (scratchbuf, disp); | |
15486 | else | |
15487 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15488 | oappend (scratchbuf); |
52b15da3 JH |
15489 | if (riprel) |
15490 | { | |
15491 | set_op (disp, 1); | |
28596323 | 15492 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 15493 | } |
db6eb5be | 15494 | } |
2da11e11 | 15495 | |
1bc60e56 | 15496 | if ((havebase || haveindex || needaddr32 || riprel) |
7e8b059b | 15497 | && (bytemode != v_bnd_mode) |
d276ec69 | 15498 | && (bytemode != v_bndmk_mode) |
9f79e886 JB |
15499 | && (bytemode != bnd_mode) |
15500 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
15501 | used_prefixes |= PREFIX_ADDR; |
15502 | ||
5d669648 | 15503 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15504 | { |
252b5132 | 15505 | *obufp++ = open_char; |
52b15da3 | 15506 | if (intel_syntax && riprel) |
185b1163 L |
15507 | { |
15508 | set_op (disp, 1); | |
28596323 | 15509 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 15510 | } |
db6eb5be | 15511 | *obufp = '\0'; |
252b5132 | 15512 | if (havebase) |
7e8b059b | 15513 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15514 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15515 | if (havesib) |
15516 | { | |
db51cc60 L |
15517 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15518 | print index to tell base + index from base. */ | |
15519 | if (scale != 0 | |
20afcfb7 | 15520 | || needindex |
db51cc60 L |
15521 | || haveindex |
15522 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15523 | { |
9306ca4a | 15524 | if (!intel_syntax || havebase) |
db6eb5be | 15525 | { |
9306ca4a JB |
15526 | *obufp++ = separator_char; |
15527 | *obufp = '\0'; | |
db6eb5be | 15528 | } |
db51cc60 | 15529 | if (haveindex) |
7e8b059b | 15530 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15531 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15532 | else |
7e8b059b | 15533 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15534 | ? index64 : index32); |
15535 | ||
db6eb5be AM |
15536 | *obufp++ = scale_char; |
15537 | *obufp = '\0'; | |
15538 | sprintf (scratchbuf, "%d", 1 << scale); | |
15539 | oappend (scratchbuf); | |
15540 | } | |
252b5132 | 15541 | } |
185b1163 | 15542 | if (intel_syntax |
82c18208 | 15543 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15544 | { |
db51cc60 | 15545 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15546 | { |
15547 | *obufp++ = '+'; | |
15548 | *obufp = '\0'; | |
15549 | } | |
05203043 | 15550 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15551 | { |
15552 | *obufp++ = '-'; | |
15553 | *obufp = '\0'; | |
15554 | disp = - (bfd_signed_vma) disp; | |
15555 | } | |
15556 | ||
db51cc60 L |
15557 | if (havedisp) |
15558 | print_displacement (scratchbuf, disp); | |
15559 | else | |
15560 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15561 | oappend (scratchbuf); |
15562 | } | |
252b5132 RH |
15563 | |
15564 | *obufp++ = close_char; | |
db6eb5be | 15565 | *obufp = '\0'; |
252b5132 RH |
15566 | } |
15567 | else if (intel_syntax) | |
db6eb5be | 15568 | { |
82c18208 | 15569 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15570 | { |
285ca992 | 15571 | if (!active_seg_prefix) |
252b5132 | 15572 | { |
d708bcba | 15573 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15574 | oappend (":"); |
15575 | } | |
52b15da3 | 15576 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15577 | oappend (scratchbuf); |
15578 | } | |
15579 | } | |
252b5132 RH |
15580 | } |
15581 | else | |
f16cd0d5 L |
15582 | { |
15583 | /* 16 bit address mode */ | |
15584 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15585 | switch (modrm.mod) |
252b5132 RH |
15586 | { |
15587 | case 0: | |
7967e09e | 15588 | if (modrm.rm == 6) |
252b5132 RH |
15589 | { |
15590 | disp = get16 (); | |
15591 | if ((disp & 0x8000) != 0) | |
15592 | disp -= 0x10000; | |
15593 | } | |
15594 | break; | |
15595 | case 1: | |
15596 | FETCH_DATA (the_info, codep + 1); | |
15597 | disp = *codep++; | |
15598 | if ((disp & 0x80) != 0) | |
15599 | disp -= 0x100; | |
65f3ed04 JB |
15600 | if (vex.evex && shift > 0) |
15601 | disp <<= shift; | |
252b5132 RH |
15602 | break; |
15603 | case 2: | |
15604 | disp = get16 (); | |
15605 | if ((disp & 0x8000) != 0) | |
15606 | disp -= 0x10000; | |
15607 | break; | |
15608 | } | |
15609 | ||
15610 | if (!intel_syntax) | |
7967e09e | 15611 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15612 | { |
5d669648 | 15613 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15614 | oappend (scratchbuf); |
15615 | } | |
252b5132 | 15616 | |
7967e09e | 15617 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15618 | { |
15619 | *obufp++ = open_char; | |
db6eb5be | 15620 | *obufp = '\0'; |
7967e09e | 15621 | oappend (index16[modrm.rm]); |
5d669648 L |
15622 | if (intel_syntax |
15623 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15624 | { |
5d669648 | 15625 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15626 | { |
15627 | *obufp++ = '+'; | |
15628 | *obufp = '\0'; | |
15629 | } | |
7967e09e | 15630 | else if (modrm.mod != 1) |
3d456fa1 JB |
15631 | { |
15632 | *obufp++ = '-'; | |
15633 | *obufp = '\0'; | |
15634 | disp = - (bfd_signed_vma) disp; | |
15635 | } | |
15636 | ||
5d669648 | 15637 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15638 | oappend (scratchbuf); |
15639 | } | |
15640 | ||
db6eb5be AM |
15641 | *obufp++ = close_char; |
15642 | *obufp = '\0'; | |
252b5132 | 15643 | } |
3d456fa1 JB |
15644 | else if (intel_syntax) |
15645 | { | |
285ca992 | 15646 | if (!active_seg_prefix) |
3d456fa1 JB |
15647 | { |
15648 | oappend (names_seg[ds_reg - es_reg]); | |
15649 | oappend (":"); | |
15650 | } | |
15651 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15652 | oappend (scratchbuf); | |
15653 | } | |
252b5132 | 15654 | } |
43234a1e L |
15655 | if (vex.evex && vex.b |
15656 | && (bytemode == x_mode | |
90a915bf | 15657 | || bytemode == xmmq_mode |
43234a1e L |
15658 | || bytemode == evex_half_bcst_xmmq_mode)) |
15659 | { | |
90a915bf IT |
15660 | if (vex.w |
15661 | || bytemode == xmmq_mode | |
15662 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15663 | { |
15664 | switch (vex.length) | |
15665 | { | |
15666 | case 128: | |
15667 | oappend ("{1to2}"); | |
15668 | break; | |
15669 | case 256: | |
15670 | oappend ("{1to4}"); | |
15671 | break; | |
15672 | case 512: | |
15673 | oappend ("{1to8}"); | |
15674 | break; | |
15675 | default: | |
15676 | abort (); | |
15677 | } | |
15678 | } | |
43234a1e | 15679 | else |
b28d1bda IT |
15680 | { |
15681 | switch (vex.length) | |
15682 | { | |
15683 | case 128: | |
15684 | oappend ("{1to4}"); | |
15685 | break; | |
15686 | case 256: | |
15687 | oappend ("{1to8}"); | |
15688 | break; | |
15689 | case 512: | |
15690 | oappend ("{1to16}"); | |
15691 | break; | |
15692 | default: | |
15693 | abort (); | |
15694 | } | |
15695 | } | |
43234a1e | 15696 | } |
252b5132 RH |
15697 | } |
15698 | ||
c0f3af97 | 15699 | static void |
8b3f93e7 | 15700 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15701 | { |
15702 | /* Skip mod/rm byte. */ | |
15703 | MODRM_CHECK; | |
15704 | codep++; | |
15705 | ||
15706 | if (modrm.mod == 3) | |
15707 | OP_E_register (bytemode, sizeflag); | |
15708 | else | |
c1e679ec | 15709 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15710 | } |
15711 | ||
252b5132 | 15712 | static void |
26ca5450 | 15713 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15714 | { |
52b15da3 | 15715 | int add = 0; |
c0a30a9f | 15716 | const char **names; |
161a04f6 L |
15717 | USED_REX (REX_R); |
15718 | if (rex & REX_R) | |
52b15da3 | 15719 | add += 8; |
252b5132 RH |
15720 | switch (bytemode) |
15721 | { | |
15722 | case b_mode: | |
52b15da3 JH |
15723 | USED_REX (0); |
15724 | if (rex) | |
7967e09e | 15725 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15726 | else |
7967e09e | 15727 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15728 | break; |
15729 | case w_mode: | |
7967e09e | 15730 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15731 | break; |
15732 | case d_mode: | |
1ba585e8 IT |
15733 | case db_mode: |
15734 | case dw_mode: | |
7967e09e | 15735 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15736 | break; |
15737 | case q_mode: | |
7967e09e | 15738 | oappend (names64[modrm.reg + add]); |
252b5132 | 15739 | break; |
7e8b059b | 15740 | case bnd_mode: |
0d96e4df L |
15741 | if (modrm.reg > 0x3) |
15742 | { | |
15743 | oappend ("(bad)"); | |
15744 | return; | |
15745 | } | |
7e8b059b L |
15746 | oappend (names_bnd[modrm.reg]); |
15747 | break; | |
252b5132 | 15748 | case v_mode: |
9306ca4a | 15749 | case dq_mode: |
42903f7f L |
15750 | case dqb_mode: |
15751 | case dqd_mode: | |
9306ca4a | 15752 | case dqw_mode: |
161a04f6 L |
15753 | USED_REX (REX_W); |
15754 | if (rex & REX_W) | |
7967e09e | 15755 | oappend (names64[modrm.reg + add]); |
252b5132 | 15756 | else |
f16cd0d5 L |
15757 | { |
15758 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15759 | oappend (names32[modrm.reg + add]); | |
15760 | else | |
15761 | oappend (names16[modrm.reg + add]); | |
15762 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15763 | } | |
252b5132 | 15764 | break; |
c0a30a9f L |
15765 | case va_mode: |
15766 | names = (address_mode == mode_64bit | |
15767 | ? names64 : names32); | |
15768 | if (!(prefixes & PREFIX_ADDR)) | |
15769 | { | |
15770 | if (address_mode == mode_16bit) | |
15771 | names = names16; | |
15772 | } | |
15773 | else | |
15774 | { | |
15775 | /* Remove "addr16/addr32". */ | |
15776 | all_prefixes[last_addr_prefix] = 0; | |
15777 | names = (address_mode != mode_32bit | |
15778 | ? names32 : names16); | |
15779 | used_prefixes |= PREFIX_ADDR; | |
15780 | } | |
15781 | oappend (names[modrm.reg + add]); | |
15782 | break; | |
90700ea2 | 15783 | case m_mode: |
cb712a9e | 15784 | if (address_mode == mode_64bit) |
7967e09e | 15785 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15786 | else |
7967e09e | 15787 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15788 | break; |
1ba585e8 | 15789 | case mask_bd_mode: |
43234a1e | 15790 | case mask_mode: |
9889cbb1 L |
15791 | if ((modrm.reg + add) > 0x7) |
15792 | { | |
15793 | oappend ("(bad)"); | |
15794 | return; | |
15795 | } | |
43234a1e L |
15796 | oappend (names_mask[modrm.reg + add]); |
15797 | break; | |
252b5132 RH |
15798 | default: |
15799 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15800 | break; | |
15801 | } | |
15802 | } | |
15803 | ||
52b15da3 | 15804 | static bfd_vma |
26ca5450 | 15805 | get64 (void) |
52b15da3 | 15806 | { |
5dd0794d | 15807 | bfd_vma x; |
52b15da3 | 15808 | #ifdef BFD64 |
5dd0794d AM |
15809 | unsigned int a; |
15810 | unsigned int b; | |
15811 | ||
52b15da3 JH |
15812 | FETCH_DATA (the_info, codep + 8); |
15813 | a = *codep++ & 0xff; | |
15814 | a |= (*codep++ & 0xff) << 8; | |
15815 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15816 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15817 | b = *codep++ & 0xff; |
52b15da3 JH |
15818 | b |= (*codep++ & 0xff) << 8; |
15819 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15820 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15821 | x = a + ((bfd_vma) b << 32); |
15822 | #else | |
6608db57 | 15823 | abort (); |
5dd0794d | 15824 | x = 0; |
52b15da3 JH |
15825 | #endif |
15826 | return x; | |
15827 | } | |
15828 | ||
15829 | static bfd_signed_vma | |
26ca5450 | 15830 | get32 (void) |
252b5132 | 15831 | { |
52b15da3 | 15832 | bfd_signed_vma x = 0; |
252b5132 RH |
15833 | |
15834 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15835 | x = *codep++ & (bfd_signed_vma) 0xff; |
15836 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15837 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15838 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15839 | return x; | |
15840 | } | |
15841 | ||
15842 | static bfd_signed_vma | |
26ca5450 | 15843 | get32s (void) |
52b15da3 JH |
15844 | { |
15845 | bfd_signed_vma x = 0; | |
15846 | ||
15847 | FETCH_DATA (the_info, codep + 4); | |
15848 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15849 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15850 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15851 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15852 | ||
15853 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15854 | ||
252b5132 RH |
15855 | return x; |
15856 | } | |
15857 | ||
15858 | static int | |
26ca5450 | 15859 | get16 (void) |
252b5132 RH |
15860 | { |
15861 | int x = 0; | |
15862 | ||
15863 | FETCH_DATA (the_info, codep + 2); | |
15864 | x = *codep++ & 0xff; | |
15865 | x |= (*codep++ & 0xff) << 8; | |
15866 | return x; | |
15867 | } | |
15868 | ||
15869 | static void | |
26ca5450 | 15870 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15871 | { |
15872 | op_index[op_ad] = op_ad; | |
cb712a9e | 15873 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15874 | { |
15875 | op_address[op_ad] = op; | |
15876 | op_riprel[op_ad] = riprel; | |
15877 | } | |
15878 | else | |
15879 | { | |
15880 | /* Mask to get a 32-bit address. */ | |
15881 | op_address[op_ad] = op & 0xffffffff; | |
15882 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15883 | } | |
252b5132 RH |
15884 | } |
15885 | ||
15886 | static void | |
26ca5450 | 15887 | OP_REG (int code, int sizeflag) |
252b5132 | 15888 | { |
2da11e11 | 15889 | const char *s; |
9b60702d | 15890 | int add; |
de882298 RM |
15891 | |
15892 | switch (code) | |
15893 | { | |
15894 | case es_reg: case ss_reg: case cs_reg: | |
15895 | case ds_reg: case fs_reg: case gs_reg: | |
15896 | oappend (names_seg[code - es_reg]); | |
15897 | return; | |
15898 | } | |
15899 | ||
161a04f6 L |
15900 | USED_REX (REX_B); |
15901 | if (rex & REX_B) | |
52b15da3 | 15902 | add = 8; |
9b60702d L |
15903 | else |
15904 | add = 0; | |
52b15da3 JH |
15905 | |
15906 | switch (code) | |
15907 | { | |
52b15da3 JH |
15908 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15909 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15910 | s = names16[code - ax_reg + add]; | |
15911 | break; | |
52b15da3 JH |
15912 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15913 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15914 | USED_REX (0); | |
15915 | if (rex) | |
15916 | s = names8rex[code - al_reg + add]; | |
15917 | else | |
15918 | s = names8[code - al_reg]; | |
15919 | break; | |
6439fc28 AM |
15920 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15921 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15922 | if (address_mode == mode_64bit |
6c067bbb | 15923 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15924 | { |
15925 | s = names64[code - rAX_reg + add]; | |
15926 | break; | |
15927 | } | |
15928 | code += eAX_reg - rAX_reg; | |
6608db57 | 15929 | /* Fall through. */ |
52b15da3 JH |
15930 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15931 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15932 | USED_REX (REX_W); |
15933 | if (rex & REX_W) | |
52b15da3 | 15934 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15935 | else |
f16cd0d5 L |
15936 | { |
15937 | if (sizeflag & DFLAG) | |
15938 | s = names32[code - eAX_reg + add]; | |
15939 | else | |
15940 | s = names16[code - eAX_reg + add]; | |
15941 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15942 | } | |
52b15da3 | 15943 | break; |
52b15da3 JH |
15944 | default: |
15945 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15946 | break; | |
15947 | } | |
15948 | oappend (s); | |
15949 | } | |
15950 | ||
15951 | static void | |
26ca5450 | 15952 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15953 | { |
15954 | const char *s; | |
252b5132 RH |
15955 | |
15956 | switch (code) | |
15957 | { | |
15958 | case indir_dx_reg: | |
d708bcba | 15959 | if (intel_syntax) |
52fd6d94 | 15960 | s = "dx"; |
d708bcba | 15961 | else |
db6eb5be | 15962 | s = "(%dx)"; |
252b5132 RH |
15963 | break; |
15964 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15965 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15966 | s = names16[code - ax_reg]; | |
15967 | break; | |
15968 | case es_reg: case ss_reg: case cs_reg: | |
15969 | case ds_reg: case fs_reg: case gs_reg: | |
15970 | s = names_seg[code - es_reg]; | |
15971 | break; | |
15972 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15973 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15974 | USED_REX (0); |
15975 | if (rex) | |
15976 | s = names8rex[code - al_reg]; | |
15977 | else | |
15978 | s = names8[code - al_reg]; | |
252b5132 RH |
15979 | break; |
15980 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15981 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15982 | USED_REX (REX_W); |
15983 | if (rex & REX_W) | |
52b15da3 | 15984 | s = names64[code - eAX_reg]; |
252b5132 | 15985 | else |
f16cd0d5 L |
15986 | { |
15987 | if (sizeflag & DFLAG) | |
15988 | s = names32[code - eAX_reg]; | |
15989 | else | |
15990 | s = names16[code - eAX_reg]; | |
15991 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15992 | } | |
252b5132 | 15993 | break; |
52fd6d94 | 15994 | case z_mode_ax_reg: |
161a04f6 | 15995 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15996 | s = *names32; |
15997 | else | |
15998 | s = *names16; | |
161a04f6 | 15999 | if (!(rex & REX_W)) |
52fd6d94 JB |
16000 | used_prefixes |= (prefixes & PREFIX_DATA); |
16001 | break; | |
252b5132 RH |
16002 | default: |
16003 | s = INTERNAL_DISASSEMBLER_ERROR; | |
16004 | break; | |
16005 | } | |
16006 | oappend (s); | |
16007 | } | |
16008 | ||
16009 | static void | |
26ca5450 | 16010 | OP_I (int bytemode, int sizeflag) |
252b5132 | 16011 | { |
52b15da3 JH |
16012 | bfd_signed_vma op; |
16013 | bfd_signed_vma mask = -1; | |
252b5132 RH |
16014 | |
16015 | switch (bytemode) | |
16016 | { | |
16017 | case b_mode: | |
16018 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
16019 | op = *codep++; |
16020 | mask = 0xff; | |
16021 | break; | |
16022 | case q_mode: | |
cb712a9e | 16023 | if (address_mode == mode_64bit) |
6439fc28 AM |
16024 | { |
16025 | op = get32s (); | |
16026 | break; | |
16027 | } | |
6608db57 | 16028 | /* Fall through. */ |
252b5132 | 16029 | case v_mode: |
161a04f6 L |
16030 | USED_REX (REX_W); |
16031 | if (rex & REX_W) | |
52b15da3 | 16032 | op = get32s (); |
252b5132 | 16033 | else |
52b15da3 | 16034 | { |
f16cd0d5 L |
16035 | if (sizeflag & DFLAG) |
16036 | { | |
16037 | op = get32 (); | |
16038 | mask = 0xffffffff; | |
16039 | } | |
16040 | else | |
16041 | { | |
16042 | op = get16 (); | |
16043 | mask = 0xfffff; | |
16044 | } | |
16045 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16046 | } |
252b5132 RH |
16047 | break; |
16048 | case w_mode: | |
52b15da3 | 16049 | mask = 0xfffff; |
252b5132 RH |
16050 | op = get16 (); |
16051 | break; | |
9306ca4a JB |
16052 | case const_1_mode: |
16053 | if (intel_syntax) | |
6c067bbb | 16054 | oappend ("1"); |
9306ca4a | 16055 | return; |
252b5132 RH |
16056 | default: |
16057 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16058 | return; | |
16059 | } | |
16060 | ||
52b15da3 JH |
16061 | op &= mask; |
16062 | scratchbuf[0] = '$'; | |
d708bcba | 16063 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16064 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
16065 | scratchbuf[0] = '\0'; |
16066 | } | |
16067 | ||
16068 | static void | |
26ca5450 | 16069 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
16070 | { |
16071 | bfd_signed_vma op; | |
16072 | bfd_signed_vma mask = -1; | |
16073 | ||
cb712a9e | 16074 | if (address_mode != mode_64bit) |
6439fc28 AM |
16075 | { |
16076 | OP_I (bytemode, sizeflag); | |
16077 | return; | |
16078 | } | |
16079 | ||
52b15da3 JH |
16080 | switch (bytemode) |
16081 | { | |
16082 | case b_mode: | |
16083 | FETCH_DATA (the_info, codep + 1); | |
16084 | op = *codep++; | |
16085 | mask = 0xff; | |
16086 | break; | |
16087 | case v_mode: | |
161a04f6 L |
16088 | USED_REX (REX_W); |
16089 | if (rex & REX_W) | |
52b15da3 | 16090 | op = get64 (); |
52b15da3 JH |
16091 | else |
16092 | { | |
f16cd0d5 L |
16093 | if (sizeflag & DFLAG) |
16094 | { | |
16095 | op = get32 (); | |
16096 | mask = 0xffffffff; | |
16097 | } | |
16098 | else | |
16099 | { | |
16100 | op = get16 (); | |
16101 | mask = 0xfffff; | |
16102 | } | |
16103 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16104 | } |
52b15da3 JH |
16105 | break; |
16106 | case w_mode: | |
16107 | mask = 0xfffff; | |
16108 | op = get16 (); | |
16109 | break; | |
16110 | default: | |
16111 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16112 | return; | |
16113 | } | |
16114 | ||
16115 | op &= mask; | |
16116 | scratchbuf[0] = '$'; | |
d708bcba | 16117 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16118 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16119 | scratchbuf[0] = '\0'; |
16120 | } | |
16121 | ||
16122 | static void | |
26ca5450 | 16123 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 16124 | { |
52b15da3 | 16125 | bfd_signed_vma op; |
252b5132 RH |
16126 | |
16127 | switch (bytemode) | |
16128 | { | |
16129 | case b_mode: | |
e3949f17 | 16130 | case b_T_mode: |
252b5132 RH |
16131 | FETCH_DATA (the_info, codep + 1); |
16132 | op = *codep++; | |
16133 | if ((op & 0x80) != 0) | |
16134 | op -= 0x100; | |
e3949f17 L |
16135 | if (bytemode == b_T_mode) |
16136 | { | |
16137 | if (address_mode != mode_64bit | |
7bb15c6f | 16138 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 16139 | { |
6c067bbb RM |
16140 | /* The operand-size prefix is overridden by a REX prefix. */ |
16141 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
16142 | op &= 0xffffffff; |
16143 | else | |
16144 | op &= 0xffff; | |
16145 | } | |
16146 | } | |
16147 | else | |
16148 | { | |
16149 | if (!(rex & REX_W)) | |
16150 | { | |
16151 | if (sizeflag & DFLAG) | |
16152 | op &= 0xffffffff; | |
16153 | else | |
16154 | op &= 0xffff; | |
16155 | } | |
16156 | } | |
252b5132 RH |
16157 | break; |
16158 | case v_mode: | |
7bb15c6f RM |
16159 | /* The operand-size prefix is overridden by a REX prefix. */ |
16160 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 16161 | op = get32s (); |
252b5132 | 16162 | else |
d9e3625e | 16163 | op = get16 (); |
252b5132 RH |
16164 | break; |
16165 | default: | |
16166 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16167 | return; | |
16168 | } | |
52b15da3 JH |
16169 | |
16170 | scratchbuf[0] = '$'; | |
16171 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 16172 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16173 | } |
16174 | ||
16175 | static void | |
26ca5450 | 16176 | OP_J (int bytemode, int sizeflag) |
252b5132 | 16177 | { |
52b15da3 | 16178 | bfd_vma disp; |
7081ff04 | 16179 | bfd_vma mask = -1; |
65ca155d | 16180 | bfd_vma segment = 0; |
252b5132 RH |
16181 | |
16182 | switch (bytemode) | |
16183 | { | |
16184 | case b_mode: | |
16185 | FETCH_DATA (the_info, codep + 1); | |
16186 | disp = *codep++; | |
16187 | if ((disp & 0x80) != 0) | |
16188 | disp -= 0x100; | |
16189 | break; | |
16190 | case v_mode: | |
5db04b09 L |
16191 | if (isa64 == amd64) |
16192 | USED_REX (REX_W); | |
16193 | if ((sizeflag & DFLAG) | |
16194 | || (address_mode == mode_64bit | |
16195 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 16196 | disp = get32s (); |
252b5132 RH |
16197 | else |
16198 | { | |
16199 | disp = get16 (); | |
206717e8 L |
16200 | if ((disp & 0x8000) != 0) |
16201 | disp -= 0x10000; | |
65ca155d L |
16202 | /* In 16bit mode, address is wrapped around at 64k within |
16203 | the same segment. Otherwise, a data16 prefix on a jump | |
16204 | instruction means that the pc is masked to 16 bits after | |
16205 | the displacement is added! */ | |
16206 | mask = 0xffff; | |
16207 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 16208 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 16209 | & ~((bfd_vma) 0xffff)); |
252b5132 | 16210 | } |
5db04b09 L |
16211 | if (address_mode != mode_64bit |
16212 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 16213 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
16214 | break; |
16215 | default: | |
16216 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16217 | return; | |
16218 | } | |
42d5f9c6 | 16219 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
16220 | set_op (disp, 0); |
16221 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
16222 | oappend (scratchbuf); |
16223 | } | |
16224 | ||
252b5132 | 16225 | static void |
ed7841b3 | 16226 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 16227 | { |
ed7841b3 | 16228 | if (bytemode == w_mode) |
7967e09e | 16229 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 16230 | else |
7967e09e | 16231 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
16232 | } |
16233 | ||
16234 | static void | |
26ca5450 | 16235 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
16236 | { |
16237 | int seg, offset; | |
16238 | ||
c608c12e | 16239 | if (sizeflag & DFLAG) |
252b5132 | 16240 | { |
c608c12e AM |
16241 | offset = get32 (); |
16242 | seg = get16 (); | |
252b5132 | 16243 | } |
c608c12e AM |
16244 | else |
16245 | { | |
16246 | offset = get16 (); | |
16247 | seg = get16 (); | |
16248 | } | |
7d421014 | 16249 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 16250 | if (intel_syntax) |
3f31e633 | 16251 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
16252 | else |
16253 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 16254 | oappend (scratchbuf); |
252b5132 RH |
16255 | } |
16256 | ||
252b5132 | 16257 | static void |
3f31e633 | 16258 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 16259 | { |
52b15da3 | 16260 | bfd_vma off; |
252b5132 | 16261 | |
3f31e633 JB |
16262 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16263 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
16264 | append_seg (); |
16265 | ||
cb712a9e | 16266 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
16267 | off = get32 (); |
16268 | else | |
16269 | off = get16 (); | |
16270 | ||
16271 | if (intel_syntax) | |
16272 | { | |
285ca992 | 16273 | if (!active_seg_prefix) |
252b5132 | 16274 | { |
d708bcba | 16275 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
16276 | oappend (":"); |
16277 | } | |
16278 | } | |
52b15da3 JH |
16279 | print_operand_value (scratchbuf, 1, off); |
16280 | oappend (scratchbuf); | |
16281 | } | |
6439fc28 | 16282 | |
52b15da3 | 16283 | static void |
3f31e633 | 16284 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
16285 | { |
16286 | bfd_vma off; | |
16287 | ||
539e75ad L |
16288 | if (address_mode != mode_64bit |
16289 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16290 | { |
16291 | OP_OFF (bytemode, sizeflag); | |
16292 | return; | |
16293 | } | |
16294 | ||
3f31e633 JB |
16295 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16296 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16297 | append_seg (); |
16298 | ||
6608db57 | 16299 | off = get64 (); |
52b15da3 JH |
16300 | |
16301 | if (intel_syntax) | |
16302 | { | |
285ca992 | 16303 | if (!active_seg_prefix) |
52b15da3 | 16304 | { |
d708bcba | 16305 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16306 | oappend (":"); |
16307 | } | |
16308 | } | |
16309 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16310 | oappend (scratchbuf); |
16311 | } | |
16312 | ||
16313 | static void | |
26ca5450 | 16314 | ptr_reg (int code, int sizeflag) |
252b5132 | 16315 | { |
2da11e11 | 16316 | const char *s; |
d708bcba | 16317 | |
1d9f512f | 16318 | *obufp++ = open_char; |
20f0a1fc | 16319 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16320 | if (address_mode == mode_64bit) |
c1a64871 JH |
16321 | { |
16322 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16323 | s = names32[code - eAX_reg]; |
c1a64871 | 16324 | else |
db6eb5be | 16325 | s = names64[code - eAX_reg]; |
c1a64871 | 16326 | } |
52b15da3 | 16327 | else if (sizeflag & AFLAG) |
252b5132 RH |
16328 | s = names32[code - eAX_reg]; |
16329 | else | |
16330 | s = names16[code - eAX_reg]; | |
16331 | oappend (s); | |
1d9f512f AM |
16332 | *obufp++ = close_char; |
16333 | *obufp = 0; | |
252b5132 RH |
16334 | } |
16335 | ||
16336 | static void | |
26ca5450 | 16337 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16338 | { |
9306ca4a | 16339 | if (intel_syntax) |
52fd6d94 JB |
16340 | { |
16341 | switch (codep[-1]) | |
16342 | { | |
16343 | case 0x6d: /* insw/insl */ | |
16344 | intel_operand_size (z_mode, sizeflag); | |
16345 | break; | |
16346 | case 0xa5: /* movsw/movsl/movsq */ | |
16347 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16348 | case 0xab: /* stosw/stosl */ | |
16349 | case 0xaf: /* scasw/scasl */ | |
16350 | intel_operand_size (v_mode, sizeflag); | |
16351 | break; | |
16352 | default: | |
16353 | intel_operand_size (b_mode, sizeflag); | |
16354 | } | |
16355 | } | |
9ce09ba2 | 16356 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16357 | ptr_reg (code, sizeflag); |
16358 | } | |
16359 | ||
16360 | static void | |
26ca5450 | 16361 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16362 | { |
9306ca4a | 16363 | if (intel_syntax) |
52fd6d94 JB |
16364 | { |
16365 | switch (codep[-1]) | |
16366 | { | |
16367 | case 0x6f: /* outsw/outsl */ | |
16368 | intel_operand_size (z_mode, sizeflag); | |
16369 | break; | |
16370 | case 0xa5: /* movsw/movsl/movsq */ | |
16371 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16372 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16373 | intel_operand_size (v_mode, sizeflag); | |
16374 | break; | |
16375 | default: | |
16376 | intel_operand_size (b_mode, sizeflag); | |
16377 | } | |
16378 | } | |
285ca992 L |
16379 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16380 | default segment register DS is printed. */ | |
16381 | if (!active_seg_prefix) | |
16382 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16383 | append_seg (); |
252b5132 RH |
16384 | ptr_reg (code, sizeflag); |
16385 | } | |
16386 | ||
252b5132 | 16387 | static void |
26ca5450 | 16388 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16389 | { |
9b60702d | 16390 | int add; |
161a04f6 | 16391 | if (rex & REX_R) |
c4a530c5 | 16392 | { |
161a04f6 | 16393 | USED_REX (REX_R); |
c4a530c5 JB |
16394 | add = 8; |
16395 | } | |
cb712a9e | 16396 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16397 | { |
f16cd0d5 | 16398 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16399 | used_prefixes |= PREFIX_LOCK; |
16400 | add = 8; | |
16401 | } | |
9b60702d L |
16402 | else |
16403 | add = 0; | |
7967e09e | 16404 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16405 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16406 | } |
16407 | ||
252b5132 | 16408 | static void |
26ca5450 | 16409 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16410 | { |
9b60702d | 16411 | int add; |
161a04f6 L |
16412 | USED_REX (REX_R); |
16413 | if (rex & REX_R) | |
52b15da3 | 16414 | add = 8; |
9b60702d L |
16415 | else |
16416 | add = 0; | |
d708bcba | 16417 | if (intel_syntax) |
7967e09e | 16418 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16419 | else |
7967e09e | 16420 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16421 | oappend (scratchbuf); |
16422 | } | |
16423 | ||
252b5132 | 16424 | static void |
26ca5450 | 16425 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16426 | { |
7967e09e | 16427 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16428 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16429 | } |
16430 | ||
16431 | static void | |
6f74c397 | 16432 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16433 | { |
68f34464 L |
16434 | /* Skip mod/rm byte. */ |
16435 | MODRM_CHECK; | |
16436 | codep++; | |
16437 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16438 | } |
16439 | ||
16440 | static void | |
26ca5450 | 16441 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16442 | { |
b9733481 L |
16443 | int reg = modrm.reg; |
16444 | const char **names; | |
16445 | ||
041bd2e0 JH |
16446 | used_prefixes |= (prefixes & PREFIX_DATA); |
16447 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16448 | { |
b9733481 | 16449 | names = names_xmm; |
161a04f6 L |
16450 | USED_REX (REX_R); |
16451 | if (rex & REX_R) | |
b9733481 | 16452 | reg += 8; |
20f0a1fc | 16453 | } |
041bd2e0 | 16454 | else |
b9733481 L |
16455 | names = names_mm; |
16456 | oappend (names[reg]); | |
252b5132 RH |
16457 | } |
16458 | ||
c608c12e | 16459 | static void |
c0f3af97 | 16460 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16461 | { |
b9733481 L |
16462 | int reg = modrm.reg; |
16463 | const char **names; | |
16464 | ||
161a04f6 L |
16465 | USED_REX (REX_R); |
16466 | if (rex & REX_R) | |
b9733481 | 16467 | reg += 8; |
43234a1e L |
16468 | if (vex.evex) |
16469 | { | |
16470 | if (!vex.r) | |
16471 | reg += 16; | |
16472 | } | |
16473 | ||
539f890d L |
16474 | if (need_vex |
16475 | && bytemode != xmm_mode | |
43234a1e L |
16476 | && bytemode != xmmq_mode |
16477 | && bytemode != evex_half_bcst_xmmq_mode | |
16478 | && bytemode != ymm_mode | |
539f890d | 16479 | && bytemode != scalar_mode) |
c0f3af97 L |
16480 | { |
16481 | switch (vex.length) | |
16482 | { | |
16483 | case 128: | |
b9733481 | 16484 | names = names_xmm; |
c0f3af97 L |
16485 | break; |
16486 | case 256: | |
5fc35d96 IT |
16487 | if (vex.w |
16488 | || (bytemode != vex_vsib_q_w_dq_mode | |
16489 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16490 | names = names_ymm; |
16491 | else | |
16492 | names = names_xmm; | |
c0f3af97 | 16493 | break; |
43234a1e L |
16494 | case 512: |
16495 | names = names_zmm; | |
16496 | break; | |
c0f3af97 L |
16497 | default: |
16498 | abort (); | |
16499 | } | |
16500 | } | |
43234a1e L |
16501 | else if (bytemode == xmmq_mode |
16502 | || bytemode == evex_half_bcst_xmmq_mode) | |
16503 | { | |
16504 | switch (vex.length) | |
16505 | { | |
16506 | case 128: | |
16507 | case 256: | |
16508 | names = names_xmm; | |
16509 | break; | |
16510 | case 512: | |
16511 | names = names_ymm; | |
16512 | break; | |
16513 | default: | |
16514 | abort (); | |
16515 | } | |
16516 | } | |
16517 | else if (bytemode == ymm_mode) | |
16518 | names = names_ymm; | |
c0f3af97 | 16519 | else |
b9733481 L |
16520 | names = names_xmm; |
16521 | oappend (names[reg]); | |
c608c12e AM |
16522 | } |
16523 | ||
252b5132 | 16524 | static void |
26ca5450 | 16525 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16526 | { |
b9733481 L |
16527 | int reg; |
16528 | const char **names; | |
16529 | ||
7967e09e | 16530 | if (modrm.mod != 3) |
252b5132 | 16531 | { |
b6169b20 L |
16532 | if (intel_syntax |
16533 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16534 | { |
16535 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16536 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16537 | } |
252b5132 RH |
16538 | OP_E (bytemode, sizeflag); |
16539 | return; | |
16540 | } | |
16541 | ||
b6169b20 L |
16542 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16543 | swap_operand (); | |
16544 | ||
6608db57 | 16545 | /* Skip mod/rm byte. */ |
4bba6815 | 16546 | MODRM_CHECK; |
252b5132 | 16547 | codep++; |
041bd2e0 | 16548 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16549 | reg = modrm.rm; |
041bd2e0 | 16550 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16551 | { |
b9733481 | 16552 | names = names_xmm; |
161a04f6 L |
16553 | USED_REX (REX_B); |
16554 | if (rex & REX_B) | |
b9733481 | 16555 | reg += 8; |
20f0a1fc | 16556 | } |
041bd2e0 | 16557 | else |
b9733481 L |
16558 | names = names_mm; |
16559 | oappend (names[reg]); | |
252b5132 RH |
16560 | } |
16561 | ||
246c51aa L |
16562 | /* cvt* are the only instructions in sse2 which have |
16563 | both SSE and MMX operands and also have 0x66 prefix | |
16564 | in their opcode. 0x66 was originally used to differentiate | |
16565 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16566 | cvt* separately using OP_EMC and OP_MXC */ |
16567 | static void | |
16568 | OP_EMC (int bytemode, int sizeflag) | |
16569 | { | |
7967e09e | 16570 | if (modrm.mod != 3) |
4d9567e0 MM |
16571 | { |
16572 | if (intel_syntax && bytemode == v_mode) | |
16573 | { | |
16574 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16575 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16576 | } |
4d9567e0 MM |
16577 | OP_E (bytemode, sizeflag); |
16578 | return; | |
16579 | } | |
246c51aa | 16580 | |
4d9567e0 MM |
16581 | /* Skip mod/rm byte. */ |
16582 | MODRM_CHECK; | |
16583 | codep++; | |
16584 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16585 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16586 | } |
16587 | ||
16588 | static void | |
16589 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16590 | { | |
16591 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16592 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16593 | } |
16594 | ||
c608c12e | 16595 | static void |
26ca5450 | 16596 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16597 | { |
b9733481 L |
16598 | int reg; |
16599 | const char **names; | |
d6f574e0 L |
16600 | |
16601 | /* Skip mod/rm byte. */ | |
16602 | MODRM_CHECK; | |
16603 | codep++; | |
16604 | ||
7967e09e | 16605 | if (modrm.mod != 3) |
c608c12e | 16606 | { |
c1e679ec | 16607 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16608 | return; |
16609 | } | |
d6f574e0 | 16610 | |
b9733481 | 16611 | reg = modrm.rm; |
161a04f6 L |
16612 | USED_REX (REX_B); |
16613 | if (rex & REX_B) | |
b9733481 | 16614 | reg += 8; |
43234a1e L |
16615 | if (vex.evex) |
16616 | { | |
16617 | USED_REX (REX_X); | |
16618 | if ((rex & REX_X)) | |
16619 | reg += 16; | |
16620 | } | |
c608c12e | 16621 | |
b6169b20 | 16622 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16623 | && (bytemode == x_swap_mode |
16624 | || bytemode == d_swap_mode | |
7bb15c6f | 16625 | || bytemode == d_scalar_swap_mode |
539f890d L |
16626 | || bytemode == q_swap_mode |
16627 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16628 | swap_operand (); |
16629 | ||
c0f3af97 L |
16630 | if (need_vex |
16631 | && bytemode != xmm_mode | |
6c30d220 L |
16632 | && bytemode != xmmdw_mode |
16633 | && bytemode != xmmqd_mode | |
16634 | && bytemode != xmm_mb_mode | |
16635 | && bytemode != xmm_mw_mode | |
16636 | && bytemode != xmm_md_mode | |
16637 | && bytemode != xmm_mq_mode | |
43234a1e | 16638 | && bytemode != xmm_mdq_mode |
539f890d | 16639 | && bytemode != xmmq_mode |
43234a1e L |
16640 | && bytemode != evex_half_bcst_xmmq_mode |
16641 | && bytemode != ymm_mode | |
539f890d | 16642 | && bytemode != d_scalar_mode |
7bb15c6f | 16643 | && bytemode != d_scalar_swap_mode |
539f890d | 16644 | && bytemode != q_scalar_mode |
1c480963 L |
16645 | && bytemode != q_scalar_swap_mode |
16646 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16647 | { |
16648 | switch (vex.length) | |
16649 | { | |
16650 | case 128: | |
b9733481 | 16651 | names = names_xmm; |
c0f3af97 L |
16652 | break; |
16653 | case 256: | |
b9733481 | 16654 | names = names_ymm; |
c0f3af97 | 16655 | break; |
43234a1e L |
16656 | case 512: |
16657 | names = names_zmm; | |
16658 | break; | |
c0f3af97 L |
16659 | default: |
16660 | abort (); | |
16661 | } | |
16662 | } | |
43234a1e L |
16663 | else if (bytemode == xmmq_mode |
16664 | || bytemode == evex_half_bcst_xmmq_mode) | |
16665 | { | |
16666 | switch (vex.length) | |
16667 | { | |
16668 | case 128: | |
16669 | case 256: | |
16670 | names = names_xmm; | |
16671 | break; | |
16672 | case 512: | |
16673 | names = names_ymm; | |
16674 | break; | |
16675 | default: | |
16676 | abort (); | |
16677 | } | |
16678 | } | |
16679 | else if (bytemode == ymm_mode) | |
16680 | names = names_ymm; | |
c0f3af97 | 16681 | else |
b9733481 L |
16682 | names = names_xmm; |
16683 | oappend (names[reg]); | |
c608c12e AM |
16684 | } |
16685 | ||
252b5132 | 16686 | static void |
26ca5450 | 16687 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16688 | { |
7967e09e | 16689 | if (modrm.mod == 3) |
2da11e11 AM |
16690 | OP_EM (bytemode, sizeflag); |
16691 | else | |
6608db57 | 16692 | BadOp (); |
252b5132 RH |
16693 | } |
16694 | ||
992aaec9 | 16695 | static void |
26ca5450 | 16696 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16697 | { |
7967e09e | 16698 | if (modrm.mod == 3) |
992aaec9 AM |
16699 | OP_EX (bytemode, sizeflag); |
16700 | else | |
6608db57 | 16701 | BadOp (); |
992aaec9 AM |
16702 | } |
16703 | ||
cc0ec051 AM |
16704 | static void |
16705 | OP_M (int bytemode, int sizeflag) | |
16706 | { | |
7967e09e | 16707 | if (modrm.mod == 3) |
75413a22 L |
16708 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16709 | BadOp (); | |
cc0ec051 AM |
16710 | else |
16711 | OP_E (bytemode, sizeflag); | |
16712 | } | |
16713 | ||
16714 | static void | |
16715 | OP_0f07 (int bytemode, int sizeflag) | |
16716 | { | |
7967e09e | 16717 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16718 | BadOp (); |
16719 | else | |
16720 | OP_E (bytemode, sizeflag); | |
16721 | } | |
16722 | ||
46e883c5 | 16723 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16724 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16725 | |
cc0ec051 | 16726 | static void |
46e883c5 | 16727 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16728 | { |
8b38ad71 L |
16729 | if ((prefixes & PREFIX_DATA) != 0 |
16730 | || (rex != 0 | |
16731 | && rex != 0x48 | |
16732 | && address_mode == mode_64bit)) | |
46e883c5 L |
16733 | OP_REG (bytemode, sizeflag); |
16734 | else | |
16735 | strcpy (obuf, "nop"); | |
16736 | } | |
16737 | ||
16738 | static void | |
16739 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16740 | { | |
8b38ad71 L |
16741 | if ((prefixes & PREFIX_DATA) != 0 |
16742 | || (rex != 0 | |
16743 | && rex != 0x48 | |
16744 | && address_mode == mode_64bit)) | |
46e883c5 | 16745 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16746 | } |
16747 | ||
84037f8c | 16748 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16749 | /* 00 */ NULL, NULL, NULL, NULL, |
16750 | /* 04 */ NULL, NULL, NULL, NULL, | |
16751 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16752 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16753 | /* 10 */ NULL, NULL, NULL, NULL, |
16754 | /* 14 */ NULL, NULL, NULL, NULL, | |
16755 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16756 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16757 | /* 20 */ NULL, NULL, NULL, NULL, |
16758 | /* 24 */ NULL, NULL, NULL, NULL, | |
16759 | /* 28 */ NULL, NULL, NULL, NULL, | |
16760 | /* 2C */ NULL, NULL, NULL, NULL, | |
16761 | /* 30 */ NULL, NULL, NULL, NULL, | |
16762 | /* 34 */ NULL, NULL, NULL, NULL, | |
16763 | /* 38 */ NULL, NULL, NULL, NULL, | |
16764 | /* 3C */ NULL, NULL, NULL, NULL, | |
16765 | /* 40 */ NULL, NULL, NULL, NULL, | |
16766 | /* 44 */ NULL, NULL, NULL, NULL, | |
16767 | /* 48 */ NULL, NULL, NULL, NULL, | |
16768 | /* 4C */ NULL, NULL, NULL, NULL, | |
16769 | /* 50 */ NULL, NULL, NULL, NULL, | |
16770 | /* 54 */ NULL, NULL, NULL, NULL, | |
16771 | /* 58 */ NULL, NULL, NULL, NULL, | |
16772 | /* 5C */ NULL, NULL, NULL, NULL, | |
16773 | /* 60 */ NULL, NULL, NULL, NULL, | |
16774 | /* 64 */ NULL, NULL, NULL, NULL, | |
16775 | /* 68 */ NULL, NULL, NULL, NULL, | |
16776 | /* 6C */ NULL, NULL, NULL, NULL, | |
16777 | /* 70 */ NULL, NULL, NULL, NULL, | |
16778 | /* 74 */ NULL, NULL, NULL, NULL, | |
16779 | /* 78 */ NULL, NULL, NULL, NULL, | |
16780 | /* 7C */ NULL, NULL, NULL, NULL, | |
16781 | /* 80 */ NULL, NULL, NULL, NULL, | |
16782 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16783 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16784 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16785 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16786 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16787 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16788 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16789 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16790 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16791 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16792 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16793 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16794 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16795 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16796 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16797 | /* C0 */ NULL, NULL, NULL, NULL, | |
16798 | /* C4 */ NULL, NULL, NULL, NULL, | |
16799 | /* C8 */ NULL, NULL, NULL, NULL, | |
16800 | /* CC */ NULL, NULL, NULL, NULL, | |
16801 | /* D0 */ NULL, NULL, NULL, NULL, | |
16802 | /* D4 */ NULL, NULL, NULL, NULL, | |
16803 | /* D8 */ NULL, NULL, NULL, NULL, | |
16804 | /* DC */ NULL, NULL, NULL, NULL, | |
16805 | /* E0 */ NULL, NULL, NULL, NULL, | |
16806 | /* E4 */ NULL, NULL, NULL, NULL, | |
16807 | /* E8 */ NULL, NULL, NULL, NULL, | |
16808 | /* EC */ NULL, NULL, NULL, NULL, | |
16809 | /* F0 */ NULL, NULL, NULL, NULL, | |
16810 | /* F4 */ NULL, NULL, NULL, NULL, | |
16811 | /* F8 */ NULL, NULL, NULL, NULL, | |
16812 | /* FC */ NULL, NULL, NULL, NULL, | |
16813 | }; | |
16814 | ||
16815 | static void | |
26ca5450 | 16816 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16817 | { |
16818 | const char *mnemonic; | |
16819 | ||
16820 | FETCH_DATA (the_info, codep + 1); | |
16821 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16822 | place where an 8-bit immediate would normally go. ie. the last | |
16823 | byte of the instruction. */ | |
ea397f5b | 16824 | obufp = mnemonicendp; |
c608c12e | 16825 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16826 | if (mnemonic) |
2da11e11 | 16827 | oappend (mnemonic); |
252b5132 RH |
16828 | else |
16829 | { | |
16830 | /* Since a variable sized modrm/sib chunk is between the start | |
16831 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16832 | all the modrm processing first, and don't know until now that | |
16833 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16834 | op_out[0][0] = '\0'; |
16835 | op_out[1][0] = '\0'; | |
6608db57 | 16836 | BadOp (); |
252b5132 | 16837 | } |
ea397f5b | 16838 | mnemonicendp = obufp; |
252b5132 | 16839 | } |
c608c12e | 16840 | |
ea397f5b L |
16841 | static struct op simd_cmp_op[] = |
16842 | { | |
16843 | { STRING_COMMA_LEN ("eq") }, | |
16844 | { STRING_COMMA_LEN ("lt") }, | |
16845 | { STRING_COMMA_LEN ("le") }, | |
16846 | { STRING_COMMA_LEN ("unord") }, | |
16847 | { STRING_COMMA_LEN ("neq") }, | |
16848 | { STRING_COMMA_LEN ("nlt") }, | |
16849 | { STRING_COMMA_LEN ("nle") }, | |
16850 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16851 | }; |
16852 | ||
16853 | static void | |
ad19981d | 16854 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16855 | { |
16856 | unsigned int cmp_type; | |
16857 | ||
16858 | FETCH_DATA (the_info, codep + 1); | |
16859 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16860 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16861 | { |
ad19981d | 16862 | char suffix [3]; |
ea397f5b | 16863 | char *p = mnemonicendp - 2; |
ad19981d L |
16864 | suffix[0] = p[0]; |
16865 | suffix[1] = p[1]; | |
16866 | suffix[2] = '\0'; | |
ea397f5b L |
16867 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16868 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16869 | } |
16870 | else | |
16871 | { | |
ad19981d L |
16872 | /* We have a reserved extension byte. Output it directly. */ |
16873 | scratchbuf[0] = '$'; | |
16874 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16875 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16876 | scratchbuf[0] = '\0'; |
c608c12e AM |
16877 | } |
16878 | } | |
16879 | ||
9916071f AP |
16880 | static void |
16881 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16882 | int sizeflag ATTRIBUTE_UNUSED) | |
16883 | { | |
16884 | /* mwaitx %eax,%ecx,%ebx */ | |
16885 | if (!intel_syntax) | |
16886 | { | |
16887 | const char **names = (address_mode == mode_64bit | |
16888 | ? names64 : names32); | |
16889 | strcpy (op_out[0], names[0]); | |
16890 | strcpy (op_out[1], names[1]); | |
16891 | strcpy (op_out[2], names[3]); | |
16892 | two_source_ops = 1; | |
16893 | } | |
16894 | /* Skip mod/rm byte. */ | |
16895 | MODRM_CHECK; | |
16896 | codep++; | |
16897 | } | |
16898 | ||
ca164297 | 16899 | static void |
b844680a L |
16900 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16901 | int sizeflag ATTRIBUTE_UNUSED) | |
16902 | { | |
16903 | /* mwait %eax,%ecx */ | |
16904 | if (!intel_syntax) | |
16905 | { | |
16906 | const char **names = (address_mode == mode_64bit | |
16907 | ? names64 : names32); | |
16908 | strcpy (op_out[0], names[0]); | |
16909 | strcpy (op_out[1], names[1]); | |
16910 | two_source_ops = 1; | |
16911 | } | |
16912 | /* Skip mod/rm byte. */ | |
16913 | MODRM_CHECK; | |
16914 | codep++; | |
16915 | } | |
16916 | ||
16917 | static void | |
16918 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16919 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16920 | { |
b844680a L |
16921 | /* monitor %eax,%ecx,%edx" */ |
16922 | if (!intel_syntax) | |
ca164297 | 16923 | { |
b844680a | 16924 | const char **op1_names; |
cb712a9e L |
16925 | const char **names = (address_mode == mode_64bit |
16926 | ? names64 : names32); | |
1d9f512f | 16927 | |
b844680a L |
16928 | if (!(prefixes & PREFIX_ADDR)) |
16929 | op1_names = (address_mode == mode_16bit | |
16930 | ? names16 : names); | |
ca164297 L |
16931 | else |
16932 | { | |
b844680a | 16933 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16934 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16935 | op1_names = (address_mode != mode_32bit |
16936 | ? names32 : names16); | |
16937 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16938 | } |
b844680a L |
16939 | strcpy (op_out[0], op1_names[0]); |
16940 | strcpy (op_out[1], names[1]); | |
16941 | strcpy (op_out[2], names[2]); | |
16942 | two_source_ops = 1; | |
ca164297 | 16943 | } |
b844680a L |
16944 | /* Skip mod/rm byte. */ |
16945 | MODRM_CHECK; | |
16946 | codep++; | |
30123838 JB |
16947 | } |
16948 | ||
6608db57 KH |
16949 | static void |
16950 | BadOp (void) | |
2da11e11 | 16951 | { |
6608db57 KH |
16952 | /* Throw away prefixes and 1st. opcode byte. */ |
16953 | codep = insn_codep + 1; | |
2da11e11 AM |
16954 | oappend ("(bad)"); |
16955 | } | |
4cc91dba | 16956 | |
35c52694 L |
16957 | static void |
16958 | REP_Fixup (int bytemode, int sizeflag) | |
16959 | { | |
16960 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16961 | lods and stos. */ | |
35c52694 | 16962 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16963 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16964 | |
16965 | switch (bytemode) | |
16966 | { | |
16967 | case al_reg: | |
16968 | case eAX_reg: | |
16969 | case indir_dx_reg: | |
16970 | OP_IMREG (bytemode, sizeflag); | |
16971 | break; | |
16972 | case eDI_reg: | |
16973 | OP_ESreg (bytemode, sizeflag); | |
16974 | break; | |
16975 | case eSI_reg: | |
16976 | OP_DSreg (bytemode, sizeflag); | |
16977 | break; | |
16978 | default: | |
16979 | abort (); | |
16980 | break; | |
16981 | } | |
16982 | } | |
f5804c90 | 16983 | |
7e8b059b L |
16984 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16985 | "bnd". */ | |
16986 | ||
16987 | static void | |
16988 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16989 | { | |
16990 | if (prefixes & PREFIX_REPNZ) | |
16991 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16992 | } | |
16993 | ||
04ef582a L |
16994 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16995 | "notrack". */ | |
16996 | ||
16997 | static void | |
16998 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16999 | int sizeflag ATTRIBUTE_UNUSED) | |
17000 | { | |
9fef80d6 | 17001 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
17002 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
17003 | { | |
4e9ac44a | 17004 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 17005 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
17006 | active_seg_prefix = 0; |
17007 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
17008 | } | |
17009 | } | |
17010 | ||
42164a71 L |
17011 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
17012 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
17013 | */ | |
17014 | ||
17015 | static void | |
17016 | HLE_Fixup1 (int bytemode, int sizeflag) | |
17017 | { | |
17018 | if (modrm.mod != 3 | |
17019 | && (prefixes & PREFIX_LOCK) != 0) | |
17020 | { | |
17021 | if (prefixes & PREFIX_REPZ) | |
17022 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17023 | if (prefixes & PREFIX_REPNZ) | |
17024 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17025 | } | |
17026 | ||
17027 | OP_E (bytemode, sizeflag); | |
17028 | } | |
17029 | ||
17030 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
17031 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
17032 | */ | |
17033 | ||
17034 | static void | |
17035 | HLE_Fixup2 (int bytemode, int sizeflag) | |
17036 | { | |
17037 | if (modrm.mod != 3) | |
17038 | { | |
17039 | if (prefixes & PREFIX_REPZ) | |
17040 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17041 | if (prefixes & PREFIX_REPNZ) | |
17042 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17043 | } | |
17044 | ||
17045 | OP_E (bytemode, sizeflag); | |
17046 | } | |
17047 | ||
17048 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
17049 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
17050 | ||
17051 | static void | |
17052 | HLE_Fixup3 (int bytemode, int sizeflag) | |
17053 | { | |
17054 | if (modrm.mod != 3 | |
17055 | && last_repz_prefix > last_repnz_prefix | |
17056 | && (prefixes & PREFIX_REPZ) != 0) | |
17057 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17058 | ||
17059 | OP_E (bytemode, sizeflag); | |
17060 | } | |
17061 | ||
f5804c90 L |
17062 | static void |
17063 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
17064 | { | |
161a04f6 L |
17065 | USED_REX (REX_W); |
17066 | if (rex & REX_W) | |
f5804c90 L |
17067 | { |
17068 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
17069 | char *p = mnemonicendp - 2; |
17070 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 17071 | bytemode = o_mode; |
f5804c90 | 17072 | } |
42164a71 L |
17073 | else if ((prefixes & PREFIX_LOCK) != 0) |
17074 | { | |
17075 | if (prefixes & PREFIX_REPZ) | |
17076 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17077 | if (prefixes & PREFIX_REPNZ) | |
17078 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17079 | } | |
17080 | ||
f5804c90 L |
17081 | OP_M (bytemode, sizeflag); |
17082 | } | |
42903f7f L |
17083 | |
17084 | static void | |
17085 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
17086 | { | |
b9733481 L |
17087 | const char **names; |
17088 | ||
c0f3af97 L |
17089 | if (need_vex) |
17090 | { | |
17091 | switch (vex.length) | |
17092 | { | |
17093 | case 128: | |
b9733481 | 17094 | names = names_xmm; |
c0f3af97 L |
17095 | break; |
17096 | case 256: | |
b9733481 | 17097 | names = names_ymm; |
c0f3af97 L |
17098 | break; |
17099 | default: | |
17100 | abort (); | |
17101 | } | |
17102 | } | |
17103 | else | |
b9733481 L |
17104 | names = names_xmm; |
17105 | oappend (names[reg]); | |
42903f7f | 17106 | } |
381d071f L |
17107 | |
17108 | static void | |
17109 | CRC32_Fixup (int bytemode, int sizeflag) | |
17110 | { | |
17111 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 17112 | char *p = mnemonicendp; |
381d071f L |
17113 | |
17114 | switch (bytemode) | |
17115 | { | |
17116 | case b_mode: | |
20592a94 | 17117 | if (intel_syntax) |
ea397f5b | 17118 | goto skip; |
20592a94 | 17119 | |
381d071f L |
17120 | *p++ = 'b'; |
17121 | break; | |
17122 | case v_mode: | |
20592a94 | 17123 | if (intel_syntax) |
ea397f5b | 17124 | goto skip; |
20592a94 | 17125 | |
381d071f L |
17126 | USED_REX (REX_W); |
17127 | if (rex & REX_W) | |
17128 | *p++ = 'q'; | |
7bb15c6f | 17129 | else |
f16cd0d5 L |
17130 | { |
17131 | if (sizeflag & DFLAG) | |
17132 | *p++ = 'l'; | |
17133 | else | |
17134 | *p++ = 'w'; | |
17135 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17136 | } | |
381d071f L |
17137 | break; |
17138 | default: | |
17139 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17140 | break; | |
17141 | } | |
ea397f5b | 17142 | mnemonicendp = p; |
381d071f L |
17143 | *p = '\0'; |
17144 | ||
ea397f5b | 17145 | skip: |
381d071f L |
17146 | if (modrm.mod == 3) |
17147 | { | |
17148 | int add; | |
17149 | ||
17150 | /* Skip mod/rm byte. */ | |
17151 | MODRM_CHECK; | |
17152 | codep++; | |
17153 | ||
17154 | USED_REX (REX_B); | |
17155 | add = (rex & REX_B) ? 8 : 0; | |
17156 | if (bytemode == b_mode) | |
17157 | { | |
17158 | USED_REX (0); | |
17159 | if (rex) | |
17160 | oappend (names8rex[modrm.rm + add]); | |
17161 | else | |
17162 | oappend (names8[modrm.rm + add]); | |
17163 | } | |
17164 | else | |
17165 | { | |
17166 | USED_REX (REX_W); | |
17167 | if (rex & REX_W) | |
17168 | oappend (names64[modrm.rm + add]); | |
17169 | else if ((prefixes & PREFIX_DATA)) | |
17170 | oappend (names16[modrm.rm + add]); | |
17171 | else | |
17172 | oappend (names32[modrm.rm + add]); | |
17173 | } | |
17174 | } | |
17175 | else | |
9344ff29 | 17176 | OP_E (bytemode, sizeflag); |
381d071f | 17177 | } |
85f10a01 | 17178 | |
eacc9c89 L |
17179 | static void |
17180 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
17181 | { | |
17182 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
17183 | USED_REX (REX_W); | |
17184 | if (rex & REX_W) | |
17185 | { | |
17186 | char *p = mnemonicendp; | |
17187 | *p++ = '6'; | |
17188 | *p++ = '4'; | |
17189 | *p = '\0'; | |
17190 | mnemonicendp = p; | |
17191 | } | |
17192 | OP_M (bytemode, sizeflag); | |
17193 | } | |
17194 | ||
15c7c1d8 JB |
17195 | static void |
17196 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
17197 | { | |
17198 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
17199 | if (!intel_syntax) | |
17200 | { | |
17201 | char *p = mnemonicendp; | |
17202 | ||
17203 | USED_REX (REX_W); | |
17204 | if (rex & REX_W) | |
17205 | *p++ = 'q'; | |
17206 | else if (sizeflag & SUFFIX_ALWAYS) | |
17207 | *p++ = 'l'; | |
17208 | ||
17209 | *p = '\0'; | |
17210 | mnemonicendp = p; | |
17211 | } | |
17212 | ||
17213 | OP_EX (bytemode, sizeflag); | |
17214 | } | |
17215 | ||
c0f3af97 L |
17216 | /* Display the destination register operand for instructions with |
17217 | VEX. */ | |
17218 | ||
17219 | static void | |
17220 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17221 | { | |
539f890d | 17222 | int reg; |
b9733481 L |
17223 | const char **names; |
17224 | ||
c0f3af97 L |
17225 | if (!need_vex) |
17226 | abort (); | |
17227 | ||
17228 | if (!need_vex_reg) | |
17229 | return; | |
17230 | ||
539f890d | 17231 | reg = vex.register_specifier; |
5f847646 JB |
17232 | if (address_mode != mode_64bit) |
17233 | reg &= 7; | |
17234 | else if (vex.evex && !vex.v) | |
17235 | reg += 16; | |
43234a1e | 17236 | |
539f890d L |
17237 | if (bytemode == vex_scalar_mode) |
17238 | { | |
17239 | oappend (names_xmm[reg]); | |
17240 | return; | |
17241 | } | |
17242 | ||
c0f3af97 L |
17243 | switch (vex.length) |
17244 | { | |
17245 | case 128: | |
17246 | switch (bytemode) | |
17247 | { | |
17248 | case vex_mode: | |
17249 | case vex128_mode: | |
6c30d220 | 17250 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 17251 | case vex_vsib_q_w_d_mode: |
cb21baef L |
17252 | names = names_xmm; |
17253 | break; | |
17254 | case dq_mode: | |
390a6789 | 17255 | if (rex & REX_W) |
cb21baef L |
17256 | names = names64; |
17257 | else | |
17258 | names = names32; | |
c0f3af97 | 17259 | break; |
1ba585e8 | 17260 | case mask_bd_mode: |
43234a1e | 17261 | case mask_mode: |
9889cbb1 L |
17262 | if (reg > 0x7) |
17263 | { | |
17264 | oappend ("(bad)"); | |
17265 | return; | |
17266 | } | |
43234a1e L |
17267 | names = names_mask; |
17268 | break; | |
c0f3af97 L |
17269 | default: |
17270 | abort (); | |
17271 | return; | |
17272 | } | |
c0f3af97 L |
17273 | break; |
17274 | case 256: | |
17275 | switch (bytemode) | |
17276 | { | |
17277 | case vex_mode: | |
17278 | case vex256_mode: | |
6c30d220 L |
17279 | names = names_ymm; |
17280 | break; | |
17281 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 17282 | case vex_vsib_q_w_d_mode: |
6c30d220 | 17283 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 17284 | break; |
1ba585e8 | 17285 | case mask_bd_mode: |
43234a1e | 17286 | case mask_mode: |
9889cbb1 L |
17287 | if (reg > 0x7) |
17288 | { | |
17289 | oappend ("(bad)"); | |
17290 | return; | |
17291 | } | |
43234a1e L |
17292 | names = names_mask; |
17293 | break; | |
c0f3af97 | 17294 | default: |
a37a2806 NC |
17295 | /* See PR binutils/20893 for a reproducer. */ |
17296 | oappend ("(bad)"); | |
c0f3af97 L |
17297 | return; |
17298 | } | |
c0f3af97 | 17299 | break; |
43234a1e L |
17300 | case 512: |
17301 | names = names_zmm; | |
17302 | break; | |
c0f3af97 L |
17303 | default: |
17304 | abort (); | |
17305 | break; | |
17306 | } | |
539f890d | 17307 | oappend (names[reg]); |
c0f3af97 L |
17308 | } |
17309 | ||
922d8de8 DR |
17310 | /* Get the VEX immediate byte without moving codep. */ |
17311 | ||
17312 | static unsigned char | |
ccc5981b | 17313 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17314 | { |
17315 | int bytes_before_imm = 0; | |
17316 | ||
922d8de8 DR |
17317 | if (modrm.mod != 3) |
17318 | { | |
17319 | /* There are SIB/displacement bytes. */ | |
17320 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17321 | { |
922d8de8 | 17322 | /* 32/64 bit address mode */ |
6c067bbb | 17323 | int base = modrm.rm; |
922d8de8 DR |
17324 | |
17325 | /* Check SIB byte. */ | |
6c067bbb RM |
17326 | if (base == 4) |
17327 | { | |
17328 | FETCH_DATA (the_info, codep + 1); | |
17329 | base = *codep & 7; | |
17330 | /* When decoding the third source, don't increase | |
17331 | bytes_before_imm as this has already been incremented | |
17332 | by one in OP_E_memory while decoding the second | |
17333 | source operand. */ | |
17334 | if (opnum == 0) | |
17335 | bytes_before_imm++; | |
17336 | } | |
17337 | ||
17338 | /* Don't increase bytes_before_imm when decoding the third source, | |
17339 | it has already been incremented by OP_E_memory while decoding | |
17340 | the second source operand. */ | |
17341 | if (opnum == 0) | |
17342 | { | |
17343 | switch (modrm.mod) | |
17344 | { | |
17345 | case 0: | |
17346 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17347 | SIB == 5, there is a 4 byte displacement. */ | |
17348 | if (base != 5) | |
17349 | /* No displacement. */ | |
17350 | break; | |
1a0670f3 | 17351 | /* Fall through. */ |
6c067bbb RM |
17352 | case 2: |
17353 | /* 4 byte displacement. */ | |
17354 | bytes_before_imm += 4; | |
17355 | break; | |
17356 | case 1: | |
17357 | /* 1 byte displacement. */ | |
17358 | bytes_before_imm++; | |
17359 | break; | |
17360 | } | |
17361 | } | |
17362 | } | |
922d8de8 | 17363 | else |
02e647f9 SP |
17364 | { |
17365 | /* 16 bit address mode */ | |
6c067bbb RM |
17366 | /* Don't increase bytes_before_imm when decoding the third source, |
17367 | it has already been incremented by OP_E_memory while decoding | |
17368 | the second source operand. */ | |
17369 | if (opnum == 0) | |
17370 | { | |
02e647f9 SP |
17371 | switch (modrm.mod) |
17372 | { | |
17373 | case 0: | |
17374 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17375 | if (modrm.rm != 6) | |
17376 | /* No displacement. */ | |
17377 | break; | |
1a0670f3 | 17378 | /* Fall through. */ |
02e647f9 SP |
17379 | case 2: |
17380 | /* 2 byte displacement. */ | |
17381 | bytes_before_imm += 2; | |
17382 | break; | |
17383 | case 1: | |
17384 | /* 1 byte displacement: when decoding the third source, | |
17385 | don't increase bytes_before_imm as this has already | |
17386 | been incremented by one in OP_E_memory while decoding | |
17387 | the second source operand. */ | |
17388 | if (opnum == 0) | |
17389 | bytes_before_imm++; | |
ccc5981b | 17390 | |
02e647f9 SP |
17391 | break; |
17392 | } | |
922d8de8 DR |
17393 | } |
17394 | } | |
17395 | } | |
17396 | ||
17397 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17398 | return codep [bytes_before_imm]; | |
17399 | } | |
17400 | ||
17401 | static void | |
17402 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17403 | { | |
b9733481 L |
17404 | const char **names; |
17405 | ||
922d8de8 DR |
17406 | if (reg == -1 && modrm.mod != 3) |
17407 | { | |
17408 | OP_E_memory (bytemode, sizeflag); | |
17409 | return; | |
17410 | } | |
17411 | else | |
17412 | { | |
17413 | if (reg == -1) | |
17414 | { | |
17415 | reg = modrm.rm; | |
17416 | USED_REX (REX_B); | |
17417 | if (rex & REX_B) | |
17418 | reg += 8; | |
17419 | } | |
5f847646 JB |
17420 | if (address_mode != mode_64bit) |
17421 | reg &= 7; | |
922d8de8 DR |
17422 | } |
17423 | ||
17424 | switch (vex.length) | |
17425 | { | |
17426 | case 128: | |
b9733481 | 17427 | names = names_xmm; |
922d8de8 DR |
17428 | break; |
17429 | case 256: | |
b9733481 | 17430 | names = names_ymm; |
922d8de8 DR |
17431 | break; |
17432 | default: | |
17433 | abort (); | |
17434 | } | |
b9733481 | 17435 | oappend (names[reg]); |
922d8de8 DR |
17436 | } |
17437 | ||
a683cc34 SP |
17438 | static void |
17439 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17440 | { | |
17441 | int reg = -1; | |
17442 | static unsigned char vex_imm8; | |
17443 | ||
17444 | if (vex_w_done == 0) | |
17445 | { | |
17446 | vex_w_done = 1; | |
17447 | ||
17448 | /* Skip mod/rm byte. */ | |
17449 | MODRM_CHECK; | |
17450 | codep++; | |
17451 | ||
17452 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17453 | ||
17454 | if (vex.w) | |
17455 | reg = vex_imm8 >> 4; | |
17456 | ||
17457 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17458 | } | |
17459 | else if (vex_w_done == 1) | |
17460 | { | |
17461 | vex_w_done = 2; | |
17462 | ||
17463 | if (!vex.w) | |
17464 | reg = vex_imm8 >> 4; | |
17465 | ||
17466 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17467 | } | |
17468 | else | |
17469 | { | |
17470 | /* Output the imm8 directly. */ | |
17471 | scratchbuf[0] = '$'; | |
17472 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17473 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17474 | scratchbuf[0] = '\0'; |
17475 | codep++; | |
17476 | } | |
17477 | } | |
17478 | ||
5dd85c99 SP |
17479 | static void |
17480 | OP_Vex_2src (int bytemode, int sizeflag) | |
17481 | { | |
17482 | if (modrm.mod == 3) | |
17483 | { | |
b9733481 | 17484 | int reg = modrm.rm; |
5dd85c99 | 17485 | USED_REX (REX_B); |
b9733481 L |
17486 | if (rex & REX_B) |
17487 | reg += 8; | |
17488 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17489 | } |
17490 | else | |
17491 | { | |
17492 | if (intel_syntax | |
17493 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17494 | { | |
17495 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17496 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17497 | } | |
17498 | OP_E (bytemode, sizeflag); | |
17499 | } | |
17500 | } | |
17501 | ||
17502 | static void | |
17503 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17504 | { | |
17505 | if (modrm.mod == 3) | |
17506 | { | |
17507 | /* Skip mod/rm byte. */ | |
17508 | MODRM_CHECK; | |
17509 | codep++; | |
17510 | } | |
17511 | ||
17512 | if (vex.w) | |
5f847646 JB |
17513 | { |
17514 | unsigned int reg = vex.register_specifier; | |
17515 | ||
17516 | if (address_mode != mode_64bit) | |
17517 | reg &= 7; | |
17518 | oappend (names_xmm[reg]); | |
17519 | } | |
5dd85c99 SP |
17520 | else |
17521 | OP_Vex_2src (bytemode, sizeflag); | |
17522 | } | |
17523 | ||
17524 | static void | |
17525 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17526 | { | |
17527 | if (vex.w) | |
17528 | OP_Vex_2src (bytemode, sizeflag); | |
17529 | else | |
5f847646 JB |
17530 | { |
17531 | unsigned int reg = vex.register_specifier; | |
17532 | ||
17533 | if (address_mode != mode_64bit) | |
17534 | reg &= 7; | |
17535 | oappend (names_xmm[reg]); | |
17536 | } | |
5dd85c99 SP |
17537 | } |
17538 | ||
922d8de8 DR |
17539 | static void |
17540 | OP_EX_VexW (int bytemode, int sizeflag) | |
17541 | { | |
17542 | int reg = -1; | |
17543 | ||
17544 | if (!vex_w_done) | |
17545 | { | |
41effecb SP |
17546 | /* Skip mod/rm byte. */ |
17547 | MODRM_CHECK; | |
17548 | codep++; | |
17549 | ||
922d8de8 | 17550 | if (vex.w) |
ccc5981b | 17551 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17552 | } |
17553 | else | |
17554 | { | |
17555 | if (!vex.w) | |
ccc5981b | 17556 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17557 | } |
17558 | ||
17559 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 17560 | |
3a2430e0 JB |
17561 | if (vex_w_done) |
17562 | codep++; | |
17563 | vex_w_done = 1; | |
922d8de8 DR |
17564 | } |
17565 | ||
c0f3af97 L |
17566 | static void |
17567 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17568 | { | |
17569 | int reg; | |
b9733481 L |
17570 | const char **names; |
17571 | ||
c0f3af97 L |
17572 | FETCH_DATA (the_info, codep + 1); |
17573 | reg = *codep++; | |
17574 | ||
17575 | if (bytemode != x_mode) | |
17576 | abort (); | |
17577 | ||
c0f3af97 | 17578 | reg >>= 4; |
5f847646 JB |
17579 | if (address_mode != mode_64bit) |
17580 | reg &= 7; | |
dae39acc | 17581 | |
c0f3af97 L |
17582 | switch (vex.length) |
17583 | { | |
17584 | case 128: | |
b9733481 | 17585 | names = names_xmm; |
c0f3af97 L |
17586 | break; |
17587 | case 256: | |
b9733481 | 17588 | names = names_ymm; |
c0f3af97 L |
17589 | break; |
17590 | default: | |
17591 | abort (); | |
17592 | } | |
b9733481 | 17593 | oappend (names[reg]); |
c0f3af97 L |
17594 | } |
17595 | ||
922d8de8 DR |
17596 | static void |
17597 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17598 | { | |
17599 | /* Turn off the REX.W bit since it is used for swapping operands | |
17600 | now. */ | |
17601 | rex &= ~REX_W; | |
17602 | OP_XMM (bytemode, sizeflag); | |
17603 | } | |
17604 | ||
c0f3af97 L |
17605 | static void |
17606 | OP_EX_Vex (int bytemode, int sizeflag) | |
17607 | { | |
17608 | if (modrm.mod != 3) | |
17609 | { | |
17610 | if (vex.register_specifier != 0) | |
17611 | BadOp (); | |
17612 | need_vex_reg = 0; | |
17613 | } | |
17614 | OP_EX (bytemode, sizeflag); | |
17615 | } | |
17616 | ||
17617 | static void | |
17618 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17619 | { | |
17620 | if (modrm.mod != 3) | |
17621 | { | |
17622 | if (vex.register_specifier != 0) | |
17623 | BadOp (); | |
17624 | need_vex_reg = 0; | |
17625 | } | |
17626 | OP_XMM (bytemode, sizeflag); | |
17627 | } | |
17628 | ||
17629 | static void | |
17630 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17631 | { | |
17632 | switch (vex.length) | |
17633 | { | |
17634 | case 128: | |
ea397f5b | 17635 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17636 | break; |
17637 | case 256: | |
ea397f5b | 17638 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17639 | break; |
17640 | default: | |
17641 | abort (); | |
17642 | } | |
17643 | } | |
17644 | ||
ea397f5b L |
17645 | static struct op vex_cmp_op[] = |
17646 | { | |
17647 | { STRING_COMMA_LEN ("eq") }, | |
17648 | { STRING_COMMA_LEN ("lt") }, | |
17649 | { STRING_COMMA_LEN ("le") }, | |
17650 | { STRING_COMMA_LEN ("unord") }, | |
17651 | { STRING_COMMA_LEN ("neq") }, | |
17652 | { STRING_COMMA_LEN ("nlt") }, | |
17653 | { STRING_COMMA_LEN ("nle") }, | |
17654 | { STRING_COMMA_LEN ("ord") }, | |
17655 | { STRING_COMMA_LEN ("eq_uq") }, | |
17656 | { STRING_COMMA_LEN ("nge") }, | |
17657 | { STRING_COMMA_LEN ("ngt") }, | |
17658 | { STRING_COMMA_LEN ("false") }, | |
17659 | { STRING_COMMA_LEN ("neq_oq") }, | |
17660 | { STRING_COMMA_LEN ("ge") }, | |
17661 | { STRING_COMMA_LEN ("gt") }, | |
17662 | { STRING_COMMA_LEN ("true") }, | |
17663 | { STRING_COMMA_LEN ("eq_os") }, | |
17664 | { STRING_COMMA_LEN ("lt_oq") }, | |
17665 | { STRING_COMMA_LEN ("le_oq") }, | |
17666 | { STRING_COMMA_LEN ("unord_s") }, | |
17667 | { STRING_COMMA_LEN ("neq_us") }, | |
17668 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17669 | { STRING_COMMA_LEN ("nle_uq") }, | |
17670 | { STRING_COMMA_LEN ("ord_s") }, | |
17671 | { STRING_COMMA_LEN ("eq_us") }, | |
17672 | { STRING_COMMA_LEN ("nge_uq") }, | |
17673 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17674 | { STRING_COMMA_LEN ("false_os") }, | |
17675 | { STRING_COMMA_LEN ("neq_os") }, | |
17676 | { STRING_COMMA_LEN ("ge_oq") }, | |
17677 | { STRING_COMMA_LEN ("gt_oq") }, | |
17678 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17679 | }; |
17680 | ||
17681 | static void | |
17682 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17683 | { | |
17684 | unsigned int cmp_type; | |
17685 | ||
17686 | FETCH_DATA (the_info, codep + 1); | |
17687 | cmp_type = *codep++ & 0xff; | |
17688 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17689 | { | |
17690 | char suffix [3]; | |
ea397f5b | 17691 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17692 | suffix[0] = p[0]; |
17693 | suffix[1] = p[1]; | |
17694 | suffix[2] = '\0'; | |
ea397f5b L |
17695 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17696 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17697 | } |
17698 | else | |
17699 | { | |
17700 | /* We have a reserved extension byte. Output it directly. */ | |
17701 | scratchbuf[0] = '$'; | |
17702 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17703 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17704 | scratchbuf[0] = '\0'; |
17705 | } | |
17706 | } | |
17707 | ||
43234a1e L |
17708 | static void |
17709 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17710 | int sizeflag ATTRIBUTE_UNUSED) | |
17711 | { | |
17712 | unsigned int cmp_type; | |
17713 | ||
17714 | if (!vex.evex) | |
17715 | abort (); | |
17716 | ||
17717 | FETCH_DATA (the_info, codep + 1); | |
17718 | cmp_type = *codep++ & 0xff; | |
17719 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17720 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17721 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17722 | && cmp_type != 3 | |
17723 | && cmp_type != 7) | |
17724 | { | |
17725 | char suffix [3]; | |
17726 | char *p = mnemonicendp - 2; | |
17727 | ||
17728 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17729 | if (p[0] == 'p') | |
17730 | { | |
17731 | p++; | |
17732 | suffix[0] = p[0]; | |
17733 | suffix[1] = '\0'; | |
17734 | } | |
17735 | else | |
17736 | { | |
17737 | suffix[0] = p[0]; | |
17738 | suffix[1] = p[1]; | |
17739 | suffix[2] = '\0'; | |
17740 | } | |
17741 | ||
17742 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17743 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17744 | } | |
be92cb14 JB |
17745 | else |
17746 | { | |
17747 | /* We have a reserved extension byte. Output it directly. */ | |
17748 | scratchbuf[0] = '$'; | |
17749 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
17750 | oappend_maybe_intel (scratchbuf); | |
17751 | scratchbuf[0] = '\0'; | |
17752 | } | |
17753 | } | |
17754 | ||
17755 | static const struct op xop_cmp_op[] = | |
17756 | { | |
17757 | { STRING_COMMA_LEN ("lt") }, | |
17758 | { STRING_COMMA_LEN ("le") }, | |
17759 | { STRING_COMMA_LEN ("gt") }, | |
17760 | { STRING_COMMA_LEN ("ge") }, | |
17761 | { STRING_COMMA_LEN ("eq") }, | |
17762 | { STRING_COMMA_LEN ("neq") }, | |
17763 | { STRING_COMMA_LEN ("false") }, | |
17764 | { STRING_COMMA_LEN ("true") } | |
17765 | }; | |
17766 | ||
17767 | static void | |
17768 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17769 | int sizeflag ATTRIBUTE_UNUSED) | |
17770 | { | |
17771 | unsigned int cmp_type; | |
17772 | ||
17773 | FETCH_DATA (the_info, codep + 1); | |
17774 | cmp_type = *codep++ & 0xff; | |
17775 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
17776 | { | |
17777 | char suffix[3]; | |
17778 | char *p = mnemonicendp - 2; | |
17779 | ||
17780 | /* vpcom* can have both one- and two-lettered suffix. */ | |
17781 | if (p[0] == 'm') | |
17782 | { | |
17783 | p++; | |
17784 | suffix[0] = p[0]; | |
17785 | suffix[1] = '\0'; | |
17786 | } | |
17787 | else | |
17788 | { | |
17789 | suffix[0] = p[0]; | |
17790 | suffix[1] = p[1]; | |
17791 | suffix[2] = '\0'; | |
17792 | } | |
17793 | ||
17794 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
17795 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
17796 | } | |
43234a1e L |
17797 | else |
17798 | { | |
17799 | /* We have a reserved extension byte. Output it directly. */ | |
17800 | scratchbuf[0] = '$'; | |
17801 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17802 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17803 | scratchbuf[0] = '\0'; |
17804 | } | |
17805 | } | |
17806 | ||
ea397f5b L |
17807 | static const struct op pclmul_op[] = |
17808 | { | |
17809 | { STRING_COMMA_LEN ("lql") }, | |
17810 | { STRING_COMMA_LEN ("hql") }, | |
17811 | { STRING_COMMA_LEN ("lqh") }, | |
17812 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17813 | }; |
17814 | ||
17815 | static void | |
17816 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17817 | int sizeflag ATTRIBUTE_UNUSED) | |
17818 | { | |
17819 | unsigned int pclmul_type; | |
17820 | ||
17821 | FETCH_DATA (the_info, codep + 1); | |
17822 | pclmul_type = *codep++ & 0xff; | |
17823 | switch (pclmul_type) | |
17824 | { | |
17825 | case 0x10: | |
17826 | pclmul_type = 2; | |
17827 | break; | |
17828 | case 0x11: | |
17829 | pclmul_type = 3; | |
17830 | break; | |
17831 | default: | |
17832 | break; | |
7bb15c6f | 17833 | } |
c0f3af97 L |
17834 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17835 | { | |
17836 | char suffix [4]; | |
ea397f5b | 17837 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17838 | suffix[0] = p[0]; |
17839 | suffix[1] = p[1]; | |
17840 | suffix[2] = p[2]; | |
17841 | suffix[3] = '\0'; | |
ea397f5b L |
17842 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17843 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17844 | } |
17845 | else | |
17846 | { | |
17847 | /* We have a reserved extension byte. Output it directly. */ | |
17848 | scratchbuf[0] = '$'; | |
17849 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17850 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17851 | scratchbuf[0] = '\0'; |
17852 | } | |
17853 | } | |
17854 | ||
f1f8f695 L |
17855 | static void |
17856 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17857 | { | |
17858 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17859 | char *p = mnemonicendp; |
f1f8f695 L |
17860 | |
17861 | switch (bytemode) | |
17862 | { | |
17863 | case v_mode: | |
17864 | if (intel_syntax) | |
ea397f5b | 17865 | goto skip; |
f1f8f695 L |
17866 | |
17867 | USED_REX (REX_W); | |
17868 | if (sizeflag & SUFFIX_ALWAYS) | |
17869 | { | |
17870 | if (rex & REX_W) | |
17871 | *p++ = 'q'; | |
f1f8f695 | 17872 | else |
f16cd0d5 L |
17873 | { |
17874 | if (sizeflag & DFLAG) | |
17875 | *p++ = 'l'; | |
17876 | else | |
17877 | *p++ = 'w'; | |
17878 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17879 | } | |
f1f8f695 | 17880 | } |
f1f8f695 L |
17881 | break; |
17882 | default: | |
17883 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17884 | break; | |
17885 | } | |
ea397f5b | 17886 | mnemonicendp = p; |
f1f8f695 L |
17887 | *p = '\0'; |
17888 | ||
ea397f5b | 17889 | skip: |
f1f8f695 L |
17890 | OP_M (bytemode, sizeflag); |
17891 | } | |
f88c9eb0 SP |
17892 | |
17893 | static void | |
17894 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17895 | { | |
17896 | int reg; | |
17897 | const char **names; | |
17898 | ||
17899 | /* Skip mod/rm byte. */ | |
17900 | MODRM_CHECK; | |
17901 | codep++; | |
17902 | ||
390a6789 | 17903 | if (rex & REX_W) |
f88c9eb0 | 17904 | names = names64; |
f88c9eb0 | 17905 | else |
ce7d077e | 17906 | names = names32; |
f88c9eb0 SP |
17907 | |
17908 | reg = modrm.rm; | |
17909 | USED_REX (REX_B); | |
17910 | if (rex & REX_B) | |
17911 | reg += 8; | |
17912 | ||
17913 | oappend (names[reg]); | |
17914 | } | |
17915 | ||
17916 | static void | |
17917 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17918 | { | |
17919 | const char **names; | |
5f847646 | 17920 | unsigned int reg = vex.register_specifier; |
f88c9eb0 | 17921 | |
390a6789 | 17922 | if (rex & REX_W) |
f88c9eb0 | 17923 | names = names64; |
f88c9eb0 | 17924 | else |
ce7d077e | 17925 | names = names32; |
f88c9eb0 | 17926 | |
5f847646 JB |
17927 | if (address_mode != mode_64bit) |
17928 | reg &= 7; | |
17929 | oappend (names[reg]); | |
f88c9eb0 | 17930 | } |
43234a1e L |
17931 | |
17932 | static void | |
17933 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17934 | { | |
17935 | if (!vex.evex | |
1ba585e8 | 17936 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17937 | abort (); |
17938 | ||
17939 | USED_REX (REX_R); | |
17940 | if ((rex & REX_R) != 0 || !vex.r) | |
17941 | { | |
17942 | BadOp (); | |
17943 | return; | |
17944 | } | |
17945 | ||
17946 | oappend (names_mask [modrm.reg]); | |
17947 | } | |
17948 | ||
17949 | static void | |
17950 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17951 | { | |
17952 | if (!vex.evex | |
17953 | || (bytemode != evex_rounding_mode | |
70df6fc9 | 17954 | && bytemode != evex_rounding_64_mode |
43234a1e L |
17955 | && bytemode != evex_sae_mode)) |
17956 | abort (); | |
17957 | if (modrm.mod == 3 && vex.b) | |
17958 | switch (bytemode) | |
17959 | { | |
70df6fc9 L |
17960 | case evex_rounding_64_mode: |
17961 | if (address_mode != mode_64bit) | |
17962 | { | |
17963 | oappend ("(bad)"); | |
17964 | break; | |
17965 | } | |
17966 | /* Fall through. */ | |
43234a1e L |
17967 | case evex_rounding_mode: |
17968 | oappend (names_rounding[vex.ll]); | |
17969 | break; | |
17970 | case evex_sae_mode: | |
17971 | oappend ("{sae}"); | |
17972 | break; | |
17973 | default: | |
17974 | break; | |
17975 | } | |
17976 | } |