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(Set Breaks): Fix a typo.
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450
AJ		 97static void OP_3DNowSuffix (int, int);
98static void OP_SIMD_Suffix (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
239#define Gb { OP_G, b_mode }
240#define Gv { OP_G, v_mode }
241#define Gd { OP_G, d_mode }
242#define Gdq { OP_G, dq_mode }
243#define Gm { OP_G, m_mode }
244#define Gw { OP_G, w_mode }
6f74c397
L		 245#define Rd { OP_R, d_mode }
246#define Rm { OP_R, m_mode }
ce518a5f
L		 247#define Ib { OP_I, b_mode }
248#define sIb { OP_sI, b_mode } /* sign extened byte */
249#define Iv { OP_I, v_mode }
250#define Iq { OP_I, q_mode }
251#define Iv64 { OP_I64, v_mode }
252#define Iw { OP_I, w_mode }
253#define I1 { OP_I, const_1_mode }
254#define Jb { OP_J, b_mode }
255#define Jv { OP_J, v_mode }
256#define Cm { OP_C, m_mode }
257#define Dm { OP_D, m_mode }
258#define Td { OP_T, d_mode }
b844680a 259#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 260
261#define RMeAX { OP_REG, eAX_reg }
262#define RMeBX { OP_REG, eBX_reg }
263#define RMeCX { OP_REG, eCX_reg }
264#define RMeDX { OP_REG, eDX_reg }
265#define RMeSP { OP_REG, eSP_reg }
266#define RMeBP { OP_REG, eBP_reg }
267#define RMeSI { OP_REG, eSI_reg }
268#define RMeDI { OP_REG, eDI_reg }
269#define RMrAX { OP_REG, rAX_reg }
270#define RMrBX { OP_REG, rBX_reg }
271#define RMrCX { OP_REG, rCX_reg }
272#define RMrDX { OP_REG, rDX_reg }
273#define RMrSP { OP_REG, rSP_reg }
274#define RMrBP { OP_REG, rBP_reg }
275#define RMrSI { OP_REG, rSI_reg }
276#define RMrDI { OP_REG, rDI_reg }
277#define RMAL { OP_REG, al_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMCL { OP_REG, cl_reg }
280#define RMDL { OP_REG, dl_reg }
281#define RMBL { OP_REG, bl_reg }
282#define RMAH { OP_REG, ah_reg }
283#define RMCH { OP_REG, ch_reg }
284#define RMDH { OP_REG, dh_reg }
285#define RMBH { OP_REG, bh_reg }
286#define RMAX { OP_REG, ax_reg }
287#define RMDX { OP_REG, dx_reg }
288
289#define eAX { OP_IMREG, eAX_reg }
290#define eBX { OP_IMREG, eBX_reg }
291#define eCX { OP_IMREG, eCX_reg }
292#define eDX { OP_IMREG, eDX_reg }
293#define eSP { OP_IMREG, eSP_reg }
294#define eBP { OP_IMREG, eBP_reg }
295#define eSI { OP_IMREG, eSI_reg }
296#define eDI { OP_IMREG, eDI_reg }
297#define AL { OP_IMREG, al_reg }
298#define CL { OP_IMREG, cl_reg }
299#define DL { OP_IMREG, dl_reg }
300#define BL { OP_IMREG, bl_reg }
301#define AH { OP_IMREG, ah_reg }
302#define CH { OP_IMREG, ch_reg }
303#define DH { OP_IMREG, dh_reg }
304#define BH { OP_IMREG, bh_reg }
305#define AX { OP_IMREG, ax_reg }
306#define DX { OP_IMREG, dx_reg }
307#define zAX { OP_IMREG, z_mode_ax_reg }
308#define indirDX { OP_IMREG, indir_dx_reg }
309
310#define Sw { OP_SEG, w_mode }
311#define Sv { OP_SEG, v_mode }
312#define Ap { OP_DIR, 0 }
313#define Ob { OP_OFF64, b_mode }
314#define Ov { OP_OFF64, v_mode }
315#define Xb { OP_DSreg, eSI_reg }
316#define Xv { OP_DSreg, eSI_reg }
317#define Xz { OP_DSreg, eSI_reg }
318#define Yb { OP_ESreg, eDI_reg }
319#define Yv { OP_ESreg, eDI_reg }
320#define DSBX { OP_DSreg, eBX_reg }
321
322#define es { OP_REG, es_reg }
323#define ss { OP_REG, ss_reg }
324#define cs { OP_REG, cs_reg }
325#define ds { OP_REG, ds_reg }
326#define fs { OP_REG, fs_reg }
327#define gs { OP_REG, gs_reg }
328
329#define MX { OP_MMX, 0 }
330#define XM { OP_XMM, 0 }
331#define EM { OP_EM, v_mode }
09a2c6cf 332#define EMd { OP_EM, d_mode }
14051056 333#define EMx { OP_EM, x_mode }
8976381e 334#define EXw { OP_EX, w_mode }
09a2c6cf
L		 335#define EXd { OP_EX, d_mode }
336#define EXq { OP_EX, q_mode }
337#define EXx { OP_EX, x_mode }
ce518a5f
L		 338#define MS { OP_MS, v_mode }
339#define XS { OP_XS, v_mode }
09335d05 340#define EMCq { OP_EMC, q_mode }
ce518a5f 341#define MXC { OP_MXC, 0 }
ce518a5f
L		 342#define OPSUF { OP_3DNowSuffix, 0 }
343#define OPSIMD { OP_SIMD_Suffix, 0 }
42903f7f 344#define XMM0 { XMM_Fixup, 0 }
252b5132 345
35c52694 346/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 347#define Xbr { REP_Fixup, eSI_reg }
348#define Xvr { REP_Fixup, eSI_reg }
349#define Ybr { REP_Fixup, eDI_reg }
350#define Yvr { REP_Fixup, eDI_reg }
351#define Yzr { REP_Fixup, eDI_reg }
352#define indirDXr { REP_Fixup, indir_dx_reg }
353#define ALr { REP_Fixup, al_reg }
354#define eAXr { REP_Fixup, eAX_reg }
355
356#define cond_jump_flag { NULL, cond_jump_mode }
357#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 358
252b5132 359/* bits in sizeflag */
252b5132 360#define SUFFIX_ALWAYS 4
252b5132
RH		 361#define AFLAG 2
362#define DFLAG 1
363
52b15da3
JH		 364#define b_mode 1 /* byte operand */
365#define v_mode 2 /* operand size depends on prefixes */
366#define w_mode 3 /* word operand */
367#define d_mode 4 /* double word operand */
368#define q_mode 5 /* quad word operand */
9306ca4a
JB		 369#define t_mode 6 /* ten-byte operand */
370#define x_mode 7 /* 16-byte XMM operand */
371#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
372#define cond_jump_mode 9
373#define loop_jcxz_mode 10
374#define dq_mode 11 /* operand size depends on REX prefixes. */
375#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
376#define f_mode 13 /* 4- or 6-byte pointer operand */
377#define const_1_mode 14
1a114b12 378#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
52fd6d94 379#define z_mode 16 /* non-quad operand size depends on prefixes */
fb9c77c7 380#define o_mode 17 /* 16-byte operand */
42903f7f
L		 381#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
382#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
252b5132 383
85f10a01
MM		 384/* Flags that are OR'ed into the bytemode field to pass extra information. */
385#define DREX_OC1 0x4000 /* OC1 bit set */
386#define DREX_NO_OC0 0x2000 /* OC0 bit not used */
387#define DREX_MASK 0x6000 /* mask to delete */
388
252b5132
RH		 389#define es_reg 100
390#define cs_reg 101
391#define ss_reg 102
392#define ds_reg 103
393#define fs_reg 104
394#define gs_reg 105
252b5132 395
c608c12e
AM		 396#define eAX_reg 108
397#define eCX_reg 109
398#define eDX_reg 110
399#define eBX_reg 111
400#define eSP_reg 112
401#define eBP_reg 113
402#define eSI_reg 114
403#define eDI_reg 115
252b5132
RH		 404
405#define al_reg 116
406#define cl_reg 117
407#define dl_reg 118
408#define bl_reg 119
409#define ah_reg 120
410#define ch_reg 121
411#define dh_reg 122
412#define bh_reg 123
413
414#define ax_reg 124
415#define cx_reg 125
416#define dx_reg 126
417#define bx_reg 127
418#define sp_reg 128
419#define bp_reg 129
420#define si_reg 130
421#define di_reg 131
422
52b15da3
JH		 423#define rAX_reg 132
424#define rCX_reg 133
425#define rDX_reg 134
426#define rBX_reg 135
427#define rSP_reg 136
428#define rBP_reg 137
429#define rSI_reg 138
430#define rDI_reg 139
431
52fd6d94 432#define z_mode_ax_reg 149
252b5132
RH		 433#define indir_dx_reg 150
434
6439fc28
AM		 435#define FLOATCODE 1
436#define USE_GROUPS 2
437#define USE_PREFIX_USER_TABLE 3
438#define X86_64_SPECIAL 4
331d2d0d 439#define IS_3BYTE_OPCODE 5
b844680a
L		 440#define USE_OPC_EXT_TABLE 6
441#define USE_OPC_EXT_RM_TABLE 7
6439fc28 442
4efba78c
L		 443#define FLOAT NULL, { { NULL, FLOATCODE } }
444
7967e09e
L		 445#define GRP1a NULL, { { NULL, USE_GROUPS }, { NULL, 0 } }
446#define GRP1b NULL, { { NULL, USE_GROUPS }, { NULL, 1 } }
447#define GRP1S NULL, { { NULL, USE_GROUPS }, { NULL, 2 } }
448#define GRP1Ss NULL, { { NULL, USE_GROUPS }, { NULL, 3 } }
449#define GRP2b NULL, { { NULL, USE_GROUPS }, { NULL, 4 } }
450#define GRP2S NULL, { { NULL, USE_GROUPS }, { NULL, 5 } }
451#define GRP2b_one NULL, { { NULL, USE_GROUPS }, { NULL, 6 } }
452#define GRP2S_one NULL, { { NULL, USE_GROUPS }, { NULL, 7 } }
453#define GRP2b_cl NULL, { { NULL, USE_GROUPS }, { NULL, 8 } }
454#define GRP2S_cl NULL, { { NULL, USE_GROUPS }, { NULL, 9 } }
455#define GRP3b NULL, { { NULL, USE_GROUPS }, { NULL, 10 } }
456#define GRP3S NULL, { { NULL, USE_GROUPS }, { NULL, 11 } }
457#define GRP4 NULL, { { NULL, USE_GROUPS }, { NULL, 12 } }
458#define GRP5 NULL, { { NULL, USE_GROUPS }, { NULL, 13 } }
459#define GRP6 NULL, { { NULL, USE_GROUPS }, { NULL, 14 } }
460#define GRP7 NULL, { { NULL, USE_GROUPS }, { NULL, 15 } }
461#define GRP8 NULL, { { NULL, USE_GROUPS }, { NULL, 16 } }
462#define GRP9 NULL, { { NULL, USE_GROUPS }, { NULL, 17 } }
463#define GRP11_C6 NULL, { { NULL, USE_GROUPS }, { NULL, 18 } }
464#define GRP11_C7 NULL, { { NULL, USE_GROUPS }, { NULL, 19 } }
465#define GRP12 NULL, { { NULL, USE_GROUPS }, { NULL, 20 } }
466#define GRP13 NULL, { { NULL, USE_GROUPS }, { NULL, 21 } }
467#define GRP14 NULL, { { NULL, USE_GROUPS }, { NULL, 22 } }
468#define GRP15 NULL, { { NULL, USE_GROUPS }, { NULL, 23 } }
469#define GRP16 NULL, { { NULL, USE_GROUPS }, { NULL, 24 } }
470#define GRPAMD NULL, { { NULL, USE_GROUPS }, { NULL, 25 } }
471#define GRPPADLCK1 NULL, { { NULL, USE_GROUPS }, { NULL, 26 } }
472#define GRPPADLCK2 NULL, { { NULL, USE_GROUPS }, { NULL, 27 } }
4efba78c
L		 473
474#define PREGRP0 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 0 } }
475#define PREGRP1 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 1 } }
476#define PREGRP2 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 2 } }
477#define PREGRP3 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 3 } }
478#define PREGRP4 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 4 } }
479#define PREGRP5 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 5 } }
480#define PREGRP6 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 6 } }
481#define PREGRP7 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 7 } }
482#define PREGRP8 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 8 } }
483#define PREGRP9 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 9 } }
484#define PREGRP10 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 10 } }
485#define PREGRP11 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 11 } }
486#define PREGRP12 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 12 } }
487#define PREGRP13 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 13 } }
488#define PREGRP14 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 14 } }
489#define PREGRP15 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 15 } }
490#define PREGRP16 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 16 } }
491#define PREGRP17 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 17 } }
492#define PREGRP18 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 18 } }
493#define PREGRP19 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 19 } }
494#define PREGRP20 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 20 } }
495#define PREGRP21 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 21 } }
496#define PREGRP22 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 22 } }
497#define PREGRP23 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 23 } }
498#define PREGRP24 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 24 } }
499#define PREGRP25 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 25 } }
500#define PREGRP26 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 26 } }
501#define PREGRP27 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 27 } }
502#define PREGRP28 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 28 } }
503#define PREGRP29 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 29 } }
504#define PREGRP30 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 30 } }
505#define PREGRP31 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 31 } }
506#define PREGRP32 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 32 } }
507#define PREGRP33 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 33 } }
508#define PREGRP34 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 34 } }
509#define PREGRP35 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 35 } }
510#define PREGRP36 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 36 } }
511#define PREGRP37 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 37 } }
8b38ad71 512#define PREGRP38 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 38 } }
42903f7f
L		 513#define PREGRP39 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 39 } }
514#define PREGRP40 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 40 } }
515#define PREGRP41 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 41 } }
516#define PREGRP42 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 42 } }
517#define PREGRP43 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 43 } }
518#define PREGRP44 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 44 } }
519#define PREGRP45 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 45 } }
520#define PREGRP46 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 46 } }
521#define PREGRP47 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 47 } }
522#define PREGRP48 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 48 } }
523#define PREGRP49 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 49 } }
524#define PREGRP50 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 50 } }
525#define PREGRP51 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 51 } }
526#define PREGRP52 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 52 } }
527#define PREGRP53 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 53 } }
528#define PREGRP54 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 54 } }
529#define PREGRP55 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 55 } }
530#define PREGRP56 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 56 } }
531#define PREGRP57 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 57 } }
532#define PREGRP58 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 58 } }
533#define PREGRP59 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 59 } }
534#define PREGRP60 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 60 } }
535#define PREGRP61 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 61 } }
536#define PREGRP62 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 62 } }
537#define PREGRP63 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 63 } }
538#define PREGRP64 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 64 } }
539#define PREGRP65 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 65 } }
540#define PREGRP66 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 66 } }
541#define PREGRP67 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 67 } }
542#define PREGRP68 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 68 } }
543#define PREGRP69 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 69 } }
544#define PREGRP70 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 70 } }
545#define PREGRP71 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 71 } }
546#define PREGRP72 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 72 } }
547#define PREGRP73 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 73 } }
548#define PREGRP74 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 74 } }
549#define PREGRP75 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 75 } }
550#define PREGRP76 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 76 } }
551#define PREGRP77 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 77 } }
552#define PREGRP78 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 78 } }
553#define PREGRP79 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 79 } }
554#define PREGRP80 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 80 } }
555#define PREGRP81 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 81 } }
556#define PREGRP82 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 82 } }
557#define PREGRP83 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 83 } }
558#define PREGRP84 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 84 } }
559#define PREGRP85 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 85 } }
381d071f
L		 560#define PREGRP86 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 86 } }
561#define PREGRP87 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 87 } }
562#define PREGRP88 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 88 } }
563#define PREGRP89 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 89 } }
564#define PREGRP90 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 90 } }
565#define PREGRP91 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 91 } }
566#define PREGRP92 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 92 } }
09a2c6cf
L		 567#define PREGRP93 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 93 } }
568#define PREGRP94 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 94 } }
569#define PREGRP95 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 95 } }
570#define PREGRP96 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 96 } }
571#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } }
b844680a
L		 572#define PREGRP98 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 98 } }
573#define PREGRP99 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 99 } }
574#define PREGRP100 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 100 } }
4efba78c
L		 575
576
577#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
578#define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } }
579#define X86_64_2 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 2 } }
580#define X86_64_3 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 3 } }
7c52e0e8
L		 581#define X86_64_4 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 4 } }
582#define X86_64_5 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 5 } }
583#define X86_64_6 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 6 } }
584#define X86_64_7 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 7 } }
585#define X86_64_8 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 8 } }
586#define X86_64_9 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 9 } }
587#define X86_64_10 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 10 } }
588#define X86_64_11 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 11 } }
589#define X86_64_12 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 12 } }
590#define X86_64_13 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 13 } }
591#define X86_64_14 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 14 } }
592#define X86_64_15 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 15 } }
593#define X86_64_16 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 16 } }
594#define X86_64_17 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 17 } }
595#define X86_64_18 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 18 } }
596#define X86_64_19 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 19 } }
597#define X86_64_20 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 20 } }
598#define X86_64_21 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 21 } }
599#define X86_64_22 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 22 } }
600#define X86_64_23 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 23 } }
601#define X86_64_24 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 24 } }
602#define X86_64_25 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 25 } }
603#define X86_64_26 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 26 } }
604#define X86_64_27 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 27 } }
4efba78c
L		 605
606#define THREE_BYTE_0 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 0 } }
607#define THREE_BYTE_1 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 1 } }
85f10a01
MM		 608#define THREE_BYTE_SSE5_0F24 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 2 } }
609#define THREE_BYTE_SSE5_0F25 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 3 } }
610#define THREE_BYTE_SSE5_0F7A NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 4 } }
611#define THREE_BYTE_SSE5_0F7B NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 5 } }
331d2d0d 612
b844680a
L		 613#define OPC_EXT_0 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 0 } }
614#define OPC_EXT_1 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 1 } }
615#define OPC_EXT_2 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 2 } }
616#define OPC_EXT_3 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 3 } }
617#define OPC_EXT_4 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 4 } }
618#define OPC_EXT_5 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 5 } }
619#define OPC_EXT_6 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 6 } }
620#define OPC_EXT_7 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 7 } }
621#define OPC_EXT_8 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 8 } }
622#define OPC_EXT_9 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 9 } }
623#define OPC_EXT_10 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 10 } }
624#define OPC_EXT_11 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 11 } }
625#define OPC_EXT_12 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 12 } }
626#define OPC_EXT_13 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 13 } }
627#define OPC_EXT_14 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 14 } }
628#define OPC_EXT_15 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 15 } }
629#define OPC_EXT_16 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 16 } }
630#define OPC_EXT_17 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 17 } }
631#define OPC_EXT_18 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 18 } }
632#define OPC_EXT_19 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 19 } }
633#define OPC_EXT_20 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 20 } }
634#define OPC_EXT_21 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 21 } }
635#define OPC_EXT_22 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 22 } }
636#define OPC_EXT_23 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 23 } }
637#define OPC_EXT_24 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 24 } }
d8faab4e
L		 638#define OPC_EXT_25 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 25 } }
639#define OPC_EXT_26 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 26 } }
640#define OPC_EXT_27 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 27 } }
641#define OPC_EXT_28 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 28 } }
642#define OPC_EXT_29 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 29 } }
643#define OPC_EXT_30 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 30 } }
644#define OPC_EXT_31 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 31 } }
645#define OPC_EXT_32 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 32 } }
646#define OPC_EXT_33 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 33 } }
876d4bfa
L		 647#define OPC_EXT_34 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 34 } }
648#define OPC_EXT_35 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 35 } }
649#define OPC_EXT_36 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 36 } }
650#define OPC_EXT_37 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 37 } }
bbedc832 651#define OPC_EXT_38 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 38 } }
144c41d9 652#define OPC_EXT_39 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 39 } }
1afd85e3
L		 653#define OPC_EXT_40 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 40 } }
654#define OPC_EXT_41 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 41 } }
655#define OPC_EXT_42 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 42 } }
656#define OPC_EXT_43 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 43 } }
657#define OPC_EXT_44 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 44 } }
658#define OPC_EXT_45 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 45 } }
b844680a
L		 659
660#define OPC_EXT_RM_0 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 0 } }
661#define OPC_EXT_RM_1 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 1 } }
662#define OPC_EXT_RM_2 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 2 } }
663#define OPC_EXT_RM_3 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 3 } }
664#define OPC_EXT_RM_4 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 4 } }
bbedc832 665#define OPC_EXT_RM_5 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 5 } }
144c41d9 666#define OPC_EXT_RM_6 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 6 } }
b844680a 667
26ca5450 668typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 669
670struct dis386 {
2da11e11 671 const char *name;
ce518a5f
L		 672 struct
673 {
674 op_rtn rtn;
675 int bytemode;
676 } op[MAX_OPERANDS];
252b5132
RH		 677};
678
679/* Upper case letters in the instruction names here are macros.
680 'A' => print 'b' if no register operands or suffix_always is true
681 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 682 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
683 . size prefix
ed7841b3
JB		 684 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
685 . suffix_always is true
252b5132 686 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 687 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 688 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 689 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 690 'I' => honor following macro letter even in Intel mode (implemented only
691 . for some of the macro letters)
692 'J' => print 'l'
42903f7f 693 'K' => print 'd' or 'q' if rex prefix is present.
252b5132
RH		 694 'L' => print 'l' if suffix_always is true
695 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 696 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 697 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 698 . or suffix_always is true. print 'q' if rex prefix is present.
699 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
700 . is true
a35ca55a 701 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 702 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 703 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
704 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 705 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 706 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 707 'X' => print 's', 'd' depending on data16 prefix (for XMM)
76f227a5 708 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
6dd5059a 709 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
52b15da3 710
6439fc28
AM		 711 Many of the above letters print nothing in Intel mode. See "putop"
712 for the details.
52b15da3 713
6439fc28 714 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 715 mnemonic strings for AT&T and Intel. */
252b5132 716
6439fc28 717static const struct dis386 dis386[] = {
252b5132 718 /* 00 */
ce518a5f
L		 719 { "addB", { Eb, Gb } },
720 { "addS", { Ev, Gv } },
721 { "addB", { Gb, Eb } },
722 { "addS", { Gv, Ev } },
723 { "addB", { AL, Ib } },
724 { "addS", { eAX, Iv } },
7c52e0e8
L		 725 { X86_64_4 },
726 { X86_64_5 },
252b5132 727 /* 08 */
ce518a5f
L		 728 { "orB", { Eb, Gb } },
729 { "orS", { Ev, Gv } },
730 { "orB", { Gb, Eb } },
731 { "orS", { Gv, Ev } },
732 { "orB", { AL, Ib } },
733 { "orS", { eAX, Iv } },
7c52e0e8 734 { X86_64_6 },
ce518a5f 735 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 736 /* 10 */
ce518a5f
L		 737 { "adcB", { Eb, Gb } },
738 { "adcS", { Ev, Gv } },
739 { "adcB", { Gb, Eb } },
740 { "adcS", { Gv, Ev } },
741 { "adcB", { AL, Ib } },
742 { "adcS", { eAX, Iv } },
7c52e0e8
L		 743 { X86_64_7 },
744 { X86_64_8 },
252b5132 745 /* 18 */
ce518a5f
L		 746 { "sbbB", { Eb, Gb } },
747 { "sbbS", { Ev, Gv } },
748 { "sbbB", { Gb, Eb } },
749 { "sbbS", { Gv, Ev } },
750 { "sbbB", { AL, Ib } },
751 { "sbbS", { eAX, Iv } },
7c52e0e8
L		 752 { X86_64_9 },
753 { X86_64_10 },
252b5132 754 /* 20 */
ce518a5f
L		 755 { "andB", { Eb, Gb } },
756 { "andS", { Ev, Gv } },
757 { "andB", { Gb, Eb } },
758 { "andS", { Gv, Ev } },
759 { "andB", { AL, Ib } },
760 { "andS", { eAX, Iv } },
761 { "(bad)", { XX } }, /* SEG ES prefix */
7c52e0e8 762 { X86_64_11 },
252b5132 763 /* 28 */
ce518a5f
L		 764 { "subB", { Eb, Gb } },
765 { "subS", { Ev, Gv } },
766 { "subB", { Gb, Eb } },
767 { "subS", { Gv, Ev } },
768 { "subB", { AL, Ib } },
769 { "subS", { eAX, Iv } },
770 { "(bad)", { XX } }, /* SEG CS prefix */
7c52e0e8 771 { X86_64_12 },
252b5132 772 /* 30 */
ce518a5f
L		 773 { "xorB", { Eb, Gb } },
774 { "xorS", { Ev, Gv } },
775 { "xorB", { Gb, Eb } },
776 { "xorS", { Gv, Ev } },
777 { "xorB", { AL, Ib } },
778 { "xorS", { eAX, Iv } },
779 { "(bad)", { XX } }, /* SEG SS prefix */
7c52e0e8 780 { X86_64_13 },
252b5132 781 /* 38 */
ce518a5f
L		 782 { "cmpB", { Eb, Gb } },
783 { "cmpS", { Ev, Gv } },
784 { "cmpB", { Gb, Eb } },
785 { "cmpS", { Gv, Ev } },
786 { "cmpB", { AL, Ib } },
787 { "cmpS", { eAX, Iv } },
788 { "(bad)", { XX } }, /* SEG DS prefix */
7c52e0e8 789 { X86_64_14 },
252b5132 790 /* 40 */
ce518a5f
L		 791 { "inc{S|}", { RMeAX } },
792 { "inc{S|}", { RMeCX } },
793 { "inc{S|}", { RMeDX } },
794 { "inc{S|}", { RMeBX } },
795 { "inc{S|}", { RMeSP } },
796 { "inc{S|}", { RMeBP } },
797 { "inc{S|}", { RMeSI } },
798 { "inc{S|}", { RMeDI } },
252b5132 799 /* 48 */
ce518a5f
L		 800 { "dec{S|}", { RMeAX } },
801 { "dec{S|}", { RMeCX } },
802 { "dec{S|}", { RMeDX } },
803 { "dec{S|}", { RMeBX } },
804 { "dec{S|}", { RMeSP } },
805 { "dec{S|}", { RMeBP } },
806 { "dec{S|}", { RMeSI } },
807 { "dec{S|}", { RMeDI } },
252b5132 808 /* 50 */
ce518a5f
L		 809 { "pushV", { RMrAX } },
810 { "pushV", { RMrCX } },
811 { "pushV", { RMrDX } },
812 { "pushV", { RMrBX } },
813 { "pushV", { RMrSP } },
814 { "pushV", { RMrBP } },
815 { "pushV", { RMrSI } },
816 { "pushV", { RMrDI } },
252b5132 817 /* 58 */
ce518a5f
L		 818 { "popV", { RMrAX } },
819 { "popV", { RMrCX } },
820 { "popV", { RMrDX } },
821 { "popV", { RMrBX } },
822 { "popV", { RMrSP } },
823 { "popV", { RMrBP } },
824 { "popV", { RMrSI } },
825 { "popV", { RMrDI } },
252b5132 826 /* 60 */
6439fc28 827 { X86_64_0 },
5f754f58
L		 828 { X86_64_1 },
829 { X86_64_2 },
830 { X86_64_3 },
ce518a5f
L		 831 { "(bad)", { XX } }, /* seg fs */
832 { "(bad)", { XX } }, /* seg gs */
833 { "(bad)", { XX } }, /* op size prefix */
834 { "(bad)", { XX } }, /* adr size prefix */
252b5132 835 /* 68 */
ce518a5f
L		 836 { "pushT", { Iq } },
837 { "imulS", { Gv, Ev, Iv } },
838 { "pushT", { sIb } },
839 { "imulS", { Gv, Ev, sIb } },
7c52e0e8
L		 840 { "ins{b|}", { Ybr, indirDX } },
841 { X86_64_15 },
842 { "outs{b|}", { indirDXr, Xb } },
843 { X86_64_16 },
252b5132 844 /* 70 */
ce518a5f
L		 845 { "joH", { Jb, XX, cond_jump_flag } },
846 { "jnoH", { Jb, XX, cond_jump_flag } },
847 { "jbH", { Jb, XX, cond_jump_flag } },
848 { "jaeH", { Jb, XX, cond_jump_flag } },
849 { "jeH", { Jb, XX, cond_jump_flag } },
850 { "jneH", { Jb, XX, cond_jump_flag } },
851 { "jbeH", { Jb, XX, cond_jump_flag } },
852 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 853 /* 78 */
ce518a5f
L		 854 { "jsH", { Jb, XX, cond_jump_flag } },
855 { "jnsH", { Jb, XX, cond_jump_flag } },
856 { "jpH", { Jb, XX, cond_jump_flag } },
857 { "jnpH", { Jb, XX, cond_jump_flag } },
858 { "jlH", { Jb, XX, cond_jump_flag } },
859 { "jgeH", { Jb, XX, cond_jump_flag } },
860 { "jleH", { Jb, XX, cond_jump_flag } },
861 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132
RH		 862 /* 80 */
863 { GRP1b },
864 { GRP1S },
ce518a5f 865 { "(bad)", { XX } },
252b5132 866 { GRP1Ss },
ce518a5f
L		 867 { "testB", { Eb, Gb } },
868 { "testS", { Ev, Gv } },
869 { "xchgB", { Eb, Gb } },
870 { "xchgS", { Ev, Gv } },
252b5132 871 /* 88 */
ce518a5f
L		 872 { "movB", { Eb, Gb } },
873 { "movS", { Ev, Gv } },
874 { "movB", { Gb, Eb } },
875 { "movS", { Gv, Ev } },
876 { "movD", { Sv, Sw } },
d8faab4e 877 { OPC_EXT_0 },
ce518a5f 878 { "movD", { Sw, Sv } },
7967e09e 879 { GRP1a },
252b5132 880 /* 90 */
8b38ad71 881 { PREGRP38 },
ce518a5f
L		 882 { "xchgS", { RMeCX, eAX } },
883 { "xchgS", { RMeDX, eAX } },
884 { "xchgS", { RMeBX, eAX } },
885 { "xchgS", { RMeSP, eAX } },
886 { "xchgS", { RMeBP, eAX } },
887 { "xchgS", { RMeSI, eAX } },
888 { "xchgS", { RMeDI, eAX } },
252b5132 889 /* 98 */
7c52e0e8
L		 890 { "cW{t|}R", { XX } },
891 { "cR{t|}O", { XX } },
892 { X86_64_17 },
ce518a5f
L		 893 { "(bad)", { XX } }, /* fwait */
894 { "pushfT", { XX } },
895 { "popfT", { XX } },
7c52e0e8
L		 896 { "sahf", { XX } },
897 { "lahf", { XX } },
252b5132 898 /* a0 */
ce518a5f
L		 899 { "movB", { AL, Ob } },
900 { "movS", { eAX, Ov } },
901 { "movB", { Ob, AL } },
902 { "movS", { Ov, eAX } },
7c52e0e8
L		 903 { "movs{b|}", { Ybr, Xb } },
904 { "movs{R|}", { Yvr, Xv } },
905 { "cmps{b|}", { Xb, Yb } },
906 { "cmps{R|}", { Xv, Yv } },
252b5132 907 /* a8 */
ce518a5f
L		 908 { "testB", { AL, Ib } },
909 { "testS", { eAX, Iv } },
910 { "stosB", { Ybr, AL } },
911 { "stosS", { Yvr, eAX } },
912 { "lodsB", { ALr, Xb } },
913 { "lodsS", { eAXr, Xv } },
914 { "scasB", { AL, Yb } },
915 { "scasS", { eAX, Yv } },
252b5132 916 /* b0 */
ce518a5f
L		 917 { "movB", { RMAL, Ib } },
918 { "movB", { RMCL, Ib } },
919 { "movB", { RMDL, Ib } },
920 { "movB", { RMBL, Ib } },
921 { "movB", { RMAH, Ib } },
922 { "movB", { RMCH, Ib } },
923 { "movB", { RMDH, Ib } },
924 { "movB", { RMBH, Ib } },
252b5132 925 /* b8 */
ce518a5f
L		 926 { "movS", { RMeAX, Iv64 } },
927 { "movS", { RMeCX, Iv64 } },
928 { "movS", { RMeDX, Iv64 } },
929 { "movS", { RMeBX, Iv64 } },
930 { "movS", { RMeSP, Iv64 } },
931 { "movS", { RMeBP, Iv64 } },
932 { "movS", { RMeSI, Iv64 } },
933 { "movS", { RMeDI, Iv64 } },
252b5132
RH		 934 /* c0 */
935 { GRP2b },
936 { GRP2S },
ce518a5f
L		 937 { "retT", { Iw } },
938 { "retT", { XX } },
d8faab4e 939 { OPC_EXT_1 },
6807063e 940 { X86_64_27 },
a6bd098c
L		 941 { GRP11_C6 },
942 { GRP11_C7 },
252b5132 943 /* c8 */
ce518a5f
L		 944 { "enterT", { Iw, Ib } },
945 { "leaveT", { XX } },
946 { "lretP", { Iw } },
947 { "lretP", { XX } },
948 { "int3", { XX } },
949 { "int", { Ib } },
7c52e0e8 950 { X86_64_18 },
ce518a5f 951 { "iretP", { XX } },
252b5132
RH		 952 /* d0 */
953 { GRP2b_one },
954 { GRP2S_one },
955 { GRP2b_cl },
956 { GRP2S_cl },
7c52e0e8
L		 957 { X86_64_19 },
958 { X86_64_20 },
ce518a5f
L		 959 { "(bad)", { XX } },
960 { "xlat", { DSBX } },
252b5132
RH		 961 /* d8 */
962 { FLOAT },
963 { FLOAT },
964 { FLOAT },
965 { FLOAT },
966 { FLOAT },
967 { FLOAT },
968 { FLOAT },
969 { FLOAT },
970 /* e0 */
ce518a5f
L		 971 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
972 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
973 { "loopFH", { Jb, XX, loop_jcxz_flag } },
974 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
975 { "inB", { AL, Ib } },
976 { "inG", { zAX, Ib } },
977 { "outB", { Ib, AL } },
978 { "outG", { Ib, zAX } },
252b5132 979 /* e8 */
ce518a5f
L		 980 { "callT", { Jv } },
981 { "jmpT", { Jv } },
7c52e0e8 982 { X86_64_21 },
ce518a5f
L		 983 { "jmp", { Jb } },
984 { "inB", { AL, indirDX } },
985 { "inG", { zAX, indirDX } },
986 { "outB", { indirDX, AL } },
987 { "outG", { indirDX, zAX } },
252b5132 988 /* f0 */
ce518a5f
L		 989 { "(bad)", { XX } }, /* lock prefix */
990 { "icebp", { XX } },
991 { "(bad)", { XX } }, /* repne */
992 { "(bad)", { XX } }, /* repz */
993 { "hlt", { XX } },
994 { "cmc", { XX } },
252b5132
RH		 995 { GRP3b },
996 { GRP3S },
997 /* f8 */
ce518a5f
L		 998 { "clc", { XX } },
999 { "stc", { XX } },
1000 { "cli", { XX } },
1001 { "sti", { XX } },
1002 { "cld", { XX } },
1003 { "std", { XX } },
252b5132
RH		 1004 { GRP4 },
1005 { GRP5 },
1006};
1007
6439fc28 1008static const struct dis386 dis386_twobyte[] = {
252b5132
RH		 1009 /* 00 */
1010 { GRP6 },
1011 { GRP7 },
ce518a5f
L		 1012 { "larS", { Gv, Ew } },
1013 { "lslS", { Gv, Ew } },
1014 { "(bad)", { XX } },
1015 { "syscall", { XX } },
1016 { "clts", { XX } },
1017 { "sysretP", { XX } },
252b5132 1018 /* 08 */
ce518a5f
L		 1019 { "invd", { XX } },
1020 { "wbinvd", { XX } },
1021 { "(bad)", { XX } },
1022 { "ud2a", { XX } },
1023 { "(bad)", { XX } },
c608c12e 1024 { GRPAMD },
ce518a5f
L		 1025 { "femms", { XX } },
1026 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1027 /* 10 */
c608c12e
AM		 1028 { PREGRP8 },
1029 { PREGRP9 },
ca164297 1030 { PREGRP30 },
876d4bfa 1031 { OPC_EXT_34 },
09a2c6cf
L		 1032 { "unpcklpX", { XM, EXq } },
1033 { "unpckhpX", { XM, EXq } },
ca164297 1034 { PREGRP31 },
876d4bfa 1035 { OPC_EXT_35 },
252b5132 1036 /* 18 */
b3882df9 1037 { GRP16 },
ce518a5f
L		 1038 { "(bad)", { XX } },
1039 { "(bad)", { XX } },
1040 { "(bad)", { XX } },
1041 { "(bad)", { XX } },
1042 { "(bad)", { XX } },
1043 { "(bad)", { XX } },
1044 { "nopQ", { Ev } },
252b5132 1045 /* 20 */
1afd85e3
L		 1046 { OPC_EXT_40 },
1047 { OPC_EXT_41 },
1048 { OPC_EXT_42 },
1049 { OPC_EXT_43 },
1050 { OPC_EXT_44 },
85f10a01 1051 { THREE_BYTE_SSE5_0F25 },
1afd85e3 1052 { OPC_EXT_45 },
ce518a5f 1053 { "(bad)", { XX } },
252b5132 1054 /* 28 */
09a2c6cf
L		 1055 { "movapX", { XM, EXx } },
1056 { "movapX", { EXx, XM } },
c608c12e 1057 { PREGRP2 },
050dfa73 1058 { PREGRP33 },
2da11e11 1059 { PREGRP4 },
c608c12e 1060 { PREGRP3 },
09a2c6cf
L		 1061 { PREGRP93 },
1062 { PREGRP94 },
252b5132 1063 /* 30 */
ce518a5f
L		 1064 { "wrmsr", { XX } },
1065 { "rdtsc", { XX } },
1066 { "rdmsr", { XX } },
1067 { "rdpmc", { XX } },
1068 { "sysenter", { XX } },
1069 { "sysexit", { XX } },
1070 { "(bad)", { XX } },
1071 { "(bad)", { XX } },
252b5132 1072 /* 38 */
331d2d0d 1073 { THREE_BYTE_0 },
ce518a5f 1074 { "(bad)", { XX } },
331d2d0d 1075 { THREE_BYTE_1 },
ce518a5f
L		 1076 { "(bad)", { XX } },
1077 { "(bad)", { XX } },
1078 { "(bad)", { XX } },
1079 { "(bad)", { XX } },
1080 { "(bad)", { XX } },
252b5132 1081 /* 40 */
ce518a5f
L		 1082 { "cmovo", { Gv, Ev } },
1083 { "cmovno", { Gv, Ev } },
1084 { "cmovb", { Gv, Ev } },
1085 { "cmovae", { Gv, Ev } },
1086 { "cmove", { Gv, Ev } },
1087 { "cmovne", { Gv, Ev } },
1088 { "cmovbe", { Gv, Ev } },
1089 { "cmova", { Gv, Ev } },
252b5132 1090 /* 48 */
ce518a5f
L		 1091 { "cmovs", { Gv, Ev } },
1092 { "cmovns", { Gv, Ev } },
1093 { "cmovp", { Gv, Ev } },
1094 { "cmovnp", { Gv, Ev } },
1095 { "cmovl", { Gv, Ev } },
1096 { "cmovge", { Gv, Ev } },
1097 { "cmovle", { Gv, Ev } },
1098 { "cmovg", { Gv, Ev } },
252b5132 1099 /* 50 */
ce518a5f 1100 { "movmskpX", { Gdq, XS } },
c608c12e
AM		 1101 { PREGRP13 },
1102 { PREGRP12 },
1103 { PREGRP11 },
09a2c6cf
L		 1104 { "andpX", { XM, EXx } },
1105 { "andnpX", { XM, EXx } },
1106 { "orpX", { XM, EXx } },
1107 { "xorpX", { XM, EXx } },
252b5132 1108 /* 58 */
c608c12e
AM		 1109 { PREGRP0 },
1110 { PREGRP10 },
041bd2e0
JH		 1111 { PREGRP17 },
1112 { PREGRP16 },
c608c12e
AM		 1113 { PREGRP14 },
1114 { PREGRP7 },
1115 { PREGRP5 },
2da11e11 1116 { PREGRP6 },
252b5132 1117 /* 60 */
09a2c6cf
L		 1118 { PREGRP95 },
1119 { PREGRP96 },
1120 { PREGRP97 },
ce518a5f
L		 1121 { "packsswb", { MX, EM } },
1122 { "pcmpgtb", { MX, EM } },
1123 { "pcmpgtw", { MX, EM } },
1124 { "pcmpgtd", { MX, EM } },
1125 { "packuswb", { MX, EM } },
252b5132 1126 /* 68 */
ce518a5f
L		 1127 { "punpckhbw", { MX, EM } },
1128 { "punpckhwd", { MX, EM } },
1129 { "punpckhdq", { MX, EM } },
1130 { "packssdw", { MX, EM } },
0f17484f 1131 { PREGRP26 },
041bd2e0 1132 { PREGRP24 },
231af070 1133 { "movK", { MX, Edq } },
041bd2e0 1134 { PREGRP19 },
252b5132 1135 /* 70 */
041bd2e0 1136 { PREGRP22 },
252b5132 1137 { GRP12 },
b3882df9
L		 1138 { GRP13 },
1139 { GRP14 },
ce518a5f
L		 1140 { "pcmpeqb", { MX, EM } },
1141 { "pcmpeqw", { MX, EM } },
1142 { "pcmpeqd", { MX, EM } },
1143 { "emms", { XX } },
252b5132 1144 /* 78 */
050dfa73
MM		 1145 { PREGRP34 },
1146 { PREGRP35 },
85f10a01
MM		 1147 { THREE_BYTE_SSE5_0F7A },
1148 { THREE_BYTE_SSE5_0F7B },
ca164297
L		 1149 { PREGRP28 },
1150 { PREGRP29 },
041bd2e0
JH		 1151 { PREGRP23 },
1152 { PREGRP20 },
252b5132 1153 /* 80 */
ce518a5f
L		 1154 { "joH", { Jv, XX, cond_jump_flag } },
1155 { "jnoH", { Jv, XX, cond_jump_flag } },
1156 { "jbH", { Jv, XX, cond_jump_flag } },
1157 { "jaeH", { Jv, XX, cond_jump_flag } },
1158 { "jeH", { Jv, XX, cond_jump_flag } },
1159 { "jneH", { Jv, XX, cond_jump_flag } },
1160 { "jbeH", { Jv, XX, cond_jump_flag } },
1161 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1162 /* 88 */
ce518a5f
L		 1163 { "jsH", { Jv, XX, cond_jump_flag } },
1164 { "jnsH", { Jv, XX, cond_jump_flag } },
1165 { "jpH", { Jv, XX, cond_jump_flag } },
1166 { "jnpH", { Jv, XX, cond_jump_flag } },
1167 { "jlH", { Jv, XX, cond_jump_flag } },
1168 { "jgeH", { Jv, XX, cond_jump_flag } },
1169 { "jleH", { Jv, XX, cond_jump_flag } },
1170 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1171 /* 90 */
ce518a5f
L		 1172 { "seto", { Eb } },
1173 { "setno", { Eb } },
1174 { "setb", { Eb } },
1175 { "setae", { Eb } },
1176 { "sete", { Eb } },
1177 { "setne", { Eb } },
1178 { "setbe", { Eb } },
1179 { "seta", { Eb } },
252b5132 1180 /* 98 */
ce518a5f
L		 1181 { "sets", { Eb } },
1182 { "setns", { Eb } },
1183 { "setp", { Eb } },
1184 { "setnp", { Eb } },
1185 { "setl", { Eb } },
1186 { "setge", { Eb } },
1187 { "setle", { Eb } },
1188 { "setg", { Eb } },
252b5132 1189 /* a0 */
ce518a5f
L		 1190 { "pushT", { fs } },
1191 { "popT", { fs } },
1192 { "cpuid", { XX } },
1193 { "btS", { Ev, Gv } },
1194 { "shldS", { Ev, Gv, Ib } },
1195 { "shldS", { Ev, Gv, CL } },
30d1c836
ML		 1196 { GRPPADLCK2 },
1197 { GRPPADLCK1 },
252b5132 1198 /* a8 */
ce518a5f
L		 1199 { "pushT", { gs } },
1200 { "popT", { gs } },
1201 { "rsm", { XX } },
1202 { "btsS", { Ev, Gv } },
1203 { "shrdS", { Ev, Gv, Ib } },
1204 { "shrdS", { Ev, Gv, CL } },
b3882df9 1205 { GRP15 },
ce518a5f 1206 { "imulS", { Gv, Ev } },
252b5132 1207 /* b0 */
ce518a5f
L		 1208 { "cmpxchgB", { Eb, Gb } },
1209 { "cmpxchgS", { Ev, Gv } },
d8faab4e 1210 { OPC_EXT_3 },
ce518a5f 1211 { "btrS", { Ev, Gv } },
d8faab4e
L		 1212 { OPC_EXT_4 },
1213 { OPC_EXT_5 },
7c52e0e8
L		 1214 { "movz{bR|x}", { Gv, Eb } },
1215 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1216 /* b8 */
7918206c 1217 { PREGRP37 },
ce518a5f 1218 { "ud2b", { XX } },
252b5132 1219 { GRP8 },
ce518a5f
L		 1220 { "btcS", { Ev, Gv } },
1221 { "bsfS", { Gv, Ev } },
050dfa73 1222 { PREGRP36 },
7c52e0e8
L		 1223 { "movs{bR|x}", { Gv, Eb } },
1224 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1225 /* c0 */
ce518a5f
L		 1226 { "xaddB", { Eb, Gb } },
1227 { "xaddS", { Ev, Gv } },
c608c12e 1228 { PREGRP1 },
ce518a5f
L		 1229 { "movntiS", { Ev, Gv } },
1230 { "pinsrw", { MX, Edqw, Ib } },
1231 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1232 { "shufpX", { XM, EXx, Ib } },
252b5132
RH		 1233 { GRP9 },
1234 /* c8 */
ce518a5f
L		 1235 { "bswap", { RMeAX } },
1236 { "bswap", { RMeCX } },
1237 { "bswap", { RMeDX } },
1238 { "bswap", { RMeBX } },
1239 { "bswap", { RMeSP } },
1240 { "bswap", { RMeBP } },
1241 { "bswap", { RMeSI } },
1242 { "bswap", { RMeDI } },
252b5132 1243 /* d0 */
ca164297 1244 { PREGRP27 },
ce518a5f
L		 1245 { "psrlw", { MX, EM } },
1246 { "psrld", { MX, EM } },
1247 { "psrlq", { MX, EM } },
1248 { "paddq", { MX, EM } },
1249 { "pmullw", { MX, EM } },
041bd2e0 1250 { PREGRP21 },
ce518a5f 1251 { "pmovmskb", { Gdq, MS } },
252b5132 1252 /* d8 */
ce518a5f
L		 1253 { "psubusb", { MX, EM } },
1254 { "psubusw", { MX, EM } },
1255 { "pminub", { MX, EM } },
1256 { "pand", { MX, EM } },
1257 { "paddusb", { MX, EM } },
1258 { "paddusw", { MX, EM } },
1259 { "pmaxub", { MX, EM } },
1260 { "pandn", { MX, EM } },
252b5132 1261 /* e0 */
ce518a5f
L		 1262 { "pavgb", { MX, EM } },
1263 { "psraw", { MX, EM } },
1264 { "psrad", { MX, EM } },
1265 { "pavgw", { MX, EM } },
1266 { "pmulhuw", { MX, EM } },
1267 { "pmulhw", { MX, EM } },
041bd2e0 1268 { PREGRP15 },
0f17484f 1269 { PREGRP25 },
252b5132 1270 /* e8 */
ce518a5f
L		 1271 { "psubsb", { MX, EM } },
1272 { "psubsw", { MX, EM } },
1273 { "pminsw", { MX, EM } },
1274 { "por", { MX, EM } },
1275 { "paddsb", { MX, EM } },
1276 { "paddsw", { MX, EM } },
1277 { "pmaxsw", { MX, EM } },
1278 { "pxor", { MX, EM } },
252b5132 1279 /* f0 */
ca164297 1280 { PREGRP32 },
ce518a5f
L		 1281 { "psllw", { MX, EM } },
1282 { "pslld", { MX, EM } },
1283 { "psllq", { MX, EM } },
1284 { "pmuludq", { MX, EM } },
1285 { "pmaddwd", { MX, EM } },
1286 { "psadbw", { MX, EM } },
041bd2e0 1287 { PREGRP18 },
252b5132 1288 /* f8 */
ce518a5f
L		 1289 { "psubb", { MX, EM } },
1290 { "psubw", { MX, EM } },
1291 { "psubd", { MX, EM } },
1292 { "psubq", { MX, EM } },
1293 { "paddb", { MX, EM } },
1294 { "paddw", { MX, EM } },
1295 { "paddd", { MX, EM } },
1296 { "(bad)", { XX } },
252b5132
RH		 1297};
1298
1299static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1300 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1301 /* ------------------------------- */
1302 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1303 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1304 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1305 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1306 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1307 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1308 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1309 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1310 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1311 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1312 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1313 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1314 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1315 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1316 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1317 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1318 /* ------------------------------- */
1319 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1320};
1321
1322static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1323 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1324 /* ------------------------------- */
252b5132 1325 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1326 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
85f10a01 1327 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1328 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1329 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1330 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1331 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1332 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1333 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1334 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1335 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1336 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1337 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1338 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1339 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1340 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1341 /* ------------------------------- */
1342 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1343};
1344
252b5132
RH		 1345static char obuf[100];
1346static char *obufp;
1347static char scratchbuf[100];
1348static unsigned char *start_codep;
1349static unsigned char *insn_codep;
1350static unsigned char *codep;
b844680a
L		 1351static const char *lock_prefix;
1352static const char *data_prefix;
1353static const char *addr_prefix;
1354static const char *repz_prefix;
1355static const char *repnz_prefix;
252b5132 1356static disassemble_info *the_info;
7967e09e
L		 1357static struct
1358 {
1359 int mod;
7967e09e 1360 int reg;
484c222e 1361 int rm;
7967e09e
L		 1362 }
1363modrm;
4bba6815 1364static unsigned char need_modrm;
252b5132 1365
4bba6815
AM		 1366/* If we are accessing mod/rm/reg without need_modrm set, then the
1367 values are stale. Hitting this abort likely indicates that you
1368 need to update onebyte_has_modrm or twobyte_has_modrm. */
1369#define MODRM_CHECK if (!need_modrm) abort ()
1370
d708bcba
AM		 1371static const char **names64;
1372static const char **names32;
1373static const char **names16;
1374static const char **names8;
1375static const char **names8rex;
1376static const char **names_seg;
db51cc60
L		 1377static const char *index64;
1378static const char *index32;
d708bcba
AM		 1379static const char **index16;
1380
1381static const char *intel_names64[] = {
1382 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1383 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1384};
1385static const char *intel_names32[] = {
1386 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1387 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1388};
1389static const char *intel_names16[] = {
1390 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1391 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1392};
1393static const char *intel_names8[] = {
1394 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1395};
1396static const char *intel_names8rex[] = {
1397 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1398 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1399};
1400static const char *intel_names_seg[] = {
1401 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1402};
db51cc60
L		 1403static const char *intel_index64 = "riz";
1404static const char *intel_index32 = "eiz";
d708bcba
AM		 1405static const char *intel_index16[] = {
1406 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1407};
1408
1409static const char *att_names64[] = {
1410 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1411 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1412};
d708bcba
AM		 1413static const char *att_names32[] = {
1414 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1415 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1416};
d708bcba
AM		 1417static const char *att_names16[] = {
1418 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1419 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1420};
d708bcba
AM		 1421static const char *att_names8[] = {
1422 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1423};
d708bcba
AM		 1424static const char *att_names8rex[] = {
1425 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1426 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1427};
d708bcba
AM		 1428static const char *att_names_seg[] = {
1429 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1430};
db51cc60
L		 1431static const char *att_index64 = "%riz";
1432static const char *att_index32 = "%eiz";
d708bcba
AM		 1433static const char *att_index16[] = {
1434 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1435};
1436
2da11e11 1437static const struct dis386 grps[][8] = {
7967e09e
L		 1438 /* GRP1a */
1439 {
1440 { "popU", { stackEv } },
1441 { "(bad)", { XX } },
1442 { "(bad)", { XX } },
1443 { "(bad)", { XX } },
1444 { "(bad)", { XX } },
1445 { "(bad)", { XX } },
1446 { "(bad)", { XX } },
1447 { "(bad)", { XX } },
1448 },
252b5132
RH		 1449 /* GRP1b */
1450 {
ce518a5f
L		 1451 { "addA", { Eb, Ib } },
1452 { "orA", { Eb, Ib } },
1453 { "adcA", { Eb, Ib } },
1454 { "sbbA", { Eb, Ib } },
1455 { "andA", { Eb, Ib } },
1456 { "subA", { Eb, Ib } },
1457 { "xorA", { Eb, Ib } },
1458 { "cmpA", { Eb, Ib } },
252b5132
RH		 1459 },
1460 /* GRP1S */
1461 {
ce518a5f
L		 1462 { "addQ", { Ev, Iv } },
1463 { "orQ", { Ev, Iv } },
1464 { "adcQ", { Ev, Iv } },
1465 { "sbbQ", { Ev, Iv } },
1466 { "andQ", { Ev, Iv } },
1467 { "subQ", { Ev, Iv } },
1468 { "xorQ", { Ev, Iv } },
1469 { "cmpQ", { Ev, Iv } },
252b5132
RH		 1470 },
1471 /* GRP1Ss */
1472 {
ce518a5f
L		 1473 { "addQ", { Ev, sIb } },
1474 { "orQ", { Ev, sIb } },
1475 { "adcQ", { Ev, sIb } },
1476 { "sbbQ", { Ev, sIb } },
1477 { "andQ", { Ev, sIb } },
1478 { "subQ", { Ev, sIb } },
1479 { "xorQ", { Ev, sIb } },
1480 { "cmpQ", { Ev, sIb } },
252b5132
RH		 1481 },
1482 /* GRP2b */
1483 {
ce518a5f
L		 1484 { "rolA", { Eb, Ib } },
1485 { "rorA", { Eb, Ib } },
1486 { "rclA", { Eb, Ib } },
1487 { "rcrA", { Eb, Ib } },
1488 { "shlA", { Eb, Ib } },
1489 { "shrA", { Eb, Ib } },
1490 { "(bad)", { XX } },
1491 { "sarA", { Eb, Ib } },
252b5132
RH		 1492 },
1493 /* GRP2S */
1494 {
ce518a5f
L		 1495 { "rolQ", { Ev, Ib } },
1496 { "rorQ", { Ev, Ib } },
1497 { "rclQ", { Ev, Ib } },
1498 { "rcrQ", { Ev, Ib } },
1499 { "shlQ", { Ev, Ib } },
1500 { "shrQ", { Ev, Ib } },
1501 { "(bad)", { XX } },
1502 { "sarQ", { Ev, Ib } },
252b5132
RH		 1503 },
1504 /* GRP2b_one */
1505 {
ce518a5f
L		 1506 { "rolA", { Eb, I1 } },
1507 { "rorA", { Eb, I1 } },
1508 { "rclA", { Eb, I1 } },
1509 { "rcrA", { Eb, I1 } },
1510 { "shlA", { Eb, I1 } },
1511 { "shrA", { Eb, I1 } },
1512 { "(bad)", { XX } },
1513 { "sarA", { Eb, I1 } },
252b5132
RH		 1514 },
1515 /* GRP2S_one */
1516 {
ce518a5f
L		 1517 { "rolQ", { Ev, I1 } },
1518 { "rorQ", { Ev, I1 } },
1519 { "rclQ", { Ev, I1 } },
1520 { "rcrQ", { Ev, I1 } },
1521 { "shlQ", { Ev, I1 } },
1522 { "shrQ", { Ev, I1 } },
1523 { "(bad)", { XX } },
1524 { "sarQ", { Ev, I1 } },
252b5132
RH		 1525 },
1526 /* GRP2b_cl */
1527 {
ce518a5f
L		 1528 { "rolA", { Eb, CL } },
1529 { "rorA", { Eb, CL } },
1530 { "rclA", { Eb, CL } },
1531 { "rcrA", { Eb, CL } },
1532 { "shlA", { Eb, CL } },
1533 { "shrA", { Eb, CL } },
1534 { "(bad)", { XX } },
1535 { "sarA", { Eb, CL } },
252b5132
RH		 1536 },
1537 /* GRP2S_cl */
1538 {
ce518a5f
L		 1539 { "rolQ", { Ev, CL } },
1540 { "rorQ", { Ev, CL } },
1541 { "rclQ", { Ev, CL } },
1542 { "rcrQ", { Ev, CL } },
1543 { "shlQ", { Ev, CL } },
1544 { "shrQ", { Ev, CL } },
1545 { "(bad)", { XX } },
1546 { "sarQ", { Ev, CL } },
252b5132
RH		 1547 },
1548 /* GRP3b */
1549 {
ce518a5f
L		 1550 { "testA", { Eb, Ib } },
1551 { "(bad)", { Eb } },
1552 { "notA", { Eb } },
1553 { "negA", { Eb } },
1554 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1555 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1556 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1557 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132
RH		 1558 },
1559 /* GRP3S */
1560 {
ce518a5f
L		 1561 { "testQ", { Ev, Iv } },
1562 { "(bad)", { XX } },
1563 { "notQ", { Ev } },
1564 { "negQ", { Ev } },
1565 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1566 { "imulQ", { Ev } },
1567 { "divQ", { Ev } },
1568 { "idivQ", { Ev } },
252b5132
RH		 1569 },
1570 /* GRP4 */
1571 {
ce518a5f
L		 1572 { "incA", { Eb } },
1573 { "decA", { Eb } },
1574 { "(bad)", { XX } },
1575 { "(bad)", { XX } },
1576 { "(bad)", { XX } },
1577 { "(bad)", { XX } },
1578 { "(bad)", { XX } },
1579 { "(bad)", { XX } },
252b5132
RH		 1580 },
1581 /* GRP5 */
1582 {
ce518a5f
L		 1583 { "incQ", { Ev } },
1584 { "decQ", { Ev } },
1585 { "callT", { indirEv } },
1586 { "JcallT", { indirEp } },
1587 { "jmpT", { indirEv } },
1588 { "JjmpT", { indirEp } },
1589 { "pushU", { stackEv } },
1590 { "(bad)", { XX } },
252b5132
RH		 1591 },
1592 /* GRP6 */
1593 {
ce518a5f
L		 1594 { "sldtD", { Sv } },
1595 { "strD", { Sv } },
1596 { "lldt", { Ew } },
1597 { "ltr", { Ew } },
1598 { "verr", { Ew } },
1599 { "verw", { Ew } },
1600 { "(bad)", { XX } },
1601 { "(bad)", { XX } },
252b5132
RH		 1602 },
1603 /* GRP7 */
1604 {
d8faab4e
L		 1605 { OPC_EXT_6 },
1606 { OPC_EXT_7 },
1607 { OPC_EXT_8 },
144c41d9 1608 { OPC_EXT_39 },
ce518a5f
L		 1609 { "smswD", { Sv } },
1610 { "(bad)", { XX } },
1611 { "lmsw", { Ew } },
bbedc832 1612 { OPC_EXT_38 },
252b5132
RH		 1613 },
1614 /* GRP8 */
1615 {
ce518a5f
L		 1616 { "(bad)", { XX } },
1617 { "(bad)", { XX } },
1618 { "(bad)", { XX } },
1619 { "(bad)", { XX } },
1620 { "btQ", { Ev, Ib } },
1621 { "btsQ", { Ev, Ib } },
1622 { "btrQ", { Ev, Ib } },
1623 { "btcQ", { Ev, Ib } },
252b5132
RH		 1624 },
1625 /* GRP9 */
1626 {
ce518a5f
L		 1627 { "(bad)", { XX } },
1628 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
1629 { "(bad)", { XX } },
1630 { "(bad)", { XX } },
1631 { "(bad)", { XX } },
1632 { "(bad)", { XX } },
d8faab4e
L		 1633 { OPC_EXT_9 },
1634 { OPC_EXT_10 },
252b5132 1635 },
a6bd098c
L		 1636 /* GRP11_C6 */
1637 {
ce518a5f
L		 1638 { "movA", { Eb, Ib } },
1639 { "(bad)", { XX } },
1640 { "(bad)", { XX } },
1641 { "(bad)", { XX } },
1642 { "(bad)", { XX } },
1643 { "(bad)", { XX } },
1644 { "(bad)", { XX } },
1645 { "(bad)", { XX } },
a6bd098c
L		 1646 },
1647 /* GRP11_C7 */
1648 {
ce518a5f
L		 1649 { "movQ", { Ev, Iv } },
1650 { "(bad)", { XX } },
1651 { "(bad)", { XX } },
1652 { "(bad)", { XX } },
1653 { "(bad)", { XX } },
1654 { "(bad)", { XX } },
1655 { "(bad)", { XX } },
1656 { "(bad)", { XX } },
a6bd098c 1657 },
b3882df9 1658 /* GRP12 */
252b5132 1659 {
ce518a5f
L		 1660 { "(bad)", { XX } },
1661 { "(bad)", { XX } },
d8faab4e 1662 { OPC_EXT_11 },
ce518a5f 1663 { "(bad)", { XX } },
d8faab4e 1664 { OPC_EXT_12 },
ce518a5f 1665 { "(bad)", { XX } },
d8faab4e 1666 { OPC_EXT_13 },
ce518a5f 1667 { "(bad)", { XX } },
252b5132 1668 },
b3882df9 1669 /* GRP13 */
252b5132 1670 {
ce518a5f
L		 1671 { "(bad)", { XX } },
1672 { "(bad)", { XX } },
d8faab4e 1673 { OPC_EXT_14 },
ce518a5f 1674 { "(bad)", { XX } },
d8faab4e 1675 { OPC_EXT_15 },
ce518a5f 1676 { "(bad)", { XX } },
d8faab4e 1677 { OPC_EXT_16 },
ce518a5f 1678 { "(bad)", { XX } },
252b5132 1679 },
b3882df9 1680 /* GRP14 */
252b5132 1681 {
ce518a5f
L		 1682 { "(bad)", { XX } },
1683 { "(bad)", { XX } },
b844680a 1684 { OPC_EXT_17 },
b844680a 1685 { OPC_EXT_18 },
d8faab4e
L		 1686 { "(bad)", { XX } },
1687 { "(bad)", { XX } },
b844680a
L		 1688 { OPC_EXT_19 },
1689 { OPC_EXT_20 },
c608c12e 1690 },
d8faab4e 1691 /* GRP15 */
c608c12e 1692 {
b844680a
L		 1693 { OPC_EXT_21 },
1694 { OPC_EXT_22 },
1695 { OPC_EXT_23 },
1696 { OPC_EXT_24 },
1697 { "(bad)", { XX } },
d8faab4e
L		 1698 { OPC_EXT_25 },
1699 { OPC_EXT_26 },
1700 { OPC_EXT_27 },
1701 },
1702 /* GRP16 */
1703 {
1704 { OPC_EXT_28 },
1705 { OPC_EXT_29 },
1706 { OPC_EXT_30 },
1707 { OPC_EXT_31 },
1708 { "(bad)", { XX } },
b844680a
L		 1709 { "(bad)", { XX } },
1710 { "(bad)", { XX } },
1711 { "(bad)", { XX } },
252b5132 1712 },
c608c12e 1713 /* GRPAMD */
252b5132 1714 {
ce518a5f
L		 1715 { "prefetch", { Eb } },
1716 { "prefetchw", { Eb } },
1717 { "(bad)", { XX } },
1718 { "(bad)", { XX } },
1719 { "(bad)", { XX } },
1720 { "(bad)", { XX } },
1721 { "(bad)", { XX } },
1722 { "(bad)", { XX } },
0f10071e 1723 },
30d1c836 1724 /* GRPPADLCK1 */
cc0ec051 1725 {
ce518a5f
L		 1726 { "xstore-rng", { { OP_0f07, 0 } } },
1727 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1728 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1729 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1730 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1731 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1732 { "(bad)", { { OP_0f07, 0 } } },
1733 { "(bad)", { { OP_0f07, 0 } } },
30d1c836
ML		 1734 },
1735 /* GRPPADLCK2 */
1736 {
ce518a5f
L		 1737 { "montmul", { { OP_0f07, 0 } } },
1738 { "xsha1", { { OP_0f07, 0 } } },
1739 { "xsha256", { { OP_0f07, 0 } } },
1740 { "(bad)", { { OP_0f07, 0 } } },
1741 { "(bad)", { { OP_0f07, 0 } } },
1742 { "(bad)", { { OP_0f07, 0 } } },
1743 { "(bad)", { { OP_0f07, 0 } } },
1744 { "(bad)", { { OP_0f07, 0 } } },
252b5132 1745 }
252b5132
RH		 1746};
1747
041bd2e0 1748static const struct dis386 prefix_user_table[][4] = {
c608c12e
AM		 1749 /* PREGRP0 */
1750 {
09a2c6cf
L		 1751 { "addps", { XM, EXx } },
1752 { "addss", { XM, EXd } },
1753 { "addpd", { XM, EXx } },
1754 { "addsd", { XM, EXq } },
c608c12e
AM		 1755 },
1756 /* PREGRP1 */
1757 {
09a2c6cf 1758 { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
09335d05 1759 { "", { XM, EXd, OPSIMD } },
09a2c6cf 1760 { "", { XM, EXx, OPSIMD } },
09335d05 1761 { "", { XM, EXq, OPSIMD } },
c608c12e
AM		 1762 },
1763 /* PREGRP2 */
1764 {
09335d05 1765 { "cvtpi2ps", { XM, EMCq } },
ce518a5f 1766 { "cvtsi2ssY", { XM, Ev } },
09335d05 1767 { "cvtpi2pd", { XM, EMCq } },
ce518a5f 1768 { "cvtsi2sdY", { XM, Ev } },
c608c12e
AM		 1769 },
1770 /* PREGRP3 */
1771 {
09335d05
L		 1772 { "cvtps2pi", { MXC, EXq } },
1773 { "cvtss2siY", { Gv, EXd } },
09a2c6cf 1774 { "cvtpd2pi", { MXC, EXx } },
09335d05 1775 { "cvtsd2siY", { Gv, EXq } },
c608c12e
AM		 1776 },
1777 /* PREGRP4 */
1778 {
09335d05
L		 1779 { "cvttps2pi", { MXC, EXq } },
1780 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1781 { "cvttpd2pi", { MXC, EXx } },
09335d05 1782 { "cvttsd2siY", { Gv, EXq } },
c608c12e
AM		 1783 },
1784 /* PREGRP5 */
1785 {
09a2c6cf 1786 { "divps", { XM, EXx } },
09335d05 1787 { "divss", { XM, EXd } },
09a2c6cf 1788 { "divpd", { XM, EXx } },
09335d05 1789 { "divsd", { XM, EXq } },
c608c12e
AM		 1790 },
1791 /* PREGRP6 */
1792 {
09a2c6cf 1793 { "maxps", { XM, EXx } },
09335d05 1794 { "maxss", { XM, EXd } },
09a2c6cf 1795 { "maxpd", { XM, EXx } },
09335d05 1796 { "maxsd", { XM, EXq } },
c608c12e
AM		 1797 },
1798 /* PREGRP7 */
1799 {
09a2c6cf 1800 { "minps", { XM, EXx } },
09335d05 1801 { "minss", { XM, EXd } },
09a2c6cf 1802 { "minpd", { XM, EXx } },
09335d05 1803 { "minsd", { XM, EXq } },
c608c12e
AM		 1804 },
1805 /* PREGRP8 */
1806 {
09a2c6cf 1807 { "movups", { XM, EXx } },
09335d05 1808 { "movss", { XM, EXd } },
09a2c6cf 1809 { "movupd", { XM, EXx } },
09335d05 1810 { "movsd", { XM, EXq } },
c608c12e
AM		 1811 },
1812 /* PREGRP9 */
1813 {
09a2c6cf 1814 { "movups", { EXx, XM } },
09335d05 1815 { "movss", { EXd, XM } },
09a2c6cf 1816 { "movupd", { EXx, XM } },
09335d05 1817 { "movsd", { EXq, XM } },
c608c12e
AM		 1818 },
1819 /* PREGRP10 */
1820 {
09a2c6cf 1821 { "mulps", { XM, EXx } },
09335d05 1822 { "mulss", { XM, EXd } },
09a2c6cf 1823 { "mulpd", { XM, EXx } },
09335d05 1824 { "mulsd", { XM, EXq } },
c608c12e
AM		 1825 },
1826 /* PREGRP11 */
1827 {
09a2c6cf 1828 { "rcpps", { XM, EXx } },
09335d05 1829 { "rcpss", { XM, EXd } },
09a2c6cf
L		 1830 { "(bad)", { XM, EXx } },
1831 { "(bad)", { XM, EXx } },
c608c12e
AM		 1832 },
1833 /* PREGRP12 */
1834 {
09a2c6cf 1835 { "rsqrtps",{ XM, EXx } },
09335d05 1836 { "rsqrtss",{ XM, EXd } },
09a2c6cf
L		 1837 { "(bad)", { XM, EXx } },
1838 { "(bad)", { XM, EXx } },
c608c12e
AM		 1839 },
1840 /* PREGRP13 */
1841 {
09a2c6cf 1842 { "sqrtps", { XM, EXx } },
09335d05 1843 { "sqrtss", { XM, EXd } },
09a2c6cf 1844 { "sqrtpd", { XM, EXx } },
09335d05 1845 { "sqrtsd", { XM, EXq } },
c608c12e
AM		 1846 },
1847 /* PREGRP14 */
1848 {
09a2c6cf 1849 { "subps", { XM, EXx } },
09335d05 1850 { "subss", { XM, EXd } },
09a2c6cf 1851 { "subpd", { XM, EXx } },
09335d05 1852 { "subsd", { XM, EXq } },
041bd2e0
JH		 1853 },
1854 /* PREGRP15 */
1855 {
09a2c6cf
L		 1856 { "(bad)", { XM, EXx } },
1857 { "cvtdq2pd", { XM, EXq } },
1858 { "cvttpd2dq", { XM, EXx } },
1859 { "cvtpd2dq", { XM, EXx } },
041bd2e0
JH		 1860 },
1861 /* PREGRP16 */
1862 {
09a2c6cf
L		 1863 { "cvtdq2ps", { XM, EXx } },
1864 { "cvttps2dq", { XM, EXx } },
1865 { "cvtps2dq", { XM, EXx } },
1866 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1867 },
1868 /* PREGRP17 */
1869 {
09a2c6cf 1870 { "cvtps2pd", { XM, EXq } },
09335d05 1871 { "cvtss2sd", { XM, EXd } },
09a2c6cf 1872 { "cvtpd2ps", { XM, EXx } },
09335d05 1873 { "cvtsd2ss", { XM, EXq } },
041bd2e0
JH		 1874 },
1875 /* PREGRP18 */
1876 {
ce518a5f 1877 { "maskmovq", { MX, MS } },
09a2c6cf 1878 { "(bad)", { XM, EXx } },
ce518a5f 1879 { "maskmovdqu", { XM, XS } },
09a2c6cf 1880 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1881 },
1882 /* PREGRP19 */
1883 {
ce518a5f 1884 { "movq", { MX, EM } },
09a2c6cf
L		 1885 { "movdqu", { XM, EXx } },
1886 { "movdqa", { XM, EXx } },
1887 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1888 },
1889 /* PREGRP20 */
1890 {
ce518a5f 1891 { "movq", { EM, MX } },
09a2c6cf
L		 1892 { "movdqu", { EXx, XM } },
1893 { "movdqa", { EXx, XM } },
1894 { "(bad)", { EXx, XM } },
041bd2e0
JH		 1895 },
1896 /* PREGRP21 */
1897 {
09a2c6cf 1898 { "(bad)", { EXx, XM } },
ce518a5f 1899 { "movq2dq",{ XM, MS } },
231af070 1900 { "movq", { EXq, XM } },
ce518a5f 1901 { "movdq2q",{ MX, XS } },
041bd2e0
JH		 1902 },
1903 /* PREGRP22 */
1904 {
ce518a5f 1905 { "pshufw", { MX, EM, Ib } },
09a2c6cf
L		 1906 { "pshufhw",{ XM, EXx, Ib } },
1907 { "pshufd", { XM, EXx, Ib } },
1908 { "pshuflw",{ XM, EXx, Ib } },
041bd2e0
JH		 1909 },
1910 /* PREGRP23 */
1911 {
231af070
L		 1912 { "movK", { Edq, MX } },
1913 { "movq", { XM, EXq } },
1914 { "movK", { Edq, XM } },
ce518a5f 1915 { "(bad)", { Ed, XM } },
041bd2e0
JH		 1916 },
1917 /* PREGRP24 */
1918 {
09a2c6cf
L		 1919 { "(bad)", { MX, EXx } },
1920 { "(bad)", { XM, EXx } },
1921 { "punpckhqdq", { XM, EXx } },
1922 { "(bad)", { XM, EXx } },
0f17484f
AM		 1923 },
1924 /* PREGRP25 */
1925 {
ce518a5f
L		 1926 { "movntq", { EM, MX } },
1927 { "(bad)", { EM, XM } },
1928 { "movntdq",{ EM, XM } },
1929 { "(bad)", { EM, XM } },
0f17484f
AM		 1930 },
1931 /* PREGRP26 */
1932 {
09a2c6cf
L		 1933 { "(bad)", { MX, EXx } },
1934 { "(bad)", { XM, EXx } },
1935 { "punpcklqdq", { XM, EXx } },
1936 { "(bad)", { XM, EXx } },
041bd2e0 1937 },
ca164297
L		 1938 /* PREGRP27 */
1939 {
09a2c6cf
L		 1940 { "(bad)", { MX, EXx } },
1941 { "(bad)", { XM, EXx } },
1942 { "addsubpd", { XM, EXx } },
1943 { "addsubps", { XM, EXx } },
ca164297
L		 1944 },
1945 /* PREGRP28 */
1946 {
09a2c6cf
L		 1947 { "(bad)", { MX, EXx } },
1948 { "(bad)", { XM, EXx } },
1949 { "haddpd", { XM, EXx } },
1950 { "haddps", { XM, EXx } },
ca164297
L		 1951 },
1952 /* PREGRP29 */
1953 {
09a2c6cf
L		 1954 { "(bad)", { MX, EXx } },
1955 { "(bad)", { XM, EXx } },
1956 { "hsubpd", { XM, EXx } },
1957 { "hsubps", { XM, EXx } },
ca164297
L		 1958 },
1959 /* PREGRP30 */
1960 {
876d4bfa 1961 { OPC_EXT_36 },
09a2c6cf
L		 1962 { "movsldup", { XM, EXx } },
1963 { "movlpd", { XM, EXq } },
1964 { "movddup", { XM, EXq } },
ca164297
L		 1965 },
1966 /* PREGRP31 */
1967 {
876d4bfa 1968 { OPC_EXT_37 },
09a2c6cf
L		 1969 { "movshdup", { XM, EXx } },
1970 { "movhpd", { XM, EXq } },
1971 { "(bad)", { XM, EXq } },
ca164297
L		 1972 },
1973 /* PREGRP32 */
1974 {
09a2c6cf
L		 1975 { "(bad)", { XM, EXx } },
1976 { "(bad)", { XM, EXx } },
1977 { "(bad)", { XM, EXx } },
d8faab4e 1978 { OPC_EXT_32 },
ca164297 1979 },
050dfa73
MM		 1980 /* PREGRP33 */
1981 {
ce518a5f 1982 {"movntps", { Ev, XM } },
09335d05 1983 {"movntss", { Ed, XM } },
ce518a5f 1984 {"movntpd", { Ev, XM } },
09335d05 1985 {"movntsd", { Eq, XM } },
050dfa73
MM		 1986 },
1987
1988 /* PREGRP34 */
1989 {
ce518a5f
L		 1990 {"vmread", { Em, Gm } },
1991 {"(bad)", { XX } },
1992 {"extrq", { XS, Ib, Ib } },
1993 {"insertq", { XM, XS, Ib, Ib } },
050dfa73 1994 },
246c51aa
L		 1995
1996 /* PREGRP35 */
050dfa73 1997 {
ce518a5f
L		 1998 {"vmwrite", { Gm, Em } },
1999 {"(bad)", { XX } },
2000 {"extrq", { XM, XS } },
2001 {"insertq", { XM, XS } },
246c51aa 2002 },
050dfa73
MM		 2003
2004 /* PREGRP36 */
2005 {
ce518a5f
L		 2006 { "bsrS", { Gv, Ev } },
2007 { "lzcntS", { Gv, Ev } },
2008 { "bsrS", { Gv, Ev } },
2009 { "(bad)", { XX } },
050dfa73
MM		 2010 },
2011
7918206c
MM		 2012 /* PREGRP37 */
2013 {
d25a0fc5 2014 { "(bad)", { XX } },
ce518a5f 2015 { "popcntS", { Gv, Ev } },
d25a0fc5 2016 { "(bad)", { XX } },
246c51aa 2017 { "(bad)", { XX } },
7918206c 2018 },
8b38ad71
L		 2019
2020 /* PREGRP38 */
2021 {
2022 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2023 { "pause", { XX } },
2024 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
246c51aa 2025 { "(bad)", { XX } },
8b38ad71 2026 },
42903f7f
L		 2027
2028 /* PREGRP39 */
2029 {
2030 { "(bad)", { XX } },
2031 { "(bad)", { XX } },
09a2c6cf 2032 { "pblendvb", {XM, EXx, XMM0 } },
42903f7f
L		 2033 { "(bad)", { XX } },
2034 },
2035
2036 /* PREGRP40 */
2037 {
2038 { "(bad)", { XX } },
2039 { "(bad)", { XX } },
09a2c6cf 2040 { "blendvps", {XM, EXx, XMM0 } },
42903f7f
L		 2041 { "(bad)", { XX } },
2042 },
2043
2044 /* PREGRP41 */
2045 {
2046 { "(bad)", { XX } },
2047 { "(bad)", { XX } },
09a2c6cf 2048 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2049 { "(bad)", { XX } },
2050 },
2051
2052 /* PREGRP42 */
2053 {
2054 { "(bad)", { XX } },
2055 { "(bad)", { XX } },
09a2c6cf 2056 { "ptest", { XM, EXx } },
42903f7f
L		 2057 { "(bad)", { XX } },
2058 },
2059
2060 /* PREGRP43 */
2061 {
2062 { "(bad)", { XX } },
2063 { "(bad)", { XX } },
8976381e 2064 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2065 { "(bad)", { XX } },
2066 },
2067
2068 /* PREGRP44 */
2069 {
2070 { "(bad)", { XX } },
2071 { "(bad)", { XX } },
8976381e 2072 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2073 { "(bad)", { XX } },
2074 },
2075
2076 /* PREGRP45 */
2077 {
2078 { "(bad)", { XX } },
2079 { "(bad)", { XX } },
8976381e 2080 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2081 { "(bad)", { XX } },
2082 },
2083
2084 /* PREGRP46 */
2085 {
2086 { "(bad)", { XX } },
2087 { "(bad)", { XX } },
8976381e 2088 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2089 { "(bad)", { XX } },
2090 },
2091
2092 /* PREGRP47 */
2093 {
2094 { "(bad)", { XX } },
2095 { "(bad)", { XX } },
8976381e 2096 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2097 { "(bad)", { XX } },
2098 },
2099
2100 /* PREGRP48 */
2101 {
2102 { "(bad)", { XX } },
2103 { "(bad)", { XX } },
8976381e 2104 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2105 { "(bad)", { XX } },
2106 },
2107
2108 /* PREGRP49 */
2109 {
2110 { "(bad)", { XX } },
2111 { "(bad)", { XX } },
09a2c6cf 2112 { "pmuldq", { XM, EXx } },
42903f7f
L		 2113 { "(bad)", { XX } },
2114 },
2115
2116 /* PREGRP50 */
2117 {
2118 { "(bad)", { XX } },
2119 { "(bad)", { XX } },
09a2c6cf 2120 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2121 { "(bad)", { XX } },
2122 },
2123
2124 /* PREGRP51 */
2125 {
2126 { "(bad)", { XX } },
2127 { "(bad)", { XX } },
2128 { "movntdqa", { XM, EM } },
2129 { "(bad)", { XX } },
2130 },
2131
2132 /* PREGRP52 */
2133 {
2134 { "(bad)", { XX } },
2135 { "(bad)", { XX } },
09a2c6cf 2136 { "packusdw", { XM, EXx } },
42903f7f
L		 2137 { "(bad)", { XX } },
2138 },
2139
2140 /* PREGRP53 */
2141 {
2142 { "(bad)", { XX } },
2143 { "(bad)", { XX } },
8976381e 2144 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2145 { "(bad)", { XX } },
2146 },
2147
2148 /* PREGRP54 */
2149 {
2150 { "(bad)", { XX } },
2151 { "(bad)", { XX } },
8976381e 2152 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2153 { "(bad)", { XX } },
2154 },
2155
2156 /* PREGRP55 */
2157 {
2158 { "(bad)", { XX } },
2159 { "(bad)", { XX } },
8976381e 2160 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2161 { "(bad)", { XX } },
2162 },
2163
2164 /* PREGRP56 */
2165 {
2166 { "(bad)", { XX } },
2167 { "(bad)", { XX } },
8976381e 2168 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2169 { "(bad)", { XX } },
2170 },
2171
2172 /* PREGRP57 */
2173 {
2174 { "(bad)", { XX } },
2175 { "(bad)", { XX } },
8976381e 2176 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2177 { "(bad)", { XX } },
2178 },
2179
2180 /* PREGRP58 */
2181 {
2182 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
8976381e 2184 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2185 { "(bad)", { XX } },
2186 },
2187
2188 /* PREGRP59 */
2189 {
2190 { "(bad)", { XX } },
2191 { "(bad)", { XX } },
09a2c6cf 2192 { "pminsb", { XM, EXx } },
42903f7f
L		 2193 { "(bad)", { XX } },
2194 },
2195
2196 /* PREGRP60 */
2197 {
2198 { "(bad)", { XX } },
2199 { "(bad)", { XX } },
09a2c6cf 2200 { "pminsd", { XM, EXx } },
42903f7f
L		 2201 { "(bad)", { XX } },
2202 },
2203
2204 /* PREGRP61 */
2205 {
2206 { "(bad)", { XX } },
2207 { "(bad)", { XX } },
09a2c6cf 2208 { "pminuw", { XM, EXx } },
42903f7f
L		 2209 { "(bad)", { XX } },
2210 },
2211
2212 /* PREGRP62 */
2213 {
2214 { "(bad)", { XX } },
2215 { "(bad)", { XX } },
09a2c6cf 2216 { "pminud", { XM, EXx } },
42903f7f
L		 2217 { "(bad)", { XX } },
2218 },
2219
2220 /* PREGRP63 */
2221 {
2222 { "(bad)", { XX } },
2223 { "(bad)", { XX } },
09a2c6cf 2224 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2225 { "(bad)", { XX } },
2226 },
2227
2228 /* PREGRP64 */
2229 {
2230 { "(bad)", { XX } },
2231 { "(bad)", { XX } },
09a2c6cf 2232 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2233 { "(bad)", { XX } },
2234 },
2235
2236 /* PREGRP65 */
2237 {
2238 { "(bad)", { XX } },
2239 { "(bad)", { XX } },
09a2c6cf 2240 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2241 { "(bad)", { XX } },
2242 },
2243
2244 /* PREGRP66 */
2245 {
2246 { "(bad)", { XX } },
2247 { "(bad)", { XX } },
09a2c6cf 2248 { "pmaxud", { XM, EXx } },
42903f7f
L		 2249 { "(bad)", { XX } },
2250 },
2251
2252 /* PREGRP67 */
2253 {
2254 { "(bad)", { XX } },
2255 { "(bad)", { XX } },
09a2c6cf 2256 { "pmulld", { XM, EXx } },
42903f7f
L		 2257 { "(bad)", { XX } },
2258 },
2259
2260 /* PREGRP68 */
2261 {
2262 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
09a2c6cf 2264 { "phminposuw", { XM, EXx } },
42903f7f
L		 2265 { "(bad)", { XX } },
2266 },
2267
2268 /* PREGRP69 */
2269 {
2270 { "(bad)", { XX } },
2271 { "(bad)", { XX } },
09a2c6cf 2272 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2273 { "(bad)", { XX } },
2274 },
2275
2276 /* PREGRP70 */
2277 {
2278 { "(bad)", { XX } },
2279 { "(bad)", { XX } },
09a2c6cf 2280 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2281 { "(bad)", { XX } },
2282 },
2283
2284 /* PREGRP71 */
2285 {
2286 { "(bad)", { XX } },
2287 { "(bad)", { XX } },
09335d05 2288 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2289 { "(bad)", { XX } },
2290 },
2291
2292 /* PREGRP72 */
2293 {
2294 { "(bad)", { XX } },
2295 { "(bad)", { XX } },
09335d05 2296 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2297 { "(bad)", { XX } },
2298 },
2299
2300 /* PREGRP73 */
2301 {
2302 { "(bad)", { XX } },
2303 { "(bad)", { XX } },
09a2c6cf 2304 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2305 { "(bad)", { XX } },
2306 },
2307
2308 /* PREGRP74 */
2309 {
2310 { "(bad)", { XX } },
2311 { "(bad)", { XX } },
09a2c6cf 2312 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2313 { "(bad)", { XX } },
2314 },
2315
2316 /* PREGRP75 */
2317 {
2318 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
09a2c6cf 2320 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2321 { "(bad)", { XX } },
2322 },
2323
2324 /* PREGRP76 */
2325 {
2326 { "(bad)", { XX } },
2327 { "(bad)", { XX } },
2328 { "pextrb", { Edqb, XM, Ib } },
2329 { "(bad)", { XX } },
2330 },
2331
2332 /* PREGRP77 */
2333 {
2334 { "(bad)", { XX } },
2335 { "(bad)", { XX } },
2336 { "pextrw", { Edqw, XM, Ib } },
2337 { "(bad)", { XX } },
2338 },
2339
2340 /* PREGRP78 */
2341 {
2342 { "(bad)", { XX } },
2343 { "(bad)", { XX } },
2344 { "pextrK", { Edq, XM, Ib } },
2345 { "(bad)", { XX } },
2346 },
2347
2348 /* PREGRP79 */
2349 {
2350 { "(bad)", { XX } },
2351 { "(bad)", { XX } },
2352 { "extractps", { Edqd, XM, Ib } },
2353 { "(bad)", { XX } },
2354 },
2355
2356 /* PREGRP80 */
2357 {
2358 { "(bad)", { XX } },
2359 { "(bad)", { XX } },
2360 { "pinsrb", { XM, Edqb, Ib } },
2361 { "(bad)", { XX } },
2362 },
2363
2364 /* PREGRP81 */
2365 {
2366 { "(bad)", { XX } },
2367 { "(bad)", { XX } },
8976381e 2368 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2369 { "(bad)", { XX } },
2370 },
2371
2372 /* PREGRP82 */
2373 {
2374 { "(bad)", { XX } },
2375 { "(bad)", { XX } },
2376 { "pinsrK", { XM, Edq, Ib } },
2377 { "(bad)", { XX } },
2378 },
2379
2380 /* PREGRP83 */
2381 {
2382 { "(bad)", { XX } },
2383 { "(bad)", { XX } },
09a2c6cf 2384 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2385 { "(bad)", { XX } },
2386 },
2387
2388 /* PREGRP84 */
2389 {
2390 { "(bad)", { XX } },
2391 { "(bad)", { XX } },
09a2c6cf 2392 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2393 { "(bad)", { XX } },
2394 },
2395
2396 /* PREGRP85 */
2397 {
2398 { "(bad)", { XX } },
2399 { "(bad)", { XX } },
09a2c6cf 2400 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2401 { "(bad)", { XX } },
2402 },
381d071f
L		 2403
2404 /* PREGRP86 */
2405 {
2406 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
09a2c6cf 2408 { "pcmpgtq", { XM, EXx } },
381d071f
L		 2409 { "(bad)", { XX } },
2410 },
2411
2412 /* PREGRP87 */
2413 {
2414 { "(bad)", { XX } },
2415 { "(bad)", { XX } },
2416 { "(bad)", { XX } },
2417 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2418 },
2419
2420 /* PREGRP88 */
2421 {
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
2424 { "(bad)", { XX } },
2425 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2426 },
2427
2428 /* PREGRP89 */
2429 {
2430 { "(bad)", { XX } },
2431 { "(bad)", { XX } },
09a2c6cf 2432 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2433 { "(bad)", { XX } },
2434 },
2435
2436 /* PREGRP90 */
2437 {
2438 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
09a2c6cf 2440 { "pcmpestri", { XM, EXx, Ib } },
381d071f
L		 2441 { "(bad)", { XX } },
2442 },
2443
2444 /* PREGRP91 */
2445 {
2446 { "(bad)", { XX } },
2447 { "(bad)", { XX } },
09a2c6cf 2448 { "pcmpistrm", { XM, EXx, Ib } },
381d071f
L		 2449 { "(bad)", { XX } },
2450 },
2451
2452 /* PREGRP92 */
2453 {
2454 { "(bad)", { XX } },
2455 { "(bad)", { XX } },
09a2c6cf
L		 2456 { "pcmpistri", { XM, EXx, Ib } },
2457 { "(bad)", { XX } },
2458 },
2459
2460 /* PREGRP93 */
2461 {
2462 { "ucomiss",{ XM, EXd } },
2463 { "(bad)", { XX } },
2464 { "ucomisd",{ XM, EXq } },
2465 { "(bad)", { XX } },
2466 },
2467
2468 /* PREGRP94 */
2469 {
2470 { "comiss", { XM, EXd } },
2471 { "(bad)", { XX } },
2472 { "comisd", { XM, EXq } },
2473 { "(bad)", { XX } },
2474 },
2475
2476 /* PREGRP95 */
2477 {
2478 { "punpcklbw",{ MX, EMd } },
2479 { "(bad)", { XX } },
14051056 2480 { "punpcklbw",{ MX, EMx } },
09a2c6cf
L		 2481 { "(bad)", { XX } },
2482 },
2483
2484 /* PREGRP96 */
2485 {
2486 { "punpcklwd",{ MX, EMd } },
2487 { "(bad)", { XX } },
14051056 2488 { "punpcklwd",{ MX, EMx } },
09a2c6cf
L		 2489 { "(bad)", { XX } },
2490 },
2491
2492 /* PREGRP97 */
2493 {
2494 { "punpckldq",{ MX, EMd } },
2495 { "(bad)", { XX } },
14051056 2496 { "punpckldq",{ MX, EMx } },
381d071f
L		 2497 { "(bad)", { XX } },
2498 },
b844680a
L		 2499
2500 /* PREGRP98 */
2501 {
2502 { "vmptrld",{ Mq } },
2503 { "vmxon", { Mq } },
2504 { "vmclear",{ Mq } },
2505 { "(bad)", { XX } },
2506 },
2507
2508 /* PREGRP99 */
2509 {
2510 { "(bad)", { XX } },
2511 { "(bad)", { XX } },
2512 { "psrldq", { MS, Ib } },
2513 { "(bad)", { XX } },
2514 },
2515
c25c34f8 2516 /* PREGRP100 */
b844680a
L		 2517 {
2518 { "(bad)", { XX } },
2519 { "(bad)", { XX } },
2520 { "pslldq", { MS, Ib } },
2521 { "(bad)", { XX } },
2522 },
c608c12e
AM		 2523};
2524
6439fc28 2525static const struct dis386 x86_64_table[][2] = {
7c52e0e8 2526 /* X86_64_0 */
6439fc28 2527 {
ce518a5f
L		 2528 { "pusha{P|}", { XX } },
2529 { "(bad)", { XX } },
5f754f58 2530 },
7c52e0e8
L		 2531
2532 /* X86_64_1 */
5f754f58 2533 {
ce518a5f
L		 2534 { "popa{P|}", { XX } },
2535 { "(bad)", { XX } },
5f754f58 2536 },
7c52e0e8
L		 2537
2538 /* X86_64_2 */
5f754f58 2539 {
d8faab4e 2540 { OPC_EXT_33 },
ce518a5f 2541 { "(bad)", { XX } },
5f754f58 2542 },
7c52e0e8
L		 2543
2544 /* X86_64_3 */
5f754f58 2545 {
ce518a5f 2546 { "arpl", { Ew, Gw } },
7c52e0e8
L		 2547 { "movs{lq|xd}", { Gv, Ed } },
2548 },
2549
2550 /* X86_64_4 */
2551 {
2552 { "push{T|}", { es } },
2553 { "(bad)", { XX } },
2554 },
2555
2556 /* X86_64_5 */
2557 {
2558 { "pop{T|}", { es } },
2559 { "(bad)", { XX } },
2560 },
2561
2562 /* X86_64_6 */
2563 {
2564 { "push{T|}", { cs } },
2565 { "(bad)", { XX } },
2566 },
2567
2568 /* X86_64_7 */
2569 {
2570 { "push{T|}", { ss } },
2571 { "(bad)", { XX } },
2572 },
2573
2574 /* X86_64_8 */
2575 {
2576 { "pop{T|}", { ss } },
2577 { "(bad)", { XX } },
2578 },
2579
2580 /* X86_64_9 */
2581 {
2582 { "push{T|}", { ds } },
2583 { "(bad)", { XX } },
2584 },
2585
2586 /* X86_64_10 */
2587 {
2588 { "pop{T|}", { ds } },
2589 { "(bad)", { XX } },
2590 },
2591
2592 /* X86_64_11 */
2593 {
2594 { "daa", { XX } },
2595 { "(bad)", { XX } },
2596 },
2597
2598 /* X86_64_12 */
2599 {
2600 { "das", { XX } },
2601 { "(bad)", { XX } },
2602 },
2603
2604 /* X86_64_13 */
2605 {
2606 { "aaa", { XX } },
2607 { "(bad)", { XX } },
2608 },
2609
2610 /* X86_64_14 */
2611 {
2612 { "aas", { XX } },
2613 { "(bad)", { XX } },
2614 },
2615
2616 /* X86_64_15 */
2617 {
2618 { "ins{R|}", { Yzr, indirDX } },
2619 { "ins{G|}", { Yzr, indirDX } },
2620 },
2621
2622 /* X86_64_16 */
2623 {
2624 { "outs{R|}", { indirDXr, Xz } },
2625 { "outs{G|}", { indirDXr, Xz } },
2626 },
2627
2628 /* X86_64_17 */
2629 {
2630 { "Jcall{T|}", { Ap } },
2631 { "(bad)", { XX } },
2632 },
2633
2634 /* X86_64_18 */
2635 {
2636 { "into", { XX } },
2637 { "(bad)", { XX } },
2638 },
2639
2640 /* X86_64_19 */
2641 {
2642 { "aam", { sIb } },
2643 { "(bad)", { XX } },
2644 },
2645
2646 /* X86_64_20 */
2647 {
2648 { "aad", { sIb } },
2649 { "(bad)", { XX } },
2650 },
2651
2652 /* X86_64_21 */
2653 {
2654 { "Jjmp{T|}", { Ap } },
2655 { "(bad)", { XX } },
2656 },
2657
2658 /* X86_64_22 */
2659 {
2660 { "sgdt{Q|IQ}", { M } },
2661 { "sgdt", { M } },
2662 },
2663
2664 /* X86_64_23 */
2665 {
2666 { "sidt{Q|IQ}", { M } },
2667 { "sidt", { M } },
2668 },
2669
2670 /* X86_64_24 */
2671 {
2672 { "lgdt{Q|Q}", { M } },
2673 { "lgdt", { M } },
2674 },
2675
2676 /* X86_64_25 */
2677 {
2678 { "lidt{Q|Q}", { M } },
2679 { "lidt", { M } },
2680 },
2681
2682 /* X86_64_26 */
2683 {
2684 { "lesS", { Gv, Mp } },
2685 { "(bad)", { XX } },
2686 },
2687
2688 /* X86_64_27 */
2689 {
6807063e 2690 { OPC_EXT_2 },
7c52e0e8 2691 { "(bad)", { XX } },
6439fc28
AM		 2692 },
2693};
2694
96fbad73 2695static const struct dis386 three_byte_table[][256] = {
331d2d0d
L		 2696 /* THREE_BYTE_0 */
2697 {
96fbad73 2698 /* 00 */
ce518a5f
L		 2699 { "pshufb", { MX, EM } },
2700 { "phaddw", { MX, EM } },
2701 { "phaddd", { MX, EM } },
2702 { "phaddsw", { MX, EM } },
2703 { "pmaddubsw", { MX, EM } },
2704 { "phsubw", { MX, EM } },
2705 { "phsubd", { MX, EM } },
2706 { "phsubsw", { MX, EM } },
96fbad73 2707 /* 08 */
ce518a5f
L		 2708 { "psignb", { MX, EM } },
2709 { "psignw", { MX, EM } },
2710 { "psignd", { MX, EM } },
2711 { "pmulhrsw", { MX, EM } },
2712 { "(bad)", { XX } },
2713 { "(bad)", { XX } },
2714 { "(bad)", { XX } },
2715 { "(bad)", { XX } },
85f10a01
MM		 2716 /* 10 */
2717 { PREGRP39 },
2718 { "(bad)", { XX } },
2719 { "(bad)", { XX } },
2720 { "(bad)", { XX } },
2721 { PREGRP40 },
2722 { PREGRP41 },
2723 { "(bad)", { XX } },
2724 { PREGRP42 },
2725 /* 18 */
2726 { "(bad)", { XX } },
2727 { "(bad)", { XX } },
2728 { "(bad)", { XX } },
2729 { "(bad)", { XX } },
2730 { "pabsb", { MX, EM } },
2731 { "pabsw", { MX, EM } },
2732 { "pabsd", { MX, EM } },
2733 { "(bad)", { XX } },
2734 /* 20 */
2735 { PREGRP43 },
2736 { PREGRP44 },
2737 { PREGRP45 },
2738 { PREGRP46 },
2739 { PREGRP47 },
2740 { PREGRP48 },
2741 { "(bad)", { XX } },
2742 { "(bad)", { XX } },
2743 /* 28 */
2744 { PREGRP49 },
2745 { PREGRP50 },
2746 { PREGRP51 },
2747 { PREGRP52 },
2748 { "(bad)", { XX } },
2749 { "(bad)", { XX } },
2750 { "(bad)", { XX } },
2751 { "(bad)", { XX } },
2752 /* 30 */
2753 { PREGRP53 },
2754 { PREGRP54 },
2755 { PREGRP55 },
2756 { PREGRP56 },
2757 { PREGRP57 },
2758 { PREGRP58 },
2759 { "(bad)", { XX } },
2760 { PREGRP86 },
2761 /* 38 */
2762 { PREGRP59 },
2763 { PREGRP60 },
2764 { PREGRP61 },
2765 { PREGRP62 },
2766 { PREGRP63 },
2767 { PREGRP64 },
2768 { PREGRP65 },
2769 { PREGRP66 },
2770 /* 40 */
2771 { PREGRP67 },
2772 { PREGRP68 },
2773 { "(bad)", { XX } },
2774 { "(bad)", { XX } },
2775 { "(bad)", { XX } },
2776 { "(bad)", { XX } },
2777 { "(bad)", { XX } },
2778 { "(bad)", { XX } },
2779 /* 48 */
2780 { "(bad)", { XX } },
2781 { "(bad)", { XX } },
2782 { "(bad)", { XX } },
2783 { "(bad)", { XX } },
2784 { "(bad)", { XX } },
2785 { "(bad)", { XX } },
2786 { "(bad)", { XX } },
2787 { "(bad)", { XX } },
2788 /* 50 */
2789 { "(bad)", { XX } },
2790 { "(bad)", { XX } },
2791 { "(bad)", { XX } },
2792 { "(bad)", { XX } },
2793 { "(bad)", { XX } },
2794 { "(bad)", { XX } },
2795 { "(bad)", { XX } },
2796 { "(bad)", { XX } },
2797 /* 58 */
2798 { "(bad)", { XX } },
2799 { "(bad)", { XX } },
2800 { "(bad)", { XX } },
2801 { "(bad)", { XX } },
2802 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 { "(bad)", { XX } },
2805 { "(bad)", { XX } },
2806 /* 60 */
2807 { "(bad)", { XX } },
2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
2810 { "(bad)", { XX } },
2811 { "(bad)", { XX } },
2812 { "(bad)", { XX } },
2813 { "(bad)", { XX } },
2814 { "(bad)", { XX } },
2815 /* 68 */
2816 { "(bad)", { XX } },
2817 { "(bad)", { XX } },
2818 { "(bad)", { XX } },
2819 { "(bad)", { XX } },
2820 { "(bad)", { XX } },
2821 { "(bad)", { XX } },
2822 { "(bad)", { XX } },
2823 { "(bad)", { XX } },
2824 /* 70 */
2825 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2829 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 /* 78 */
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
2842 /* 80 */
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
2847 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 /* 88 */
2852 { "(bad)", { XX } },
2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 { "(bad)", { XX } },
2856 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 /* 90 */
2861 { "(bad)", { XX } },
2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 /* 98 */
2870 { "(bad)", { XX } },
2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 /* a0 */
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 /* a8 */
2888 { "(bad)", { XX } },
2889 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 /* b0 */
2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 /* b8 */
2906 { "(bad)", { XX } },
2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 /* c0 */
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
2923 /* c8 */
2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "(bad)", { XX } },
2927 { "(bad)", { XX } },
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 /* d0 */
2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
2941 /* d8 */
2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
2950 /* e0 */
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 /* e8 */
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 /* f0 */
2969 { PREGRP87 },
2970 { PREGRP88 },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 /* f8 */
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 },
2987 /* THREE_BYTE_1 */
2988 {
2989 /* 00 */
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 /* 08 */
2999 { PREGRP69 },
3000 { PREGRP70 },
3001 { PREGRP71 },
3002 { PREGRP72 },
3003 { PREGRP73 },
3004 { PREGRP74 },
3005 { PREGRP75 },
3006 { "palignr", { MX, EM, Ib } },
3007 /* 10 */
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { PREGRP76 },
3013 { PREGRP77 },
3014 { PREGRP78 },
3015 { PREGRP79 },
3016 /* 18 */
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 /* 20 */
3026 { PREGRP80 },
3027 { PREGRP81 },
3028 { PREGRP82 },
3029 { "(bad)", { XX } },
3030 { "(bad)", { XX } },
3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 /* 28 */
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3039 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 /* 30 */
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 /* 38 */
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 /* 40 */
3062 { PREGRP83 },
3063 { PREGRP84 },
3064 { PREGRP85 },
3065 { "(bad)", { XX } },
3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 /* 48 */
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 /* 50 */
3080 { "(bad)", { XX } },
3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 /* 58 */
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "(bad)", { XX } },
3097 /* 60 */
3098 { PREGRP89 },
3099 { PREGRP90 },
3100 { PREGRP91 },
3101 { PREGRP92 },
3102 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
3106 /* 68 */
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
3111 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
3114 { "(bad)", { XX } },
3115 /* 70 */
3116 { "(bad)", { XX } },
3117 { "(bad)", { XX } },
3118 { "(bad)", { XX } },
3119 { "(bad)", { XX } },
3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 /* 78 */
3125 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
3133 /* 80 */
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
3141 { "(bad)", { XX } },
3142 /* 88 */
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
3149 { "(bad)", { XX } },
3150 { "(bad)", { XX } },
3151 /* 90 */
3152 { "(bad)", { XX } },
3153 { "(bad)", { XX } },
3154 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 /* 98 */
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3165 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 /* a0 */
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 /* a8 */
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
3187 /* b0 */
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 /* b8 */
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 /* c0 */
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 /* c8 */
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 /* d0 */
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 /* d8 */
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 /* e0 */
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 /* e8 */
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 /* f0 */
3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 /* f8 */
3269 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 },
3278 /* THREE_BYTE_SSE5_0F24 */
3279 {
3280 /* 00 */
3281 { "fmaddps", { { OP_DREX4, q_mode } } },
3282 { "fmaddpd", { { OP_DREX4, q_mode } } },
3283 { "fmaddss", { { OP_DREX4, w_mode } } },
3284 { "fmaddsd", { { OP_DREX4, d_mode } } },
3285 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3286 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3287 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3288 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3289 /* 08 */
3290 { "fmsubps", { { OP_DREX4, q_mode } } },
3291 { "fmsubpd", { { OP_DREX4, q_mode } } },
3292 { "fmsubss", { { OP_DREX4, w_mode } } },
3293 { "fmsubsd", { { OP_DREX4, d_mode } } },
3294 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3295 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3296 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3297 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3298 /* 10 */
3299 { "fnmaddps", { { OP_DREX4, q_mode } } },
3300 { "fnmaddpd", { { OP_DREX4, q_mode } } },
3301 { "fnmaddss", { { OP_DREX4, w_mode } } },
3302 { "fnmaddsd", { { OP_DREX4, d_mode } } },
3303 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3304 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3305 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3306 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3307 /* 18 */
3308 { "fnmsubps", { { OP_DREX4, q_mode } } },
3309 { "fnmsubpd", { { OP_DREX4, q_mode } } },
3310 { "fnmsubss", { { OP_DREX4, w_mode } } },
3311 { "fnmsubsd", { { OP_DREX4, d_mode } } },
3312 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3313 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3314 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3315 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3316 /* 20 */
3317 { "permps", { { OP_DREX4, q_mode } } },
3318 { "permpd", { { OP_DREX4, q_mode } } },
3319 { "pcmov", { { OP_DREX4, q_mode } } },
3320 { "pperm", { { OP_DREX4, q_mode } } },
3321 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3322 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3323 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
3324 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
3325 /* 28 */
3326 { "(bad)", { XX } },
3327 { "(bad)", { XX } },
3328 { "(bad)", { XX } },
3329 { "(bad)", { XX } },
3330 { "(bad)", { XX } },
3331 { "(bad)", { XX } },
3332 { "(bad)", { XX } },
3333 { "(bad)", { XX } },
3334 /* 30 */
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3339 { "(bad)", { XX } },
3340 { "(bad)", { XX } },
3341 { "(bad)", { XX } },
3342 { "(bad)", { XX } },
3343 /* 38 */
3344 { "(bad)", { XX } },
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
3347 { "(bad)", { XX } },
3348 { "(bad)", { XX } },
3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 { "(bad)", { XX } },
3352 /* 40 */
3353 { "protb", { { OP_DREX3, q_mode } } },
3354 { "protw", { { OP_DREX3, q_mode } } },
3355 { "protd", { { OP_DREX3, q_mode } } },
3356 { "protq", { { OP_DREX3, q_mode } } },
3357 { "pshlb", { { OP_DREX3, q_mode } } },
3358 { "pshlw", { { OP_DREX3, q_mode } } },
3359 { "pshld", { { OP_DREX3, q_mode } } },
3360 { "pshlq", { { OP_DREX3, q_mode } } },
3361 /* 48 */
3362 { "pshab", { { OP_DREX3, q_mode } } },
3363 { "pshaw", { { OP_DREX3, q_mode } } },
3364 { "pshad", { { OP_DREX3, q_mode } } },
3365 { "pshaq", { { OP_DREX3, q_mode } } },
3366 { "(bad)", { XX } },
3367 { "(bad)", { XX } },
3368 { "(bad)", { XX } },
3369 { "(bad)", { XX } },
3370 /* 50 */
3371 { "(bad)", { XX } },
3372 { "(bad)", { XX } },
3373 { "(bad)", { XX } },
3374 { "(bad)", { XX } },
3375 { "(bad)", { XX } },
3376 { "(bad)", { XX } },
3377 { "(bad)", { XX } },
3378 { "(bad)", { XX } },
3379 /* 58 */
3380 { "(bad)", { XX } },
3381 { "(bad)", { XX } },
3382 { "(bad)", { XX } },
3383 { "(bad)", { XX } },
3384 { "(bad)", { XX } },
3385 { "(bad)", { XX } },
3386 { "(bad)", { XX } },
3387 { "(bad)", { XX } },
3388 /* 60 */
3389 { "(bad)", { XX } },
3390 { "(bad)", { XX } },
3391 { "(bad)", { XX } },
3392 { "(bad)", { XX } },
3393 { "(bad)", { XX } },
3394 { "(bad)", { XX } },
3395 { "(bad)", { XX } },
3396 { "(bad)", { XX } },
3397 /* 68 */
3398 { "(bad)", { XX } },
3399 { "(bad)", { XX } },
3400 { "(bad)", { XX } },
3401 { "(bad)", { XX } },
3402 { "(bad)", { XX } },
3403 { "(bad)", { XX } },
3404 { "(bad)", { XX } },
3405 { "(bad)", { XX } },
3406 /* 70 */
3407 { "(bad)", { XX } },
3408 { "(bad)", { XX } },
3409 { "(bad)", { XX } },
3410 { "(bad)", { XX } },
3411 { "(bad)", { XX } },
3412 { "(bad)", { XX } },
3413 { "(bad)", { XX } },
3414 { "(bad)", { XX } },
3415 /* 78 */
3416 { "(bad)", { XX } },
3417 { "(bad)", { XX } },
3418 { "(bad)", { XX } },
3419 { "(bad)", { XX } },
3420 { "(bad)", { XX } },
3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
3423 { "(bad)", { XX } },
3424 /* 80 */
3425 { "(bad)", { XX } },
3426 { "(bad)", { XX } },
3427 { "(bad)", { XX } },
3428 { "(bad)", { XX } },
3429 { "(bad)", { XX } },
3430 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3431 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3432 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3433 /* 88 */
3434 { "(bad)", { XX } },
3435 { "(bad)", { XX } },
3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3438 { "(bad)", { XX } },
3439 { "(bad)", { XX } },
3440 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3441 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3442 /* 90 */
3443 { "(bad)", { XX } },
3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3447 { "(bad)", { XX } },
3448 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3449 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3450 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3451 /* 98 */
3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3459 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3460 /* a0 */
3461 { "(bad)", { XX } },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
3467 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3468 { "(bad)", { XX } },
3469 /* a8 */
3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 /* b0 */
3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
3485 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3486 { "(bad)", { XX } },
3487 /* b8 */
3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 /* c0 */
3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 /* c8 */
3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 /* d0 */
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 /* d8 */
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 /* e0 */
3533 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 /* e8 */
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 /* f0 */
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 /* f8 */
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 },
3569 /* THREE_BYTE_SSE5_0F25 */
3570 {
3571 /* 00 */
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 /* 08 */
3581 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 /* 10 */
3590 { "(bad)", { XX } },
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 /* 18 */
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 { "(bad)", { XX } },
3607 /* 20 */
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
3612 { "(bad)", { XX } },
3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 /* 28 */
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
3621 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3622 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3623 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3624 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
3625 /* 30 */
3626 { "(bad)", { XX } },
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { "(bad)", { XX } },
3630 { "(bad)", { XX } },
3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 /* 38 */
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
3638 { "(bad)", { XX } },
3639 { "(bad)", { XX } },
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { "(bad)", { XX } },
3643 /* 40 */
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
3648 { "(bad)", { XX } },
3649 { "(bad)", { XX } },
3650 { "(bad)", { XX } },
3651 { "(bad)", { XX } },
3652 /* 48 */
3653 { "(bad)", { XX } },
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
3657 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3658 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3659 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3660 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3661 /* 50 */
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 { "(bad)", { XX } },
3670 /* 58 */
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
3673 { "(bad)", { XX } },
3674 { "(bad)", { XX } },
3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 /* 60 */
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { "(bad)", { XX } },
3684 { "(bad)", { XX } },
3685 { "(bad)", { XX } },
3686 { "(bad)", { XX } },
3687 { "(bad)", { XX } },
3688 /* 68 */
3689 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3694 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3695 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3696 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3697 /* 70 */
3698 { "(bad)", { XX } },
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 /* 78 */
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 /* 80 */
3716 { "(bad)", { XX } },
3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 { "(bad)", { XX } },
3723 { "(bad)", { XX } },
3724 /* 88 */
3725 { "(bad)", { XX } },
3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 /* 90 */
3734 { "(bad)", { XX } },
3735 { "(bad)", { XX } },
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 /* 98 */
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 /* a0 */
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
3754 { "(bad)", { XX } },
3755 { "(bad)", { XX } },
3756 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 /* a8 */
3761 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
3764 { "(bad)", { XX } },
3765 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 /* b0 */
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3774 { "(bad)", { XX } },
3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 /* b8 */
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 /* c0 */
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 /* c8 */
3797 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 /* d0 */
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 /* d8 */
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 /* e0 */
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 /* e8 */
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 /* f0 */
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 /* f8 */
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 },
3860 /* THREE_BYTE_SSE5_0F7A */
3861 {
3862 /* 00 */
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 /* 08 */
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 /* 10 */
3881 { "frczps", { XM, EXq } },
3882 { "frczpd", { XM, EXq } },
3883 { "frczss", { XM, EXq } },
3884 { "frczsd", { XM, EXq } },
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 /* 18 */
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 /* 20 */
3899 { "ptest", { XX } },
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 { "(bad)", { XX } },
3903 { "(bad)", { XX } },
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 /* 28 */
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
ce518a5f
L		 3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
85f10a01
MM		 3916 /* 30 */
3917 { "cvtph2ps", { XM, EXd } },
3918 { "cvtps2ph", { EXd, XM } },
ce518a5f
L		 3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
ce518a5f
L		 3921 { "(bad)", { XX } },
3922 { "(bad)", { XX } },
3923 { "(bad)", { XX } },
3924 { "(bad)", { XX } },
85f10a01 3925 /* 38 */
ce518a5f 3926 { "(bad)", { XX } },
ce518a5f
L		 3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
ce518a5f
L		 3929 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
ce518a5f 3933 { "(bad)", { XX } },
96fbad73 3934 /* 40 */
ce518a5f 3935 { "(bad)", { XX } },
85f10a01
MM		 3936 { "phaddbw", { XM, EXq } },
3937 { "phaddbd", { XM, EXq } },
3938 { "phaddbq", { XM, EXq } },
ce518a5f
L		 3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
85f10a01
MM		 3941 { "phaddwd", { XM, EXq } },
3942 { "phaddwq", { XM, EXq } },
96fbad73 3943 /* 48 */
ce518a5f
L		 3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
85f10a01 3947 { "phadddq", { XM, EXq } },
ce518a5f
L		 3948 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
96fbad73 3952 /* 50 */
ce518a5f 3953 { "(bad)", { XX } },
85f10a01
MM		 3954 { "phaddubw", { XM, EXq } },
3955 { "phaddubd", { XM, EXq } },
3956 { "phaddubq", { XM, EXq } },
ce518a5f
L		 3957 { "(bad)", { XX } },
3958 { "(bad)", { XX } },
85f10a01
MM		 3959 { "phadduwd", { XM, EXq } },
3960 { "phadduwq", { XM, EXq } },
96fbad73 3961 /* 58 */
ce518a5f
L		 3962 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
85f10a01 3965 { "phaddudq", { XM, EXq } },
ce518a5f
L		 3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
96fbad73 3970 /* 60 */
ce518a5f 3971 { "(bad)", { XX } },
85f10a01
MM		 3972 { "phsubbw", { XM, EXq } },
3973 { "phsubbd", { XM, EXq } },
3974 { "phsubbq", { XM, EXq } },
ce518a5f
L		 3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
3978 { "(bad)", { XX } },
96fbad73 3979 /* 68 */
ce518a5f
L		 3980 { "(bad)", { XX } },
3981 { "(bad)", { XX } },
3982 { "(bad)", { XX } },
3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
96fbad73 3988 /* 70 */
ce518a5f
L		 3989 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
96fbad73 3997 /* 78 */
ce518a5f
L		 3998 { "(bad)", { XX } },
3999 { "(bad)", { XX } },
4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { "(bad)", { XX } },
96fbad73 4006 /* 80 */
ce518a5f
L		 4007 { "(bad)", { XX } },
4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { "(bad)", { XX } },
4014 { "(bad)", { XX } },
96fbad73 4015 /* 88 */
ce518a5f
L		 4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
4020 { "(bad)", { XX } },
4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
96fbad73 4024 /* 90 */
ce518a5f
L		 4025 { "(bad)", { XX } },
4026 { "(bad)", { XX } },
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
4029 { "(bad)", { XX } },
4030 { "(bad)", { XX } },
4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
96fbad73 4033 /* 98 */
ce518a5f
L		 4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
4037 { "(bad)", { XX } },
4038 { "(bad)", { XX } },
4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
96fbad73 4042 /* a0 */
ce518a5f
L		 4043 { "(bad)", { XX } },
4044 { "(bad)", { XX } },
4045 { "(bad)", { XX } },
4046 { "(bad)", { XX } },
4047 { "(bad)", { XX } },
4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
96fbad73 4051 /* a8 */
ce518a5f
L		 4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
96fbad73 4060 /* b0 */
ce518a5f
L		 4061 { "(bad)", { XX } },
4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
96fbad73 4069 /* b8 */
ce518a5f
L		 4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
96fbad73 4078 /* c0 */
ce518a5f
L		 4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
96fbad73 4087 /* c8 */
ce518a5f
L		 4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
96fbad73 4096 /* d0 */
ce518a5f
L		 4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
96fbad73 4105 /* d8 */
ce518a5f
L		 4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
96fbad73 4114 /* e0 */
ce518a5f
L		 4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
96fbad73 4123 /* e8 */
ce518a5f
L		 4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
96fbad73 4132 /* f0 */
85f10a01
MM		 4133 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
ce518a5f
L		 4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
96fbad73 4141 /* f8 */
ce518a5f
L		 4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
331d2d0d 4150 },
85f10a01 4151 /* THREE_BYTE_SSE5_0F7B */
331d2d0d 4152 {
96fbad73 4153 /* 00 */
ce518a5f
L		 4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
96fbad73 4162 /* 08 */
ce518a5f
L		 4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
ce518a5f
L		 4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
85f10a01 4171 /* 10 */
ce518a5f
L		 4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
ce518a5f
L		 4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
85f10a01 4180 /* 18 */
ce518a5f 4181 { "(bad)", { XX } },
ce518a5f
L		 4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
85f10a01 4189 /* 20 */
ce518a5f 4190 { "(bad)", { XX } },
ce518a5f
L		 4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
4194 { "(bad)", { XX } },
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
85f10a01 4198 /* 28 */
ce518a5f 4199 { "(bad)", { XX } },
ce518a5f
L		 4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
4206 { "(bad)", { XX } },
85f10a01 4207 /* 30 */
ce518a5f 4208 { "(bad)", { XX } },
ce518a5f
L		 4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
85f10a01
MM		 4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
4216 /* 38 */
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
ce518a5f
L		 4220 { "(bad)", { XX } },
4221 { "(bad)", { XX } },
4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
4224 { "(bad)", { XX } },
85f10a01
MM		 4225 /* 40 */
4226 { "protb", { XM, EXq, Ib } },
4227 { "protw", { XM, EXq, Ib } },
4228 { "protd", { XM, EXq, Ib } },
4229 { "protq", { XM, EXq, Ib } },
4230 { "pshlb", { XM, EXq, Ib } },
4231 { "pshlw", { XM, EXq, Ib } },
4232 { "pshld", { XM, EXq, Ib } },
4233 { "pshlq", { XM, EXq, Ib } },
4234 /* 48 */
4235 { "pshab", { XM, EXq, Ib } },
4236 { "pshaw", { XM, EXq, Ib } },
4237 { "pshad", { XM, EXq, Ib } },
4238 { "pshaq", { XM, EXq, Ib } },
4239 { "(bad)", { XX } },
ce518a5f
L		 4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
96fbad73 4243 /* 50 */
ce518a5f
L		 4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
96fbad73 4252 /* 58 */
ce518a5f
L		 4253 { "(bad)", { XX } },
4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
96fbad73 4261 /* 60 */
85f10a01
MM		 4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
ce518a5f
L		 4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 { "(bad)", { XX } },
96fbad73 4270 /* 68 */
ce518a5f
L		 4271 { "(bad)", { XX } },
4272 { "(bad)", { XX } },
4273 { "(bad)", { XX } },
4274 { "(bad)", { XX } },
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
4277 { "(bad)", { XX } },
4278 { "(bad)", { XX } },
96fbad73 4279 /* 70 */
ce518a5f
L		 4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
96fbad73 4288 /* 78 */
ce518a5f
L		 4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4293 { "(bad)", { XX } },
4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
4296 { "(bad)", { XX } },
96fbad73 4297 /* 80 */
ce518a5f
L		 4298 { "(bad)", { XX } },
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { "(bad)", { XX } },
4302 { "(bad)", { XX } },
4303 { "(bad)", { XX } },
4304 { "(bad)", { XX } },
4305 { "(bad)", { XX } },
96fbad73 4306 /* 88 */
ce518a5f
L		 4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
4309 { "(bad)", { XX } },
4310 { "(bad)", { XX } },
4311 { "(bad)", { XX } },
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
96fbad73 4315 /* 90 */
ce518a5f
L		 4316 { "(bad)", { XX } },
4317 { "(bad)", { XX } },
4318 { "(bad)", { XX } },
4319 { "(bad)", { XX } },
4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
96fbad73 4324 /* 98 */
ce518a5f
L		 4325 { "(bad)", { XX } },
4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
96fbad73 4333 /* a0 */
ce518a5f
L		 4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
96fbad73 4342 /* a8 */
ce518a5f
L		 4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { "(bad)", { XX } },
96fbad73 4351 /* b0 */
ce518a5f
L		 4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
96fbad73 4360 /* b8 */
ce518a5f
L		 4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
96fbad73 4369 /* c0 */
ce518a5f
L		 4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
96fbad73 4378 /* c8 */
ce518a5f
L		 4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
96fbad73 4387 /* d0 */
ce518a5f
L		 4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
96fbad73 4396 /* d8 */
ce518a5f
L		 4397 { "(bad)", { XX } },
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
96fbad73 4405 /* e0 */
ce518a5f
L		 4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
96fbad73 4414 /* e8 */
ce518a5f
L		 4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { "(bad)", { XX } },
96fbad73 4423 /* f0 */
ce518a5f
L		 4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
96fbad73 4432 /* f8 */
ce518a5f
L		 4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 }
331d2d0d
L		 4442};
4443
b844680a
L		 4444static const struct dis386 opc_ext_table[][2] = {
4445 {
4446 /* OPC_EXT_0 */
d8faab4e
L		 4447 { "leaS", { Gv, M } },
4448 { "(bad)", { XX } },
4449 },
4450 {
4451 /* OPC_EXT_1 */
7c52e0e8 4452 { X86_64_26 },
d8faab4e
L		 4453 { "(bad)", { XX } },
4454 },
4455 {
4456 /* OPC_EXT_2 */
6807063e 4457 { "ldsS", { Gv, Mp } },
d8faab4e
L		 4458 { "(bad)", { XX } },
4459 },
4460 {
4461 /* OPC_EXT_3 */
4462 { "lssS", { Gv, Mp } },
4463 { "(bad)", { XX } },
4464 },
4465 {
4466 /* OPC_EXT_4 */
4467 { "lfsS", { Gv, Mp } },
4468 { "(bad)", { XX } },
4469 },
4470 {
4471 /* OPC_EXT_5 */
4472 { "lgsS", { Gv, Mp } },
4473 { "(bad)", { XX } },
4474 },
4475 {
4476 /* OPC_EXT_6 */
7c52e0e8 4477 { X86_64_22 },
b844680a
L		 4478 { OPC_EXT_RM_0 },
4479 },
4480 {
d8faab4e 4481 /* OPC_EXT_7 */
7c52e0e8 4482 { X86_64_23 },
b844680a
L		 4483 { OPC_EXT_RM_1 },
4484 },
4485 {
d8faab4e 4486 /* OPC_EXT_8 */
7c52e0e8 4487 { X86_64_24 },
d8faab4e
L		 4488 { "(bad)", { XX } },
4489 },
4490 {
4491 /* OPC_EXT_9 */
b844680a
L		 4492 { PREGRP98 },
4493 { "(bad)", { XX } },
4494 },
4495 {
d8faab4e 4496 /* OPC_EXT_10 */
b844680a
L		 4497 { "vmptrst", { Mq } },
4498 { "(bad)", { XX } },
4499 },
4500 {
d8faab4e 4501 /* OPC_EXT_11 */
b844680a
L		 4502 { "(bad)", { XX } },
4503 { "psrlw", { MS, Ib } },
4504 },
4505 {
d8faab4e 4506 /* OPC_EXT_12 */
b844680a
L		 4507 { "(bad)", { XX } },
4508 { "psraw", { MS, Ib } },
4509 },
4510 {
d8faab4e 4511 /* OPC_EXT_13 */
b844680a
L		 4512 { "(bad)", { XX } },
4513 { "psllw", { MS, Ib } },
4514 },
4515 {
d8faab4e 4516 /* OPC_EXT_14 */
b844680a
L		 4517 { "(bad)", { XX } },
4518 { "psrld", { MS, Ib } },
4519 },
4520 {
d8faab4e 4521 /* OPC_EXT_15 */
b844680a
L		 4522 { "(bad)", { XX } },
4523 { "psrad", { MS, Ib } },
4524 },
4525 {
d8faab4e 4526 /* OPC_EXT_16 */
b844680a
L		 4527 { "(bad)", { XX } },
4528 { "pslld", { MS, Ib } },
4529 },
4530 {
d8faab4e 4531 /* OPC_EXT_17 */
b844680a
L		 4532 { "(bad)", { XX } },
4533 { "psrlq", { MS, Ib } },
4534 },
4535 {
d8faab4e 4536 /* OPC_EXT_18 */
b844680a
L		 4537 { "(bad)", { XX } },
4538 { PREGRP99 },
4539 },
4540 {
d8faab4e 4541 /* OPC_EXT_19 */
b844680a
L		 4542 { "(bad)", { XX } },
4543 { "psllq", { MS, Ib } },
4544 },
4545 {
d8faab4e 4546 /* OPC_EXT_20 */
b844680a
L		 4547 { "(bad)", { XX } },
4548 { PREGRP100 },
4549 },
4550 {
d8faab4e 4551 /* OPC_EXT_21 */
b844680a
L		 4552 { "fxsave", { M } },
4553 { "(bad)", { XX } },
4554 },
4555 {
d8faab4e 4556 /* OPC_EXT_22 */
b844680a
L		 4557 { "fxrstor", { M } },
4558 { "(bad)", { XX } },
4559 },
4560 {
d8faab4e 4561 /* OPC_EXT_23 */
b844680a
L		 4562 { "ldmxcsr", { Md } },
4563 { "(bad)", { XX } },
4564 },
4565 {
d8faab4e 4566 /* OPC_EXT_24 */
b844680a
L		 4567 { "stmxcsr", { Md } },
4568 { "(bad)", { XX } },
4569 },
4570 {
d8faab4e 4571 /* OPC_EXT_25 */
b844680a
L		 4572 { "(bad)", { XX } },
4573 { OPC_EXT_RM_2 },
4574 },
4575 {
d8faab4e 4576 /* OPC_EXT_26 */
b844680a
L		 4577 { "(bad)", { XX } },
4578 { OPC_EXT_RM_3 },
4579 },
4580 {
d8faab4e 4581 /* OPC_EXT_27 */
b844680a
L		 4582 { "clflush", { Mb } },
4583 { OPC_EXT_RM_4 },
4584 },
4585 {
d8faab4e 4586 /* OPC_EXT_28 */
b844680a
L		 4587 { "prefetchnta", { Mb } },
4588 { "(bad)", { XX } },
4589 },
4590 {
d8faab4e 4591 /* OPC_EXT_29 */
b844680a
L		 4592 { "prefetcht0", { Mb } },
4593 { "(bad)", { XX } },
4594 },
4595 {
d8faab4e 4596 /* OPC_EXT_30 */
b844680a
L		 4597 { "prefetcht1", { Mb } },
4598 { "(bad)", { XX } },
4599 },
4600 {
d8faab4e 4601 /* OPC_EXT_31 */
b844680a
L		 4602 { "prefetcht2", { Mb } },
4603 { "(bad)", { XX } },
4604 },
d8faab4e
L		 4605 {
4606 /* OPC_EXT_32 */
4607 { "lddqu", { XM, M } },
4608 { "(bad)", { XX } },
4609 },
4610 {
4611 /* OPC_EXT_33 */
4612 { "bound{S|}", { Gv, Ma } },
4613 { "(bad)", { XX } },
4614 },
876d4bfa
L		 4615 {
4616 /* OPC_EXT_34 */
4617 { "movlpX", { EXq, XM } },
4618 { "(bad)", { XX } },
4619 },
4620 {
4621 /* OPC_EXT_35 */
4622 { "movhpX", { EXq, XM } },
4623 { "(bad)", { XX } },
4624 },
4625 {
4626 /* OPC_EXT_36 */
4627 { "movlpX", { XM, EXq } },
4628 { "movhlpX", { XM, EXq } },
4629 },
4630 {
4631 /* OPC_EXT_37 */
4632 { "movhpX", { XM, EXq } },
4633 { "movlhpX", { XM, EXq } },
4634 },
bbedc832
L		 4635 {
4636 /* OPC_EXT_38 */
4637 { "invlpg", { Mb } },
4638 { OPC_EXT_RM_5 },
4639 },
144c41d9
L		 4640 {
4641 /* OPC_EXT_39 */
7c52e0e8 4642 { X86_64_25 },
144c41d9
L		 4643 { OPC_EXT_RM_6 },
4644 },
1afd85e3
L		 4645 {
4646 /* OPC_EXT_40 */
4647 { "(bad)", { XX } },
4648 { "movZ", { Rm, Cm } },
4649 },
4650 {
4651 /* OPC_EXT_41 */
4652 { "(bad)", { XX } },
4653 { "movZ", { Rm, Dm } },
4654 },
4655 {
4656 /* OPC_EXT_42 */
4657 { "(bad)", { XX } },
4658 { "movZ", { Cm, Rm } },
4659 },
4660 {
4661 /* OPC_EXT_43 */
4662 { "(bad)", { XX } },
4663 { "movZ", { Dm, Rm } },
4664 },
4665 {
4666 /* OPC_EXT_44 */
85f10a01 4667 { THREE_BYTE_SSE5_0F24 },
1afd85e3
L		 4668 { "movL", { Rd, Td } },
4669 },
4670 {
4671 /* OPC_EXT_45 */
4672 { "(bad)", { XX } },
4673 { "movL", { Td, Rd } },
4674 },
b844680a
L		 4675};
4676
4677static const struct dis386 opc_ext_rm_table[][8] = {
4678 {
4679 /* OPC_EXT_RM_0 */
4680 { "(bad)", { XX } },
4681 { "vmcall", { Skip_MODRM } },
4682 { "vmlaunch", { Skip_MODRM } },
4683 { "vmresume", { Skip_MODRM } },
4684 { "vmxoff", { Skip_MODRM } },
4685 { "(bad)", { XX } },
4686 { "(bad)", { XX } },
4687 { "(bad)", { XX } },
4688 },
4689 {
4690 /* OPC_EXT_RM_1 */
4691 { "monitor", { { OP_Monitor, 0 } } },
4692 { "mwait", { { OP_Mwait, 0 } } },
4693 { "(bad)", { XX } },
4694 { "(bad)", { XX } },
4695 { "(bad)", { XX } },
4696 { "(bad)", { XX } },
4697 { "(bad)", { XX } },
4698 { "(bad)", { XX } },
4699 },
4700 {
4701 /* OPC_EXT_RM_2 */
4702 { "lfence", { Skip_MODRM } },
4703 { "(bad)", { XX } },
4704 { "(bad)", { XX } },
4705 { "(bad)", { XX } },
4706 { "(bad)", { XX } },
4707 { "(bad)", { XX } },
4708 { "(bad)", { XX } },
4709 { "(bad)", { XX } },
4710 },
4711 {
4712 /* OPC_EXT_RM_3 */
4713 { "mfence", { Skip_MODRM } },
4714 { "(bad)", { XX } },
4715 { "(bad)", { XX } },
4716 { "(bad)", { XX } },
4717 { "(bad)", { XX } },
4718 { "(bad)", { XX } },
4719 { "(bad)", { XX } },
4720 { "(bad)", { XX } },
4721 },
4722 {
4723 /* OPC_EXT_RM_4 */
4724 { "sfence", { Skip_MODRM } },
4725 { "(bad)", { XX } },
4726 { "(bad)", { XX } },
4727 { "(bad)", { XX } },
4728 { "(bad)", { XX } },
4729 { "(bad)", { XX } },
4730 { "(bad)", { XX } },
4731 { "(bad)", { XX } },
4732 },
bbedc832
L		 4733 {
4734 /* OPC_EXT_RM_5 */
4735 { "swapgs", { Skip_MODRM } },
4736 { "rdtscp", { Skip_MODRM } },
4737 { "(bad)", { XX } },
4738 { "(bad)", { XX } },
4739 { "(bad)", { XX } },
4740 { "(bad)", { XX } },
4741 { "(bad)", { XX } },
4742 { "(bad)", { XX } },
4743 },
144c41d9
L		 4744 {
4745 /* OPC_EXT_RM_6 */
4746 { "vmrun", { Skip_MODRM } },
4747 { "vmmcall", { Skip_MODRM } },
4748 { "vmload", { Skip_MODRM } },
4749 { "vmsave", { Skip_MODRM } },
4750 { "stgi", { Skip_MODRM } },
4751 { "clgi", { Skip_MODRM } },
4752 { "skinit", { Skip_MODRM } },
4753 { "invlpga", { Skip_MODRM } },
4754 },
b844680a
L		 4755};
4756
c608c12e
AM		 4757#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4758
252b5132 4759static void
26ca5450 4760ckprefix (void)
252b5132 4761{
52b15da3
JH		 4762 int newrex;
4763 rex = 0;
252b5132 4764 prefixes = 0;
7d421014 4765 used_prefixes = 0;
52b15da3 4766 rex_used = 0;
252b5132
RH		 4767 while (1)
4768 {
4769 FETCH_DATA (the_info, codep + 1);
52b15da3 4770 newrex = 0;
252b5132
RH		 4771 switch (*codep)
4772 {
52b15da3
JH		 4773 /* REX prefixes family. */
4774 case 0x40:
4775 case 0x41:
4776 case 0x42:
4777 case 0x43:
4778 case 0x44:
4779 case 0x45:
4780 case 0x46:
4781 case 0x47:
4782 case 0x48:
4783 case 0x49:
4784 case 0x4a:
4785 case 0x4b:
4786 case 0x4c:
4787 case 0x4d:
4788 case 0x4e:
4789 case 0x4f:
cb712a9e 4790 if (address_mode == mode_64bit)
52b15da3
JH		 4791 newrex = *codep;
4792 else
4793 return;
4794 break;
252b5132
RH		 4795 case 0xf3:
4796 prefixes |= PREFIX_REPZ;
4797 break;
4798 case 0xf2:
4799 prefixes |= PREFIX_REPNZ;
4800 break;
4801 case 0xf0:
4802 prefixes |= PREFIX_LOCK;
4803 break;
4804 case 0x2e:
4805 prefixes |= PREFIX_CS;
4806 break;
4807 case 0x36:
4808 prefixes |= PREFIX_SS;
4809 break;
4810 case 0x3e:
4811 prefixes |= PREFIX_DS;
4812 break;
4813 case 0x26:
4814 prefixes |= PREFIX_ES;
4815 break;
4816 case 0x64:
4817 prefixes |= PREFIX_FS;
4818 break;
4819 case 0x65:
4820 prefixes |= PREFIX_GS;
4821 break;
4822 case 0x66:
4823 prefixes |= PREFIX_DATA;
4824 break;
4825 case 0x67:
4826 prefixes |= PREFIX_ADDR;
4827 break;
5076851f 4828 case FWAIT_OPCODE:
252b5132
RH		 4829 /* fwait is really an instruction. If there are prefixes
4830 before the fwait, they belong to the fwait, *not* to the
4831 following instruction. */
3e7d61b2 4832 if (prefixes || rex)
252b5132
RH		 4833 {
4834 prefixes |= PREFIX_FWAIT;
4835 codep++;
4836 return;
4837 }
4838 prefixes = PREFIX_FWAIT;
4839 break;
4840 default:
4841 return;
4842 }
52b15da3
JH		 4843 /* Rex is ignored when followed by another prefix. */
4844 if (rex)
4845 {
3e7d61b2
AM		 4846 rex_used = rex;
4847 return;
52b15da3
JH		 4848 }
4849 rex = newrex;
252b5132
RH		 4850 codep++;
4851 }
4852}
4853
7d421014
ILT		 4854/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4855 prefix byte. */
4856
4857static const char *
26ca5450 4858prefix_name (int pref, int sizeflag)
7d421014 4859{
0003779b
L		 4860 static const char *rexes [16] =
4861 {
4862 "rex", /* 0x40 */
4863 "rex.B", /* 0x41 */
4864 "rex.X", /* 0x42 */
4865 "rex.XB", /* 0x43 */
4866 "rex.R", /* 0x44 */
4867 "rex.RB", /* 0x45 */
4868 "rex.RX", /* 0x46 */
4869 "rex.RXB", /* 0x47 */
4870 "rex.W", /* 0x48 */
4871 "rex.WB", /* 0x49 */
4872 "rex.WX", /* 0x4a */
4873 "rex.WXB", /* 0x4b */
4874 "rex.WR", /* 0x4c */
4875 "rex.WRB", /* 0x4d */
4876 "rex.WRX", /* 0x4e */
4877 "rex.WRXB", /* 0x4f */
4878 };
4879
7d421014
ILT		 4880 switch (pref)
4881 {
52b15da3
JH		 4882 /* REX prefixes family. */
4883 case 0x40:
52b15da3 4884 case 0x41:
52b15da3 4885 case 0x42:
52b15da3 4886 case 0x43:
52b15da3 4887 case 0x44:
52b15da3 4888 case 0x45:
52b15da3 4889 case 0x46:
52b15da3 4890 case 0x47:
52b15da3 4891 case 0x48:
52b15da3 4892 case 0x49:
52b15da3 4893 case 0x4a:
52b15da3 4894 case 0x4b:
52b15da3 4895 case 0x4c:
52b15da3 4896 case 0x4d:
52b15da3 4897 case 0x4e:
52b15da3 4898 case 0x4f:
0003779b 4899 return rexes [pref - 0x40];
7d421014
ILT		 4900 case 0xf3:
4901 return "repz";
4902 case 0xf2:
4903 return "repnz";
4904 case 0xf0:
4905 return "lock";
4906 case 0x2e:
4907 return "cs";
4908 case 0x36:
4909 return "ss";
4910 case 0x3e:
4911 return "ds";
4912 case 0x26:
4913 return "es";
4914 case 0x64:
4915 return "fs";
4916 case 0x65:
4917 return "gs";
4918 case 0x66:
4919 return (sizeflag & DFLAG) ? "data16" : "data32";
4920 case 0x67:
cb712a9e 4921 if (address_mode == mode_64bit)
db6eb5be 4922 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 4923 else
2888cb7a 4924 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 4925 case FWAIT_OPCODE:
4926 return "fwait";
4927 default:
4928 return NULL;
4929 }
4930}
4931
ce518a5f
L		 4932static char op_out[MAX_OPERANDS][100];
4933static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 4934static int two_source_ops;
ce518a5f
L		 4935static bfd_vma op_address[MAX_OPERANDS];
4936static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 4937static bfd_vma start_pc;
ce518a5f 4938
252b5132
RH		 4939/*
4940 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
4941 * (see topic "Redundant prefixes" in the "Differences from 8086"
4942 * section of the "Virtual 8086 Mode" chapter.)
4943 * 'pc' should be the address of this instruction, it will
4944 * be used to print the target address if this is a relative jump or call
4945 * The function returns the length of this instruction in bytes.
4946 */
4947
252b5132
RH		 4948static char intel_syntax;
4949static char open_char;
4950static char close_char;
4951static char separator_char;
4952static char scale_char;
4953
e396998b
AM		 4954/* Here for backwards compatibility. When gdb stops using
4955 print_insn_i386_att and print_insn_i386_intel these functions can
4956 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 4957int
26ca5450 4958print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 4959{
4960 intel_syntax = 0;
e396998b
AM		 4961
4962 return print_insn (pc, info);
252b5132
RH		 4963}
4964
4965int
26ca5450 4966print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 4967{
4968 intel_syntax = 1;
e396998b
AM		 4969
4970 return print_insn (pc, info);
252b5132
RH		 4971}
4972
e396998b 4973int
26ca5450 4974print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 4975{
4976 intel_syntax = -1;
4977
4978 return print_insn (pc, info);
4979}
4980
f59a29b9
L		 4981void
4982print_i386_disassembler_options (FILE *stream)
4983{
4984 fprintf (stream, _("\n\
4985The following i386/x86-64 specific disassembler options are supported for use\n\
4986with the -M switch (multiple options should be separated by commas):\n"));
4987
4988 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
4989 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
4990 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
4991 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
4992 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
4993 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
4994 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
4995 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
4996 fprintf (stream, _(" data32 Assume 32bit data size\n"));
4997 fprintf (stream, _(" data16 Assume 16bit data size\n"));
4998 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
4999}
5000
b844680a
L		 5001/* Get a pointer to struct dis386 with a valid name. */
5002
5003static const struct dis386 *
8bb15339 5004get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 5005{
5006 int index;
5007
5008 if (dp->name != NULL)
5009 return dp;
5010
5011 switch (dp->op[0].bytemode)
5012 {
5013 case USE_GROUPS:
5014 dp = &grps[dp->op[1].bytemode][modrm.reg];
5015 break;
5016
5017 case USE_PREFIX_USER_TABLE:
5018 index = 0;
5019 used_prefixes |= (prefixes & PREFIX_REPZ);
5020 if (prefixes & PREFIX_REPZ)
5021 {
5022 index = 1;
5023 repz_prefix = NULL;
5024 }
5025 else
5026 {
5027 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5028 PREFIX_DATA. */
5029 used_prefixes |= (prefixes & PREFIX_REPNZ);
5030 if (prefixes & PREFIX_REPNZ)
5031 {
5032 index = 3;
5033 repnz_prefix = NULL;
5034 }
5035 else
5036 {
5037 used_prefixes |= (prefixes & PREFIX_DATA);
5038 if (prefixes & PREFIX_DATA)
5039 {
5040 index = 2;
5041 data_prefix = NULL;
5042 }
5043 }
5044 }
5045 dp = &prefix_user_table[dp->op[1].bytemode][index];
5046 break;
5047
5048 case X86_64_SPECIAL:
5049 index = address_mode == mode_64bit ? 1 : 0;
5050 dp = &x86_64_table[dp->op[1].bytemode][index];
5051 break;
5052
8bb15339
L		 5053 case IS_3BYTE_OPCODE:
5054 FETCH_DATA (info, codep + 2);
5055 index = *codep++;
5056 dp = &three_byte_table[dp->op[1].bytemode][index];
5057 modrm.mod = (*codep >> 6) & 3;
5058 modrm.reg = (*codep >> 3) & 7;
5059 modrm.rm = *codep & 7;
5060 break;
5061
b844680a
L		 5062 case USE_OPC_EXT_TABLE:
5063 index = modrm.mod == 0x3 ? 1 : 0;
5064 dp = &opc_ext_table[dp->op[1].bytemode][index];
5065 break;
5066
5067 case USE_OPC_EXT_RM_TABLE:
5068 index = modrm.rm;
5069 dp = &opc_ext_rm_table[dp->op[1].bytemode][index];
5070 break;
5071
5072 default:
5073 oappend (INTERNAL_DISASSEMBLER_ERROR);
5074 return NULL;
5075 }
5076
5077 if (dp->name != NULL)
5078 return dp;
5079 else
8bb15339 5080 return get_valid_dis386 (dp, info);
b844680a
L		 5081}
5082
e396998b 5083static int
26ca5450 5084print_insn (bfd_vma pc, disassemble_info *info)
252b5132 5085{
2da11e11 5086 const struct dis386 *dp;
252b5132 5087 int i;
ce518a5f 5088 char *op_txt[MAX_OPERANDS];
252b5132 5089 int needcomma;
e396998b
AM		 5090 int sizeflag;
5091 const char *p;
252b5132 5092 struct dis_private priv;
eec0f4ca 5093 unsigned char op;
b844680a
L		 5094 char prefix_obuf[32];
5095 char *prefix_obufp;
252b5132 5096
cb712a9e
L		 5097 if (info->mach == bfd_mach_x86_64_intel_syntax
5098 || info->mach == bfd_mach_x86_64)
5099 address_mode = mode_64bit;
5100 else
5101 address_mode = mode_32bit;
52b15da3 5102
8373f971 5103 if (intel_syntax == (char) -1)
e396998b
AM		 5104 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5105 || info->mach == bfd_mach_x86_64_intel_syntax);
5106
2da11e11 5107 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 5108 || info->mach == bfd_mach_x86_64
5109 || info->mach == bfd_mach_i386_i386_intel_syntax
5110 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 5111 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 5112 else if (info->mach == bfd_mach_i386_i8086)
e396998b 5113 priv.orig_sizeflag = 0;
2da11e11
AM		 5114 else
5115 abort ();
e396998b
AM		 5116
5117 for (p = info->disassembler_options; p != NULL; )
5118 {
0112cd26 5119 if (CONST_STRNEQ (p, "x86-64"))
e396998b 5120 {
cb712a9e 5121 address_mode = mode_64bit;
e396998b
AM		 5122 priv.orig_sizeflag = AFLAG | DFLAG;
5123 }
0112cd26 5124 else if (CONST_STRNEQ (p, "i386"))
e396998b 5125 {
cb712a9e 5126 address_mode = mode_32bit;
e396998b
AM		 5127 priv.orig_sizeflag = AFLAG | DFLAG;
5128 }
0112cd26 5129 else if (CONST_STRNEQ (p, "i8086"))
e396998b 5130 {
cb712a9e 5131 address_mode = mode_16bit;
e396998b
AM		 5132 priv.orig_sizeflag = 0;
5133 }
0112cd26 5134 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 5135 {
5136 intel_syntax = 1;
5137 }
0112cd26 5138 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 5139 {
5140 intel_syntax = 0;
5141 }
0112cd26 5142 else if (CONST_STRNEQ (p, "addr"))
e396998b 5143 {
f59a29b9
L		 5144 if (address_mode == mode_64bit)
5145 {
5146 if (p[4] == '3' && p[5] == '2')
5147 priv.orig_sizeflag &= ~AFLAG;
5148 else if (p[4] == '6' && p[5] == '4')
5149 priv.orig_sizeflag |= AFLAG;
5150 }
5151 else
5152 {
5153 if (p[4] == '1' && p[5] == '6')
5154 priv.orig_sizeflag &= ~AFLAG;
5155 else if (p[4] == '3' && p[5] == '2')
5156 priv.orig_sizeflag |= AFLAG;
5157 }
e396998b 5158 }
0112cd26 5159 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 5160 {
5161 if (p[4] == '1' && p[5] == '6')
5162 priv.orig_sizeflag &= ~DFLAG;
5163 else if (p[4] == '3' && p[5] == '2')
5164 priv.orig_sizeflag |= DFLAG;
5165 }
0112cd26 5166 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 5167 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5168
5169 p = strchr (p, ',');
5170 if (p != NULL)
5171 p++;
5172 }
5173
5174 if (intel_syntax)
5175 {
5176 names64 = intel_names64;
5177 names32 = intel_names32;
5178 names16 = intel_names16;
5179 names8 = intel_names8;
5180 names8rex = intel_names8rex;
5181 names_seg = intel_names_seg;
db51cc60
L		 5182 index64 = intel_index64;
5183 index32 = intel_index32;
e396998b
AM		 5184 index16 = intel_index16;
5185 open_char = '[';
5186 close_char = ']';
5187 separator_char = '+';
5188 scale_char = '*';
5189 }
5190 else
5191 {
5192 names64 = att_names64;
5193 names32 = att_names32;
5194 names16 = att_names16;
5195 names8 = att_names8;
5196 names8rex = att_names8rex;
5197 names_seg = att_names_seg;
db51cc60
L		 5198 index64 = att_index64;
5199 index32 = att_index32;
e396998b
AM		 5200 index16 = att_index16;
5201 open_char = '(';
5202 close_char = ')';
5203 separator_char = ',';
5204 scale_char = ',';
5205 }
2da11e11 5206
4fe53c98 5207 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5208 puts most long word instructions on a single line. */
4fe53c98 5209 info->bytes_per_line = 7;
252b5132 5210
26ca5450 5211 info->private_data = &priv;
252b5132
RH		 5212 priv.max_fetched = priv.the_buffer;
5213 priv.insn_start = pc;
252b5132
RH		 5214
5215 obuf[0] = 0;
ce518a5f
L		 5216 for (i = 0; i < MAX_OPERANDS; ++i)
5217 {
5218 op_out[i][0] = 0;
5219 op_index[i] = -1;
5220 }
252b5132
RH		 5221
5222 the_info = info;
5223 start_pc = pc;
e396998b
AM		 5224 start_codep = priv.the_buffer;
5225 codep = priv.the_buffer;
252b5132 5226
5076851f
ILT		 5227 if (setjmp (priv.bailout) != 0)
5228 {
7d421014
ILT		 5229 const char *name;
5230
5076851f 5231 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5232 means we have an incomplete instruction of some sort. Just
5233 print the first byte as a prefix or a .byte pseudo-op. */
5234 if (codep > priv.the_buffer)
5076851f 5235 {
e396998b 5236 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5237 if (name != NULL)
5238 (*info->fprintf_func) (info->stream, "%s", name);
5239 else
5076851f 5240 {
7d421014
ILT		 5241 /* Just print the first byte as a .byte instruction. */
5242 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5243 (unsigned int) priv.the_buffer[0]);
5076851f 5244 }
5076851f 5245
7d421014 5246 return 1;
5076851f
ILT		 5247 }
5248
5249 return -1;
5250 }
5251
52b15da3 5252 obufp = obuf;
252b5132
RH		 5253 ckprefix ();
5254
5255 insn_codep = codep;
e396998b 5256 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5257
5258 FETCH_DATA (info, codep + 1);
5259 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5260
3e7d61b2
AM		 5261 if (((prefixes & PREFIX_FWAIT)
5262 && ((*codep < 0xd8) || (*codep > 0xdf)))
5263 || (rex && rex_used))
252b5132 5264 {
7d421014
ILT		 5265 const char *name;
5266
3e7d61b2
AM		 5267 /* fwait not followed by floating point instruction, or rex followed
5268 by other prefixes. Print the first prefix. */
e396998b 5269 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5270 if (name == NULL)
5271 name = INTERNAL_DISASSEMBLER_ERROR;
5272 (*info->fprintf_func) (info->stream, "%s", name);
5273 return 1;
252b5132
RH		 5274 }
5275
eec0f4ca 5276 op = 0;
252b5132
RH		 5277 if (*codep == 0x0f)
5278 {
eec0f4ca 5279 unsigned char threebyte;
252b5132 5280 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5281 threebyte = *++codep;
5282 dp = &dis386_twobyte[threebyte];
252b5132 5283 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5284 codep++;
252b5132
RH		 5285 }
5286 else
5287 {
6439fc28 5288 dp = &dis386[*codep];
252b5132 5289 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5290 codep++;
252b5132 5291 }
246c51aa 5292
b844680a 5293 if ((prefixes & PREFIX_REPZ))
7d421014 5294 {
b844680a 5295 repz_prefix = "repz ";
7d421014
ILT		 5296 used_prefixes |= PREFIX_REPZ;
5297 }
b844680a
L		 5298 else
5299 repz_prefix = NULL;
5300
5301 if ((prefixes & PREFIX_REPNZ))
7d421014 5302 {
b844680a 5303 repnz_prefix = "repnz ";
7d421014
ILT		 5304 used_prefixes |= PREFIX_REPNZ;
5305 }
b844680a
L		 5306 else
5307 repnz_prefix = NULL;
050dfa73 5308
b844680a 5309 if ((prefixes & PREFIX_LOCK))
7d421014 5310 {
b844680a 5311 lock_prefix = "lock ";
7d421014
ILT		 5312 used_prefixes |= PREFIX_LOCK;
5313 }
b844680a
L		 5314 else
5315 lock_prefix = NULL;
c608c12e 5316
b844680a 5317 addr_prefix = NULL;
c608c12e
AM		 5318 if (prefixes & PREFIX_ADDR)
5319 {
5320 sizeflag ^= AFLAG;
ce518a5f 5321 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5322 {
cb712a9e 5323 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5324 addr_prefix = "addr32 ";
3ffd33cf 5325 else
b844680a 5326 addr_prefix = "addr16 ";
3ffd33cf
AM		 5327 used_prefixes |= PREFIX_ADDR;
5328 }
5329 }
5330
b844680a
L		 5331 data_prefix = NULL;
5332 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5333 {
5334 sizeflag ^= DFLAG;
ce518a5f
L		 5335 if (dp->op[2].bytemode == cond_jump_mode
5336 && dp->op[0].bytemode == v_mode
6439fc28 5337 && !intel_syntax)
3ffd33cf
AM		 5338 {
5339 if (sizeflag & DFLAG)
b844680a 5340 data_prefix = "data32 ";
3ffd33cf 5341 else
b844680a 5342 data_prefix = "data16 ";
3ffd33cf
AM		 5343 used_prefixes |= PREFIX_DATA;
5344 }
5345 }
5346
8bb15339 5347 if (need_modrm)
252b5132
RH		 5348 {
5349 FETCH_DATA (info, codep + 1);
7967e09e
L		 5350 modrm.mod = (*codep >> 6) & 3;
5351 modrm.reg = (*codep >> 3) & 7;
5352 modrm.rm = *codep & 7;
252b5132
RH		 5353 }
5354
ce518a5f 5355 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5356 {
5357 dofloat (sizeflag);
5358 }
5359 else
5360 {
8bb15339 5361 dp = get_valid_dis386 (dp, info);
b844680a 5362 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5363 {
5364 for (i = 0; i < MAX_OPERANDS; ++i)
5365 {
246c51aa 5366 obufp = op_out[i];
ce518a5f
L		 5367 op_ad = MAX_OPERANDS - 1 - i;
5368 if (dp->op[i].rtn)
5369 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5370 }
6439fc28 5371 }
252b5132
RH		 5372 }
5373
7d421014
ILT		 5374 /* See if any prefixes were not used. If so, print the first one
5375 separately. If we don't do this, we'll wind up printing an
5376 instruction stream which does not precisely correspond to the
5377 bytes we are disassembling. */
5378 if ((prefixes & ~used_prefixes) != 0)
5379 {
5380 const char *name;
5381
e396998b 5382 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5383 if (name == NULL)
5384 name = INTERNAL_DISASSEMBLER_ERROR;
5385 (*info->fprintf_func) (info->stream, "%s", name);
5386 return 1;
5387 }
52b15da3
JH		 5388 if (rex & ~rex_used)
5389 {
5390 const char *name;
e396998b 5391 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5392 if (name == NULL)
5393 name = INTERNAL_DISASSEMBLER_ERROR;
5394 (*info->fprintf_func) (info->stream, "%s ", name);
5395 }
7d421014 5396
b844680a
L		 5397 prefix_obuf[0] = 0;
5398 prefix_obufp = prefix_obuf;
5399 if (lock_prefix)
5400 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5401 if (repz_prefix)
5402 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5403 if (repnz_prefix)
5404 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5405 if (addr_prefix)
5406 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5407 if (data_prefix)
5408 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5409
5410 if (prefix_obuf[0] != 0)
5411 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5412
252b5132 5413 obufp = obuf + strlen (obuf);
b844680a 5414 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5415 oappend (" ");
5416 oappend (" ");
5417 (*info->fprintf_func) (info->stream, "%s", obuf);
5418
5419 /* The enter and bound instructions are printed with operands in the same
5420 order as the intel book; everything else is printed in reverse order. */
2da11e11 5421 if (intel_syntax || two_source_ops)
252b5132 5422 {
185b1163
L		 5423 bfd_vma riprel;
5424
ce518a5f
L		 5425 for (i = 0; i < MAX_OPERANDS; ++i)
5426 op_txt[i] = op_out[i];
246c51aa 5427
ce518a5f
L		 5428 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5429 {
5430 op_ad = op_index[i];
5431 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5432 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5433 riprel = op_riprel[i];
5434 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5435 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5436 }
252b5132
RH		 5437 }
5438 else
5439 {
ce518a5f
L		 5440 for (i = 0; i < MAX_OPERANDS; ++i)
5441 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5442 }
5443
ce518a5f
L		 5444 needcomma = 0;
5445 for (i = 0; i < MAX_OPERANDS; ++i)
5446 if (*op_txt[i])
5447 {
5448 if (needcomma)
5449 (*info->fprintf_func) (info->stream, ",");
5450 if (op_index[i] != -1 && !op_riprel[i])
5451 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5452 else
5453 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5454 needcomma = 1;
5455 }
050dfa73 5456
ce518a5f 5457 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5458 if (op_index[i] != -1 && op_riprel[i])
5459 {
5460 (*info->fprintf_func) (info->stream, " # ");
5461 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5462 + op_address[op_index[i]]), info);
185b1163 5463 break;
52b15da3 5464 }
e396998b 5465 return codep - priv.the_buffer;
252b5132
RH		 5466}
5467
6439fc28 5468static const char *float_mem[] = {
252b5132 5469 /* d8 */
7c52e0e8
L		 5470 "fadd{s|}",
5471 "fmul{s|}",
5472 "fcom{s|}",
5473 "fcomp{s|}",
5474 "fsub{s|}",
5475 "fsubr{s|}",
5476 "fdiv{s|}",
5477 "fdivr{s|}",
db6eb5be 5478 /* d9 */
7c52e0e8 5479 "fld{s|}",
252b5132 5480 "(bad)",
7c52e0e8
L		 5481 "fst{s|}",
5482 "fstp{s|}",
9306ca4a 5483 "fldenvIC",
252b5132 5484 "fldcw",
9306ca4a 5485 "fNstenvIC",
252b5132
RH		 5486 "fNstcw",
5487 /* da */
7c52e0e8
L		 5488 "fiadd{l|}",
5489 "fimul{l|}",
5490 "ficom{l|}",
5491 "ficomp{l|}",
5492 "fisub{l|}",
5493 "fisubr{l|}",
5494 "fidiv{l|}",
5495 "fidivr{l|}",
252b5132 5496 /* db */
7c52e0e8
L		 5497 "fild{l|}",
5498 "fisttp{l|}",
5499 "fist{l|}",
5500 "fistp{l|}",
252b5132 5501 "(bad)",
6439fc28 5502 "fld{t||t|}",
252b5132 5503 "(bad)",
6439fc28 5504 "fstp{t||t|}",
252b5132 5505 /* dc */
7c52e0e8
L		 5506 "fadd{l|}",
5507 "fmul{l|}",
5508 "fcom{l|}",
5509 "fcomp{l|}",
5510 "fsub{l|}",
5511 "fsubr{l|}",
5512 "fdiv{l|}",
5513 "fdivr{l|}",
252b5132 5514 /* dd */
7c52e0e8
L		 5515 "fld{l|}",
5516 "fisttp{ll|}",
5517 "fst{l||}",
5518 "fstp{l|}",
9306ca4a 5519 "frstorIC",
252b5132 5520 "(bad)",
9306ca4a 5521 "fNsaveIC",
252b5132
RH		 5522 "fNstsw",
5523 /* de */
5524 "fiadd",
5525 "fimul",
5526 "ficom",
5527 "ficomp",
5528 "fisub",
5529 "fisubr",
5530 "fidiv",
5531 "fidivr",
5532 /* df */
5533 "fild",
ca164297 5534 "fisttp",
252b5132
RH		 5535 "fist",
5536 "fistp",
5537 "fbld",
7c52e0e8 5538 "fild{ll|}",
252b5132 5539 "fbstp",
7c52e0e8 5540 "fistp{ll|}",
1d9f512f
AM		 5541};
5542
5543static const unsigned char float_mem_mode[] = {
5544 /* d8 */
5545 d_mode,
5546 d_mode,
5547 d_mode,
5548 d_mode,
5549 d_mode,
5550 d_mode,
5551 d_mode,
5552 d_mode,
5553 /* d9 */
5554 d_mode,
5555 0,
5556 d_mode,
5557 d_mode,
5558 0,
5559 w_mode,
5560 0,
5561 w_mode,
5562 /* da */
5563 d_mode,
5564 d_mode,
5565 d_mode,
5566 d_mode,
5567 d_mode,
5568 d_mode,
5569 d_mode,
5570 d_mode,
5571 /* db */
5572 d_mode,
5573 d_mode,
5574 d_mode,
5575 d_mode,
5576 0,
9306ca4a 5577 t_mode,
1d9f512f 5578 0,
9306ca4a 5579 t_mode,
1d9f512f
AM		 5580 /* dc */
5581 q_mode,
5582 q_mode,
5583 q_mode,
5584 q_mode,
5585 q_mode,
5586 q_mode,
5587 q_mode,
5588 q_mode,
5589 /* dd */
5590 q_mode,
5591 q_mode,
5592 q_mode,
5593 q_mode,
5594 0,
5595 0,
5596 0,
5597 w_mode,
5598 /* de */
5599 w_mode,
5600 w_mode,
5601 w_mode,
5602 w_mode,
5603 w_mode,
5604 w_mode,
5605 w_mode,
5606 w_mode,
5607 /* df */
5608 w_mode,
5609 w_mode,
5610 w_mode,
5611 w_mode,
9306ca4a 5612 t_mode,
1d9f512f 5613 q_mode,
9306ca4a 5614 t_mode,
1d9f512f 5615 q_mode
252b5132
RH		 5616};
5617
ce518a5f
L		 5618#define ST { OP_ST, 0 }
5619#define STi { OP_STi, 0 }
252b5132 5620
4efba78c
L		 5621#define FGRPd9_2 NULL, { { NULL, 0 } }
5622#define FGRPd9_4 NULL, { { NULL, 1 } }
5623#define FGRPd9_5 NULL, { { NULL, 2 } }
5624#define FGRPd9_6 NULL, { { NULL, 3 } }
5625#define FGRPd9_7 NULL, { { NULL, 4 } }
5626#define FGRPda_5 NULL, { { NULL, 5 } }
5627#define FGRPdb_4 NULL, { { NULL, 6 } }
5628#define FGRPde_3 NULL, { { NULL, 7 } }
5629#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5630
2da11e11 5631static const struct dis386 float_reg[][8] = {
252b5132
RH		 5632 /* d8 */
5633 {
ce518a5f
L		 5634 { "fadd", { ST, STi } },
5635 { "fmul", { ST, STi } },
5636 { "fcom", { STi } },
5637 { "fcomp", { STi } },
5638 { "fsub", { ST, STi } },
5639 { "fsubr", { ST, STi } },
5640 { "fdiv", { ST, STi } },
5641 { "fdivr", { ST, STi } },
252b5132
RH		 5642 },
5643 /* d9 */
5644 {
ce518a5f
L		 5645 { "fld", { STi } },
5646 { "fxch", { STi } },
252b5132 5647 { FGRPd9_2 },
ce518a5f 5648 { "(bad)", { XX } },
252b5132
RH		 5649 { FGRPd9_4 },
5650 { FGRPd9_5 },
5651 { FGRPd9_6 },
5652 { FGRPd9_7 },
5653 },
5654 /* da */
5655 {
ce518a5f
L		 5656 { "fcmovb", { ST, STi } },
5657 { "fcmove", { ST, STi } },
5658 { "fcmovbe",{ ST, STi } },
5659 { "fcmovu", { ST, STi } },
5660 { "(bad)", { XX } },
252b5132 5661 { FGRPda_5 },
ce518a5f
L		 5662 { "(bad)", { XX } },
5663 { "(bad)", { XX } },
252b5132
RH		 5664 },
5665 /* db */
5666 {
ce518a5f
L		 5667 { "fcmovnb",{ ST, STi } },
5668 { "fcmovne",{ ST, STi } },
5669 { "fcmovnbe",{ ST, STi } },
5670 { "fcmovnu",{ ST, STi } },
252b5132 5671 { FGRPdb_4 },
ce518a5f
L		 5672 { "fucomi", { ST, STi } },
5673 { "fcomi", { ST, STi } },
5674 { "(bad)", { XX } },
252b5132
RH		 5675 },
5676 /* dc */
5677 {
ce518a5f
L		 5678 { "fadd", { STi, ST } },
5679 { "fmul", { STi, ST } },
5680 { "(bad)", { XX } },
5681 { "(bad)", { XX } },
0b1cf022 5682#if SYSV386_COMPAT
ce518a5f
L		 5683 { "fsub", { STi, ST } },
5684 { "fsubr", { STi, ST } },
5685 { "fdiv", { STi, ST } },
5686 { "fdivr", { STi, ST } },
252b5132 5687#else
ce518a5f
L		 5688 { "fsubr", { STi, ST } },
5689 { "fsub", { STi, ST } },
5690 { "fdivr", { STi, ST } },
5691 { "fdiv", { STi, ST } },
252b5132
RH		 5692#endif
5693 },
5694 /* dd */
5695 {
ce518a5f
L		 5696 { "ffree", { STi } },
5697 { "(bad)", { XX } },
5698 { "fst", { STi } },
5699 { "fstp", { STi } },
5700 { "fucom", { STi } },
5701 { "fucomp", { STi } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
252b5132
RH		 5704 },
5705 /* de */
5706 {
ce518a5f
L		 5707 { "faddp", { STi, ST } },
5708 { "fmulp", { STi, ST } },
5709 { "(bad)", { XX } },
252b5132 5710 { FGRPde_3 },
0b1cf022 5711#if SYSV386_COMPAT
ce518a5f
L		 5712 { "fsubp", { STi, ST } },
5713 { "fsubrp", { STi, ST } },
5714 { "fdivp", { STi, ST } },
5715 { "fdivrp", { STi, ST } },
252b5132 5716#else
ce518a5f
L		 5717 { "fsubrp", { STi, ST } },
5718 { "fsubp", { STi, ST } },
5719 { "fdivrp", { STi, ST } },
5720 { "fdivp", { STi, ST } },
252b5132
RH		 5721#endif
5722 },
5723 /* df */
5724 {
ce518a5f
L		 5725 { "ffreep", { STi } },
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
252b5132 5729 { FGRPdf_4 },
ce518a5f
L		 5730 { "fucomip", { ST, STi } },
5731 { "fcomip", { ST, STi } },
5732 { "(bad)", { XX } },
252b5132
RH		 5733 },
5734};
5735
252b5132
RH		 5736static char *fgrps[][8] = {
5737 /* d9_2 0 */
5738 {
5739 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5740 },
5741
5742 /* d9_4 1 */
5743 {
5744 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5745 },
5746
5747 /* d9_5 2 */
5748 {
5749 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5750 },
5751
5752 /* d9_6 3 */
5753 {
5754 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5755 },
5756
5757 /* d9_7 4 */
5758 {
5759 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5760 },
5761
5762 /* da_5 5 */
5763 {
5764 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5765 },
5766
5767 /* db_4 6 */
5768 {
5769 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5770 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5771 },
5772
5773 /* de_3 7 */
5774 {
5775 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5776 },
5777
5778 /* df_4 8 */
5779 {
5780 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5781 },
5782};
5783
b844680a
L		 5784static void
5785OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5786 int sizeflag ATTRIBUTE_UNUSED)
5787{
5788 /* Skip mod/rm byte. */
5789 MODRM_CHECK;
5790 codep++;
5791}
5792
252b5132 5793static void
26ca5450 5794dofloat (int sizeflag)
252b5132 5795{
2da11e11 5796 const struct dis386 *dp;
252b5132
RH		 5797 unsigned char floatop;
5798
5799 floatop = codep[-1];
5800
7967e09e 5801 if (modrm.mod != 3)
252b5132 5802 {
7967e09e 5803 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5804
5805 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5806 obufp = op_out[0];
6e50d963 5807 op_ad = 2;
1d9f512f 5808 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5809 return;
5810 }
6608db57 5811 /* Skip mod/rm byte. */
4bba6815 5812 MODRM_CHECK;
252b5132
RH		 5813 codep++;
5814
7967e09e 5815 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5816 if (dp->name == NULL)
5817 {
7967e09e 5818 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5819
6608db57 5820 /* Instruction fnstsw is only one with strange arg. */
252b5132 5821 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5822 strcpy (op_out[0], names16[0]);
252b5132
RH		 5823 }
5824 else
5825 {
5826 putop (dp->name, sizeflag);
5827
ce518a5f 5828 obufp = op_out[0];
6e50d963 5829 op_ad = 2;
ce518a5f
L		 5830 if (dp->op[0].rtn)
5831 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5832
ce518a5f 5833 obufp = op_out[1];
6e50d963 5834 op_ad = 1;
ce518a5f
L		 5835 if (dp->op[1].rtn)
5836 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5837 }
5838}
5839
252b5132 5840static void
26ca5450 5841OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5842{
422673a9 5843 oappend ("%st" + intel_syntax);
252b5132
RH		 5844}
5845
252b5132 5846static void
26ca5450 5847OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5848{
7967e09e 5849 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5850 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5851}
5852
6608db57 5853/* Capital letters in template are macros. */
6439fc28 5854static int
26ca5450 5855putop (const char *template, int sizeflag)
252b5132 5856{
2da11e11 5857 const char *p;
9306ca4a 5858 int alt = 0;
252b5132
RH		 5859
5860 for (p = template; *p; p++)
5861 {
5862 switch (*p)
5863 {
5864 default:
5865 *obufp++ = *p;
5866 break;
6439fc28
AM		 5867 case '{':
5868 alt = 0;
5869 if (intel_syntax)
6439fc28
AM		 5870 {
5871 while (*++p != '|')
7c52e0e8
L		 5872 if (*p == '}' || *p == '\0')
5873 abort ();
6439fc28 5874 }
9306ca4a
JB		 5875 /* Fall through. */
5876 case 'I':
5877 alt = 1;
5878 continue;
6439fc28
AM		 5879 case '|':
5880 while (*++p != '}')
5881 {
5882 if (*p == '\0')
5883 abort ();
5884 }
5885 break;
5886 case '}':
5887 break;
252b5132 5888 case 'A':
db6eb5be
AM		 5889 if (intel_syntax)
5890 break;
7967e09e 5891 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 5892 *obufp++ = 'b';
5893 break;
5894 case 'B':
db6eb5be
AM		 5895 if (intel_syntax)
5896 break;
252b5132
RH		 5897 if (sizeflag & SUFFIX_ALWAYS)
5898 *obufp++ = 'b';
252b5132 5899 break;
9306ca4a
JB		 5900 case 'C':
5901 if (intel_syntax && !alt)
5902 break;
5903 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
5904 {
5905 if (sizeflag & DFLAG)
5906 *obufp++ = intel_syntax ? 'd' : 'l';
5907 else
5908 *obufp++ = intel_syntax ? 'w' : 's';
5909 used_prefixes |= (prefixes & PREFIX_DATA);
5910 }
5911 break;
ed7841b3
JB		 5912 case 'D':
5913 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
5914 break;
161a04f6 5915 USED_REX (REX_W);
7967e09e 5916 if (modrm.mod == 3)
ed7841b3 5917 {
161a04f6 5918 if (rex & REX_W)
ed7841b3
JB		 5919 *obufp++ = 'q';
5920 else if (sizeflag & DFLAG)
5921 *obufp++ = intel_syntax ? 'd' : 'l';
5922 else
5923 *obufp++ = 'w';
5924 used_prefixes |= (prefixes & PREFIX_DATA);
5925 }
5926 else
5927 *obufp++ = 'w';
5928 break;
252b5132 5929 case 'E': /* For jcxz/jecxz */
cb712a9e 5930 if (address_mode == mode_64bit)
c1a64871
JH		 5931 {
5932 if (sizeflag & AFLAG)
5933 *obufp++ = 'r';
5934 else
5935 *obufp++ = 'e';
5936 }
5937 else
5938 if (sizeflag & AFLAG)
5939 *obufp++ = 'e';
3ffd33cf
AM		 5940 used_prefixes |= (prefixes & PREFIX_ADDR);
5941 break;
5942 case 'F':
db6eb5be
AM		 5943 if (intel_syntax)
5944 break;
e396998b 5945 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 5946 {
5947 if (sizeflag & AFLAG)
cb712a9e 5948 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 5949 else
cb712a9e 5950 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 5951 used_prefixes |= (prefixes & PREFIX_ADDR);
5952 }
252b5132 5953 break;
52fd6d94
JB		 5954 case 'G':
5955 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
5956 break;
161a04f6 5957 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 5958 *obufp++ = 'l';
5959 else
5960 *obufp++ = 'w';
161a04f6 5961 if (!(rex & REX_W))
52fd6d94
JB		 5962 used_prefixes |= (prefixes & PREFIX_DATA);
5963 break;
5dd0794d 5964 case 'H':
db6eb5be
AM		 5965 if (intel_syntax)
5966 break;
5dd0794d
AM		 5967 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
5968 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
5969 {
5970 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
5971 *obufp++ = ',';
5972 *obufp++ = 'p';
5973 if (prefixes & PREFIX_DS)
5974 *obufp++ = 't';
5975 else
5976 *obufp++ = 'n';
5977 }
5978 break;
9306ca4a
JB		 5979 case 'J':
5980 if (intel_syntax)
5981 break;
5982 *obufp++ = 'l';
5983 break;
42903f7f
L		 5984 case 'K':
5985 USED_REX (REX_W);
5986 if (rex & REX_W)
5987 *obufp++ = 'q';
5988 else
5989 *obufp++ = 'd';
5990 break;
6dd5059a
L		 5991 case 'Z':
5992 if (intel_syntax)
5993 break;
5994 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
5995 {
5996 *obufp++ = 'q';
5997 break;
5998 }
5999 /* Fall through. */
252b5132 6000 case 'L':
db6eb5be
AM		 6001 if (intel_syntax)
6002 break;
252b5132
RH		 6003 if (sizeflag & SUFFIX_ALWAYS)
6004 *obufp++ = 'l';
252b5132
RH		 6005 break;
6006 case 'N':
6007 if ((prefixes & PREFIX_FWAIT) == 0)
6008 *obufp++ = 'n';
7d421014
ILT		 6009 else
6010 used_prefixes |= PREFIX_FWAIT;
252b5132 6011 break;
52b15da3 6012 case 'O':
161a04f6
L		 6013 USED_REX (REX_W);
6014 if (rex & REX_W)
6439fc28 6015 *obufp++ = 'o';
a35ca55a
JB		 6016 else if (intel_syntax && (sizeflag & DFLAG))
6017 *obufp++ = 'q';
52b15da3
JH		 6018 else
6019 *obufp++ = 'd';
161a04f6 6020 if (!(rex & REX_W))
a35ca55a 6021 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6022 break;
6439fc28 6023 case 'T':
db6eb5be
AM		 6024 if (intel_syntax)
6025 break;
cb712a9e 6026 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6027 {
6028 *obufp++ = 'q';
6029 break;
6030 }
6608db57 6031 /* Fall through. */
252b5132 6032 case 'P':
db6eb5be
AM		 6033 if (intel_syntax)
6034 break;
252b5132 6035 if ((prefixes & PREFIX_DATA)
161a04f6 6036 || (rex & REX_W)
e396998b 6037 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6038 {
161a04f6
L		 6039 USED_REX (REX_W);
6040 if (rex & REX_W)
52b15da3 6041 *obufp++ = 'q';
c2419411 6042 else
52b15da3
JH		 6043 {
6044 if (sizeflag & DFLAG)
6045 *obufp++ = 'l';
6046 else
6047 *obufp++ = 'w';
52b15da3 6048 }
1a114b12 6049 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6050 }
6051 break;
6439fc28 6052 case 'U':
db6eb5be
AM		 6053 if (intel_syntax)
6054 break;
cb712a9e 6055 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 6056 {
7967e09e 6057 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 6058 *obufp++ = 'q';
6439fc28
AM		 6059 break;
6060 }
6608db57 6061 /* Fall through. */
252b5132 6062 case 'Q':
9306ca4a 6063 if (intel_syntax && !alt)
db6eb5be 6064 break;
161a04f6 6065 USED_REX (REX_W);
7967e09e 6066 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6067 {
161a04f6 6068 if (rex & REX_W)
52b15da3 6069 *obufp++ = 'q';
252b5132 6070 else
52b15da3
JH		 6071 {
6072 if (sizeflag & DFLAG)
9306ca4a 6073 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 6074 else
6075 *obufp++ = 'w';
52b15da3 6076 }
1a114b12 6077 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6078 }
6079 break;
6080 case 'R':
161a04f6
L		 6081 USED_REX (REX_W);
6082 if (rex & REX_W)
a35ca55a
JB		 6083 *obufp++ = 'q';
6084 else if (sizeflag & DFLAG)
c608c12e 6085 {
a35ca55a 6086 if (intel_syntax)
c608c12e 6087 *obufp++ = 'd';
c608c12e 6088 else
a35ca55a 6089 *obufp++ = 'l';
c608c12e 6090 }
252b5132 6091 else
a35ca55a
JB		 6092 *obufp++ = 'w';
6093 if (intel_syntax && !p[1]
161a04f6 6094 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 6095 *obufp++ = 'e';
161a04f6 6096 if (!(rex & REX_W))
52b15da3 6097 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6098 break;
1a114b12
JB		 6099 case 'V':
6100 if (intel_syntax)
6101 break;
cb712a9e 6102 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 6103 {
6104 if (sizeflag & SUFFIX_ALWAYS)
6105 *obufp++ = 'q';
6106 break;
6107 }
6108 /* Fall through. */
252b5132 6109 case 'S':
db6eb5be
AM		 6110 if (intel_syntax)
6111 break;
252b5132
RH		 6112 if (sizeflag & SUFFIX_ALWAYS)
6113 {
161a04f6 6114 if (rex & REX_W)
52b15da3 6115 *obufp++ = 'q';
252b5132 6116 else
52b15da3
JH		 6117 {
6118 if (sizeflag & DFLAG)
6119 *obufp++ = 'l';
6120 else
6121 *obufp++ = 'w';
6122 used_prefixes |= (prefixes & PREFIX_DATA);
6123 }
252b5132 6124 }
252b5132 6125 break;
041bd2e0
JH		 6126 case 'X':
6127 if (prefixes & PREFIX_DATA)
6128 *obufp++ = 'd';
6129 else
6130 *obufp++ = 's';
db6eb5be 6131 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 6132 break;
76f227a5 6133 case 'Y':
db6eb5be
AM		 6134 if (intel_syntax)
6135 break;
161a04f6 6136 if (rex & REX_W)
76f227a5 6137 {
161a04f6 6138 USED_REX (REX_W);
76f227a5
JH		 6139 *obufp++ = 'q';
6140 }
6141 break;
52b15da3 6142 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 6143 case 'W':
252b5132 6144 /* operand size flag for cwtl, cbtw */
161a04f6
L		 6145 USED_REX (REX_W);
6146 if (rex & REX_W)
a35ca55a
JB		 6147 {
6148 if (intel_syntax)
6149 *obufp++ = 'd';
6150 else
6151 *obufp++ = 'l';
6152 }
52b15da3 6153 else if (sizeflag & DFLAG)
252b5132
RH		 6154 *obufp++ = 'w';
6155 else
6156 *obufp++ = 'b';
161a04f6 6157 if (!(rex & REX_W))
52b15da3 6158 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6159 break;
6160 }
9306ca4a 6161 alt = 0;
252b5132
RH		 6162 }
6163 *obufp = 0;
6439fc28 6164 return 0;
252b5132
RH		 6165}
6166
6167static void
26ca5450 6168oappend (const char *s)
252b5132
RH		 6169{
6170 strcpy (obufp, s);
6171 obufp += strlen (s);
6172}
6173
6174static void
26ca5450 6175append_seg (void)
252b5132
RH		 6176{
6177 if (prefixes & PREFIX_CS)
7d421014 6178 {
7d421014 6179 used_prefixes |= PREFIX_CS;
d708bcba 6180 oappend ("%cs:" + intel_syntax);
7d421014 6181 }
252b5132 6182 if (prefixes & PREFIX_DS)
7d421014 6183 {
7d421014 6184 used_prefixes |= PREFIX_DS;
d708bcba 6185 oappend ("%ds:" + intel_syntax);
7d421014 6186 }
252b5132 6187 if (prefixes & PREFIX_SS)
7d421014 6188 {
7d421014 6189 used_prefixes |= PREFIX_SS;
d708bcba 6190 oappend ("%ss:" + intel_syntax);
7d421014 6191 }
252b5132 6192 if (prefixes & PREFIX_ES)
7d421014 6193 {
7d421014 6194 used_prefixes |= PREFIX_ES;
d708bcba 6195 oappend ("%es:" + intel_syntax);
7d421014 6196 }
252b5132 6197 if (prefixes & PREFIX_FS)
7d421014 6198 {
7d421014 6199 used_prefixes |= PREFIX_FS;
d708bcba 6200 oappend ("%fs:" + intel_syntax);
7d421014 6201 }
252b5132 6202 if (prefixes & PREFIX_GS)
7d421014 6203 {
7d421014 6204 used_prefixes |= PREFIX_GS;
d708bcba 6205 oappend ("%gs:" + intel_syntax);
7d421014 6206 }
252b5132
RH		 6207}
6208
6209static void
26ca5450 6210OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6211{
6212 if (!intel_syntax)
6213 oappend ("*");
6214 OP_E (bytemode, sizeflag);
6215}
6216
52b15da3 6217static void
26ca5450 6218print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6219{
cb712a9e 6220 if (address_mode == mode_64bit)
52b15da3
JH		 6221 {
6222 if (hex)
6223 {
6224 char tmp[30];
6225 int i;
6226 buf[0] = '0';
6227 buf[1] = 'x';
6228 sprintf_vma (tmp, disp);
6608db57 6229 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6230 strcpy (buf + 2, tmp + i);
6231 }
6232 else
6233 {
6234 bfd_signed_vma v = disp;
6235 char tmp[30];
6236 int i;
6237 if (v < 0)
6238 {
6239 *(buf++) = '-';
6240 v = -disp;
6608db57 6241 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6242 if (v < 0)
6243 {
6244 strcpy (buf, "9223372036854775808");
6245 return;
6246 }
6247 }
6248 if (!v)
6249 {
6250 strcpy (buf, "0");
6251 return;
6252 }
6253
6254 i = 0;
6255 tmp[29] = 0;
6256 while (v)
6257 {
6608db57 6258 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6259 v /= 10;
6260 i++;
6261 }
6262 strcpy (buf, tmp + 29 - i);
6263 }
6264 }
6265 else
6266 {
6267 if (hex)
6268 sprintf (buf, "0x%x", (unsigned int) disp);
6269 else
6270 sprintf (buf, "%d", (int) disp);
6271 }
6272}
6273
5d669648
L		 6274/* Put DISP in BUF as signed hex number. */
6275
6276static void
6277print_displacement (char *buf, bfd_vma disp)
6278{
6279 bfd_signed_vma val = disp;
6280 char tmp[30];
6281 int i, j = 0;
6282
6283 if (val < 0)
6284 {
6285 buf[j++] = '-';
6286 val = -disp;
6287
6288 /* Check for possible overflow. */
6289 if (val < 0)
6290 {
6291 switch (address_mode)
6292 {
6293 case mode_64bit:
6294 strcpy (buf + j, "0x8000000000000000");
6295 break;
6296 case mode_32bit:
6297 strcpy (buf + j, "0x80000000");
6298 break;
6299 case mode_16bit:
6300 strcpy (buf + j, "0x8000");
6301 break;
6302 }
6303 return;
6304 }
6305 }
6306
6307 buf[j++] = '0';
6308 buf[j++] = 'x';
6309
6310 sprintf_vma (tmp, val);
6311 for (i = 0; tmp[i] == '0'; i++)
6312 continue;
6313 if (tmp[i] == '\0')
6314 i--;
6315 strcpy (buf + j, tmp + i);
6316}
6317
3f31e633
JB		 6318static void
6319intel_operand_size (int bytemode, int sizeflag)
6320{
6321 switch (bytemode)
6322 {
6323 case b_mode:
42903f7f 6324 case dqb_mode:
3f31e633
JB		 6325 oappend ("BYTE PTR ");
6326 break;
6327 case w_mode:
6328 case dqw_mode:
6329 oappend ("WORD PTR ");
6330 break;
1a114b12 6331 case stack_v_mode:
cb712a9e 6332 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6333 {
6334 oappend ("QWORD PTR ");
6335 used_prefixes |= (prefixes & PREFIX_DATA);
6336 break;
6337 }
6338 /* FALLTHRU */
6339 case v_mode:
6340 case dq_mode:
161a04f6
L		 6341 USED_REX (REX_W);
6342 if (rex & REX_W)
3f31e633
JB		 6343 oappend ("QWORD PTR ");
6344 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6345 oappend ("DWORD PTR ");
6346 else
6347 oappend ("WORD PTR ");
6348 used_prefixes |= (prefixes & PREFIX_DATA);
6349 break;
52fd6d94 6350 case z_mode:
161a04f6 6351 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6352 *obufp++ = 'D';
6353 oappend ("WORD PTR ");
161a04f6 6354 if (!(rex & REX_W))
52fd6d94
JB		 6355 used_prefixes |= (prefixes & PREFIX_DATA);
6356 break;
3f31e633 6357 case d_mode:
42903f7f 6358 case dqd_mode:
3f31e633
JB		 6359 oappend ("DWORD PTR ");
6360 break;
6361 case q_mode:
6362 oappend ("QWORD PTR ");
6363 break;
6364 case m_mode:
cb712a9e 6365 if (address_mode == mode_64bit)
3f31e633
JB		 6366 oappend ("QWORD PTR ");
6367 else
6368 oappend ("DWORD PTR ");
6369 break;
6370 case f_mode:
6371 if (sizeflag & DFLAG)
6372 oappend ("FWORD PTR ");
6373 else
6374 oappend ("DWORD PTR ");
6375 used_prefixes |= (prefixes & PREFIX_DATA);
6376 break;
6377 case t_mode:
6378 oappend ("TBYTE PTR ");
6379 break;
6380 case x_mode:
6381 oappend ("XMMWORD PTR ");
6382 break;
fb9c77c7
L		 6383 case o_mode:
6384 oappend ("OWORD PTR ");
6385 break;
3f31e633
JB		 6386 default:
6387 break;
6388 }
6389}
6390
252b5132 6391static void
85f10a01 6392OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6393{
52b15da3
JH		 6394 bfd_vma disp;
6395 int add = 0;
6396 int riprel = 0;
161a04f6
L		 6397 USED_REX (REX_B);
6398 if (rex & REX_B)
52b15da3 6399 add += 8;
252b5132 6400
6608db57 6401 /* Skip mod/rm byte. */
4bba6815 6402 MODRM_CHECK;
252b5132
RH		 6403 codep++;
6404
7967e09e 6405 if (modrm.mod == 3)
252b5132
RH		 6406 {
6407 switch (bytemode)
6408 {
6409 case b_mode:
52b15da3
JH		 6410 USED_REX (0);
6411 if (rex)
7967e09e 6412 oappend (names8rex[modrm.rm + add]);
52b15da3 6413 else
7967e09e 6414 oappend (names8[modrm.rm + add]);
252b5132
RH		 6415 break;
6416 case w_mode:
7967e09e 6417 oappend (names16[modrm.rm + add]);
252b5132 6418 break;
2da11e11 6419 case d_mode:
7967e09e 6420 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6421 break;
6422 case q_mode:
7967e09e 6423 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6424 break;
6425 case m_mode:
cb712a9e 6426 if (address_mode == mode_64bit)
7967e09e 6427 oappend (names64[modrm.rm + add]);
52b15da3 6428 else
7967e09e 6429 oappend (names32[modrm.rm + add]);
2da11e11 6430 break;
1a114b12 6431 case stack_v_mode:
cb712a9e 6432 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6433 {
7967e09e 6434 oappend (names64[modrm.rm + add]);
003519a7 6435 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6436 break;
003519a7 6437 }
1a114b12
JB		 6438 bytemode = v_mode;
6439 /* FALLTHRU */
252b5132 6440 case v_mode:
db6eb5be 6441 case dq_mode:
42903f7f
L		 6442 case dqb_mode:
6443 case dqd_mode:
9306ca4a 6444 case dqw_mode:
161a04f6
L		 6445 USED_REX (REX_W);
6446 if (rex & REX_W)
7967e09e 6447 oappend (names64[modrm.rm + add]);
9306ca4a 6448 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6449 oappend (names32[modrm.rm + add]);
252b5132 6450 else
7967e09e 6451 oappend (names16[modrm.rm + add]);
7d421014 6452 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6453 break;
2da11e11 6454 case 0:
c608c12e 6455 break;
252b5132 6456 default:
c608c12e 6457 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6458 break;
6459 }
6460 return;
6461 }
6462
6463 disp = 0;
3f31e633
JB		 6464 if (intel_syntax)
6465 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6466 append_seg ();
6467
5d669648 6468 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6469 {
5d669648
L		 6470 /* 32/64 bit address mode */
6471 int havedisp;
252b5132
RH		 6472 int havesib;
6473 int havebase;
0f7da397 6474 int haveindex;
20afcfb7 6475 int needindex;
252b5132
RH		 6476 int base;
6477 int index = 0;
6478 int scale = 0;
6479
6480 havesib = 0;
6481 havebase = 1;
0f7da397 6482 haveindex = 0;
7967e09e 6483 base = modrm.rm;
252b5132
RH		 6484
6485 if (base == 4)
6486 {
6487 havesib = 1;
6488 FETCH_DATA (the_info, codep + 1);
252b5132 6489 index = (*codep >> 3) & 7;
db51cc60 6490 scale = (*codep >> 6) & 3;
252b5132 6491 base = *codep & 7;
161a04f6
L		 6492 USED_REX (REX_X);
6493 if (rex & REX_X)
52b15da3 6494 index += 8;
0f7da397 6495 haveindex = index != 4;
252b5132
RH		 6496 codep++;
6497 }
2888cb7a 6498 base += add;
252b5132 6499
85f10a01
MM		 6500 /* If we have a DREX byte, skip it now
6501 (it has already been handled) */
6502 if (has_drex)
6503 {
6504 FETCH_DATA (the_info, codep + 1);
6505 codep++;
6506 }
6507
7967e09e 6508 switch (modrm.mod)
252b5132
RH		 6509 {
6510 case 0:
52b15da3 6511 if ((base & 7) == 5)
252b5132
RH		 6512 {
6513 havebase = 0;
cb712a9e 6514 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6515 riprel = 1;
6516 disp = get32s ();
252b5132
RH		 6517 }
6518 break;
6519 case 1:
6520 FETCH_DATA (the_info, codep + 1);
6521 disp = *codep++;
6522 if ((disp & 0x80) != 0)
6523 disp -= 0x100;
6524 break;
6525 case 2:
52b15da3 6526 disp = get32s ();
252b5132
RH		 6527 break;
6528 }
6529
20afcfb7
L		 6530 /* In 32bit mode, we need index register to tell [offset] from
6531 [eiz*1 + offset]. */
6532 needindex = (havesib
6533 && !havebase
6534 && !haveindex
6535 && address_mode == mode_32bit);
6536 havedisp = (havebase
6537 || needindex
6538 || (havesib && (haveindex || scale != 0)));
5d669648 6539
252b5132 6540 if (!intel_syntax)
7967e09e 6541 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6542 {
5d669648
L		 6543 if (havedisp || riprel)
6544 print_displacement (scratchbuf, disp);
6545 else
6546 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6547 oappend (scratchbuf);
52b15da3
JH		 6548 if (riprel)
6549 {
6550 set_op (disp, 1);
87767711 6551 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 6552 }
db6eb5be 6553 }
2da11e11 6554
87767711
JB		 6555 if (havebase || haveindex || riprel)
6556 used_prefixes |= PREFIX_ADDR;
6557
5d669648 6558 if (havedisp || (intel_syntax && riprel))
252b5132 6559 {
252b5132 6560 *obufp++ = open_char;
52b15da3 6561 if (intel_syntax && riprel)
185b1163
L		 6562 {
6563 set_op (disp, 1);
87767711 6564 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 6565 }
db6eb5be 6566 *obufp = '\0';
252b5132 6567 if (havebase)
cb712a9e 6568 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6569 ? names64[base] : names32[base]);
252b5132
RH		 6570 if (havesib)
6571 {
db51cc60
L		 6572 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6573 print index to tell base + index from base. */
6574 if (scale != 0
20afcfb7 6575 || needindex
db51cc60
L		 6576 || haveindex
6577 || (havebase && base != ESP_REG_NUM))
252b5132 6578 {
9306ca4a 6579 if (!intel_syntax || havebase)
db6eb5be 6580 {
9306ca4a
JB		 6581 *obufp++ = separator_char;
6582 *obufp = '\0';
db6eb5be 6583 }
db51cc60
L		 6584 if (haveindex)
6585 oappend (address_mode == mode_64bit
6586 && (sizeflag & AFLAG)
6587 ? names64[index] : names32[index]);
6588 else
6589 oappend (address_mode == mode_64bit
6590 && (sizeflag & AFLAG)
6591 ? index64 : index32);
6592
db6eb5be
AM		 6593 *obufp++ = scale_char;
6594 *obufp = '\0';
6595 sprintf (scratchbuf, "%d", 1 << scale);
6596 oappend (scratchbuf);
6597 }
252b5132 6598 }
185b1163
L		 6599 if (intel_syntax
6600 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6601 {
db51cc60 6602 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6603 {
6604 *obufp++ = '+';
6605 *obufp = '\0';
6606 }
7967e09e 6607 else if (modrm.mod != 1)
3d456fa1
JB		 6608 {
6609 *obufp++ = '-';
6610 *obufp = '\0';
6611 disp = - (bfd_signed_vma) disp;
6612 }
6613
db51cc60
L		 6614 if (havedisp)
6615 print_displacement (scratchbuf, disp);
6616 else
6617 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6618 oappend (scratchbuf);
6619 }
252b5132
RH		 6620
6621 *obufp++ = close_char;
db6eb5be 6622 *obufp = '\0';
252b5132
RH		 6623 }
6624 else if (intel_syntax)
db6eb5be 6625 {
7967e09e 6626 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6627 {
252b5132
RH		 6628 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6629 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6630 ;
6631 else
6632 {
d708bcba 6633 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6634 oappend (":");
6635 }
52b15da3 6636 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6637 oappend (scratchbuf);
6638 }
6639 }
252b5132
RH		 6640 }
6641 else
6642 { /* 16 bit address mode */
7967e09e 6643 switch (modrm.mod)
252b5132
RH		 6644 {
6645 case 0:
7967e09e 6646 if (modrm.rm == 6)
252b5132
RH		 6647 {
6648 disp = get16 ();
6649 if ((disp & 0x8000) != 0)
6650 disp -= 0x10000;
6651 }
6652 break;
6653 case 1:
6654 FETCH_DATA (the_info, codep + 1);
6655 disp = *codep++;
6656 if ((disp & 0x80) != 0)
6657 disp -= 0x100;
6658 break;
6659 case 2:
6660 disp = get16 ();
6661 if ((disp & 0x8000) != 0)
6662 disp -= 0x10000;
6663 break;
6664 }
6665
6666 if (!intel_syntax)
7967e09e 6667 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6668 {
5d669648 6669 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6670 oappend (scratchbuf);
6671 }
252b5132 6672
7967e09e 6673 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6674 {
6675 *obufp++ = open_char;
db6eb5be 6676 *obufp = '\0';
7967e09e 6677 oappend (index16[modrm.rm]);
5d669648
L		 6678 if (intel_syntax
6679 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6680 {
5d669648 6681 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6682 {
6683 *obufp++ = '+';
6684 *obufp = '\0';
6685 }
7967e09e 6686 else if (modrm.mod != 1)
3d456fa1
JB		 6687 {
6688 *obufp++ = '-';
6689 *obufp = '\0';
6690 disp = - (bfd_signed_vma) disp;
6691 }
6692
5d669648 6693 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6694 oappend (scratchbuf);
6695 }
6696
db6eb5be
AM		 6697 *obufp++ = close_char;
6698 *obufp = '\0';
252b5132 6699 }
3d456fa1
JB		 6700 else if (intel_syntax)
6701 {
6702 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6703 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6704 ;
6705 else
6706 {
6707 oappend (names_seg[ds_reg - es_reg]);
6708 oappend (":");
6709 }
6710 print_operand_value (scratchbuf, 1, disp & 0xffff);
6711 oappend (scratchbuf);
6712 }
252b5132
RH		 6713 }
6714}
6715
85f10a01
MM		 6716static void
6717OP_E (int bytemode, int sizeflag)
6718{
6719 OP_E_extended (bytemode, sizeflag, 0);
6720}
6721
6722
252b5132 6723static void
26ca5450 6724OP_G (int bytemode, int sizeflag)
252b5132 6725{
52b15da3 6726 int add = 0;
161a04f6
L		 6727 USED_REX (REX_R);
6728 if (rex & REX_R)
52b15da3 6729 add += 8;
252b5132
RH		 6730 switch (bytemode)
6731 {
6732 case b_mode:
52b15da3
JH		 6733 USED_REX (0);
6734 if (rex)
7967e09e 6735 oappend (names8rex[modrm.reg + add]);
52b15da3 6736 else
7967e09e 6737 oappend (names8[modrm.reg + add]);
252b5132
RH		 6738 break;
6739 case w_mode:
7967e09e 6740 oappend (names16[modrm.reg + add]);
252b5132
RH		 6741 break;
6742 case d_mode:
7967e09e 6743 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6744 break;
6745 case q_mode:
7967e09e 6746 oappend (names64[modrm.reg + add]);
252b5132
RH		 6747 break;
6748 case v_mode:
9306ca4a 6749 case dq_mode:
42903f7f
L		 6750 case dqb_mode:
6751 case dqd_mode:
9306ca4a 6752 case dqw_mode:
161a04f6
L		 6753 USED_REX (REX_W);
6754 if (rex & REX_W)
7967e09e 6755 oappend (names64[modrm.reg + add]);
9306ca4a 6756 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6757 oappend (names32[modrm.reg + add]);
252b5132 6758 else
7967e09e 6759 oappend (names16[modrm.reg + add]);
7d421014 6760 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6761 break;
90700ea2 6762 case m_mode:
cb712a9e 6763 if (address_mode == mode_64bit)
7967e09e 6764 oappend (names64[modrm.reg + add]);
90700ea2 6765 else
7967e09e 6766 oappend (names32[modrm.reg + add]);
90700ea2 6767 break;
252b5132
RH		 6768 default:
6769 oappend (INTERNAL_DISASSEMBLER_ERROR);
6770 break;
6771 }
6772}
6773
52b15da3 6774static bfd_vma
26ca5450 6775get64 (void)
52b15da3 6776{
5dd0794d 6777 bfd_vma x;
52b15da3 6778#ifdef BFD64
5dd0794d
AM		 6779 unsigned int a;
6780 unsigned int b;
6781
52b15da3
JH		 6782 FETCH_DATA (the_info, codep + 8);
6783 a = *codep++ & 0xff;
6784 a |= (*codep++ & 0xff) << 8;
6785 a |= (*codep++ & 0xff) << 16;
6786 a |= (*codep++ & 0xff) << 24;
5dd0794d 6787 b = *codep++ & 0xff;
52b15da3
JH		 6788 b |= (*codep++ & 0xff) << 8;
6789 b |= (*codep++ & 0xff) << 16;
6790 b |= (*codep++ & 0xff) << 24;
6791 x = a + ((bfd_vma) b << 32);
6792#else
6608db57 6793 abort ();
5dd0794d 6794 x = 0;
52b15da3
JH		 6795#endif
6796 return x;
6797}
6798
6799static bfd_signed_vma
26ca5450 6800get32 (void)
252b5132 6801{
52b15da3 6802 bfd_signed_vma x = 0;
252b5132
RH		 6803
6804 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6805 x = *codep++ & (bfd_signed_vma) 0xff;
6806 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6807 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6808 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6809 return x;
6810}
6811
6812static bfd_signed_vma
26ca5450 6813get32s (void)
52b15da3
JH		 6814{
6815 bfd_signed_vma x = 0;
6816
6817 FETCH_DATA (the_info, codep + 4);
6818 x = *codep++ & (bfd_signed_vma) 0xff;
6819 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6820 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6821 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6822
6823 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6824
252b5132
RH		 6825 return x;
6826}
6827
6828static int
26ca5450 6829get16 (void)
252b5132
RH		 6830{
6831 int x = 0;
6832
6833 FETCH_DATA (the_info, codep + 2);
6834 x = *codep++ & 0xff;
6835 x |= (*codep++ & 0xff) << 8;
6836 return x;
6837}
6838
6839static void
26ca5450 6840set_op (bfd_vma op, int riprel)
252b5132
RH		 6841{
6842 op_index[op_ad] = op_ad;
cb712a9e 6843 if (address_mode == mode_64bit)
7081ff04
AJ		 6844 {
6845 op_address[op_ad] = op;
6846 op_riprel[op_ad] = riprel;
6847 }
6848 else
6849 {
6850 /* Mask to get a 32-bit address. */
6851 op_address[op_ad] = op & 0xffffffff;
6852 op_riprel[op_ad] = riprel & 0xffffffff;
6853 }
252b5132
RH		 6854}
6855
6856static void
26ca5450 6857OP_REG (int code, int sizeflag)
252b5132 6858{
2da11e11 6859 const char *s;
52b15da3 6860 int add = 0;
161a04f6
L		 6861 USED_REX (REX_B);
6862 if (rex & REX_B)
52b15da3
JH		 6863 add = 8;
6864
6865 switch (code)
6866 {
52b15da3
JH		 6867 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6868 case sp_reg: case bp_reg: case si_reg: case di_reg:
6869 s = names16[code - ax_reg + add];
6870 break;
6871 case es_reg: case ss_reg: case cs_reg:
6872 case ds_reg: case fs_reg: case gs_reg:
6873 s = names_seg[code - es_reg + add];
6874 break;
6875 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6876 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6877 USED_REX (0);
6878 if (rex)
6879 s = names8rex[code - al_reg + add];
6880 else
6881 s = names8[code - al_reg];
6882 break;
6439fc28
AM		 6883 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
6884 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 6885 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6886 {
6887 s = names64[code - rAX_reg + add];
6888 break;
6889 }
6890 code += eAX_reg - rAX_reg;
6608db57 6891 /* Fall through. */
52b15da3
JH		 6892 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6893 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6894 USED_REX (REX_W);
6895 if (rex & REX_W)
52b15da3
JH		 6896 s = names64[code - eAX_reg + add];
6897 else if (sizeflag & DFLAG)
6898 s = names32[code - eAX_reg + add];
6899 else
6900 s = names16[code - eAX_reg + add];
6901 used_prefixes |= (prefixes & PREFIX_DATA);
6902 break;
52b15da3
JH		 6903 default:
6904 s = INTERNAL_DISASSEMBLER_ERROR;
6905 break;
6906 }
6907 oappend (s);
6908}
6909
6910static void
26ca5450 6911OP_IMREG (int code, int sizeflag)
52b15da3
JH		 6912{
6913 const char *s;
252b5132
RH		 6914
6915 switch (code)
6916 {
6917 case indir_dx_reg:
d708bcba 6918 if (intel_syntax)
52fd6d94 6919 s = "dx";
d708bcba 6920 else
db6eb5be 6921 s = "(%dx)";
252b5132
RH		 6922 break;
6923 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6924 case sp_reg: case bp_reg: case si_reg: case di_reg:
6925 s = names16[code - ax_reg];
6926 break;
6927 case es_reg: case ss_reg: case cs_reg:
6928 case ds_reg: case fs_reg: case gs_reg:
6929 s = names_seg[code - es_reg];
6930 break;
6931 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6932 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 6933 USED_REX (0);
6934 if (rex)
6935 s = names8rex[code - al_reg];
6936 else
6937 s = names8[code - al_reg];
252b5132
RH		 6938 break;
6939 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6940 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6941 USED_REX (REX_W);
6942 if (rex & REX_W)
52b15da3
JH		 6943 s = names64[code - eAX_reg];
6944 else if (sizeflag & DFLAG)
252b5132
RH		 6945 s = names32[code - eAX_reg];
6946 else
6947 s = names16[code - eAX_reg];
7d421014 6948 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6949 break;
52fd6d94 6950 case z_mode_ax_reg:
161a04f6 6951 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6952 s = *names32;
6953 else
6954 s = *names16;
161a04f6 6955 if (!(rex & REX_W))
52fd6d94
JB		 6956 used_prefixes |= (prefixes & PREFIX_DATA);
6957 break;
252b5132
RH		 6958 default:
6959 s = INTERNAL_DISASSEMBLER_ERROR;
6960 break;
6961 }
6962 oappend (s);
6963}
6964
6965static void
26ca5450 6966OP_I (int bytemode, int sizeflag)
252b5132 6967{
52b15da3
JH		 6968 bfd_signed_vma op;
6969 bfd_signed_vma mask = -1;
252b5132
RH		 6970
6971 switch (bytemode)
6972 {
6973 case b_mode:
6974 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 6975 op = *codep++;
6976 mask = 0xff;
6977 break;
6978 case q_mode:
cb712a9e 6979 if (address_mode == mode_64bit)
6439fc28
AM		 6980 {
6981 op = get32s ();
6982 break;
6983 }
6608db57 6984 /* Fall through. */
252b5132 6985 case v_mode:
161a04f6
L		 6986 USED_REX (REX_W);
6987 if (rex & REX_W)
52b15da3
JH		 6988 op = get32s ();
6989 else if (sizeflag & DFLAG)
6990 {
6991 op = get32 ();
6992 mask = 0xffffffff;
6993 }
252b5132 6994 else
52b15da3
JH		 6995 {
6996 op = get16 ();
6997 mask = 0xfffff;
6998 }
7d421014 6999 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7000 break;
7001 case w_mode:
52b15da3 7002 mask = 0xfffff;
252b5132
RH		 7003 op = get16 ();
7004 break;
9306ca4a
JB		 7005 case const_1_mode:
7006 if (intel_syntax)
7007 oappend ("1");
7008 return;
252b5132
RH		 7009 default:
7010 oappend (INTERNAL_DISASSEMBLER_ERROR);
7011 return;
7012 }
7013
52b15da3
JH		 7014 op &= mask;
7015 scratchbuf[0] = '$';
d708bcba
AM		 7016 print_operand_value (scratchbuf + 1, 1, op);
7017 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 7018 scratchbuf[0] = '\0';
7019}
7020
7021static void
26ca5450 7022OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 7023{
7024 bfd_signed_vma op;
7025 bfd_signed_vma mask = -1;
7026
cb712a9e 7027 if (address_mode != mode_64bit)
6439fc28
AM		 7028 {
7029 OP_I (bytemode, sizeflag);
7030 return;
7031 }
7032
52b15da3
JH		 7033 switch (bytemode)
7034 {
7035 case b_mode:
7036 FETCH_DATA (the_info, codep + 1);
7037 op = *codep++;
7038 mask = 0xff;
7039 break;
7040 case v_mode:
161a04f6
L		 7041 USED_REX (REX_W);
7042 if (rex & REX_W)
52b15da3
JH		 7043 op = get64 ();
7044 else if (sizeflag & DFLAG)
7045 {
7046 op = get32 ();
7047 mask = 0xffffffff;
7048 }
7049 else
7050 {
7051 op = get16 ();
7052 mask = 0xfffff;
7053 }
7054 used_prefixes |= (prefixes & PREFIX_DATA);
7055 break;
7056 case w_mode:
7057 mask = 0xfffff;
7058 op = get16 ();
7059 break;
7060 default:
7061 oappend (INTERNAL_DISASSEMBLER_ERROR);
7062 return;
7063 }
7064
7065 op &= mask;
7066 scratchbuf[0] = '$';
d708bcba
AM		 7067 print_operand_value (scratchbuf + 1, 1, op);
7068 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7069 scratchbuf[0] = '\0';
7070}
7071
7072static void
26ca5450 7073OP_sI (int bytemode, int sizeflag)
252b5132 7074{
52b15da3
JH		 7075 bfd_signed_vma op;
7076 bfd_signed_vma mask = -1;
252b5132
RH		 7077
7078 switch (bytemode)
7079 {
7080 case b_mode:
7081 FETCH_DATA (the_info, codep + 1);
7082 op = *codep++;
7083 if ((op & 0x80) != 0)
7084 op -= 0x100;
52b15da3 7085 mask = 0xffffffff;
252b5132
RH		 7086 break;
7087 case v_mode:
161a04f6
L		 7088 USED_REX (REX_W);
7089 if (rex & REX_W)
52b15da3
JH		 7090 op = get32s ();
7091 else if (sizeflag & DFLAG)
7092 {
7093 op = get32s ();
7094 mask = 0xffffffff;
7095 }
252b5132
RH		 7096 else
7097 {
52b15da3 7098 mask = 0xffffffff;
6608db57 7099 op = get16 ();
252b5132
RH		 7100 if ((op & 0x8000) != 0)
7101 op -= 0x10000;
7102 }
7d421014 7103 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7104 break;
7105 case w_mode:
7106 op = get16 ();
52b15da3 7107 mask = 0xffffffff;
252b5132
RH		 7108 if ((op & 0x8000) != 0)
7109 op -= 0x10000;
7110 break;
7111 default:
7112 oappend (INTERNAL_DISASSEMBLER_ERROR);
7113 return;
7114 }
52b15da3
JH		 7115
7116 scratchbuf[0] = '$';
7117 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 7118 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7119}
7120
7121static void
26ca5450 7122OP_J (int bytemode, int sizeflag)
252b5132 7123{
52b15da3 7124 bfd_vma disp;
7081ff04 7125 bfd_vma mask = -1;
65ca155d 7126 bfd_vma segment = 0;
252b5132
RH		 7127
7128 switch (bytemode)
7129 {
7130 case b_mode:
7131 FETCH_DATA (the_info, codep + 1);
7132 disp = *codep++;
7133 if ((disp & 0x80) != 0)
7134 disp -= 0x100;
7135 break;
7136 case v_mode:
161a04f6 7137 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 7138 disp = get32s ();
252b5132
RH		 7139 else
7140 {
7141 disp = get16 ();
206717e8
L		 7142 if ((disp & 0x8000) != 0)
7143 disp -= 0x10000;
65ca155d
L		 7144 /* In 16bit mode, address is wrapped around at 64k within
7145 the same segment. Otherwise, a data16 prefix on a jump
7146 instruction means that the pc is masked to 16 bits after
7147 the displacement is added! */
7148 mask = 0xffff;
7149 if ((prefixes & PREFIX_DATA) == 0)
7150 segment = ((start_pc + codep - start_codep)
7151 & ~((bfd_vma) 0xffff));
252b5132 7152 }
d807a492 7153 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7154 break;
7155 default:
7156 oappend (INTERNAL_DISASSEMBLER_ERROR);
7157 return;
7158 }
65ca155d 7159 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 7160 set_op (disp, 0);
7161 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7162 oappend (scratchbuf);
7163}
7164
252b5132 7165static void
ed7841b3 7166OP_SEG (int bytemode, int sizeflag)
252b5132 7167{
ed7841b3 7168 if (bytemode == w_mode)
7967e09e 7169 oappend (names_seg[modrm.reg]);
ed7841b3 7170 else
7967e09e 7171 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7172}
7173
7174static void
26ca5450 7175OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7176{
7177 int seg, offset;
7178
c608c12e 7179 if (sizeflag & DFLAG)
252b5132 7180 {
c608c12e
AM		 7181 offset = get32 ();
7182 seg = get16 ();
252b5132 7183 }
c608c12e
AM		 7184 else
7185 {
7186 offset = get16 ();
7187 seg = get16 ();
7188 }
7d421014 7189 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7190 if (intel_syntax)
3f31e633 7191 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7192 else
7193 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7194 oappend (scratchbuf);
252b5132
RH		 7195}
7196
252b5132 7197static void
3f31e633 7198OP_OFF (int bytemode, int sizeflag)
252b5132 7199{
52b15da3 7200 bfd_vma off;
252b5132 7201
3f31e633
JB		 7202 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7203 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7204 append_seg ();
7205
cb712a9e 7206 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7207 off = get32 ();
7208 else
7209 off = get16 ();
7210
7211 if (intel_syntax)
7212 {
7213 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7214 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7215 {
d708bcba 7216 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7217 oappend (":");
7218 }
7219 }
52b15da3
JH		 7220 print_operand_value (scratchbuf, 1, off);
7221 oappend (scratchbuf);
7222}
6439fc28 7223
52b15da3 7224static void
3f31e633 7225OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7226{
7227 bfd_vma off;
7228
539e75ad
L		 7229 if (address_mode != mode_64bit
7230 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7231 {
7232 OP_OFF (bytemode, sizeflag);
7233 return;
7234 }
7235
3f31e633
JB		 7236 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7237 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7238 append_seg ();
7239
6608db57 7240 off = get64 ();
52b15da3
JH		 7241
7242 if (intel_syntax)
7243 {
7244 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7245 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7246 {
d708bcba 7247 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7248 oappend (":");
7249 }
7250 }
7251 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7252 oappend (scratchbuf);
7253}
7254
7255static void
26ca5450 7256ptr_reg (int code, int sizeflag)
252b5132 7257{
2da11e11 7258 const char *s;
d708bcba 7259
1d9f512f 7260 *obufp++ = open_char;
20f0a1fc 7261 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7262 if (address_mode == mode_64bit)
c1a64871
JH		 7263 {
7264 if (!(sizeflag & AFLAG))
db6eb5be 7265 s = names32[code - eAX_reg];
c1a64871 7266 else
db6eb5be 7267 s = names64[code - eAX_reg];
c1a64871 7268 }
52b15da3 7269 else if (sizeflag & AFLAG)
252b5132
RH		 7270 s = names32[code - eAX_reg];
7271 else
7272 s = names16[code - eAX_reg];
7273 oappend (s);
1d9f512f
AM		 7274 *obufp++ = close_char;
7275 *obufp = 0;
252b5132
RH		 7276}
7277
7278static void
26ca5450 7279OP_ESreg (int code, int sizeflag)
252b5132 7280{
9306ca4a 7281 if (intel_syntax)
52fd6d94
JB		 7282 {
7283 switch (codep[-1])
7284 {
7285 case 0x6d: /* insw/insl */
7286 intel_operand_size (z_mode, sizeflag);
7287 break;
7288 case 0xa5: /* movsw/movsl/movsq */
7289 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7290 case 0xab: /* stosw/stosl */
7291 case 0xaf: /* scasw/scasl */
7292 intel_operand_size (v_mode, sizeflag);
7293 break;
7294 default:
7295 intel_operand_size (b_mode, sizeflag);
7296 }
7297 }
d708bcba 7298 oappend ("%es:" + intel_syntax);
252b5132
RH		 7299 ptr_reg (code, sizeflag);
7300}
7301
7302static void
26ca5450 7303OP_DSreg (int code, int sizeflag)
252b5132 7304{
9306ca4a 7305 if (intel_syntax)
52fd6d94
JB		 7306 {
7307 switch (codep[-1])
7308 {
7309 case 0x6f: /* outsw/outsl */
7310 intel_operand_size (z_mode, sizeflag);
7311 break;
7312 case 0xa5: /* movsw/movsl/movsq */
7313 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7314 case 0xad: /* lodsw/lodsl/lodsq */
7315 intel_operand_size (v_mode, sizeflag);
7316 break;
7317 default:
7318 intel_operand_size (b_mode, sizeflag);
7319 }
7320 }
252b5132
RH		 7321 if ((prefixes
7322 & (PREFIX_CS
7323 | PREFIX_DS
7324 | PREFIX_SS
7325 | PREFIX_ES
7326 | PREFIX_FS
7327 | PREFIX_GS)) == 0)
7328 prefixes |= PREFIX_DS;
6608db57 7329 append_seg ();
252b5132
RH		 7330 ptr_reg (code, sizeflag);
7331}
7332
252b5132 7333static void
26ca5450 7334OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7335{
52b15da3 7336 int add = 0;
161a04f6 7337 if (rex & REX_R)
c4a530c5 7338 {
161a04f6 7339 USED_REX (REX_R);
c4a530c5
JB		 7340 add = 8;
7341 }
cb712a9e 7342 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7343 {
b844680a 7344 lock_prefix = NULL;
c4a530c5
JB		 7345 used_prefixes |= PREFIX_LOCK;
7346 add = 8;
7347 }
7967e09e 7348 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7349 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7350}
7351
252b5132 7352static void
26ca5450 7353OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7354{
52b15da3 7355 int add = 0;
161a04f6
L		 7356 USED_REX (REX_R);
7357 if (rex & REX_R)
52b15da3 7358 add = 8;
d708bcba 7359 if (intel_syntax)
7967e09e 7360 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7361 else
7967e09e 7362 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7363 oappend (scratchbuf);
7364}
7365
252b5132 7366static void
26ca5450 7367OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7368{
7967e09e 7369 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7370 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7371}
7372
7373static void
6f74c397 7374OP_R (int bytemode, int sizeflag)
252b5132 7375{
7967e09e 7376 if (modrm.mod == 3)
2da11e11
AM		 7377 OP_E (bytemode, sizeflag);
7378 else
6608db57 7379 BadOp ();
252b5132
RH		 7380}
7381
7382static void
26ca5450 7383OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7384{
041bd2e0
JH		 7385 used_prefixes |= (prefixes & PREFIX_DATA);
7386 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 7387 {
7388 int add = 0;
161a04f6
L		 7389 USED_REX (REX_R);
7390 if (rex & REX_R)
20f0a1fc 7391 add = 8;
7967e09e 7392 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7393 }
041bd2e0 7394 else
7967e09e 7395 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7396 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7397}
7398
c608c12e 7399static void
26ca5450 7400OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7401{
041bd2e0 7402 int add = 0;
161a04f6
L		 7403 USED_REX (REX_R);
7404 if (rex & REX_R)
041bd2e0 7405 add = 8;
7967e09e 7406 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7407 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7408}
7409
252b5132 7410static void
26ca5450 7411OP_EM (int bytemode, int sizeflag)
252b5132 7412{
7967e09e 7413 if (modrm.mod != 3)
252b5132 7414 {
9306ca4a
JB		 7415 if (intel_syntax && bytemode == v_mode)
7416 {
7417 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7418 used_prefixes |= (prefixes & PREFIX_DATA);
7419 }
252b5132
RH		 7420 OP_E (bytemode, sizeflag);
7421 return;
7422 }
7423
6608db57 7424 /* Skip mod/rm byte. */
4bba6815 7425 MODRM_CHECK;
252b5132 7426 codep++;
041bd2e0
JH		 7427 used_prefixes |= (prefixes & PREFIX_DATA);
7428 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 7429 {
7430 int add = 0;
7431
161a04f6
L		 7432 USED_REX (REX_B);
7433 if (rex & REX_B)
20f0a1fc 7434 add = 8;
7967e09e 7435 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7436 }
041bd2e0 7437 else
7967e09e 7438 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7439 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7440}
7441
246c51aa
L		 7442/* cvt* are the only instructions in sse2 which have
7443 both SSE and MMX operands and also have 0x66 prefix
7444 in their opcode. 0x66 was originally used to differentiate
7445 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7446 cvt* separately using OP_EMC and OP_MXC */
7447static void
7448OP_EMC (int bytemode, int sizeflag)
7449{
7967e09e 7450 if (modrm.mod != 3)
4d9567e0
MM		 7451 {
7452 if (intel_syntax && bytemode == v_mode)
7453 {
7454 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7455 used_prefixes |= (prefixes & PREFIX_DATA);
7456 }
7457 OP_E (bytemode, sizeflag);
7458 return;
7459 }
246c51aa 7460
4d9567e0
MM		 7461 /* Skip mod/rm byte. */
7462 MODRM_CHECK;
7463 codep++;
7464 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7465 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7466 oappend (scratchbuf + intel_syntax);
7467}
7468
7469static void
7470OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7471{
7472 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7473 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7474 oappend (scratchbuf + intel_syntax);
7475}
7476
c608c12e 7477static void
26ca5450 7478OP_EX (int bytemode, int sizeflag)
c608c12e 7479{
041bd2e0 7480 int add = 0;
7967e09e 7481 if (modrm.mod != 3)
c608c12e
AM		 7482 {
7483 OP_E (bytemode, sizeflag);
7484 return;
7485 }
161a04f6
L		 7486 USED_REX (REX_B);
7487 if (rex & REX_B)
041bd2e0 7488 add = 8;
c608c12e 7489
6608db57 7490 /* Skip mod/rm byte. */
4bba6815 7491 MODRM_CHECK;
c608c12e 7492 codep++;
7967e09e 7493 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7494 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7495}
7496
252b5132 7497static void
26ca5450 7498OP_MS (int bytemode, int sizeflag)
252b5132 7499{
7967e09e 7500 if (modrm.mod == 3)
2da11e11
AM		 7501 OP_EM (bytemode, sizeflag);
7502 else
6608db57 7503 BadOp ();
252b5132
RH		 7504}
7505
992aaec9 7506static void
26ca5450 7507OP_XS (int bytemode, int sizeflag)
992aaec9 7508{
7967e09e 7509 if (modrm.mod == 3)
992aaec9
AM		 7510 OP_EX (bytemode, sizeflag);
7511 else
6608db57 7512 BadOp ();
992aaec9
AM		 7513}
7514
cc0ec051
AM		 7515static void
7516OP_M (int bytemode, int sizeflag)
7517{
7967e09e 7518 if (modrm.mod == 3)
75413a22
L		 7519 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7520 BadOp ();
cc0ec051
AM		 7521 else
7522 OP_E (bytemode, sizeflag);
7523}
7524
7525static void
7526OP_0f07 (int bytemode, int sizeflag)
7527{
7967e09e 7528 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7529 BadOp ();
7530 else
7531 OP_E (bytemode, sizeflag);
7532}
7533
46e883c5 7534/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7535 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7536
cc0ec051 7537static void
46e883c5 7538NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7539{
8b38ad71
L		 7540 if ((prefixes & PREFIX_DATA) != 0
7541 || (rex != 0
7542 && rex != 0x48
7543 && address_mode == mode_64bit))
46e883c5
L		 7544 OP_REG (bytemode, sizeflag);
7545 else
7546 strcpy (obuf, "nop");
7547}
7548
7549static void
7550NOP_Fixup2 (int bytemode, int sizeflag)
7551{
8b38ad71
L		 7552 if ((prefixes & PREFIX_DATA) != 0
7553 || (rex != 0
7554 && rex != 0x48
7555 && address_mode == mode_64bit))
46e883c5 7556 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7557}
7558
84037f8c 7559static const char *const Suffix3DNow[] = {
252b5132
RH		 7560/* 00 */ NULL, NULL, NULL, NULL,
7561/* 04 */ NULL, NULL, NULL, NULL,
7562/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7563/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7564/* 10 */ NULL, NULL, NULL, NULL,
7565/* 14 */ NULL, NULL, NULL, NULL,
7566/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7567/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7568/* 20 */ NULL, NULL, NULL, NULL,
7569/* 24 */ NULL, NULL, NULL, NULL,
7570/* 28 */ NULL, NULL, NULL, NULL,
7571/* 2C */ NULL, NULL, NULL, NULL,
7572/* 30 */ NULL, NULL, NULL, NULL,
7573/* 34 */ NULL, NULL, NULL, NULL,
7574/* 38 */ NULL, NULL, NULL, NULL,
7575/* 3C */ NULL, NULL, NULL, NULL,
7576/* 40 */ NULL, NULL, NULL, NULL,
7577/* 44 */ NULL, NULL, NULL, NULL,
7578/* 48 */ NULL, NULL, NULL, NULL,
7579/* 4C */ NULL, NULL, NULL, NULL,
7580/* 50 */ NULL, NULL, NULL, NULL,
7581/* 54 */ NULL, NULL, NULL, NULL,
7582/* 58 */ NULL, NULL, NULL, NULL,
7583/* 5C */ NULL, NULL, NULL, NULL,
7584/* 60 */ NULL, NULL, NULL, NULL,
7585/* 64 */ NULL, NULL, NULL, NULL,
7586/* 68 */ NULL, NULL, NULL, NULL,
7587/* 6C */ NULL, NULL, NULL, NULL,
7588/* 70 */ NULL, NULL, NULL, NULL,
7589/* 74 */ NULL, NULL, NULL, NULL,
7590/* 78 */ NULL, NULL, NULL, NULL,
7591/* 7C */ NULL, NULL, NULL, NULL,
7592/* 80 */ NULL, NULL, NULL, NULL,
7593/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7594/* 88 */ NULL, NULL, "pfnacc", NULL,
7595/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7596/* 90 */ "pfcmpge", NULL, NULL, NULL,
7597/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7598/* 98 */ NULL, NULL, "pfsub", NULL,
7599/* 9C */ NULL, NULL, "pfadd", NULL,
7600/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7601/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7602/* A8 */ NULL, NULL, "pfsubr", NULL,
7603/* AC */ NULL, NULL, "pfacc", NULL,
7604/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7605/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7606/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7607/* BC */ NULL, NULL, NULL, "pavgusb",
7608/* C0 */ NULL, NULL, NULL, NULL,
7609/* C4 */ NULL, NULL, NULL, NULL,
7610/* C8 */ NULL, NULL, NULL, NULL,
7611/* CC */ NULL, NULL, NULL, NULL,
7612/* D0 */ NULL, NULL, NULL, NULL,
7613/* D4 */ NULL, NULL, NULL, NULL,
7614/* D8 */ NULL, NULL, NULL, NULL,
7615/* DC */ NULL, NULL, NULL, NULL,
7616/* E0 */ NULL, NULL, NULL, NULL,
7617/* E4 */ NULL, NULL, NULL, NULL,
7618/* E8 */ NULL, NULL, NULL, NULL,
7619/* EC */ NULL, NULL, NULL, NULL,
7620/* F0 */ NULL, NULL, NULL, NULL,
7621/* F4 */ NULL, NULL, NULL, NULL,
7622/* F8 */ NULL, NULL, NULL, NULL,
7623/* FC */ NULL, NULL, NULL, NULL,
7624};
7625
7626static void
26ca5450 7627OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7628{
7629 const char *mnemonic;
7630
7631 FETCH_DATA (the_info, codep + 1);
7632 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7633 place where an 8-bit immediate would normally go. ie. the last
7634 byte of the instruction. */
6608db57 7635 obufp = obuf + strlen (obuf);
c608c12e 7636 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7637 if (mnemonic)
2da11e11 7638 oappend (mnemonic);
252b5132
RH		 7639 else
7640 {
7641 /* Since a variable sized modrm/sib chunk is between the start
7642 of the opcode (0x0f0f) and the opcode suffix, we need to do
7643 all the modrm processing first, and don't know until now that
7644 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7645 op_out[0][0] = '\0';
7646 op_out[1][0] = '\0';
6608db57 7647 BadOp ();
252b5132
RH		 7648 }
7649}
c608c12e 7650
6608db57 7651static const char *simd_cmp_op[] = {
c608c12e
AM		 7652 "eq",
7653 "lt",
7654 "le",
7655 "unord",
7656 "neq",
7657 "nlt",
7658 "nle",
7659 "ord"
7660};
7661
7662static void
26ca5450 7663OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7664{
7665 unsigned int cmp_type;
7666
7667 FETCH_DATA (the_info, codep + 1);
6608db57 7668 obufp = obuf + strlen (obuf);
c608c12e
AM		 7669 cmp_type = *codep++ & 0xff;
7670 if (cmp_type < 8)
7671 {
041bd2e0
JH		 7672 char suffix1 = 'p', suffix2 = 's';
7673 used_prefixes |= (prefixes & PREFIX_REPZ);
7674 if (prefixes & PREFIX_REPZ)
7675 suffix1 = 's';
7676 else
7677 {
7678 used_prefixes |= (prefixes & PREFIX_DATA);
7679 if (prefixes & PREFIX_DATA)
7680 suffix2 = 'd';
7681 else
7682 {
7683 used_prefixes |= (prefixes & PREFIX_REPNZ);
7684 if (prefixes & PREFIX_REPNZ)
7685 suffix1 = 's', suffix2 = 'd';
7686 }
7687 }
7688 sprintf (scratchbuf, "cmp%s%c%c",
7689 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 7690 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 7691 oappend (scratchbuf);
c608c12e
AM		 7692 }
7693 else
7694 {
7695 /* We have a bad extension byte. Clean up. */
ce518a5f
L		 7696 op_out[0][0] = '\0';
7697 op_out[1][0] = '\0';
6608db57 7698 BadOp ();
c608c12e
AM		 7699 }
7700}
7701
ca164297 7702static void
b844680a
L		 7703OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7704 int sizeflag ATTRIBUTE_UNUSED)
7705{
7706 /* mwait %eax,%ecx */
7707 if (!intel_syntax)
7708 {
7709 const char **names = (address_mode == mode_64bit
7710 ? names64 : names32);
7711 strcpy (op_out[0], names[0]);
7712 strcpy (op_out[1], names[1]);
7713 two_source_ops = 1;
7714 }
7715 /* Skip mod/rm byte. */
7716 MODRM_CHECK;
7717 codep++;
7718}
7719
7720static void
7721OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7722 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7723{
b844680a
L		 7724 /* monitor %eax,%ecx,%edx" */
7725 if (!intel_syntax)
ca164297 7726 {
b844680a 7727 const char **op1_names;
cb712a9e
L		 7728 const char **names = (address_mode == mode_64bit
7729 ? names64 : names32);
1d9f512f 7730
b844680a
L		 7731 if (!(prefixes & PREFIX_ADDR))
7732 op1_names = (address_mode == mode_16bit
7733 ? names16 : names);
ca164297
L		 7734 else
7735 {
b844680a
L		 7736 /* Remove "addr16/addr32". */
7737 addr_prefix = NULL;
7738 op1_names = (address_mode != mode_32bit
7739 ? names32 : names16);
7740 used_prefixes |= PREFIX_ADDR;
ca164297 7741 }
b844680a
L		 7742 strcpy (op_out[0], op1_names[0]);
7743 strcpy (op_out[1], names[1]);
7744 strcpy (op_out[2], names[2]);
7745 two_source_ops = 1;
ca164297 7746 }
b844680a
L		 7747 /* Skip mod/rm byte. */
7748 MODRM_CHECK;
7749 codep++;
30123838
JB		 7750}
7751
6608db57
KH		 7752static void
7753BadOp (void)
2da11e11 7754{
6608db57
KH		 7755 /* Throw away prefixes and 1st. opcode byte. */
7756 codep = insn_codep + 1;
2da11e11
AM		 7757 oappend ("(bad)");
7758}
4cc91dba 7759
35c52694
L		 7760static void
7761REP_Fixup (int bytemode, int sizeflag)
7762{
7763 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7764 lods and stos. */
35c52694 7765 if (prefixes & PREFIX_REPZ)
b844680a 7766 repz_prefix = "rep ";
35c52694
L		 7767
7768 switch (bytemode)
7769 {
7770 case al_reg:
7771 case eAX_reg:
7772 case indir_dx_reg:
7773 OP_IMREG (bytemode, sizeflag);
7774 break;
7775 case eDI_reg:
7776 OP_ESreg (bytemode, sizeflag);
7777 break;
7778 case eSI_reg:
7779 OP_DSreg (bytemode, sizeflag);
7780 break;
7781 default:
7782 abort ();
7783 break;
7784 }
7785}
f5804c90
L		 7786
7787static void
7788CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7789{
161a04f6
L		 7790 USED_REX (REX_W);
7791 if (rex & REX_W)
f5804c90
L		 7792 {
7793 /* Change cmpxchg8b to cmpxchg16b. */
7794 char *p = obuf + strlen (obuf) - 2;
7795 strcpy (p, "16b");
fb9c77c7 7796 bytemode = o_mode;
f5804c90
L		 7797 }
7798 OP_M (bytemode, sizeflag);
7799}
42903f7f
L		 7800
7801static void
7802XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7803{
7804 sprintf (scratchbuf, "%%xmm%d", reg);
7805 oappend (scratchbuf + intel_syntax);
7806}
381d071f
L		 7807
7808static void
7809CRC32_Fixup (int bytemode, int sizeflag)
7810{
7811 /* Add proper suffix to "crc32". */
7812 char *p = obuf + strlen (obuf);
7813
7814 switch (bytemode)
7815 {
7816 case b_mode:
20592a94
L		 7817 if (intel_syntax)
7818 break;
7819
381d071f
L		 7820 *p++ = 'b';
7821 break;
7822 case v_mode:
20592a94
L		 7823 if (intel_syntax)
7824 break;
7825
381d071f
L		 7826 USED_REX (REX_W);
7827 if (rex & REX_W)
7828 *p++ = 'q';
9344ff29 7829 else if (sizeflag & DFLAG)
20592a94 7830 *p++ = 'l';
381d071f 7831 else
9344ff29
L		 7832 *p++ = 'w';
7833 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 7834 break;
7835 default:
7836 oappend (INTERNAL_DISASSEMBLER_ERROR);
7837 break;
7838 }
7839 *p = '\0';
7840
7841 if (modrm.mod == 3)
7842 {
7843 int add;
7844
7845 /* Skip mod/rm byte. */
7846 MODRM_CHECK;
7847 codep++;
7848
7849 USED_REX (REX_B);
7850 add = (rex & REX_B) ? 8 : 0;
7851 if (bytemode == b_mode)
7852 {
7853 USED_REX (0);
7854 if (rex)
7855 oappend (names8rex[modrm.rm + add]);
7856 else
7857 oappend (names8[modrm.rm + add]);
7858 }
7859 else
7860 {
7861 USED_REX (REX_W);
7862 if (rex & REX_W)
7863 oappend (names64[modrm.rm + add]);
7864 else if ((prefixes & PREFIX_DATA))
7865 oappend (names16[modrm.rm + add]);
7866 else
7867 oappend (names32[modrm.rm + add]);
7868 }
7869 }
7870 else
9344ff29 7871 OP_E (bytemode, sizeflag);
381d071f 7872}
85f10a01
MM		 7873
7874/* Print a DREX argument as either a register or memory operation. */
7875static void
7876print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7877{
7878 if (reg == DREX_REG_UNKNOWN)
7879 BadOp ();
7880
7881 else if (reg != DREX_REG_MEMORY)
7882 {
7883 sprintf (scratchbuf, "%%xmm%d", reg);
7884 oappend (scratchbuf + intel_syntax);
7885 }
7886
7887 else
7888 OP_E_extended (bytemode, sizeflag, 1);
7889}
7890
7891/* SSE5 instructions that have 4 arguments are encoded as:
7892 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
7893
7894 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
7895 the DREX field (0x8) to determine how the arguments are laid out.
7896 The destination register must be the same register as one of the
7897 inputs, and it is encoded in the DREX byte. No REX prefix is used
7898 for these instructions, since the DREX field contains the 3 extension
7899 bits provided by the REX prefix.
7900
7901 The bytemode argument adds 2 extra bits for passing extra information:
7902 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
7903 DREX_NO_OC0 -- OC0 in DREX is invalid
7904 (but pretend it is set). */
7905
7906static void
7907OP_DREX4 (int flag_bytemode, int sizeflag)
7908{
7909 unsigned int drex_byte;
7910 unsigned int regs[4];
7911 unsigned int modrm_regmem;
7912 unsigned int modrm_reg;
7913 unsigned int drex_reg;
7914 int bytemode;
7915 int rex_save = rex;
7916 int rex_used_save = rex_used;
7917 int has_sib = 0;
7918 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
7919 int oc0;
7920 int i;
7921
7922 bytemode = flag_bytemode & ~ DREX_MASK;
7923
7924 for (i = 0; i < 4; i++)
7925 regs[i] = DREX_REG_UNKNOWN;
7926
7927 /* Determine if we have a SIB byte in addition to MODRM before the
7928 DREX byte. */
7929 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
7930 && (modrm.mod != 3)
7931 && (modrm.rm == 4))
7932 has_sib = 1;
7933
7934 /* Get the DREX byte. */
7935 FETCH_DATA (the_info, codep + 2 + has_sib);
7936 drex_byte = codep[has_sib+1];
7937 drex_reg = DREX_XMM (drex_byte);
7938 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
7939
7940 /* Is OC0 legal? If not, hardwire oc0 == 1. */
7941 if (flag_bytemode & DREX_NO_OC0)
7942 {
7943 oc0 = 1;
7944 if (DREX_OC0 (drex_byte))
7945 BadOp ();
7946 }
7947 else
7948 oc0 = DREX_OC0 (drex_byte);
7949
7950 if (modrm.mod == 3)
7951 {
7952 /* regmem == register */
7953 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
7954 rex = rex_used = 0;
7955 /* skip modrm/drex since we don't call OP_E_extended */
7956 codep += 2;
7957 }
7958 else
7959 {
7960 /* regmem == memory, fill in appropriate REX bits */
7961 modrm_regmem = DREX_REG_MEMORY;
7962 rex = drex_byte & (REX_B | REX_X | REX_R);
7963 if (rex)
7964 rex |= REX_OPCODE;
7965 rex_used = rex;
7966 }
7967
7968 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
7969 order. */
7970 switch (oc0 + oc1)
7971 {
7972 default:
7973 BadOp ();
7974 return;
7975
7976 case 0:
7977 regs[0] = modrm_regmem;
7978 regs[1] = modrm_reg;
7979 regs[2] = drex_reg;
7980 regs[3] = drex_reg;
7981 break;
7982
7983 case 1:
7984 regs[0] = modrm_reg;
7985 regs[1] = modrm_regmem;
7986 regs[2] = drex_reg;
7987 regs[3] = drex_reg;
7988 break;
7989
7990 case 2:
7991 regs[0] = drex_reg;
7992 regs[1] = modrm_regmem;
7993 regs[2] = modrm_reg;
7994 regs[3] = drex_reg;
7995 break;
7996
7997 case 3:
7998 regs[0] = drex_reg;
7999 regs[1] = modrm_reg;
8000 regs[2] = modrm_regmem;
8001 regs[3] = drex_reg;
8002 break;
8003 }
8004
8005 /* Print out the arguments. */
8006 for (i = 0; i < 4; i++)
8007 {
8008 int j = (intel_syntax) ? 3 - i : i;
8009 if (i > 0)
8010 {
8011 *obufp++ = ',';
8012 *obufp = '\0';
8013 }
8014
8015 print_drex_arg (regs[j], bytemode, sizeflag);
8016 }
8017
8018 rex = rex_save;
8019 rex_used = rex_used_save;
8020}
8021
8022/* SSE5 instructions that have 3 arguments, and are encoded as:
8023 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8024 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8025
8026 The DREX field has 1 bit (0x8) to determine how the arguments are
8027 laid out. The destination register is encoded in the DREX byte.
8028 No REX prefix is used for these instructions, since the DREX field
8029 contains the 3 extension bits provided by the REX prefix. */
8030
8031static void
8032OP_DREX3 (int flag_bytemode, int sizeflag)
8033{
8034 unsigned int drex_byte;
8035 unsigned int regs[3];
8036 unsigned int modrm_regmem;
8037 unsigned int modrm_reg;
8038 unsigned int drex_reg;
8039 int bytemode;
8040 int rex_save = rex;
8041 int rex_used_save = rex_used;
8042 int has_sib = 0;
8043 int oc0;
8044 int i;
8045
8046 bytemode = flag_bytemode & ~ DREX_MASK;
8047
8048 for (i = 0; i < 3; i++)
8049 regs[i] = DREX_REG_UNKNOWN;
8050
8051 /* Determine if we have a SIB byte in addition to MODRM before the
8052 DREX byte. */
8053 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8054 && (modrm.mod != 3)
8055 && (modrm.rm == 4))
8056 has_sib = 1;
8057
8058 /* Get the DREX byte. */
8059 FETCH_DATA (the_info, codep + 2 + has_sib);
8060 drex_byte = codep[has_sib+1];
8061 drex_reg = DREX_XMM (drex_byte);
8062 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8063
8064 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8065 oc0 = DREX_OC0 (drex_byte);
8066 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8067 BadOp ();
8068
8069 if (modrm.mod == 3)
8070 {
8071 /* regmem == register */
8072 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8073 rex = rex_used = 0;
8074 /* skip modrm/drex since we don't call OP_E_extended. */
8075 codep += 2;
8076 }
8077 else
8078 {
8079 /* regmem == memory, fill in appropriate REX bits. */
8080 modrm_regmem = DREX_REG_MEMORY;
8081 rex = drex_byte & (REX_B | REX_X | REX_R);
8082 if (rex)
8083 rex |= REX_OPCODE;
8084 rex_used = rex;
8085 }
8086
8087 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8088 order. */
8089 switch (oc0)
8090 {
8091 default:
8092 BadOp ();
8093 return;
8094
8095 case 0:
8096 regs[0] = modrm_regmem;
8097 regs[1] = modrm_reg;
8098 regs[2] = drex_reg;
8099 break;
8100
8101 case 1:
8102 regs[0] = modrm_reg;
8103 regs[1] = modrm_regmem;
8104 regs[2] = drex_reg;
8105 break;
8106 }
8107
8108 /* Print out the arguments. */
8109 for (i = 0; i < 3; i++)
8110 {
8111 int j = (intel_syntax) ? 2 - i : i;
8112 if (i > 0)
8113 {
8114 *obufp++ = ',';
8115 *obufp = '\0';
8116 }
8117
8118 print_drex_arg (regs[j], bytemode, sizeflag);
8119 }
8120
8121 rex = rex_save;
8122 rex_used = rex_used_save;
8123}
8124
8125/* Emit a floating point comparison for comp<xx> instructions. */
8126
8127static void
8128OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8129 int sizeflag ATTRIBUTE_UNUSED)
8130{
8131 unsigned char byte;
8132
8133 static const char *const cmp_test[] = {
8134 "eq",
8135 "lt",
8136 "le",
8137 "unord",
8138 "ne",
8139 "nlt",
8140 "nle",
8141 "ord",
8142 "ueq",
8143 "ult",
8144 "ule",
8145 "false",
8146 "une",
8147 "unlt",
8148 "unle",
8149 "true"
8150 };
8151
8152 FETCH_DATA (the_info, codep + 1);
8153 byte = *codep & 0xff;
8154
8155 if (byte >= ARRAY_SIZE (cmp_test)
8156 || obuf[0] != 'c'
8157 || obuf[1] != 'o'
8158 || obuf[2] != 'm')
8159 {
8160 /* The instruction isn't one we know about, so just append the
8161 extension byte as a numeric value. */
8162 OP_I (b_mode, 0);
8163 }
8164
8165 else
8166 {
8167 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8168 strcpy (obuf, scratchbuf);
8169 codep++;
8170 }
8171}
8172
8173/* Emit an integer point comparison for pcom<xx> instructions,
8174 rewriting the instruction to have the test inside of it. */
8175
8176static void
8177OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8178 int sizeflag ATTRIBUTE_UNUSED)
8179{
8180 unsigned char byte;
8181
8182 static const char *const cmp_test[] = {
8183 "lt",
8184 "le",
8185 "gt",
8186 "ge",
8187 "eq",
8188 "ne",
8189 "false",
8190 "true"
8191 };
8192
8193 FETCH_DATA (the_info, codep + 1);
8194 byte = *codep & 0xff;
8195
8196 if (byte >= ARRAY_SIZE (cmp_test)
8197 || obuf[0] != 'p'
8198 || obuf[1] != 'c'
8199 || obuf[2] != 'o'
8200 || obuf[3] != 'm')
8201 {
8202 /* The instruction isn't one we know about, so just print the
8203 comparison test byte as a numeric value. */
8204 OP_I (b_mode, 0);
8205 }
8206
8207 else
8208 {
8209 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8210 strcpy (obuf, scratchbuf);
8211 codep++;
8212 }
8213}
GDB Binutils - Deliverables
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