Commit | Line | Data |
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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
0bfee649 | 2 | Copyright 2007, 2008, 2009 |
0b1cf022 L |
3 | Free Software Foundation, Inc. |
4 | ||
9b201bb5 | 5 | This file is part of the GNU opcodes library. |
0b1cf022 | 6 | |
9b201bb5 | 7 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 8 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 9 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
10 | any later version. |
11 | ||
9b201bb5 NC |
12 | It is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
0b1cf022 L |
16 | |
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
20 | 02110-1301, USA. */ | |
21 | ||
22 | #include "opcode/i386.h" | |
40fb9820 L |
23 | #ifdef HAVE_LIMITS_H |
24 | #include <limits.h> | |
25 | #endif | |
26 | ||
27 | #ifndef CHAR_BIT | |
28 | #define CHAR_BIT 8 | |
29 | #endif | |
30 | ||
31 | /* Position of cpu flags bitfiled. */ | |
32 | ||
33 | /* i186 or better required */ | |
34 | #define Cpu186 0 | |
35 | /* i286 or better required */ | |
36 | #define Cpu286 (Cpu186 + 1) | |
37 | /* i386 or better required */ | |
38 | #define Cpu386 (Cpu286 + 1) | |
39 | /* i486 or better required */ | |
40 | #define Cpu486 (Cpu386 + 1) | |
41 | /* i585 or better required */ | |
42 | #define Cpu586 (Cpu486 + 1) | |
43 | /* i686 or better required */ | |
44 | #define Cpu686 (Cpu586 + 1) | |
bd5295b2 L |
45 | /* CLFLUSH Instuction support required */ |
46 | #define CpuClflush (Cpu686 + 1) | |
47 | /* SYSCALL Instuctions support required */ | |
48 | #define CpuSYSCALL (CpuClflush + 1) | |
40fb9820 | 49 | /* MMX support required */ |
bd5295b2 | 50 | #define CpuMMX (CpuSYSCALL + 1) |
40fb9820 | 51 | /* SSE support required */ |
115c7c25 | 52 | #define CpuSSE (CpuMMX + 1) |
40fb9820 L |
53 | /* SSE2 support required */ |
54 | #define CpuSSE2 (CpuSSE + 1) | |
55 | /* 3dnow! support required */ | |
56 | #define Cpu3dnow (CpuSSE2 + 1) | |
57 | /* 3dnow! Extensions support required */ | |
58 | #define Cpu3dnowA (Cpu3dnow + 1) | |
59 | /* SSE3 support required */ | |
60 | #define CpuSSE3 (Cpu3dnowA + 1) | |
61 | /* VIA PadLock required */ | |
62 | #define CpuPadLock (CpuSSE3 + 1) | |
63 | /* AMD Secure Virtual Machine Ext-s required */ | |
64 | #define CpuSVME (CpuPadLock + 1) | |
65 | /* VMX Instructions required */ | |
66 | #define CpuVMX (CpuSVME + 1) | |
47dd174c L |
67 | /* SMX Instructions required */ |
68 | #define CpuSMX (CpuVMX + 1) | |
40fb9820 | 69 | /* SSSE3 support required */ |
47dd174c | 70 | #define CpuSSSE3 (CpuSMX + 1) |
40fb9820 L |
71 | /* SSE4a support required */ |
72 | #define CpuSSE4a (CpuSSSE3 + 1) | |
73 | /* ABM New Instructions required */ | |
74 | #define CpuABM (CpuSSE4a + 1) | |
75 | /* SSE4.1 support required */ | |
76 | #define CpuSSE4_1 (CpuABM + 1) | |
77 | /* SSE4.2 support required */ | |
78 | #define CpuSSE4_2 (CpuSSE4_1 + 1) | |
c0f3af97 | 79 | /* AVX support required */ |
c1e679ec | 80 | #define CpuAVX (CpuSSE4_2 + 1) |
475a2301 | 81 | /* Xsave/xrstor New Instuctions support required */ |
c0f3af97 L |
82 | #define CpuXsave (CpuAVX + 1) |
83 | /* AES support required */ | |
84 | #define CpuAES (CpuXsave + 1) | |
594ab6a3 L |
85 | /* PCLMUL support required */ |
86 | #define CpuPCLMUL (CpuAES + 1) | |
c0f3af97 | 87 | /* FMA support required */ |
594ab6a3 | 88 | #define CpuFMA (CpuPCLMUL + 1) |
f1f8f695 L |
89 | /* MOVBE Instuction support required */ |
90 | #define CpuMovbe (CpuFMA + 1) | |
91 | /* EPT Instructions required */ | |
92 | #define CpuEPT (CpuMovbe + 1) | |
1b7f3fb0 L |
93 | /* RDTSCP Instuction support required */ |
94 | #define CpuRdtscp (CpuEPT + 1) | |
40fb9820 | 95 | /* 64bit support available, used by -march= in assembler. */ |
1b7f3fb0 | 96 | #define CpuLM (CpuRdtscp + 1) |
40fb9820 L |
97 | /* 64bit support required */ |
98 | #define Cpu64 (CpuLM + 1) | |
99 | /* Not supported in the 64bit mode */ | |
100 | #define CpuNo64 (Cpu64 + 1) | |
101 | /* The last bitfield in i386_cpu_flags. */ | |
102 | #define CpuMax CpuNo64 | |
103 | ||
104 | #define CpuNumOfUints \ | |
105 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
106 | #define CpuNumOfBits \ | |
107 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
108 | ||
109 | /* If you get a compiler error for zero width of the unused field, | |
110 | comment it out. */ | |
8c6c9809 | 111 | #define CpuUnused (CpuMax + 1) |
40fb9820 L |
112 | |
113 | /* We can check if an instruction is available with array instead | |
114 | of bitfield. */ | |
115 | typedef union i386_cpu_flags | |
116 | { | |
117 | struct | |
118 | { | |
119 | unsigned int cpui186:1; | |
120 | unsigned int cpui286:1; | |
121 | unsigned int cpui386:1; | |
122 | unsigned int cpui486:1; | |
123 | unsigned int cpui586:1; | |
124 | unsigned int cpui686:1; | |
bd5295b2 L |
125 | unsigned int cpuclflush:1; |
126 | unsigned int cpusyscall:1; | |
40fb9820 | 127 | unsigned int cpummx:1; |
40fb9820 L |
128 | unsigned int cpusse:1; |
129 | unsigned int cpusse2:1; | |
130 | unsigned int cpua3dnow:1; | |
131 | unsigned int cpua3dnowa:1; | |
132 | unsigned int cpusse3:1; | |
133 | unsigned int cpupadlock:1; | |
134 | unsigned int cpusvme:1; | |
135 | unsigned int cpuvmx:1; | |
47dd174c | 136 | unsigned int cpusmx:1; |
40fb9820 L |
137 | unsigned int cpussse3:1; |
138 | unsigned int cpusse4a:1; | |
139 | unsigned int cpuabm:1; | |
140 | unsigned int cpusse4_1:1; | |
141 | unsigned int cpusse4_2:1; | |
c0f3af97 | 142 | unsigned int cpuavx:1; |
475a2301 | 143 | unsigned int cpuxsave:1; |
c0f3af97 | 144 | unsigned int cpuaes:1; |
594ab6a3 | 145 | unsigned int cpupclmul:1; |
c0f3af97 | 146 | unsigned int cpufma:1; |
f1f8f695 L |
147 | unsigned int cpumovbe:1; |
148 | unsigned int cpuept:1; | |
1b7f3fb0 | 149 | unsigned int cpurdtscp:1; |
40fb9820 L |
150 | unsigned int cpulm:1; |
151 | unsigned int cpu64:1; | |
152 | unsigned int cpuno64:1; | |
153 | #ifdef CpuUnused | |
154 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
155 | #endif | |
156 | } bitfield; | |
157 | unsigned int array[CpuNumOfUints]; | |
158 | } i386_cpu_flags; | |
159 | ||
160 | /* Position of opcode_modifier bits. */ | |
161 | ||
162 | /* has direction bit. */ | |
163 | #define D 0 | |
164 | /* set if operands can be words or dwords encoded the canonical way */ | |
165 | #define W (D + 1) | |
fa99fab2 L |
166 | /* Skip the current insn and use the next insn in i386-opc.tbl to swap |
167 | operand in encoding. */ | |
b6169b20 | 168 | #define S (W + 1) |
40fb9820 | 169 | /* insn has a modrm byte. */ |
b6169b20 | 170 | #define Modrm (S + 1) |
40fb9820 L |
171 | /* register is in low 3 bits of opcode */ |
172 | #define ShortForm (Modrm + 1) | |
173 | /* special case for jump insns. */ | |
174 | #define Jump (ShortForm + 1) | |
175 | /* call and jump */ | |
176 | #define JumpDword (Jump + 1) | |
177 | /* loop and jecxz */ | |
178 | #define JumpByte (JumpDword + 1) | |
179 | /* special case for intersegment leaps/calls */ | |
180 | #define JumpInterSegment (JumpByte + 1) | |
181 | /* FP insn memory format bit, sized by 0x4 */ | |
182 | #define FloatMF (JumpInterSegment + 1) | |
183 | /* src/dest swap for floats. */ | |
184 | #define FloatR (FloatMF + 1) | |
185 | /* has float insn direction bit. */ | |
186 | #define FloatD (FloatR + 1) | |
187 | /* needs size prefix if in 32-bit mode */ | |
188 | #define Size16 (FloatD + 1) | |
189 | /* needs size prefix if in 16-bit mode */ | |
190 | #define Size32 (Size16 + 1) | |
191 | /* needs size prefix if in 64-bit mode */ | |
192 | #define Size64 (Size32 + 1) | |
f2a9c676 L |
193 | /* instruction ignores operand size prefix and in Intel mode ignores |
194 | mnemonic size suffix check. */ | |
40fb9820 L |
195 | #define IgnoreSize (Size64 + 1) |
196 | /* default insn size depends on mode */ | |
197 | #define DefaultSize (IgnoreSize + 1) | |
198 | /* b suffix on instruction illegal */ | |
199 | #define No_bSuf (DefaultSize + 1) | |
200 | /* w suffix on instruction illegal */ | |
201 | #define No_wSuf (No_bSuf + 1) | |
202 | /* l suffix on instruction illegal */ | |
203 | #define No_lSuf (No_wSuf + 1) | |
204 | /* s suffix on instruction illegal */ | |
205 | #define No_sSuf (No_lSuf + 1) | |
206 | /* q suffix on instruction illegal */ | |
207 | #define No_qSuf (No_sSuf + 1) | |
7ce189b3 L |
208 | /* long double suffix on instruction illegal */ |
209 | #define No_ldSuf (No_qSuf + 1) | |
40fb9820 | 210 | /* instruction needs FWAIT */ |
7d5e4556 | 211 | #define FWait (No_ldSuf + 1) |
40fb9820 L |
212 | /* quick test for string instructions */ |
213 | #define IsString (FWait + 1) | |
214 | /* fake an extra reg operand for clr, imul and special register | |
215 | processing for some instructions. */ | |
216 | #define RegKludge (IsString + 1) | |
e2ec9d29 L |
217 | /* The first operand must be xmm0 */ |
218 | #define FirstXmm0 (RegKludge + 1) | |
c0f3af97 L |
219 | /* An implicit xmm0 as the first operand */ |
220 | #define Implicit1stXmm0 (FirstXmm0 + 1) | |
ca61edf2 | 221 | /* BYTE is OK in Intel syntax. */ |
c0f3af97 | 222 | #define ByteOkIntel (Implicit1stXmm0 + 1) |
ca61edf2 L |
223 | /* Convert to DWORD */ |
224 | #define ToDword (ByteOkIntel + 1) | |
225 | /* Convert to QWORD */ | |
226 | #define ToQword (ToDword + 1) | |
227 | /* Address prefix changes operand 0 */ | |
228 | #define AddrPrefixOp0 (ToQword + 1) | |
40fb9820 | 229 | /* opcode is a prefix */ |
ca61edf2 | 230 | #define IsPrefix (AddrPrefixOp0 + 1) |
40fb9820 L |
231 | /* instruction has extension in 8 bit imm */ |
232 | #define ImmExt (IsPrefix + 1) | |
233 | /* instruction don't need Rex64 prefix. */ | |
234 | #define NoRex64 (ImmExt + 1) | |
235 | /* instruction require Rex64 prefix. */ | |
236 | #define Rex64 (NoRex64 + 1) | |
237 | /* deprecated fp insn, gets a warning */ | |
238 | #define Ugh (Rex64 + 1) | |
c0f3af97 | 239 | /* insn has VEX prefix. */ |
c1e679ec | 240 | #define Vex (Ugh + 1) |
c0f3af97 L |
241 | /* insn has 256bit VEX prefix. */ |
242 | #define Vex256 (Vex + 1) | |
0bfee649 L |
243 | /* insn has VEX NDS. Register-only source is encoded in Vex prefix. |
244 | We use VexNDS on insns with VEX DDS since the register-only source | |
245 | is the second source register. */ | |
c0f3af97 L |
246 | #define VexNDS (Vex256 + 1) |
247 | /* insn has VEX NDD. Register destination is encoded in Vex | |
248 | prefix. */ | |
249 | #define VexNDD (VexNDS + 1) | |
250 | /* insn has VEX W0. */ | |
251 | #define VexW0 (VexNDD + 1) | |
252 | /* insn has VEX W1. */ | |
253 | #define VexW1 (VexW0 + 1) | |
254 | /* insn has VEX 0x0F opcode prefix. */ | |
255 | #define Vex0F (VexW1 + 1) | |
256 | /* insn has VEX 0x0F38 opcode prefix. */ | |
257 | #define Vex0F38 (Vex0F + 1) | |
258 | /* insn has VEX 0x0F3A opcode prefix. */ | |
259 | #define Vex0F3A (Vex0F38 + 1) | |
260 | /* insn has VEX prefix with 3 soures. */ | |
261 | #define Vex3Sources (Vex0F3A + 1) | |
262 | /* instruction has VEX 8 bit imm */ | |
263 | #define VexImmExt (Vex3Sources + 1) | |
264 | /* SSE to AVX support required */ | |
265 | #define SSE2AVX (VexImmExt + 1) | |
81f8a913 L |
266 | /* No AVX equivalent */ |
267 | #define NoAVX (SSE2AVX + 1) | |
1efbbeb4 | 268 | /* Compatible with old (<= 2.8.1) versions of gcc */ |
81f8a913 | 269 | #define OldGcc (NoAVX + 1) |
1efbbeb4 L |
270 | /* AT&T mnemonic. */ |
271 | #define ATTMnemonic (OldGcc + 1) | |
e1d4d893 L |
272 | /* AT&T syntax. */ |
273 | #define ATTSyntax (ATTMnemonic + 1) | |
5c07affc L |
274 | /* Intel syntax. */ |
275 | #define IntelSyntax (ATTSyntax + 1) | |
40fb9820 | 276 | /* The last bitfield in i386_opcode_modifier. */ |
5c07affc | 277 | #define Opcode_Modifier_Max IntelSyntax |
40fb9820 L |
278 | |
279 | typedef struct i386_opcode_modifier | |
280 | { | |
281 | unsigned int d:1; | |
282 | unsigned int w:1; | |
b6169b20 | 283 | unsigned int s:1; |
40fb9820 L |
284 | unsigned int modrm:1; |
285 | unsigned int shortform:1; | |
286 | unsigned int jump:1; | |
287 | unsigned int jumpdword:1; | |
288 | unsigned int jumpbyte:1; | |
289 | unsigned int jumpintersegment:1; | |
290 | unsigned int floatmf:1; | |
291 | unsigned int floatr:1; | |
292 | unsigned int floatd:1; | |
293 | unsigned int size16:1; | |
294 | unsigned int size32:1; | |
295 | unsigned int size64:1; | |
296 | unsigned int ignoresize:1; | |
297 | unsigned int defaultsize:1; | |
298 | unsigned int no_bsuf:1; | |
299 | unsigned int no_wsuf:1; | |
300 | unsigned int no_lsuf:1; | |
301 | unsigned int no_ssuf:1; | |
302 | unsigned int no_qsuf:1; | |
7ce189b3 | 303 | unsigned int no_ldsuf:1; |
40fb9820 L |
304 | unsigned int fwait:1; |
305 | unsigned int isstring:1; | |
306 | unsigned int regkludge:1; | |
e2ec9d29 | 307 | unsigned int firstxmm0:1; |
c0f3af97 | 308 | unsigned int implicit1stxmm0:1; |
ca61edf2 L |
309 | unsigned int byteokintel:1; |
310 | unsigned int todword:1; | |
311 | unsigned int toqword:1; | |
312 | unsigned int addrprefixop0:1; | |
40fb9820 L |
313 | unsigned int isprefix:1; |
314 | unsigned int immext:1; | |
315 | unsigned int norex64:1; | |
316 | unsigned int rex64:1; | |
317 | unsigned int ugh:1; | |
c0f3af97 L |
318 | unsigned int vex:1; |
319 | unsigned int vex256:1; | |
320 | unsigned int vexnds:1; | |
321 | unsigned int vexndd:1; | |
322 | unsigned int vexw0:1; | |
323 | unsigned int vexw1:1; | |
324 | unsigned int vex0f:1; | |
325 | unsigned int vex0f38:1; | |
326 | unsigned int vex0f3a:1; | |
327 | unsigned int vex3sources:1; | |
328 | unsigned int veximmext:1; | |
329 | unsigned int sse2avx:1; | |
81f8a913 | 330 | unsigned int noavx:1; |
1efbbeb4 L |
331 | unsigned int oldgcc:1; |
332 | unsigned int attmnemonic:1; | |
e1d4d893 | 333 | unsigned int attsyntax:1; |
5c07affc | 334 | unsigned int intelsyntax:1; |
40fb9820 L |
335 | } i386_opcode_modifier; |
336 | ||
337 | /* Position of operand_type bits. */ | |
338 | ||
7d5e4556 | 339 | /* 8bit register */ |
40fb9820 | 340 | #define Reg8 0 |
7d5e4556 | 341 | /* 16bit register */ |
40fb9820 | 342 | #define Reg16 (Reg8 + 1) |
7d5e4556 | 343 | /* 32bit register */ |
40fb9820 | 344 | #define Reg32 (Reg16 + 1) |
7d5e4556 | 345 | /* 64bit register */ |
40fb9820 | 346 | #define Reg64 (Reg32 + 1) |
7d5e4556 L |
347 | /* Floating pointer stack register */ |
348 | #define FloatReg (Reg64 + 1) | |
349 | /* MMX register */ | |
350 | #define RegMMX (FloatReg + 1) | |
351 | /* SSE register */ | |
352 | #define RegXMM (RegMMX + 1) | |
c0f3af97 L |
353 | /* AVX registers */ |
354 | #define RegYMM (RegXMM + 1) | |
7d5e4556 | 355 | /* Control register */ |
c0f3af97 | 356 | #define Control (RegYMM + 1) |
7d5e4556 L |
357 | /* Debug register */ |
358 | #define Debug (Control + 1) | |
359 | /* Test register */ | |
360 | #define Test (Debug + 1) | |
361 | /* 2 bit segment register */ | |
362 | #define SReg2 (Test + 1) | |
363 | /* 3 bit segment register */ | |
364 | #define SReg3 (SReg2 + 1) | |
365 | /* 1 bit immediate */ | |
366 | #define Imm1 (SReg3 + 1) | |
40fb9820 | 367 | /* 8 bit immediate */ |
7d5e4556 | 368 | #define Imm8 (Imm1 + 1) |
40fb9820 L |
369 | /* 8 bit immediate sign extended */ |
370 | #define Imm8S (Imm8 + 1) | |
371 | /* 16 bit immediate */ | |
372 | #define Imm16 (Imm8S + 1) | |
373 | /* 32 bit immediate */ | |
374 | #define Imm32 (Imm16 + 1) | |
375 | /* 32 bit immediate sign extended */ | |
376 | #define Imm32S (Imm32 + 1) | |
377 | /* 64 bit immediate */ | |
378 | #define Imm64 (Imm32S + 1) | |
7d5e4556 L |
379 | /* 8bit/16bit/32bit displacements are used in different ways, |
380 | depending on the instruction. For jumps, they specify the | |
381 | size of the PC relative displacement, for instructions with | |
382 | memory operand, they specify the size of the offset relative | |
383 | to the base register, and for instructions with memory offset | |
384 | such as `mov 1234,%al' they specify the size of the offset | |
385 | relative to the segment base. */ | |
40fb9820 | 386 | /* 8 bit displacement */ |
7d5e4556 | 387 | #define Disp8 (Imm64 + 1) |
40fb9820 L |
388 | /* 16 bit displacement */ |
389 | #define Disp16 (Disp8 + 1) | |
390 | /* 32 bit displacement */ | |
391 | #define Disp32 (Disp16 + 1) | |
392 | /* 32 bit signed displacement */ | |
393 | #define Disp32S (Disp32 + 1) | |
394 | /* 64 bit displacement */ | |
395 | #define Disp64 (Disp32S + 1) | |
7d5e4556 L |
396 | /* Accumulator %al/%ax/%eax/%rax */ |
397 | #define Acc (Disp64 + 1) | |
398 | /* Floating pointer top stack register %st(0) */ | |
399 | #define FloatAcc (Acc + 1) | |
400 | /* Register which can be used for base or index in memory operand. */ | |
401 | #define BaseIndex (FloatAcc + 1) | |
402 | /* Register to hold in/out port addr = dx */ | |
403 | #define InOutPortReg (BaseIndex + 1) | |
404 | /* Register to hold shift count = cl */ | |
40fb9820 | 405 | #define ShiftCount (InOutPortReg + 1) |
7d5e4556 L |
406 | /* Absolute address for jump. */ |
407 | #define JumpAbsolute (ShiftCount + 1) | |
40fb9820 | 408 | /* String insn operand with fixed es segment */ |
7d5e4556 | 409 | #define EsSeg (JumpAbsolute + 1) |
40fb9820 L |
410 | /* RegMem is for instructions with a modrm byte where the register |
411 | destination operand should be encoded in the mod and regmem fields. | |
412 | Normally, it will be encoded in the reg field. We add a RegMem | |
413 | flag to the destination register operand to indicate that it should | |
414 | be encoded in the regmem field. */ | |
415 | #define RegMem (EsSeg + 1) | |
5c07affc L |
416 | /* Memory. */ |
417 | #define Mem (RegMem + 1) | |
7d5e4556 | 418 | /* BYTE memory. */ |
5c07affc | 419 | #define Byte (Mem + 1) |
7d5e4556 L |
420 | /* WORD memory. 2 byte */ |
421 | #define Word (Byte + 1) | |
422 | /* DWORD memory. 4 byte */ | |
423 | #define Dword (Word + 1) | |
424 | /* FWORD memory. 6 byte */ | |
425 | #define Fword (Dword + 1) | |
426 | /* QWORD memory. 8 byte */ | |
427 | #define Qword (Fword + 1) | |
428 | /* TBYTE memory. 10 byte */ | |
429 | #define Tbyte (Qword + 1) | |
430 | /* XMMWORD memory. */ | |
431 | #define Xmmword (Tbyte + 1) | |
c0f3af97 L |
432 | /* YMMWORD memory. */ |
433 | #define Ymmword (Xmmword + 1) | |
7d5e4556 | 434 | /* Unspecified memory size. */ |
c0f3af97 | 435 | #define Unspecified (Ymmword + 1) |
7d5e4556 L |
436 | /* Any memory size. */ |
437 | #define Anysize (Unspecified + 1) | |
40fb9820 L |
438 | |
439 | /* The last bitfield in i386_operand_type. */ | |
4c664d7b | 440 | #define OTMax Anysize |
40fb9820 L |
441 | |
442 | #define OTNumOfUints \ | |
443 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
444 | #define OTNumOfBits \ | |
445 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
446 | ||
447 | /* If you get a compiler error for zero width of the unused field, | |
448 | comment it out. */ | |
8c6c9809 | 449 | #define OTUnused (OTMax + 1) |
40fb9820 L |
450 | |
451 | typedef union i386_operand_type | |
452 | { | |
453 | struct | |
454 | { | |
455 | unsigned int reg8:1; | |
456 | unsigned int reg16:1; | |
457 | unsigned int reg32:1; | |
458 | unsigned int reg64:1; | |
7d5e4556 L |
459 | unsigned int floatreg:1; |
460 | unsigned int regmmx:1; | |
461 | unsigned int regxmm:1; | |
c0f3af97 | 462 | unsigned int regymm:1; |
7d5e4556 L |
463 | unsigned int control:1; |
464 | unsigned int debug:1; | |
465 | unsigned int test:1; | |
466 | unsigned int sreg2:1; | |
467 | unsigned int sreg3:1; | |
468 | unsigned int imm1:1; | |
40fb9820 L |
469 | unsigned int imm8:1; |
470 | unsigned int imm8s:1; | |
471 | unsigned int imm16:1; | |
472 | unsigned int imm32:1; | |
473 | unsigned int imm32s:1; | |
474 | unsigned int imm64:1; | |
40fb9820 L |
475 | unsigned int disp8:1; |
476 | unsigned int disp16:1; | |
477 | unsigned int disp32:1; | |
478 | unsigned int disp32s:1; | |
479 | unsigned int disp64:1; | |
7d5e4556 L |
480 | unsigned int acc:1; |
481 | unsigned int floatacc:1; | |
482 | unsigned int baseindex:1; | |
40fb9820 L |
483 | unsigned int inoutportreg:1; |
484 | unsigned int shiftcount:1; | |
40fb9820 | 485 | unsigned int jumpabsolute:1; |
40fb9820 L |
486 | unsigned int esseg:1; |
487 | unsigned int regmem:1; | |
5c07affc | 488 | unsigned int mem:1; |
7d5e4556 L |
489 | unsigned int byte:1; |
490 | unsigned int word:1; | |
491 | unsigned int dword:1; | |
492 | unsigned int fword:1; | |
493 | unsigned int qword:1; | |
494 | unsigned int tbyte:1; | |
495 | unsigned int xmmword:1; | |
c0f3af97 | 496 | unsigned int ymmword:1; |
7d5e4556 L |
497 | unsigned int unspecified:1; |
498 | unsigned int anysize:1; | |
40fb9820 L |
499 | #ifdef OTUnused |
500 | unsigned int unused:(OTNumOfBits - OTUnused); | |
501 | #endif | |
502 | } bitfield; | |
503 | unsigned int array[OTNumOfUints]; | |
504 | } i386_operand_type; | |
0b1cf022 L |
505 | |
506 | typedef struct template | |
507 | { | |
508 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
509 | char *name; | |
510 | ||
511 | /* how many operands */ | |
512 | unsigned int operands; | |
513 | ||
514 | /* base_opcode is the fundamental opcode byte without optional | |
515 | prefix(es). */ | |
516 | unsigned int base_opcode; | |
517 | #define Opcode_D 0x2 /* Direction bit: | |
518 | set if Reg --> Regmem; | |
519 | unset if Regmem --> Reg. */ | |
520 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ | |
521 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ | |
522 | ||
523 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
524 | This field is also used to store the 8-bit opcode suffix for the | |
525 | AMD 3DNow! instructions. | |
85f10a01 | 526 | If this template has no extension opcode (the usual case) use None |
c1e679ec | 527 | Instructions */ |
0b1cf022 L |
528 | unsigned int extension_opcode; |
529 | #define None 0xffff /* If no extension_opcode is possible. */ | |
530 | ||
4dffcebc L |
531 | /* Opcode length. */ |
532 | unsigned char opcode_length; | |
533 | ||
0b1cf022 | 534 | /* cpu feature flags */ |
40fb9820 | 535 | i386_cpu_flags cpu_flags; |
0b1cf022 L |
536 | |
537 | /* the bits in opcode_modifier are used to generate the final opcode from | |
538 | the base_opcode. These bits also are used to detect alternate forms of | |
539 | the same instruction */ | |
40fb9820 | 540 | i386_opcode_modifier opcode_modifier; |
0b1cf022 L |
541 | |
542 | /* operand_types[i] describes the type of operand i. This is made | |
543 | by OR'ing together all of the possible type masks. (e.g. | |
544 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
545 | either a register or an immediate operand. */ | |
40fb9820 | 546 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 L |
547 | } |
548 | template; | |
549 | ||
550 | extern const template i386_optab[]; | |
551 | ||
552 | /* these are for register name --> number & type hash lookup */ | |
553 | typedef struct | |
554 | { | |
555 | char *reg_name; | |
40fb9820 | 556 | i386_operand_type reg_type; |
a60de03c | 557 | unsigned char reg_flags; |
0b1cf022 L |
558 | #define RegRex 0x1 /* Extended register. */ |
559 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
a60de03c JB |
560 | unsigned char reg_num; |
561 | #define RegRip ((unsigned char ) ~0) | |
9a04903e | 562 | #define RegEip (RegRip - 1) |
db51cc60 | 563 | /* EIZ and RIZ are fake index registers. */ |
9a04903e | 564 | #define RegEiz (RegEip - 1) |
db51cc60 | 565 | #define RegRiz (RegEiz - 1) |
b7240065 JB |
566 | /* FLAT is a fake segment register (Intel mode). */ |
567 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
568 | signed char dw2_regnum[2]; |
569 | #define Dw2Inval (-1) | |
0b1cf022 L |
570 | } |
571 | reg_entry; | |
572 | ||
573 | /* Entries in i386_regtab. */ | |
574 | #define REGNAM_AL 1 | |
575 | #define REGNAM_AX 25 | |
576 | #define REGNAM_EAX 41 | |
577 | ||
578 | extern const reg_entry i386_regtab[]; | |
c3fe08fa | 579 | extern const unsigned int i386_regtab_size; |
0b1cf022 L |
580 | |
581 | typedef struct | |
582 | { | |
583 | char *seg_name; | |
584 | unsigned int seg_prefix; | |
585 | } | |
586 | seg_entry; | |
587 | ||
588 | extern const seg_entry cs; | |
589 | extern const seg_entry ds; | |
590 | extern const seg_entry ss; | |
591 | extern const seg_entry es; | |
592 | extern const seg_entry fs; | |
593 | extern const seg_entry gs; |