Commit | Line | Data |
---|---|---|
0b1cf022 L |
1 | /* Declarations for Intel 80386 opcode table |
2 | Copyright 2007 | |
3 | Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
20 | 02110-1301, USA. */ | |
21 | ||
22 | #include "opcode/i386.h" | |
23 | ||
24 | typedef struct template | |
25 | { | |
26 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
27 | char *name; | |
28 | ||
29 | /* how many operands */ | |
30 | unsigned int operands; | |
31 | ||
32 | /* base_opcode is the fundamental opcode byte without optional | |
33 | prefix(es). */ | |
34 | unsigned int base_opcode; | |
35 | #define Opcode_D 0x2 /* Direction bit: | |
36 | set if Reg --> Regmem; | |
37 | unset if Regmem --> Reg. */ | |
38 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ | |
39 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ | |
40 | ||
41 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
42 | This field is also used to store the 8-bit opcode suffix for the | |
43 | AMD 3DNow! instructions. | |
44 | If this template has no extension opcode (the usual case) use None */ | |
45 | unsigned int extension_opcode; | |
46 | #define None 0xffff /* If no extension_opcode is possible. */ | |
47 | ||
48 | /* cpu feature flags */ | |
49 | unsigned int cpu_flags; | |
50 | #define Cpu186 0x1 /* i186 or better required */ | |
51 | #define Cpu286 0x2 /* i286 or better required */ | |
52 | #define Cpu386 0x4 /* i386 or better required */ | |
53 | #define Cpu486 0x8 /* i486 or better required */ | |
54 | #define Cpu586 0x10 /* i585 or better required */ | |
55 | #define Cpu686 0x20 /* i686 or better required */ | |
56 | #define CpuP4 0x40 /* Pentium4 or better required */ | |
57 | #define CpuK6 0x80 /* AMD K6 or better required*/ | |
58 | #define CpuSledgehammer 0x100 /* Sledgehammer or better required */ | |
59 | #define CpuMMX 0x200 /* MMX support required */ | |
60 | #define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */ | |
61 | #define CpuSSE 0x800 /* Streaming SIMD extensions required */ | |
62 | #define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */ | |
63 | #define Cpu3dnow 0x2000 /* 3dnow! support required */ | |
64 | #define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */ | |
65 | #define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */ | |
66 | #define CpuPadLock 0x10000 /* VIA PadLock required */ | |
67 | #define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */ | |
68 | #define CpuVMX 0x40000 /* VMX Instructions required */ | |
69 | #define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */ | |
70 | #define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */ | |
71 | #define CpuABM 0x200000 /* ABM New Instructions required */ | |
72 | ||
73 | /* These flags are set by gas depending on the flag_code. */ | |
74 | #define Cpu64 0x4000000 /* 64bit support required */ | |
75 | #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ | |
76 | ||
77 | /* The default value for unknown CPUs - enable all features to avoid problems. */ | |
78 | #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ | |
79 | |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ | |
80 | |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a) | |
81 | ||
82 | /* the bits in opcode_modifier are used to generate the final opcode from | |
83 | the base_opcode. These bits also are used to detect alternate forms of | |
84 | the same instruction */ | |
85 | unsigned int opcode_modifier; | |
86 | ||
87 | /* opcode_modifier bits: */ | |
88 | #define D 0x1 /* has direction bit. */ | |
89 | #define W 0x2 /* set if operands can be words or dwords | |
90 | encoded the canonical way */ | |
91 | #define Modrm 0x4 /* insn has a modrm byte. */ | |
92 | #define ShortForm 0x10 /* register is in low 3 bits of opcode */ | |
93 | #define Jump 0x40 /* special case for jump insns. */ | |
94 | #define JumpDword 0x80 /* call and jump */ | |
95 | #define JumpByte 0x100 /* loop and jecxz */ | |
96 | #define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ | |
97 | #define FloatMF 0x400 /* FP insn memory format bit, sized by 0x4 */ | |
98 | #define FloatR 0x800 /* src/dest swap for floats. */ | |
99 | #define FloatD 0x1000 /* has float insn direction bit. */ | |
100 | #define Size16 0x2000 /* needs size prefix if in 32-bit mode */ | |
101 | #define Size32 0x4000 /* needs size prefix if in 16-bit mode */ | |
102 | #define Size64 0x8000 /* needs size prefix if in 64-bit mode */ | |
103 | #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ | |
104 | #define DefaultSize 0x20000 /* default insn size depends on mode */ | |
105 | #define No_bSuf 0x40000 /* b suffix on instruction illegal */ | |
106 | #define No_wSuf 0x80000 /* w suffix on instruction illegal */ | |
107 | #define No_lSuf 0x100000 /* l suffix on instruction illegal */ | |
108 | #define No_sSuf 0x200000 /* s suffix on instruction illegal */ | |
109 | #define No_qSuf 0x400000 /* q suffix on instruction illegal */ | |
110 | #define No_xSuf 0x800000 /* x suffix on instruction illegal */ | |
111 | #define FWait 0x1000000 /* instruction needs FWAIT */ | |
112 | #define IsString 0x2000000 /* quick test for string instructions */ | |
113 | #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ | |
114 | #define IsPrefix 0x8000000 /* opcode is a prefix */ | |
115 | #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ | |
116 | #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ | |
117 | #define Rex64 0x40000000 /* instruction require Rex64 prefix. */ | |
118 | #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ | |
119 | ||
120 | /* operand_types[i] describes the type of operand i. This is made | |
121 | by OR'ing together all of the possible type masks. (e.g. | |
122 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
123 | either a register or an immediate operand. */ | |
124 | unsigned int operand_types[MAX_OPERANDS]; | |
125 | ||
126 | /* operand_types[i] bits */ | |
127 | /* register */ | |
128 | #define Reg8 0x1 /* 8 bit reg */ | |
129 | #define Reg16 0x2 /* 16 bit reg */ | |
130 | #define Reg32 0x4 /* 32 bit reg */ | |
131 | #define Reg64 0x8 /* 64 bit reg */ | |
132 | /* immediate */ | |
133 | #define Imm8 0x10 /* 8 bit immediate */ | |
134 | #define Imm8S 0x20 /* 8 bit immediate sign extended */ | |
135 | #define Imm16 0x40 /* 16 bit immediate */ | |
136 | #define Imm32 0x80 /* 32 bit immediate */ | |
137 | #define Imm32S 0x100 /* 32 bit immediate sign extended */ | |
138 | #define Imm64 0x200 /* 64 bit immediate */ | |
139 | #define Imm1 0x400 /* 1 bit immediate */ | |
140 | /* memory */ | |
141 | #define BaseIndex 0x800 | |
142 | /* Disp8,16,32 are used in different ways, depending on the | |
143 | instruction. For jumps, they specify the size of the PC relative | |
144 | displacement, for baseindex type instructions, they specify the | |
145 | size of the offset relative to the base register, and for memory | |
146 | offset instructions such as `mov 1234,%al' they specify the size of | |
147 | the offset relative to the segment base. */ | |
148 | #define Disp8 0x1000 /* 8 bit displacement */ | |
149 | #define Disp16 0x2000 /* 16 bit displacement */ | |
150 | #define Disp32 0x4000 /* 32 bit displacement */ | |
151 | #define Disp32S 0x8000 /* 32 bit signed displacement */ | |
152 | #define Disp64 0x10000 /* 64 bit displacement */ | |
153 | /* specials */ | |
154 | #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ | |
155 | #define ShiftCount 0x40000 /* register to hold shift count = cl */ | |
156 | #define Control 0x80000 /* Control register */ | |
157 | #define Debug 0x100000 /* Debug register */ | |
158 | #define Test 0x200000 /* Test register */ | |
159 | #define FloatReg 0x400000 /* Float register */ | |
160 | #define FloatAcc 0x800000 /* Float stack top %st(0) */ | |
161 | #define SReg2 0x1000000 /* 2 bit segment register */ | |
162 | #define SReg3 0x2000000 /* 3 bit segment register */ | |
163 | #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ | |
164 | #define JumpAbsolute 0x8000000 | |
165 | #define RegMMX 0x10000000 /* MMX register */ | |
166 | #define RegXMM 0x20000000 /* XMM registers in PIII */ | |
167 | #define EsSeg 0x40000000 /* String insn operand with fixed es segment */ | |
168 | ||
e72cf3ec L |
169 | /* RegMem is for instructions with a modrm byte where the register |
170 | destination operand should be encoded in the mod and regmem fields. | |
171 | Normally, it will be encoded in the reg field. We add a RegMem | |
172 | flag to the destination register operand to indicate that it should | |
173 | be encoded in the regmem field. */ | |
174 | #define RegMem 0x80000000 | |
0b1cf022 L |
175 | |
176 | #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ | |
177 | #define WordReg (Reg16|Reg32|Reg64) | |
178 | #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) | |
179 | #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ | |
180 | #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ | |
181 | #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ | |
e72cf3ec | 182 | #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */ |
0b1cf022 L |
183 | /* The following aliases are defined because the opcode table |
184 | carefully specifies the allowed memory types for each instruction. | |
185 | At the moment we can only tell a memory reference size by the | |
186 | instruction suffix, so there's not much point in defining Mem8, | |
187 | Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use | |
188 | the suffix directly to check memory operands. */ | |
189 | #define LLongMem AnyMem /* 64 bits (or more) */ | |
190 | #define LongMem AnyMem /* 32 bit memory ref */ | |
191 | #define ShortMem AnyMem /* 16 bit memory ref */ | |
192 | #define WordMem AnyMem /* 16, 32 or 64 bit memory ref */ | |
193 | #define ByteMem AnyMem /* 8 bit memory ref */ | |
194 | } | |
195 | template; | |
196 | ||
197 | extern const template i386_optab[]; | |
198 | ||
199 | /* these are for register name --> number & type hash lookup */ | |
200 | typedef struct | |
201 | { | |
202 | char *reg_name; | |
203 | unsigned int reg_type; | |
204 | unsigned int reg_flags; | |
205 | #define RegRex 0x1 /* Extended register. */ | |
206 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
207 | unsigned int reg_num; | |
208 | } | |
209 | reg_entry; | |
210 | ||
211 | /* Entries in i386_regtab. */ | |
212 | #define REGNAM_AL 1 | |
213 | #define REGNAM_AX 25 | |
214 | #define REGNAM_EAX 41 | |
215 | ||
216 | extern const reg_entry i386_regtab[]; | |
c3fe08fa | 217 | extern const unsigned int i386_regtab_size; |
0b1cf022 | 218 | extern const reg_entry i386_float_regtab[]; |
c3fe08fa | 219 | extern const unsigned int i386_float_regtab_size; |
0b1cf022 L |
220 | |
221 | typedef struct | |
222 | { | |
223 | char *seg_name; | |
224 | unsigned int seg_prefix; | |
225 | } | |
226 | seg_entry; | |
227 | ||
228 | extern const seg_entry cs; | |
229 | extern const seg_entry ds; | |
230 | extern const seg_entry ss; | |
231 | extern const seg_entry es; | |
232 | extern const seg_entry fs; | |
233 | extern const seg_entry gs; |