MIPS/opcodes: Reorder LSA and DLSA instructions
[deliverable/binutils-gdb.git] / opcodes / lm32-opc.h
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1/* Instruction opcode header for lm32.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
2571583a 5Copyright (C) 1996-2017 Free Software Foundation, Inc.
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6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
25#ifndef LM32_OPC_H
26#define LM32_OPC_H
27
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28#ifdef __cplusplus
29extern "C" {
30#endif
31
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32/* -- opc.h */
33
34/* Allows reason codes to be output when assembler errors occur. */
35#define CGEN_VERBOSE_ASSEMBLER_ERRORS
36
37#define CGEN_DIS_HASH_SIZE 64
43e65147 38#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f)
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39
40/* -- asm.c */
41/* Enum declaration for lm32 instruction types. */
42typedef enum cgen_insn_type {
43 LM32_INSN_INVALID, LM32_INSN_ADD, LM32_INSN_ADDI, LM32_INSN_AND
44 , LM32_INSN_ANDI, LM32_INSN_ANDHII, LM32_INSN_B, LM32_INSN_BI
45 , LM32_INSN_BE, LM32_INSN_BG, LM32_INSN_BGE, LM32_INSN_BGEU
46 , LM32_INSN_BGU, LM32_INSN_BNE, LM32_INSN_CALL, LM32_INSN_CALLI
47 , LM32_INSN_CMPE, LM32_INSN_CMPEI, LM32_INSN_CMPG, LM32_INSN_CMPGI
48 , LM32_INSN_CMPGE, LM32_INSN_CMPGEI, LM32_INSN_CMPGEU, LM32_INSN_CMPGEUI
49 , LM32_INSN_CMPGU, LM32_INSN_CMPGUI, LM32_INSN_CMPNE, LM32_INSN_CMPNEI
50 , LM32_INSN_DIVU, LM32_INSN_LB, LM32_INSN_LBU, LM32_INSN_LH
51 , LM32_INSN_LHU, LM32_INSN_LW, LM32_INSN_MODU, LM32_INSN_MUL
52 , LM32_INSN_MULI, LM32_INSN_NOR, LM32_INSN_NORI, LM32_INSN_OR
53 , LM32_INSN_ORI, LM32_INSN_ORHII, LM32_INSN_RCSR, LM32_INSN_SB
54 , LM32_INSN_SEXTB, LM32_INSN_SEXTH, LM32_INSN_SH, LM32_INSN_SL
55 , LM32_INSN_SLI, LM32_INSN_SR, LM32_INSN_SRI, LM32_INSN_SRU
56 , LM32_INSN_SRUI, LM32_INSN_SUB, LM32_INSN_SW, LM32_INSN_USER
57 , LM32_INSN_WCSR, LM32_INSN_XOR, LM32_INSN_XORI, LM32_INSN_XNOR
58 , LM32_INSN_XNORI, LM32_INSN_BREAK, LM32_INSN_SCALL, LM32_INSN_BRET
59 , LM32_INSN_ERET, LM32_INSN_RET, LM32_INSN_MV, LM32_INSN_MVI
60 , LM32_INSN_MVUI, LM32_INSN_MVHI, LM32_INSN_MVA, LM32_INSN_NOT
61 , LM32_INSN_NOP, LM32_INSN_LBGPREL, LM32_INSN_LBUGPREL, LM32_INSN_LHGPREL
62 , LM32_INSN_LHUGPREL, LM32_INSN_LWGPREL, LM32_INSN_SBGPREL, LM32_INSN_SHGPREL
63 , LM32_INSN_SWGPREL, LM32_INSN_LWGOTREL, LM32_INSN_ORHIGOTOFFI, LM32_INSN_ADDGOTOFF
64 , LM32_INSN_SWGOTOFF, LM32_INSN_LWGOTOFF, LM32_INSN_SHGOTOFF, LM32_INSN_LHGOTOFF
65 , LM32_INSN_LHUGOTOFF, LM32_INSN_SBGOTOFF, LM32_INSN_LBGOTOFF, LM32_INSN_LBUGOTOFF
66} CGEN_INSN_TYPE;
67
68/* Index of `invalid' insn place holder. */
69#define CGEN_INSN_INVALID LM32_INSN_INVALID
70
71/* Total number of insns in table. */
72#define MAX_INSNS ((int) LM32_INSN_LBUGOTOFF + 1)
73
74/* This struct records data prior to insertion or after extraction. */
75struct cgen_fields
76{
77 int length;
78 long f_nil;
79 long f_anyof;
80 long f_opcode;
81 long f_r0;
82 long f_r1;
83 long f_r2;
84 long f_resv0;
85 long f_shift;
86 long f_imm;
87 long f_uimm;
88 long f_csr;
89 long f_user;
90 long f_exception;
91 long f_branch;
92 long f_call;
93};
94
95#define CGEN_INIT_PARSE(od) \
96{\
97}
98#define CGEN_INIT_INSERT(od) \
99{\
100}
101#define CGEN_INIT_EXTRACT(od) \
102{\
103}
104#define CGEN_INIT_PRINT(od) \
105{\
106}
107
108
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109 #ifdef __cplusplus
110 }
111 #endif
112
84e94c90 113#endif /* LM32_OPC_H */
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