[deliverable/binutils-gdb.git] / opcodes / m10200-opc.c

/* Assemble Matsushita MN10200 instructions.
   Copyright (C) 1996-2014 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "sysdep.h"
#include "opcode/mn10200.h"

\f
const struct mn10200_operand mn10200_operands[] = {
#define UNUSED	0
  {0, 0, 0}, 

/* dn register in the first register operand position.  */
#define DN0      (UNUSED+1)
  {2, 0, MN10200_OPERAND_DREG},

/* dn register in the second register operand position.  */
#define DN1      (DN0+1)
  {2, 2, MN10200_OPERAND_DREG},

/* dm register in the first register operand position.  */
#define DM0      (DN1+1)
  {2, 0, MN10200_OPERAND_DREG},

/* dm register in the second register operand position.  */
#define DM1      (DM0+1)
  {2, 2, MN10200_OPERAND_DREG},

/* an register in the first register operand position.  */
#define AN0      (DM1+1)
  {2, 0, MN10200_OPERAND_AREG},

/* an register in the second register operand position.  */
#define AN1      (AN0+1)
  {2, 2, MN10200_OPERAND_AREG},

/* am register in the first register operand position.  */
#define AM0      (AN1+1)
  {2, 0, MN10200_OPERAND_AREG},

/* am register in the second register operand position.  */
#define AM1      (AM0+1)
  {2, 2, MN10200_OPERAND_AREG},

/* 8 bit unsigned immediate which may promote to a 16bit
   unsigned immediate.  */
#define IMM8    (AM1+1)
  {8, 0, MN10200_OPERAND_PROMOTE},

/* 16 bit unsigned immediate which may promote to a 32bit
   unsigned immediate.  */
#define IMM16    (IMM8+1)
  {16, 0, MN10200_OPERAND_PROMOTE},

/* 16 bit pc-relative immediate which may promote to a 16bit
   pc-relative immediate.  */
#define IMM16_PCREL    (IMM16+1)
  {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED},

/* 16bit unsigned dispacement in a memory operation which
   may promote to a 32bit displacement.  */
#define IMM16_MEM    (IMM16_PCREL+1)
  {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR},

/* 24 immediate, low 16 bits in the main instruction
   word, 8 in the extension word.  */

#define IMM24    (IMM16_MEM+1)
  {24, 0, MN10200_OPERAND_EXTENDED},

/* 32bit pc-relative offset.  */
#define IMM24_PCREL    (IMM24+1)
  {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED},

/* 32bit memory offset.  */
#define IMM24_MEM    (IMM24_PCREL+1)
  {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR},

/* Processor status word.  */
#define PSW    (IMM24_MEM+1)
  {0, 0, MN10200_OPERAND_PSW},

/* MDR register.  */
#define MDR    (PSW+1)
  {0, 0, MN10200_OPERAND_MDR},

/* Index register.  */
#define DI (MDR+1)
  {2, 4, MN10200_OPERAND_DREG},

/* 8 bit signed displacement, may promote to 16bit signed dispacement.  */
#define SD8    (DI+1)
  {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},

/* 16 bit signed displacement, may promote to 32bit dispacement.  */
#define SD16    (SD8+1)
  {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},

/* 8 bit pc-relative displacement.  */
#define SD8N_PCREL    (SD16+1)
  {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX},

/* 8 bit signed immediate which may promote to 16bit signed immediate.  */
#define SIMM8    (SD8N_PCREL+1)
  {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},

/* 16 bit signed immediate which may promote to 32bit  immediate.  */
#define SIMM16    (SIMM8+1)
  {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},

/* 16 bit signed immediate which may not promote.  */
#define SIMM16N    (SIMM16+1)
  {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK},

/* Either an open paren or close paren.  */
#define PAREN	(SIMM16N+1)
  {0, 0, MN10200_OPERAND_PAREN}, 

/* dn register that appears in the first and second register positions.  */
#define DN01     (PAREN+1)
  {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED},

/* an register that appears in the first and second register positions.  */
#define AN01     (DN01+1)
  {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
} ; 

#define MEM(ADDR) PAREN, ADDR, PAREN 
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct mn10200_opcode mn10200_opcodes[] = {
{ "mov",	0x8000,		0xf000,		FMT_2, {SIMM8, DN01}},
{ "mov",	0x80,		0xf0,		FMT_1, {DN1, DM0}},
{ "mov",	0xf230,		0xfff0,		FMT_4, {DM1, AN0}},
{ "mov",	0xf2f0,		0xfff0,		FMT_4, {AN1, DM0}},
{ "mov",	0xf270,		0xfff0,		FMT_4, {AN1, AM0}},
{ "mov",	0xf3f0,		0xfffc,		FMT_4, {PSW, DN0}},
{ "mov",	0xf3d0,		0xfff3,		FMT_4, {DN1, PSW}},
{ "mov",	0xf3e0,		0xfffc,		FMT_4, {MDR, DN0}},
{ "mov",	0xf3c0,		0xfff3,		FMT_4, {DN1, MDR}},
{ "mov",	0x20,		0xf0,		FMT_1, {MEM(AN1), DM0}},
{ "mov",	0x6000,		0xf000,		FMT_2, {MEM2(SD8, AN1), DM0}},
{ "mov",	0xf7c00000,	0xfff00000,	FMT_6, {MEM2(SD16, AN1), DM0}},
{ "mov",	0xf4800000,	0xfff00000,	FMT_7, {MEM2(IMM24,AN1), DM0}},
{ "mov",	0xf140,		0xffc0,		FMT_4, {MEM2(DI, AN1), DM0}},
{ "mov",	0xc80000,	0xfc0000,	FMT_3, {MEM(IMM16_MEM), DN0}},
{ "mov",	0xf4c00000,	0xfffc0000,	FMT_7, {MEM(IMM24_MEM), DN0}},
{ "mov",	0x7000,		0xf000,		FMT_2, {MEM2(SD8,AN1), AM0}},
{ "mov",	0x7000,		0xf000,		FMT_2, {MEM(AN1), AM0}},
{ "mov",	0xf7b00000,	0xfff00000,	FMT_6, {MEM2(SD16, AN1), AM0}},
{ "mov",	0xf4f00000,	0xfff00000,	FMT_7, {MEM2(IMM24,AN1), AM0}},
{ "mov",	0xf100,		0xffc0,		FMT_4, {MEM2(DI, AN1), AM0}},
{ "mov",	0xf7300000,	0xfffc0000,	FMT_6, {MEM(IMM16_MEM), AN0}},
{ "mov",	0xf4d00000,	0xfffc0000,	FMT_7, {MEM(IMM24_MEM), AN0}},
{ "mov",	0x00,		0xf0,		FMT_1, {DM0, MEM(AN1)}},
{ "mov",	0x4000,		0xf000,		FMT_2, {DM0, MEM2(SD8, AN1)}},
{ "mov",	0xf7800000,	0xfff00000,	FMT_6, {DM0, MEM2(SD16, AN1)}},
{ "mov",	0xf4000000,	0xfff00000,	FMT_7, {DM0, MEM2(IMM24, AN1)}},
{ "mov",	0xf1c0,		0xffc0,		FMT_4, {DM0, MEM2(DI, AN1)}},
{ "mov",	0xc00000,	0xfc0000,	FMT_3, {DN0, MEM(IMM16_MEM)}},
{ "mov",	0xf4400000,	0xfffc0000,	FMT_7, {DN0, MEM(IMM24_MEM)}},
{ "mov",	0x5000,		0xf000,		FMT_2, {AM0, MEM2(SD8, AN1)}},
{ "mov",	0x5000,		0xf000,		FMT_2, {AM0, MEM(AN1)}},
{ "mov",	0xf7a00000,	0xfff00000,	FMT_6, {AM0, MEM2(SD16, AN1)}},
{ "mov",	0xf4100000,	0xfff00000,	FMT_7, {AM0, MEM2(IMM24,AN1)}},
{ "mov",	0xf180,		0xffc0,		FMT_4, {AM0, MEM2(DI, AN1)}},
{ "mov",	0xf7200000,	0xfffc0000,	FMT_6, {AN0, MEM(IMM16_MEM)}},
{ "mov",	0xf4500000,	0xfffc0000,	FMT_7, {AN0, MEM(IMM24_MEM)}},
{ "mov",	0xf80000,	0xfc0000,	FMT_3, {SIMM16, DN0}},
{ "mov",	0xf4700000,	0xfffc0000,	FMT_7, {IMM24, DN0}},
{ "mov",	0xdc0000,	0xfc0000,	FMT_3, {IMM16, AN0}},
{ "mov",	0xf4740000,	0xfffc0000,	FMT_7, {IMM24, AN0}},

{ "movx",	0xf57000,	0xfff000,	FMT_5, {MEM2(SD8, AN1), DM0}},
{ "movx",	0xf7700000,	0xfff00000,	FMT_6, {MEM2(SD16, AN1), DM0}},
{ "movx",	0xf4b00000,	0xfff00000,	FMT_7, {MEM2(IMM24,AN1), DM0}},
{ "movx",	0xf55000,	0xfff000,	FMT_5, {DM0, MEM2(SD8, AN1)}},
{ "movx",	0xf7600000,	0xfff00000,	FMT_6, {DM0, MEM2(SD16, AN1)}},
{ "movx",	0xf4300000,	0xfff00000,	FMT_7, {DM0, MEM2(IMM24, AN1)}},

{ "movb",	0xf52000,	0xfff000,	FMT_5, {MEM2(SD8, AN1), DM0}},
{ "movb",	0xf7d00000,	0xfff00000,	FMT_6, {MEM2(SD16, AN1), DM0}},
{ "movb",	0xf4a00000,	0xfff00000,	FMT_7, {MEM2(IMM24,AN1), DM0}},
{ "movb",	0xf040,		0xffc0,		FMT_4, {MEM2(DI, AN1), DM0}},
{ "movb",	0xf4c40000,	0xfffc0000,	FMT_7, {MEM(IMM24_MEM), DN0}},
{ "movb",	0x10,		0xf0,		FMT_1, {DM0, MEM(AN1)}},
{ "movb",	0xf51000,	0xfff000,	FMT_5, {DM0, MEM2(SD8, AN1)}},
{ "movb",	0xf7900000,	0xfff00000,	FMT_6, {DM0, MEM2(SD16, AN1)}},
{ "movb",	0xf4200000,	0xfff00000,	FMT_7, {DM0, MEM2(IMM24, AN1)}},
{ "movb",	0xf0c0,		0xffc0,		FMT_4, {DM0, MEM2(DI, AN1)}},
{ "movb",	0xc40000,	0xfc0000,	FMT_3, {DN0, MEM(IMM16_MEM)}},
{ "movb",	0xf4440000,	0xfffc0000,	FMT_7, {DN0, MEM(IMM24_MEM)}},

{ "movbu",	0x30,		0xf0,		FMT_1, {MEM(AN1), DM0}},
{ "movbu",	0xf53000,	0xfff000,	FMT_5, {MEM2(SD8, AN1), DM0}},
{ "movbu",	0xf7500000,	0xfff00000,	FMT_6, {MEM2(SD16, AN1), DM0}},
{ "movbu",	0xf4900000,	0xfff00000,	FMT_7, {MEM2(IMM24,AN1), DM0}},
{ "movbu",	0xf080,		0xffc0,		FMT_4, {MEM2(DI, AN1), DM0}},
{ "movbu",	0xcc0000,	0xfc0000,	FMT_3, {MEM(IMM16_MEM), DN0}},
{ "movbu",	0xf4c80000,	0xfffc0000,	FMT_7, {MEM(IMM24_MEM), DN0}},

{ "ext",	0xf3c1,		0xfff3,		FMT_4, {DN1}},
{ "extx",	0xb0, 		0xfc,		FMT_1, {DN0}},
{ "extxu",	0xb4,		0xfc,		FMT_1, {DN0}},
{ "extxb",	0xb8,		0xfc,		FMT_1, {DN0}},
{ "extxbu",	0xbc,		0xfc,		FMT_1, {DN0}},

{ "add",	0x90,		0xf0,		FMT_1, {DN1, DM0}},
{ "add",	0xf200,		0xfff0,		FMT_4, {DM1, AN0}},
{ "add",	0xf2c0,		0xfff0,		FMT_4, {AN1, DM0}},
{ "add",	0xf240,		0xfff0,		FMT_4, {AN1, AM0}},
{ "add",	0xd400,		0xfc00,		FMT_2, {SIMM8, DN0}},
{ "add",	0xf7180000,	0xfffc0000,	FMT_6, {SIMM16, DN0}},
{ "add",	0xf4600000,	0xfffc0000,	FMT_7, {IMM24, DN0}},
{ "add",	0xd000,		0xfc00,		FMT_2, {SIMM8, AN0}},
{ "add",	0xf7080000,	0xfffc0000,	FMT_6, {SIMM16, AN0}},
{ "add",	0xf4640000,	0xfffc0000,	FMT_7, {IMM24, AN0}},
{ "addc",	0xf280,		0xfff0,		FMT_4, {DN1, DM0}},
{ "addnf",	0xf50c00,	0xfffc00,	FMT_5, {SIMM8, AN0}},

{ "sub",	0xa0,		0xf0,		FMT_1, {DN1, DM0}},
{ "sub",	0xf210,		0xfff0,		FMT_4, {DN1, AN0}},
{ "sub",	0xf2d0,		0xfff0,		FMT_4, {AN1, DM0}},
{ "sub",	0xf250,		0xfff0,		FMT_4, {AN1, AM0}},
{ "sub",	0xf71c0000,	0xfffc0000,	FMT_6, {IMM16, DN0}},
{ "sub",	0xf4680000,	0xfffc0000,	FMT_7, {IMM24, DN0}},
{ "sub",	0xf70c0000,	0xfffc0000,	FMT_6, {IMM16, AN0}},
{ "sub",	0xf46c0000,	0xfffc0000,	FMT_7, {IMM24, AN0}},
{ "subc",	0xf290,		0xfff0,		FMT_4, {DN1, DM0}},

{ "mul",	0xf340,		0xfff0,		FMT_4, {DN1, DM0}},
{ "mulu",	0xf350,		0xfff0,		FMT_4, {DN1, DM0}},

{ "divu",	0xf360,		0xfff0,		FMT_4, {DN1, DM0}},

{ "cmp",	0xf390,		0xfff0,		FMT_4, {DN1, DM0}},
{ "cmp",	0xf220,		0xfff0,		FMT_4, {DM1, AN0}},
{ "cmp",	0xf2e0,		0xfff0,		FMT_4, {AN1, DM0}},
{ "cmp",	0xf260,		0xfff0,		FMT_4, {AN1, AM0}},
{ "cmp",	0xd800,		0xfc00,		FMT_2, {SIMM8, DN0}},
{ "cmp",	0xf7480000,	0xfffc0000,	FMT_6, {SIMM16, DN0}},
{ "cmp",	0xf4780000,	0xfffc0000,	FMT_7, {IMM24, DN0}},
{ "cmp",	0xec0000,	0xfc0000,	FMT_3, {IMM16, AN0}},
{ "cmp",	0xf47c0000,	0xfffc0000,	FMT_7, {IMM24, AN0}},

{ "and",	0xf300,		0xfff0,		FMT_4, {DN1, DM0}},
{ "and",	0xf50000,	0xfffc00,	FMT_5, {IMM8, DN0}},
{ "and",	0xf7000000,	0xfffc0000,	FMT_6, {SIMM16N, DN0}},
{ "and",	0xf7100000,	0xffff0000,	FMT_6, {SIMM16N, PSW}},
{ "or",		0xf310,		0xfff0,		FMT_4, {DN1, DM0}},
{ "or",		0xf50800,	0xfffc00,	FMT_5, {IMM8, DN0}},
{ "or",		0xf7400000,	0xfffc0000,	FMT_6, {SIMM16N, DN0}},
{ "or",		0xf7140000,	0xffff0000,	FMT_6, {SIMM16N, PSW}},
{ "xor",	0xf320,		0xfff0,		FMT_4, {DN1, DM0}},
{ "xor",	0xf74c0000,	0xfffc0000,	FMT_6, {SIMM16N, DN0}},
{ "not",	0xf3e4,		0xfffc,		FMT_4, {DN0}},

{ "asr",	0xf338,		0xfffc,		FMT_4, {DN0}},
{ "lsr",	0xf33c,		0xfffc,		FMT_4, {DN0}},
{ "ror",	0xf334,		0xfffc,		FMT_4, {DN0}},
{ "rol",	0xf330,		0xfffc,		FMT_4, {DN0}},

{ "btst",	0xf50400,	0xfffc00,	FMT_5, {IMM8, DN0}},
{ "btst",	0xf7040000,	0xfffc0000,	FMT_6, {SIMM16N, DN0}},
{ "bset",	0xf020,		0xfff0,		FMT_4, {DM0, MEM(AN1)}},
{ "bclr",	0xf030,		0xfff0,		FMT_4, {DM0, MEM(AN1)}},

{ "beq",	0xe800,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bne",	0xe900,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "blt",	0xe000,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "ble",	0xe300,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bge",	0xe200,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bgt",	0xe100,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bcs",	0xe400,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bls",	0xe700,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bcc",	0xe600,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bhi",	0xe500,		0xff00,		FMT_2, {SD8N_PCREL}},
{ "bvc",	0xf5fc00,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bvs",	0xf5fd00,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bnc",	0xf5fe00,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bns",	0xf5ff00,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bra",	0xea00,		0xff00,		FMT_2, {SD8N_PCREL}},

{ "beqx",	0xf5e800,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bnex",	0xf5e900,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bltx",	0xf5e000,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "blex",	0xf5e300,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bgex",	0xf5e200,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bgtx",	0xf5e100,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bcsx",	0xf5e400,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "blsx",	0xf5e700,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bccx",	0xf5e600,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bhix",	0xf5e500,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bvcx",	0xf5ec00,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bvsx",	0xf5ed00,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bncx",	0xf5ee00,	0xffff00,	FMT_5, {SD8N_PCREL}},
{ "bnsx",	0xf5ef00,	0xffff00,	FMT_5, {SD8N_PCREL}},

{ "jmp",	0xfc0000,	0xff0000,	FMT_3, {IMM16_PCREL}},
{ "jmp",	0xf4e00000,	0xffff0000,	FMT_7, {IMM24_PCREL}},
{ "jmp",	0xf000,		0xfff3,		FMT_4, {PAREN,AN1,PAREN}},
{ "jsr",	0xfd0000,	0xff0000,	FMT_3, {IMM16_PCREL}},
{ "jsr",	0xf4e10000,	0xffff0000,	FMT_7, {IMM24_PCREL}},
{ "jsr",	0xf001,		0xfff3,		FMT_4, {PAREN,AN1,PAREN}},

{ "nop",	0xf6,		0xff,		FMT_1, {UNUSED}},

{ "rts",	0xfe,		0xff,		FMT_1, {UNUSED}},
{ "rti",	0xeb,		0xff,		FMT_1, {UNUSED}},

/* Extension.  We need some instruction to trigger "emulated syscalls"
   for our simulator.  */
{ "syscall",	0xf010,		0xffff,		FMT_4, {UNUSED}},

/* Extension.  When talking to the simulator, gdb requires some instruction
   that will trigger a "breakpoint" (really just an instruction that isn't
   otherwise used by the tools.  This instruction must be the same size
   as the smallest instruction on the target machine.  In the case of the
   mn10x00 the "break" instruction must be one byte.  0xff is available on
   both mn10x00 architectures.  */
{ "break",      0xff,           0xff,           FMT_1, {UNUSED}},

{ 0, 0, 0, 0, {0}},

} ;

const int mn10200_num_opcodes =
  sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);

\f
Commit	Line	Data
252b5132	1	/* Assemble Matsushita MN10200 instructions.
4b95cf5c	2	Copyright (C) 1996-2014 Free Software Foundation, Inc.
252b5132	3
9b201bb5	4	This file is part of the GNU opcodes library.
252b5132	5
9b201bb5 NC	6	This library is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 3, or (at your option)
	9	any later version.
252b5132	10
9b201bb5 NC	11	It is distributed in the hope that it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	14	License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
	19	MA 02110-1301, USA. */
252b5132	20
0d8dfecf	21	#include "sysdep.h"
252b5132 RH	22	#include "opcode/mn10200.h"
	23
	24	\f
	25	const struct mn10200_operand mn10200_operands[] = {
	26	#define UNUSED 0
	27	{0, 0, 0},
	28
	29	/* dn register in the first register operand position. */
	30	#define DN0 (UNUSED+1)
	31	{2, 0, MN10200_OPERAND_DREG},
	32
	33	/* dn register in the second register operand position. */
	34	#define DN1 (DN0+1)
	35	{2, 2, MN10200_OPERAND_DREG},
	36
	37	/* dm register in the first register operand position. */
	38	#define DM0 (DN1+1)
	39	{2, 0, MN10200_OPERAND_DREG},
	40
	41	/* dm register in the second register operand position. */
	42	#define DM1 (DM0+1)
	43	{2, 2, MN10200_OPERAND_DREG},
	44
	45	/* an register in the first register operand position. */
	46	#define AN0 (DM1+1)
	47	{2, 0, MN10200_OPERAND_AREG},
	48
	49	/* an register in the second register operand position. */
	50	#define AN1 (AN0+1)
	51	{2, 2, MN10200_OPERAND_AREG},
	52
	53	/* am register in the first register operand position. */
	54	#define AM0 (AN1+1)
	55	{2, 0, MN10200_OPERAND_AREG},
	56
	57	/* am register in the second register operand position. */
	58	#define AM1 (AM0+1)
	59	{2, 2, MN10200_OPERAND_AREG},
	60
	61	/* 8 bit unsigned immediate which may promote to a 16bit
	62	unsigned immediate. */
	63	#define IMM8 (AM1+1)
	64	{8, 0, MN10200_OPERAND_PROMOTE},
	65
	66	/* 16 bit unsigned immediate which may promote to a 32bit
	67	unsigned immediate. */
	68	#define IMM16 (IMM8+1)
	69	{16, 0, MN10200_OPERAND_PROMOTE},
	70
	71	/* 16 bit pc-relative immediate which may promote to a 16bit
	72	pc-relative immediate. */
	73	#define IMM16_PCREL (IMM16+1)
	74	{16, 0, MN10200_OPERAND_PCREL \| MN10200_OPERAND_RELAX \| MN10200_OPERAND_SIGNED},
	75
	76	/* 16bit unsigned dispacement in a memory operation which
	77	may promote to a 32bit displacement. */
	78	#define IMM16_MEM (IMM16_PCREL+1)
	79	{16, 0, MN10200_OPERAND_PROMOTE \| MN10200_OPERAND_MEMADDR},
	80
	81	/* 24 immediate, low 16 bits in the main instruction
	82	word, 8 in the extension word. */
	83
	84	#define IMM24 (IMM16_MEM+1)
	85	{24, 0, MN10200_OPERAND_EXTENDED},
86
87	/* 32bit pc-relative offset. */
88	#define IMM24_PCREL (IMM24+1)
89	{24, 0, MN10200_OPERAND_EXTENDED \| MN10200_OPERAND_PCREL \| MN10200_OPERAND_SIGNED},
90
91	/* 32bit memory offset. */
92	#define IMM24_MEM (IMM24_PCREL+1)
93	{24, 0, MN10200_OPERAND_EXTENDED \| MN10200_OPERAND_MEMADDR},
94
95	/* Processor status word. */
96	#define PSW (IMM24_MEM+1)
97	{0, 0, MN10200_OPERAND_PSW},
98
99	/* MDR register. */
100	#define MDR (PSW+1)
101	{0, 0, MN10200_OPERAND_MDR},
102
103	/* Index register. */
104	#define DI (MDR+1)
105	{2, 4, MN10200_OPERAND_DREG},
106
107	/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
108	#define SD8 (DI+1)
109	{8, 0, MN10200_OPERAND_SIGNED \| MN10200_OPERAND_PROMOTE},
110
111	/* 16 bit signed displacement, may promote to 32bit dispacement. */
112	#define SD16 (SD8+1)
113	{16, 0, MN10200_OPERAND_SIGNED \| MN10200_OPERAND_PROMOTE},
114
115	/* 8 bit pc-relative displacement. */
116	#define SD8N_PCREL (SD16+1)
117	{8, 0, MN10200_OPERAND_SIGNED \| MN10200_OPERAND_PCREL \| MN10200_OPERAND_RELAX},
118
119	/* 8 bit signed immediate which may promote to 16bit signed immediate. */
120	#define SIMM8 (SD8N_PCREL+1)
121	{8, 0, MN10200_OPERAND_SIGNED \| MN10200_OPERAND_PROMOTE},
122
123	/* 16 bit signed immediate which may promote to 32bit immediate. */
124	#define SIMM16 (SIMM8+1)
125	{16, 0, MN10200_OPERAND_SIGNED \| MN10200_OPERAND_PROMOTE},
126
127	/* 16 bit signed immediate which may not promote. */
128	#define SIMM16N (SIMM16+1)
129	{16, 0, MN10200_OPERAND_SIGNED \| MN10200_OPERAND_NOCHECK},
130
131	/* Either an open paren or close paren. */
132	#define PAREN (SIMM16N+1)
133	{0, 0, MN10200_OPERAND_PAREN},
134
135	/* dn register that appears in the first and second register positions. */
136	#define DN01 (PAREN+1)
137	{2, 0, MN10200_OPERAND_DREG \| MN10200_OPERAND_REPEATED},
138
139	/* an register that appears in the first and second register positions. */
140	#define AN01 (DN01+1)
141	{2, 0, MN10200_OPERAND_AREG \| MN10200_OPERAND_REPEATED},
142	} ;
143
144	#define MEM(ADDR) PAREN, ADDR, PAREN
145	#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
146	\f
147	/* The opcode table.
148
149	The format of the opcode table is:
150
151	NAME OPCODE MASK { OPERANDS }
152
153	NAME is the name of the instruction.
154	OPCODE is the instruction opcode.
155	MASK is the opcode mask; this is used to tell the disassembler
156	which bits in the actual opcode must match OPCODE.
157	OPERANDS is the list of operands.
158
159	The disassembler reads the table in order and prints the first
160	instruction which matches, so this table is sorted to put more
161	specific instructions before more general instructions. It is also
162	sorted by major opcode. */
163
164	const struct mn10200_opcode mn10200_opcodes[] = {
165	{ "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}},
166	{ "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}},
167	{ "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
168	{ "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}},
169	{ "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}},
170	{ "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
171	{ "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
172	{ "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
173	{ "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
174	{ "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}},
175	{ "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
176	{ "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
177	{ "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
178	{ "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
179	{ "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
180	{ "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
181	{ "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
182	{ "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}},
183	{ "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
184	{ "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
185	{ "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
186	{ "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}},
187	{ "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}},
188	{ "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}},
189	{ "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}},
190	{ "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
191	{ "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
192	{ "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
193	{ "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
194	{ "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
195	{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}},
196	{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}},
197	{ "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}},
198	{ "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
199	{ "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}},
200	{ "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}},
201	{ "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}},
202	{ "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
203	{ "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
204	{ "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
205	{ "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
206
207	{ "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
208	{ "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
209	{ "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
210	{ "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
211	{ "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
212	{ "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
213
214	{ "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
215	{ "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
216	{ "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
217	{ "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
218	{ "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
219	{ "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}},
220	{ "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
221	{ "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
222	{ "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
223	{ "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
224	{ "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
225	{ "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
226
227	{ "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}},
228	{ "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
229	{ "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
230	{ "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
231	{ "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
232	{ "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
233	{ "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
234
235	{ "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}},
236	{ "extx", 0xb0, 0xfc, FMT_1, {DN0}},
237	{ "extxu", 0xb4, 0xfc, FMT_1, {DN0}},
238	{ "extxb", 0xb8, 0xfc, FMT_1, {DN0}},
239	{ "extxbu", 0xbc, 0xfc, FMT_1, {DN0}},
240
241	{ "add", 0x90, 0xf0, FMT_1, {DN1, DM0}},
242	{ "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
243	{ "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}},
244	{ "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}},
245	{ "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
246	{ "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
247	{ "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}},
248	{ "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
249	{ "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}},
250	{ "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}},
251	{ "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}},
252	{ "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
253
254	{ "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}},
255	{ "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
256	{ "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}},
257	{ "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}},
258	{ "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}},
259	{ "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}},
260	{ "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}},
261	{ "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
262	{ "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}},
263
264	{ "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}},
265	{ "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}},
266
267	{ "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}},
268
269	{ "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}},
270	{ "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
271	{ "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}},
272	{ "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}},
273	{ "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
274	{ "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
275	{ "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}},
276	{ "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}},
277	{ "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
278
279	{ "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}},
280	{ "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}},
281	{ "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
282	{ "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
283	{ "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}},
284	{ "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}},
285	{ "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
286	{ "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
287	{ "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}},
288	{ "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
289	{ "not", 0xf3e4, 0xfffc, FMT_4, {DN0}},
290
291	{ "asr", 0xf338, 0xfffc, FMT_4, {DN0}},
292	{ "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}},
293	{ "ror", 0xf334, 0xfffc, FMT_4, {DN0}},
294	{ "rol", 0xf330, 0xfffc, FMT_4, {DN0}},
295
296	{ "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}},
297	{ "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
298	{ "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
299	{ "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
300
301	{ "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}},
302	{ "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}},
303	{ "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}},
304	{ "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}},
305	{ "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}},
306	{ "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}},
307	{ "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}},
308	{ "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}},
309	{ "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}},
310	{ "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}},
311	{ "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}},
312	{ "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}},
313	{ "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}},
314	{ "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}},
315	{ "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}},
316
317	{ "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}},
318	{ "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}},
319	{ "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}},
320	{ "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}},
321	{ "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}},
322	{ "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}},
323	{ "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}},
324	{ "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}},
325	{ "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}},
326	{ "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}},
327	{ "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}},
328	{ "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}},
329	{ "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}},
330	{ "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}},
331
332	{ "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}},
333	{ "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}},
334	{ "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
335	{ "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}},
336	{ "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}},
337	{ "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
338
339	{ "nop", 0xf6, 0xff, FMT_1, {UNUSED}},
340
341	{ "rts", 0xfe, 0xff, FMT_1, {UNUSED}},
342	{ "rti", 0xeb, 0xff, FMT_1, {UNUSED}},
343
344	/* Extension. We need some instruction to trigger "emulated syscalls"
345	for our simulator. */
346	{ "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}},
347
348	/* Extension. When talking to the simulator, gdb requires some instruction
349	that will trigger a "breakpoint" (really just an instruction that isn't
350	otherwise used by the tools. This instruction must be the same size
351	as the smallest instruction on the target machine. In the case of the
352	mn10x00 the "break" instruction must be one byte. 0xff is available on
353	both mn10x00 architectures. */
354	{ "break", 0xff, 0xff, FMT_1, {UNUSED}},
355
356	{ 0, 0, 0, 0, {0}},
357
358	} ;
359
360	const int mn10200_num_opcodes =
361	sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);
362
363	\f