projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 252b5132 | 1 | /* Assemble Matsushita MN10300 instructions. |
| d164ea7f | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2004 Free Software Foundation, Inc. |
| 252b5132 RH |
3 | |
| 4 | This program is free software; you can redistribute it and/or modify | |
| 5 | it under the terms of the GNU General Public License as published by | |
| 6 | the Free Software Foundation; either version 2 of the License, or | |
| 7 | (at your option) any later version. | |
| 8 | ||
| 9 | This program is distributed in the hope that it will be useful, | |
| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | GNU General Public License for more details. | |
| 13 | ||
| 14 | You should have received a copy of the GNU General Public License | |
| 15 | along with this program; if not, write to the Free Software | |
| 16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
| 17 | ||
| 18 | /* This file is formatted at > 80 columns. Attempting to read it on a | |
| 19 | screeen with less than 80 columns will be difficult. */ | |
| 0d8dfecf | 20 | #include "sysdep.h" |
| 252b5132 RH |
21 | #include "opcode/mn10300.h" |
| 22 | ||
| 23 | \f | |
| 24 | const struct mn10300_operand mn10300_operands[] = { | |
| 25 | #define UNUSED 0 | |
| 26 | {0, 0, 0}, | |
| 27 | ||
| 28 | /* dn register in the first register operand position. */ | |
| 29 | #define DN0 (UNUSED+1) | |
| 30 | {2, 0, MN10300_OPERAND_DREG}, | |
| 31 | ||
| 32 | /* dn register in the second register operand position. */ | |
| 33 | #define DN1 (DN0+1) | |
| 34 | {2, 2, MN10300_OPERAND_DREG}, | |
| 35 | ||
| 36 | /* dn register in the third register operand position. */ | |
| 37 | #define DN2 (DN1+1) | |
| 38 | {2, 4, MN10300_OPERAND_DREG}, | |
| 39 | ||
| 40 | /* dm register in the first register operand position. */ | |
| 41 | #define DM0 (DN2+1) | |
| 42 | {2, 0, MN10300_OPERAND_DREG}, | |
| 43 | ||
| 44 | /* dm register in the second register operand position. */ | |
| 45 | #define DM1 (DM0+1) | |
| 46 | {2, 2, MN10300_OPERAND_DREG}, | |
| 47 | ||
| 48 | /* dm register in the third register operand position. */ | |
| 49 | #define DM2 (DM1+1) | |
| 50 | {2, 4, MN10300_OPERAND_DREG}, | |
| 51 | ||
| 52 | /* an register in the first register operand position. */ | |
| 53 | #define AN0 (DM2+1) | |
| 54 | {2, 0, MN10300_OPERAND_AREG}, | |
| 55 | ||
| 56 | /* an register in the second register operand position. */ | |
| 57 | #define AN1 (AN0+1) | |
| 58 | {2, 2, MN10300_OPERAND_AREG}, | |
| 59 | ||
| 60 | /* an register in the third register operand position. */ | |
| 61 | #define AN2 (AN1+1) | |
| 62 | {2, 4, MN10300_OPERAND_AREG}, | |
| 63 | ||
| 64 | /* am register in the first register operand position. */ | |
| 65 | #define AM0 (AN2+1) | |
| 66 | {2, 0, MN10300_OPERAND_AREG}, | |
| 67 | ||
| 68 | /* am register in the second register operand position. */ | |
| 69 | #define AM1 (AM0+1) | |
| 70 | {2, 2, MN10300_OPERAND_AREG}, | |
| 71 | ||
| 72 | /* am register in the third register operand position. */ | |
| 73 | #define AM2 (AM1+1) | |
| 74 | {2, 4, MN10300_OPERAND_AREG}, | |
| 75 | ||
| 76 | /* 8 bit unsigned immediate which may promote to a 16bit | |
| 77 | unsigned immediate. */ | |
| 78 | #define IMM8 (AM2+1) | |
| 79 | {8, 0, MN10300_OPERAND_PROMOTE}, | |
| 80 | ||
| 81 | /* 16 bit unsigned immediate which may promote to a 32bit | |
| 82 | unsigned immediate. */ | |
| 83 | #define IMM16 (IMM8+1) | |
| 84 | {16, 0, MN10300_OPERAND_PROMOTE}, | |
| 85 | ||
| 86 | /* 16 bit pc-relative immediate which may promote to a 16bit | |
| 87 | pc-relative immediate. */ | |
| 88 | #define IMM16_PCREL (IMM16+1) | |
| 89 | {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, | |
| 90 | ||
| fa5e0d8d | 91 | /* 16bit unsigned displacement in a memory operation which |
| 252b5132 RH |
92 | may promote to a 32bit displacement. */ |
| 93 | #define IMM16_MEM (IMM16_PCREL+1) | |
| 94 | {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, | |
| 95 | ||
| 96 | /* 32bit immediate, high 16 bits in the main instruction | |
| 97 | word, 16bits in the extension word. | |
| 98 | ||
| 99 | The "bits" field indicates how many bits are in the | |
| 100 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 101 | #define IMM32 (IMM16_MEM+1) | |
| 102 | {16, 0, MN10300_OPERAND_SPLIT}, | |
| 103 | ||
| 104 | /* 32bit pc-relative offset. */ | |
| 105 | #define IMM32_PCREL (IMM32+1) | |
| 106 | {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, | |
| 107 | ||
| 108 | /* 32bit memory offset. */ | |
| 109 | #define IMM32_MEM (IMM32_PCREL+1) | |
| 110 | {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, | |
| 111 | ||
| 112 | /* 32bit immediate, high 16 bits in the main instruction | |
| 113 | word, 16bits in the extension word, low 16bits are left | |
| 114 | shifted 8 places. | |
| 115 | ||
| 116 | The "bits" field indicates how many bits are in the | |
| 117 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 118 | #define IMM32_LOWSHIFT8 (IMM32_MEM+1) | |
| 119 | {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, | |
| 120 | ||
| 121 | /* 32bit immediate, high 24 bits in the main instruction | |
| 122 | word, 8 in the extension word. | |
| 123 | ||
| 124 | The "bits" field indicates how many bits are in the | |
| 125 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 126 | #define IMM32_HIGH24 (IMM32_LOWSHIFT8+1) | |
| 127 | {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, | |
| 128 | ||
| 129 | /* 32bit immediate, high 24 bits in the main instruction | |
| 130 | word, 8 in the extension word, low 8 bits are left | |
| 131 | shifted 16 places. | |
| 132 | ||
| 133 | The "bits" field indicates how many bits are in the | |
| 134 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 135 | #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) | |
| 136 | {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, | |
| 137 | ||
| 138 | /* Stack pointer. */ | |
| 139 | #define SP (IMM32_HIGH24_LOWSHIFT16+1) | |
| 140 | {8, 0, MN10300_OPERAND_SP}, | |
| 141 | ||
| 142 | /* Processor status word. */ | |
| 143 | #define PSW (SP+1) | |
| 144 | {0, 0, MN10300_OPERAND_PSW}, | |
| 145 | ||
| 146 | /* MDR register. */ | |
| 147 | #define MDR (PSW+1) | |
| 148 | {0, 0, MN10300_OPERAND_MDR}, | |
| 149 | ||
| 150 | /* Index register. */ | |
| 151 | #define DI (MDR+1) | |
| 152 | {2, 2, MN10300_OPERAND_DREG}, | |
| 153 | ||
| fa5e0d8d | 154 | /* 8 bit signed displacement, may promote to 16bit signed displacement. */ |
| 252b5132 RH |
155 | #define SD8 (DI+1) |
| 156 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 157 | ||
| fa5e0d8d | 158 | /* 16 bit signed displacement, may promote to 32bit displacement. */ |
| 252b5132 RH |
159 | #define SD16 (SD8+1) |
| 160 | {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 161 | ||
| 162 | /* 8 bit signed displacement that can not promote. */ | |
| 163 | #define SD8N (SD16+1) | |
| 164 | {8, 0, MN10300_OPERAND_SIGNED}, | |
| 165 | ||
| 166 | /* 8 bit pc-relative displacement. */ | |
| 167 | #define SD8N_PCREL (SD8N+1) | |
| 168 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX}, | |
| 169 | ||
| 170 | /* 8 bit signed displacement shifted left 8 bits in the instruction. */ | |
| 171 | #define SD8N_SHIFT8 (SD8N_PCREL+1) | |
| 172 | {8, 8, MN10300_OPERAND_SIGNED}, | |
| 173 | ||
| 174 | /* 8 bit signed immediate which may promote to 16bit signed immediate. */ | |
| 175 | #define SIMM8 (SD8N_SHIFT8+1) | |
| 176 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 177 | ||
| 178 | /* 16 bit signed immediate which may promote to 32bit immediate. */ | |
| 179 | #define SIMM16 (SIMM8+1) | |
| 180 | {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 181 | ||
| 182 | /* Either an open paren or close paren. */ | |
| 183 | #define PAREN (SIMM16+1) | |
| 184 | {0, 0, MN10300_OPERAND_PAREN}, | |
| 185 | ||
| 186 | /* dn register that appears in the first and second register positions. */ | |
| 187 | #define DN01 (PAREN+1) | |
| 188 | {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED}, | |
| 189 | ||
| 190 | /* an register that appears in the first and second register positions. */ | |
| 191 | #define AN01 (DN01+1) | |
| 192 | {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED}, | |
| 193 | ||
| 194 | /* 16bit pc-relative displacement which may promote to 32bit pc-relative | |
| 195 | displacement. */ | |
| 196 | #define D16_SHIFT (AN01+1) | |
| 197 | {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, | |
| 198 | ||
| 199 | /* 8 bit immediate found in the extension word. */ | |
| 200 | #define IMM8E (D16_SHIFT+1) | |
| 201 | {8, 0, MN10300_OPERAND_EXTENDED}, | |
| 202 | ||
| 203 | /* Register list found in the extension word shifted 8 bits left. */ | |
| 204 | #define REGSE_SHIFT8 (IMM8E+1) | |
| 205 | {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST}, | |
| 206 | ||
| 207 | /* Register list shifted 8 bits left. */ | |
| 208 | #define REGS_SHIFT8 (REGSE_SHIFT8 + 1) | |
| 209 | {8, 8, MN10300_OPERAND_REG_LIST}, | |
| 210 | ||
| 211 | /* Reigster list. */ | |
| 212 | #define REGS (REGS_SHIFT8+1) | |
| 213 | {8, 0, MN10300_OPERAND_REG_LIST}, | |
| 214 | ||
| a9af5e04 JL |
215 | /* UStack pointer. */ |
| 216 | #define USP (REGS+1) | |
| 217 | {0, 0, MN10300_OPERAND_USP}, | |
| 218 | ||
| 219 | /* SStack pointer. */ | |
| 220 | #define SSP (USP+1) | |
| 221 | {0, 0, MN10300_OPERAND_SSP}, | |
| 222 | ||
| 223 | /* MStack pointer. */ | |
| 224 | #define MSP (SSP+1) | |
| 225 | {0, 0, MN10300_OPERAND_MSP}, | |
| 226 | ||
| 227 | /* PC . */ | |
| 228 | #define PC (MSP+1) | |
| 229 | {0, 0, MN10300_OPERAND_PC}, | |
| 230 | ||
| 231 | /* 4 bit immediate for syscall. */ | |
| 232 | #define IMM4 (PC+1) | |
| 233 | {4, 0, 0}, | |
| 234 | ||
| 235 | /* Processor status word. */ | |
| 236 | #define EPSW (IMM4+1) | |
| 237 | {0, 0, MN10300_OPERAND_EPSW}, | |
| 238 | ||
| 239 | /* rn register in the first register operand position. */ | |
| 240 | #define RN0 (EPSW+1) | |
| 241 | {4, 0, MN10300_OPERAND_RREG}, | |
| 242 | ||
| 243 | /* rn register in the fourth register operand position. */ | |
| 244 | #define RN2 (RN0+1) | |
| 245 | {4, 4, MN10300_OPERAND_RREG}, | |
| 246 | ||
| 247 | /* rm register in the first register operand position. */ | |
| 248 | #define RM0 (RN2+1) | |
| 249 | {4, 0, MN10300_OPERAND_RREG}, | |
| 250 | ||
| 251 | /* rm register in the second register operand position. */ | |
| 252 | #define RM1 (RM0+1) | |
| 253 | {4, 2, MN10300_OPERAND_RREG}, | |
| 254 | ||
| 255 | /* rm register in the third register operand position. */ | |
| 256 | #define RM2 (RM1+1) | |
| 257 | {4, 4, MN10300_OPERAND_RREG}, | |
| 258 | ||
| 259 | #define RN02 (RM2+1) | |
| 260 | {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED}, | |
| 261 | ||
| 262 | #define XRN0 (RN02+1) | |
| 263 | {4, 0, MN10300_OPERAND_XRREG}, | |
| 264 | ||
| 265 | #define XRM2 (XRN0+1) | |
| 266 | {4, 4, MN10300_OPERAND_XRREG}, | |
| 267 | ||
| 268 | /* + for autoincrement */ | |
| 269 | #define PLUS (XRM2+1) | |
| 270 | {0, 0, MN10300_OPERAND_PLUS}, | |
| 271 | ||
| 272 | #define XRN02 (PLUS+1) | |
| 273 | {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED}, | |
| 274 | ||
| 275 | /* Ick */ | |
| 276 | #define RD0 (XRN02+1) | |
| 277 | {4, -8, MN10300_OPERAND_RREG}, | |
| 278 | ||
| 279 | #define RD2 (RD0+1) | |
| 280 | {4, -4, MN10300_OPERAND_RREG}, | |
| 281 | ||
| fa5e0d8d | 282 | /* 8 unsigned displacement in a memory operation which |
| a9af5e04 JL |
283 | may promote to a 32bit displacement. */ |
| 284 | #define IMM8_MEM (RD2+1) | |
| 285 | {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, | |
| 286 | ||
| 287 | /* Index register. */ | |
| 288 | #define RI (IMM8_MEM+1) | |
| 289 | {4, 4, MN10300_OPERAND_RREG}, | |
| 290 | ||
| fa5e0d8d | 291 | /* 24 bit signed displacement, may promote to 32bit displacement. */ |
| a9af5e04 JL |
292 | #define SD24 (RI+1) |
| 293 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 294 | ||
| 295 | /* 24 bit unsigned immediate which may promote to a 32bit | |
| 296 | unsigned immediate. */ | |
| 297 | #define IMM24 (SD24+1) | |
| 298 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE}, | |
| 299 | ||
| 300 | /* 24 bit signed immediate which may promote to a 32bit | |
| 301 | signed immediate. */ | |
| 302 | #define SIMM24 (IMM24+1) | |
| 303 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED}, | |
| 304 | ||
| fa5e0d8d | 305 | /* 24bit unsigned displacement in a memory operation which |
| a9af5e04 JL |
306 | may promote to a 32bit displacement. */ |
| 307 | #define IMM24_MEM (SIMM24+1) | |
| 308 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, | |
| fa5e0d8d AO |
309 | /* 32bit immediate, high 8 bits in the main instruction |
| 310 | word, 24 in the extension word. | |
| a9af5e04 JL |
311 | |
| 312 | The "bits" field indicates how many bits are in the | |
| 313 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 314 | #define IMM32_HIGH8 (IMM24_MEM+1) | |
| 315 | {8, 0, MN10300_OPERAND_SPLIT}, | |
| 316 | ||
| 317 | /* Similarly, but a memory address. */ | |
| 318 | #define IMM32_HIGH8_MEM (IMM32_HIGH8+1) | |
| 319 | {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, | |
| 320 | ||
| 321 | /* rm register in the seventh register operand position. */ | |
| 322 | #define RM6 (IMM32_HIGH8_MEM+1) | |
| 323 | {4, 12, MN10300_OPERAND_RREG}, | |
| 324 | ||
| 325 | /* rm register in the fifth register operand position. */ | |
| 326 | #define RN4 (RM6+1) | |
| 327 | {4, 8, MN10300_OPERAND_RREG}, | |
| 328 | ||
| 329 | /* 4 bit immediate for dsp instructions. */ | |
| 330 | #define IMM4_2 (RN4+1) | |
| 331 | {4, 4, 0}, | |
| 332 | ||
| 333 | /* 4 bit immediate for dsp instructions. */ | |
| 334 | #define SIMM4_2 (IMM4_2+1) | |
| 335 | {4, 4, MN10300_OPERAND_SIGNED}, | |
| 336 | ||
| 337 | /* 4 bit immediate for dsp instructions. */ | |
| 338 | #define SIMM4_6 (SIMM4_2+1) | |
| 339 | {4, 12, MN10300_OPERAND_SIGNED}, | |
| 252b5132 | 340 | |
| 40fa0207 AO |
341 | #define FPCR (SIMM4_6+1) |
| 342 | {0, 0, MN10300_OPERAND_FPCR}, | |
| 343 | ||
| 344 | /* We call f[sd]m registers those whose most significant bit is stored | |
| 345 | * within the opcode half-word, i.e., in a bit on the left of the 4 | |
| 346 | * least significant bits, and f[sd]n registers those whose most | |
| 347 | * significant bit is stored at the end of the full word, after the 4 | |
| 348 | * least significant bits. They're not numbered after their position | |
| 349 | * in the mnemonic asm instruction, but after their position in the | |
| 350 | * opcode word, i.e., depending on the amount of shift they need. | |
| 351 | * | |
| 352 | * The additional bit is shifted as follows: for `n' registers, it | |
| 353 | * will be shifted by (|shift|/4); for `m' registers, it will be | |
| 354 | * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose | |
| 355 | * specifications are only 3-bits long, the two least-significant bits | |
| 356 | * are shifted by 16, and the most-significant bit is shifted by -2 | |
| 357 | * (i.e., it's stored in the least significant bit of the full | |
| 358 | * word). */ | |
| 359 | ||
| 360 | /* fsm register in the first register operand position. */ | |
| 361 | #define FSM0 (FPCR+1) | |
| 362 | {5, 0, MN10300_OPERAND_FSREG }, | |
| 363 | ||
| 364 | /* fsm register in the second register operand position. */ | |
| 365 | #define FSM1 (FSM0+1) | |
| 366 | {5, 4, MN10300_OPERAND_FSREG }, | |
| 367 | ||
| 368 | /* fsm register in the third register operand position. */ | |
| 369 | #define FSM2 (FSM1+1) | |
| 370 | {5, 8, MN10300_OPERAND_FSREG }, | |
| 371 | ||
| 372 | /* fsm register in the fourth register operand position. */ | |
| 373 | #define FSM3 (FSM2+1) | |
| 374 | {5, 12, MN10300_OPERAND_FSREG }, | |
| 375 | ||
| 376 | /* fsn register in the first register operand position. */ | |
| 377 | #define FSN1 (FSM3+1) | |
| 378 | {5, -4, MN10300_OPERAND_FSREG }, | |
| 379 | ||
| 380 | /* fsn register in the second register operand position. */ | |
| 381 | #define FSN2 (FSN1+1) | |
| 382 | {5, -8, MN10300_OPERAND_FSREG }, | |
| 383 | ||
| 384 | /* fsm register in the third register operand position. */ | |
| 385 | #define FSN3 (FSN2+1) | |
| 386 | {5, -12, MN10300_OPERAND_FSREG }, | |
| 387 | ||
| 388 | /* fsm accumulator, in the fourth register operand position. */ | |
| 389 | #define FSACC (FSN3+1) | |
| 390 | {3, -16, MN10300_OPERAND_FSREG }, | |
| 391 | ||
| 392 | /* fdm register in the first register operand position. */ | |
| 393 | #define FDM0 (FSACC+1) | |
| 394 | {5, 0, MN10300_OPERAND_FDREG }, | |
| 395 | ||
| 396 | /* fdm register in the second register operand position. */ | |
| 397 | #define FDM1 (FDM0+1) | |
| 398 | {5, 4, MN10300_OPERAND_FDREG }, | |
| 399 | ||
| 400 | /* fdm register in the third register operand position. */ | |
| 401 | #define FDM2 (FDM1+1) | |
| 402 | {5, 8, MN10300_OPERAND_FDREG }, | |
| 403 | ||
| 404 | /* fdm register in the fourth register operand position. */ | |
| 405 | #define FDM3 (FDM2+1) | |
| 406 | {5, 12, MN10300_OPERAND_FDREG }, | |
| 407 | ||
| 408 | /* fdn register in the first register operand position. */ | |
| 409 | #define FDN1 (FDM3+1) | |
| 410 | {5, -4, MN10300_OPERAND_FDREG }, | |
| 411 | ||
| 412 | /* fdn register in the second register operand position. */ | |
| 413 | #define FDN2 (FDN1+1) | |
| 414 | {5, -8, MN10300_OPERAND_FDREG }, | |
| 415 | ||
| 416 | /* fdn register in the third register operand position. */ | |
| 417 | #define FDN3 (FDN2+1) | |
| 418 | {5, -12, MN10300_OPERAND_FDREG }, | |
| 419 | ||
| 252b5132 RH |
420 | } ; |
| 421 | ||
| 422 | #define MEM(ADDR) PAREN, ADDR, PAREN | |
| 423 | #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN | |
| 424 | #define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN | |
| 425 | #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN | |
| 426 | \f | |
| 427 | /* The opcode table. | |
| 428 | ||
| 429 | The format of the opcode table is: | |
| 430 | ||
| 431 | NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS } | |
| 432 | ||
| 433 | NAME is the name of the instruction. | |
| 434 | OPCODE is the instruction opcode. | |
| 435 | MASK is the opcode mask; this is used to tell the disassembler | |
| 436 | which bits in the actual opcode must match OPCODE. | |
| 437 | OPERANDS is the list of operands. | |
| 438 | ||
| 439 | The disassembler reads the table in order and prints the first | |
| 440 | instruction which matches, so this table is sorted to put more | |
| 441 | specific instructions before more general instructions. It is also | |
| 442 | sorted by major opcode. */ | |
| 443 | ||
| 444 | const struct mn10300_opcode mn10300_opcodes[] = { | |
| 445 | { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, | |
| 446 | { "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, | |
| 447 | { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, | |
| 448 | { "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, | |
| 449 | { "mov", 0x9000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, | |
| 450 | { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, | |
| 451 | { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}}, | |
| 452 | { "mov", 0xf2f0, 0xfff3, 0, FMT_D0, 0, {AM1, SP}}, | |
| 453 | { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}}, | |
| 454 | { "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}}, | |
| 455 | { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}}, | |
| 456 | { "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}}, | |
| 457 | { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, | |
| 458 | { "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}}, | |
| 459 | { "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, | |
| 460 | { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, | |
| 461 | { "mov", 0x5c00, 0xfcff, 0, FMT_S1, 0, {MEM(SP), AN0}}, | |
| 462 | { "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2, 0, {MEM(IMM16_MEM), AN0}}, | |
| 463 | { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, | |
| 464 | { "mov", 0x4200, 0xf3ff, 0, FMT_S1, 0, {DM1, MEM(SP)}}, | |
| 465 | { "mov", 0x010000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, | |
| 466 | { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}}, | |
| 467 | { "mov", 0x4300, 0xf3ff, 0, FMT_S1, 0, {AM1, MEM(SP)}}, | |
| 468 | { "mov", 0xfa800000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}}, | |
| 469 | { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, | |
| 470 | { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, | |
| 471 | { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, | |
| 472 | { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, | |
| 473 | { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, | |
| 474 | { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, | |
| 475 | { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, | |
| 476 | { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, | |
| 477 | { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, | |
| 478 | { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}}, | |
| 479 | { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, | |
| 480 | { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, | |
| 481 | { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, | |
| 482 | { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, | |
| 483 | { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, | |
| 484 | { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, | |
| 485 | { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, | |
| 486 | { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, | |
| 487 | { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, | |
| 488 | { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}}, | |
| 489 | ||
| a9af5e04 JL |
490 | { "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}}, |
| 491 | { "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}}, | |
| 492 | { "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}}, | |
| 493 | { "mov", 0xf02c, 0xfffc, 0, FMT_D0, AM33, {PC, AN0}}, | |
| 494 | { "mov", 0xf030, 0xfff3, 0, FMT_D0, AM33, {AN1, USP}}, | |
| 495 | { "mov", 0xf031, 0xfff3, 0, FMT_D0, AM33, {AN1, SSP}}, | |
| 496 | { "mov", 0xf032, 0xfff3, 0, FMT_D0, AM33, {AN1, MSP}}, | |
| 497 | { "mov", 0xf2ec, 0xfffc, 0, FMT_D0, AM33, {EPSW, DN0}}, | |
| 498 | { "mov", 0xf2f1, 0xfff3, 0, FMT_D0, AM33, {DM1, EPSW}}, | |
| 499 | { "mov", 0xf500, 0xffc0, 0, FMT_D0, AM33, {AM2, RN0}}, | |
| 500 | { "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}}, | |
| 501 | { "mov", 0xf580, 0xffc0, 0, FMT_D0, AM33, {RM1, AN0}}, | |
| 502 | { "mov", 0xf5c0, 0xffc0, 0, FMT_D0, AM33, {RM1, DN0}}, | |
| 503 | { "mov", 0xf90800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 504 | { "mov", 0xf9e800, 0xffff00, 0, FMT_D6, AM33, {XRM2, RN0}}, | |
| 505 | { "mov", 0xf9f800, 0xffff00, 0, FMT_D6, AM33, {RM2, XRN0}}, | |
| 506 | { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, | |
| 507 | { "mov", 0xf98a00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, | |
| 508 | { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, | |
| 509 | { "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, | |
| 510 | { "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, | |
| 511 | { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, | |
| 512 | { "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, | |
| 513 | { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, | |
| 514 | { "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, | |
| 515 | { "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, | |
| 516 | { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, | |
| 517 | { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, | |
| 518 | { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, | |
| 519 | { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, | |
| 520 | { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, | |
| 5728a7d7 AO |
521 | { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, |
| 522 | { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, | |
| 523 | { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, | |
| 524 | { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, | |
| a9af5e04 JL |
525 | { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, |
| 526 | { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, | |
| 527 | { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, | |
| 528 | { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, | |
| 529 | { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, | |
| 530 | { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, | |
| 531 | { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, | |
| 252b5132 RH |
532 | /* These must come after most of the other move instructions to avoid matching |
| 533 | a symbolic name with IMMxx operands. Ugh. */ | |
| 534 | { "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}}, | |
| 535 | { "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 536 | { "mov", 0x240000, 0xfc0000, 0, FMT_S2, 0, {IMM16, AN0}}, | |
| 537 | { "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, | |
| 538 | { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, | |
| 539 | { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, | |
| 540 | { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, | |
| 541 | { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, | |
| 542 | { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, | |
| 543 | { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, | |
| 544 | { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, | |
| 545 | { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, | |
| 546 | { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, | |
| 547 | { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, | |
| 548 | { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, | |
| 549 | { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, | |
| 550 | /* These non-promoting variants need to come after all the other memory | |
| 551 | moves. */ | |
| 552 | { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}}, | |
| 553 | { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}}, | |
| a9af5e04 JL |
554 | /* These are the same as the previous non-promoting versions. The am33 |
| 555 | does not have restrictions on the offsets used to load/store the stack | |
| 556 | pointer. */ | |
| 557 | { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, | |
| 558 | { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, | |
| 559 | /* These must come last so that we favor shorter move instructions for | |
| 560 | loading immediates into d0-d3/a0-a3. */ | |
| 561 | { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 562 | { "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 563 | { "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| d164ea7f AO |
564 | { "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, XRN02}}, |
| 565 | { "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}}, | |
| a9af5e04 JL |
566 | { "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}}, |
| 567 | { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, | |
| 568 | { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, | |
| 569 | { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, | |
| 570 | { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, | |
| 571 | { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, | |
| 572 | { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, | |
| 573 | ||
| 574 | { "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 575 | { "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 576 | { "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 577 | ||
| 578 | { "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}}, | |
| 579 | { "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}}, | |
| 580 | { "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, | |
| 581 | { "swap", 0xf9cb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 582 | { "swaph", 0xf690, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, | |
| 583 | { "swaph", 0xf9db00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 584 | { "getchx", 0xf6c0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, | |
| 585 | { "getclx", 0xf6d0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, | |
| 586 | { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, | |
| 587 | { "mac", 0xf90b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 588 | { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 589 | { "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 590 | { "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 591 | { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, | |
| 592 | { "macu", 0xf91b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 593 | { "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 594 | { "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 595 | { "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 596 | { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, | |
| 597 | { "macb", 0xf92b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 598 | { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 599 | { "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 600 | { "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 601 | { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, | |
| 602 | { "macbu", 0xf93b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 603 | { "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 604 | { "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 605 | { "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 606 | { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, | |
| 607 | { "mach", 0xf94b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 608 | { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 609 | { "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 610 | { "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 611 | { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, | |
| 612 | { "machu", 0xf95b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 613 | { "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 614 | { "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 615 | { "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 616 | { "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, | |
| 617 | { "dmach", 0xf96b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 618 | { "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 619 | { "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, | |
| 620 | { "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 621 | { "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 622 | { "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, | |
| 623 | { "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 624 | { "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 625 | { "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, | |
| 626 | { "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 627 | { "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 628 | { "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 629 | { "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 630 | { "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 252b5132 RH |
631 | |
| 632 | { "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, | |
| 633 | { "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, | |
| 634 | { "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, | |
| 635 | { "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, | |
| 636 | { "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, | |
| 637 | { "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, | |
| 638 | { "movbu", 0xf400, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, | |
| 639 | { "movbu", 0x340000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, | |
| 640 | { "movbu", 0xf050, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, | |
| 641 | { "movbu", 0xf85000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, | |
| 642 | { "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, | |
| 643 | { "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, | |
| 644 | { "movbu", 0xf89200, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, | |
| 645 | { "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, | |
| 646 | { "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, | |
| 647 | { "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, | |
| a9af5e04 JL |
648 | { "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, |
| 649 | { "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, | |
| 650 | { "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, | |
| 651 | { "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, | |
| 652 | { "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, | |
| 653 | { "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, | |
| 654 | { "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, | |
| 655 | { "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, | |
| 5728a7d7 AO |
656 | { "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, |
| 657 | { "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, | |
| 658 | { "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, | |
| 659 | { "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, | |
| a9af5e04 JL |
660 | { "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, |
| 661 | { "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, | |
| 662 | { "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, | |
| 663 | { "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, | |
| 664 | { "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, | |
| 665 | { "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, | |
| 252b5132 RH |
666 | { "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, |
| 667 | { "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, | |
| 668 | { "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, | |
| 669 | { "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, | |
| 670 | { "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, | |
| 671 | { "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, | |
| a9af5e04 JL |
672 | { "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, |
| 673 | { "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, | |
| 674 | { "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}}, | |
| 675 | { "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, | |
| 676 | { "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, | |
| 677 | { "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, | |
| 252b5132 RH |
678 | |
| 679 | { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, | |
| 680 | { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, | |
| 681 | { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, | |
| 682 | { "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, | |
| 683 | { "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, | |
| 684 | { "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, | |
| 685 | { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, | |
| 686 | { "movhu", 0x380000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, | |
| 687 | { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, | |
| 688 | { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, | |
| 689 | { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, | |
| 690 | { "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, | |
| 691 | { "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, | |
| 692 | { "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, | |
| 693 | { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, | |
| 694 | { "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, | |
| a9af5e04 JL |
695 | { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, |
| 696 | { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, | |
| 697 | { "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, | |
| 698 | { "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, | |
| 699 | { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, | |
| 700 | { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, | |
| 701 | { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, | |
| 702 | { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, | |
| 703 | { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, | |
| 704 | { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, | |
| 5728a7d7 AO |
705 | { "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, |
| 706 | { "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, | |
| 707 | { "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, | |
| 708 | { "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, | |
| a9af5e04 JL |
709 | { "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, |
| 710 | { "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, | |
| 711 | { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, | |
| 712 | { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, | |
| 252b5132 RH |
713 | { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, |
| 714 | { "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, | |
| 715 | { "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, | |
| 716 | { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, | |
| 717 | { "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, | |
| 718 | { "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, | |
| a9af5e04 JL |
719 | { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, |
| 720 | { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, | |
| 721 | { "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, | |
| 722 | { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, | |
| 723 | { "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, | |
| 724 | { "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, | |
| 725 | { "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, | |
| 726 | { "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, | |
| 727 | { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, | |
| 728 | { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, | |
| 729 | { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, | |
| 730 | { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, | |
| 731 | { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, | |
| 732 | { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, | |
| 252b5132 RH |
733 | |
| 734 | { "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}}, | |
| a9af5e04 | 735 | { "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 | 736 | |
| a9af5e04 | 737 | { "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 | 738 | { "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}}, |
| a9af5e04 | 739 | { "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 | 740 | |
| a9af5e04 | 741 | { "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 | 742 | { "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}}, |
| a9af5e04 | 743 | { "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 | 744 | |
| a9af5e04 | 745 | { "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 | 746 | { "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}}, |
| a9af5e04 | 747 | { "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 | 748 | |
| a9af5e04 | 749 | { "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 | 750 | { "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}}, |
| a9af5e04 | 751 | { "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 RH |
752 | |
| 753 | { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, | |
| 754 | { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, | |
| a9af5e04 JL |
755 | { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, |
| 756 | { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, | |
| 252b5132 RH |
757 | |
| 758 | { "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}}, | |
| a9af5e04 | 759 | { "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 | 760 | |
| a9af5e04 | 761 | { "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
762 | { "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}}, |
| 763 | { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, | |
| 764 | { "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, | |
| 765 | { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, | |
| 766 | { "add", 0x2800, 0xfc00, 0, FMT_S1, 0, {SIMM8, DN0}}, | |
| 767 | { "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 768 | { "add", 0x2000, 0xfc00, 0, FMT_S1, 0, {SIMM8, AN0}}, | |
| 769 | { "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}}, | |
| 770 | { "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}}, | |
| 771 | { "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}}, | |
| a9af5e04 | 772 | { "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 RH |
773 | { "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, |
| 774 | { "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, | |
| 775 | { "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}}, | |
| a9af5e04 JL |
776 | { "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, |
| 777 | { "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 778 | { "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 779 | |
| a9af5e04 | 780 | { "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 | 781 | { "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| a9af5e04 JL |
782 | { "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 783 | { "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 784 | { "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 785 | { "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 786 | |
| a9af5e04 | 787 | { "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
788 | { "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| 789 | { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, | |
| 790 | { "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, | |
| 791 | { "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, | |
| a9af5e04 | 792 | { "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 RH |
793 | { "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, |
| 794 | { "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, | |
| a9af5e04 JL |
795 | { "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, |
| 796 | { "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 797 | { "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 798 | |
| cb87eaaf | 799 | { "subc", 0xfbac0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 | 800 | { "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| a9af5e04 JL |
801 | { "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 802 | { "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 803 | { "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 804 | { "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 805 | |
| a9af5e04 | 806 | { "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, |
| 252b5132 | 807 | { "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| a9af5e04 JL |
808 | { "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 809 | { "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 810 | { "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 811 | { "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 812 | |
| a9af5e04 | 813 | { "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, |
| 252b5132 | 814 | { "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| a9af5e04 JL |
815 | { "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 816 | { "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 817 | { "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 818 | { "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 RH |
819 | |
| 820 | { "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| a9af5e04 | 821 | { "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 RH |
822 | |
| 823 | { "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| a9af5e04 | 824 | { "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 RH |
825 | |
| 826 | { "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}}, | |
| 827 | { "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}}, | |
| a9af5e04 | 828 | { "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 RH |
829 | |
| 830 | { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}}, | |
| a9af5e04 | 831 | { "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 RH |
832 | |
| 833 | { "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, | |
| 834 | { "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, | |
| 835 | { "cmp", 0xf1a0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, | |
| 836 | { "cmp", 0xf190, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, | |
| 837 | { "cmp", 0xb000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, | |
| 838 | { "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, | |
| 839 | { "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 840 | { "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}}, | |
| a9af5e04 | 841 | { "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 RH |
842 | { "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, |
| 843 | { "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, | |
| a9af5e04 JL |
844 | { "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, |
| 845 | { "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, | |
| 846 | { "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 847 | |
| a9af5e04 | 848 | { "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
849 | { "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| 850 | { "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 851 | { "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 852 | { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, | |
| a9af5e04 JL |
853 | { "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, |
| 854 | { "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 252b5132 | 855 | { "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, |
| a9af5e04 JL |
856 | { "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, |
| 857 | { "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 858 | { "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 859 | |
| a9af5e04 | 860 | { "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
861 | { "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| 862 | { "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 863 | { "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 864 | { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, | |
| a9af5e04 JL |
865 | { "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, |
| 866 | { "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, | |
| 252b5132 | 867 | { "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, |
| a9af5e04 JL |
868 | { "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, |
| 869 | { "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 870 | { "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 871 | |
| a9af5e04 | 872 | { "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
873 | { "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| 874 | { "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| a9af5e04 | 875 | { "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 | 876 | { "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, |
| a9af5e04 JL |
877 | { "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, |
| 878 | { "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 879 | { "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 RH |
880 | |
| 881 | { "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}}, | |
| a9af5e04 | 882 | { "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 RH |
883 | |
| 884 | { "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 885 | { "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 886 | { "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| a9af5e04 JL |
887 | /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the |
| 888 | them to match last since they do not promote. */ | |
| 889 | { "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 890 | { "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 891 | { "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 40fa0207 | 892 | { "btst", 0xfe820000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, |
| 252b5132 RH |
893 | { "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, |
| 894 | { "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, | |
| 895 | ||
| 896 | { "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, | |
| 40fa0207 | 897 | { "bset", 0xfe800000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, |
| 252b5132 RH |
898 | { "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, |
| 899 | { "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, | |
| 900 | ||
| 901 | { "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, | |
| 40fa0207 | 902 | { "bclr", 0xfe810000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, |
| 252b5132 RH |
903 | { "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, |
| 904 | { "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, | |
| 905 | ||
| a9af5e04 | 906 | { "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
907 | { "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| 908 | { "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| a9af5e04 JL |
909 | { "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 910 | { "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 911 | { "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 912 | { "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 913 | { "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}}, |
| a9af5e04 | 914 | { "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, |
| 252b5132 | 915 | |
| a9af5e04 | 916 | { "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
917 | { "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| 918 | { "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| a9af5e04 JL |
919 | { "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 920 | { "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, | |
| 921 | { "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 922 | { "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 923 | { "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}}, |
| a9af5e04 | 924 | { "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, |
| 252b5132 | 925 | |
| a9af5e04 | 926 | { "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 RH |
927 | { "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, |
| 928 | { "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| a9af5e04 JL |
929 | { "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 930 | { "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, | |
| 931 | { "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, | |
| 932 | { "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, | |
| 252b5132 | 933 | { "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}}, |
| a9af5e04 | 934 | { "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, |
| 252b5132 RH |
935 | |
| 936 | { "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}}, | |
| a9af5e04 | 937 | { "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 RH |
938 | |
| 939 | { "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}}, | |
| a9af5e04 | 940 | { "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 RH |
941 | |
| 942 | { "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}}, | |
| a9af5e04 | 943 | { "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, |
| 252b5132 RH |
944 | |
| 945 | { "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 946 | { "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 947 | { "bgt", 0xc100, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 948 | { "bge", 0xc200, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 949 | { "ble", 0xc300, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 950 | { "blt", 0xc000, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 951 | { "bhi", 0xc500, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 952 | { "bcc", 0xc600, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 953 | { "bls", 0xc700, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 954 | { "bcs", 0xc400, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 955 | { "bvc", 0xf8e800, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, | |
| 956 | { "bvs", 0xf8e900, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, | |
| 957 | { "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, | |
| 958 | { "bns", 0xf8eb00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, | |
| 959 | { "bra", 0xca00, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, | |
| 960 | ||
| 961 | { "leq", 0xd8, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 962 | { "lne", 0xd9, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 963 | { "lgt", 0xd1, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 964 | { "lge", 0xd2, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 965 | { "lle", 0xd3, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 966 | { "llt", 0xd0, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 967 | { "lhi", 0xd5, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 968 | { "lcc", 0xd6, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 969 | { "lls", 0xd7, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 970 | { "lcs", 0xd4, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 971 | { "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 972 | { "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 973 | ||
| 40fa0207 AO |
974 | { "fbeq", 0xf8d000, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, |
| 975 | { "fbne", 0xf8d100, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 976 | { "fbgt", 0xf8d200, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 977 | { "fbge", 0xf8d300, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 978 | { "fblt", 0xf8d400, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 979 | { "fble", 0xf8d500, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 980 | { "fbuo", 0xf8d600, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 981 | { "fblg", 0xf8d700, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 982 | { "fbleg", 0xf8d800, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 983 | { "fbug", 0xf8d900, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 984 | { "fbuge", 0xf8da00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 985 | { "fbul", 0xf8db00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 986 | { "fbule", 0xf8dc00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 987 | { "fbue", 0xf8dd00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, | |
| 988 | ||
| 989 | { "fleq", 0xf0d0, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 990 | { "flne", 0xf0d1, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 991 | { "flgt", 0xf0d2, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 992 | { "flge", 0xf0d3, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 993 | { "fllt", 0xf0d4, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 994 | { "flle", 0xf0d5, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 995 | { "fluo", 0xf0d6, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 996 | { "fllg", 0xf0d7, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 997 | { "flleg", 0xf0d8, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 998 | { "flug", 0xf0d9, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 999 | { "fluge", 0xf0da, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 1000 | { "flul", 0xf0db, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 1001 | { "flule", 0xf0dc, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 1002 | { "flue", 0xf0dd, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, | |
| 1003 | ||
| 252b5132 RH |
1004 | { "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, |
| 1005 | { "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}}, | |
| 1006 | { "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}}, | |
| 1007 | { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}}, | |
| 1008 | { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}}, | |
| 1009 | { "calls", 0xf0f0, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, | |
| 1010 | { "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2, 0, {IMM16_PCREL}}, | |
| 1011 | { "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4, 0, {IMM32_PCREL}}, | |
| 1012 | ||
| 1013 | { "ret", 0xdf0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, | |
| 1014 | { "retf", 0xde0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, | |
| 1015 | { "rets", 0xf0fc, 0xffff, 0, FMT_D0, 0, {UNUSED}}, | |
| 1016 | { "rti", 0xf0fd, 0xffff, 0, FMT_D0, 0, {UNUSED}}, | |
| 1017 | { "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}}, | |
| 1018 | { "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}}, | |
| 1019 | { "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 1020 | ||
| 40fa0207 AO |
1021 | { "dcpf", 0xf9a600, 0xffff0f, 0, FMT_D6, AM33_2, {MEM (RM2)}}, |
| 1022 | { "dcpf", 0xf9a700, 0xffffff, 0, FMT_D6, AM33_2, {MEM (SP)}}, | |
| 1023 | { "dcpf", 0xfba60000, 0xffff00ff, 0, FMT_D7, AM33_2, {MEM2 (RI,RM0)}}, | |
| 1024 | { "dcpf", 0xfba70000, 0xffff0f00, 0, FMT_D7, AM33_2, {MEM2 (SD8,RM2)}}, | |
| 1025 | { "dcpf", 0xfda70000, 0xffff0f00, 0, FMT_D8, AM33_2, {MEM2 (SD24,RM2)}}, | |
| 1026 | { "dcpf", 0xfe460000, 0xffff0f00, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8,RM2)}}, | |
| 1027 | ||
| 1028 | { "fmov", 0xf92000, 0xfffe00, 0, FMT_D6, AM33_2, {MEM (RM2), FSM0}}, | |
| 1029 | { "fmov", 0xf92200, 0xfffe00, 0, FMT_D6, AM33_2, {MEMINC (RM2), FSM0}}, | |
| 1030 | { "fmov", 0xf92400, 0xfffef0, 0, FMT_D6, AM33_2, {MEM (SP), FSM0}}, | |
| 1031 | { "fmov", 0xf92600, 0xfffe00, 0, FMT_D6, AM33_2, {RM2, FSM0}}, | |
| 1032 | { "fmov", 0xf93000, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEM (RM0)}}, | |
| 1033 | { "fmov", 0xf93100, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEMINC (RM0)}}, | |
| 1034 | { "fmov", 0xf93400, 0xfffd0f, 0, FMT_D6, AM33_2, {FSM1, MEM (SP)}}, | |
| 1035 | { "fmov", 0xf93500, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, RM0}}, | |
| 1036 | { "fmov", 0xf94000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, | |
| 1037 | { "fmov", 0xf9a000, 0xfffe01, 0, FMT_D6, AM33_2, {MEM (RM2), FDM0}}, | |
| 1038 | { "fmov", 0xf9a200, 0xfffe01, 0, FMT_D6, AM33_2, {MEMINC (RM2), FDM0}}, | |
| 1039 | { "fmov", 0xf9a400, 0xfffef1, 0, FMT_D6, AM33_2, {MEM (SP), FDM0}}, | |
| 1040 | { "fmov", 0xf9b000, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEM (RM0)}}, | |
| 1041 | { "fmov", 0xf9b100, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEMINC (RM0)}}, | |
| 1042 | { "fmov", 0xf9b400, 0xfffd1f, 0, FMT_D6, AM33_2, {FDM1, MEM (SP)}}, | |
| 1043 | { "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}}, | |
| 1044 | { "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}}, | |
| 1045 | { "fmov", 0xf9c000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, | |
| 1046 | { "fmov", 0xfb200000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FSM2}}, | |
| 1047 | { "fmov", 0xfb220000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FSM2}}, | |
| 1048 | { "fmov", 0xfb240000, 0xfffef000, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FSM2}}, | |
| 1049 | { "fmov", 0xfb270000, 0xffff000d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FSN1}}, | |
| 1050 | { "fmov", 0xfb300000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEM2 (SD8, RM0)}}, | |
| 1051 | { "fmov", 0xfb310000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEMINC2 (RM0, SIMM8)}}, | |
| 1052 | { "fmov", 0xfb340000, 0xfffd0f00, 0, FMT_D7, AM33_2, {FSM3, MEM2 (IMM8, SP)}}, | |
| 1053 | { "fmov", 0xfb370000, 0xffff000d, 0, FMT_D7, AM33_2, {FSN1, MEM2(RI, RM0)}}, | |
| 1054 | /* FIXME: the spec doesn't say the fd register must be even for the | |
| 1055 | * next two insns. Assuming it was a mistake in the spec. */ | |
| 1056 | { "fmov", 0xfb470000, 0xffff001d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FDN1}}, | |
| 1057 | { "fmov", 0xfb570000, 0xffff001d, 0, FMT_D7, AM33_2, {FDN1, MEM2(RI, RM0)}}, | |
| 1058 | /* END of FIXME */ | |
| 1059 | { "fmov", 0xfba00000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FDM2}}, | |
| 1060 | { "fmov", 0xfba20000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FDM2}}, | |
| 1061 | { "fmov", 0xfba40000, 0xfffef100, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FDM2}}, | |
| 1062 | { "fmov", 0xfbb00000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEM2 (SD8, RM0)}}, | |
| 1063 | { "fmov", 0xfbb10000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEMINC2 (RM0, SIMM8)}}, | |
| 1064 | { "fmov", 0xfbb40000, 0xfffd1f00, 0, FMT_D7, AM33_2, {FDM3, MEM2 (IMM8, SP)}}, | |
| 1065 | { "fmov", 0xfd200000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FSM2}}, | |
| 1066 | { "fmov", 0xfd220000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FSM2}}, | |
| 1067 | { "fmov", 0xfd240000, 0xfffef000, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FSM2}}, | |
| 1068 | { "fmov", 0xfd300000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEM2 (SIMM24, RM0)}}, | |
| 1069 | { "fmov", 0xfd310000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEMINC2 (RM0, SIMM24)}}, | |
| 1070 | { "fmov", 0xfd340000, 0xfffd0f00, 0, FMT_D8, AM33_2, {FSM3, MEM2 (IMM24, SP)}}, | |
| 1071 | { "fmov", 0xfda00000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FDM2}}, | |
| 1072 | { "fmov", 0xfda20000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FDM2}}, | |
| 1073 | { "fmov", 0xfda40000, 0xfffef100, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FDM2}}, | |
| 1074 | { "fmov", 0xfdb00000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEM2 (SIMM24, RM0)}}, | |
| 1075 | { "fmov", 0xfdb10000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEMINC2 (RM0, SIMM24)}}, | |
| 1076 | { "fmov", 0xfdb40000, 0xfffd1f00, 0, FMT_D8, AM33_2, {FDM3, MEM2 (IMM24, SP)}}, | |
| 1077 | { "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}}, | |
| 1078 | { "fmov", 0xfe200000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FSM2}}, | |
| 1079 | { "fmov", 0xfe220000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FSM2}}, | |
| 1080 | { "fmov", 0xfe240000, 0xfffef000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FSM2}}, | |
| 1081 | { "fmov", 0xfe260000, 0xfffef000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM2}}, | |
| 1082 | { "fmov", 0xfe300000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, RM0)}}, | |
| 1083 | { "fmov", 0xfe310000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEMINC2 (RM0, IMM32_HIGH8)}}, | |
| 1084 | { "fmov", 0xfe340000, 0xfffd0f00, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, SP)}}, | |
| 1085 | { "fmov", 0xfe400000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FDM2}}, | |
| 1086 | { "fmov", 0xfe420000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FDM2}}, | |
| 1087 | { "fmov", 0xfe440000, 0xfffef100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FDM2}}, | |
| 1088 | { "fmov", 0xfe500000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, RM0)}}, | |
| 1089 | { "fmov", 0xfe510000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEMINC2 (RM0, IMM32_HIGH8)}}, | |
| 1090 | { "fmov", 0xfe540000, 0xfffd1f00, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, SP)}}, | |
| 1091 | ||
| 1092 | /* FIXME: these are documented in the instruction bitmap, but not in | |
| 1093 | * the instruction manual. */ | |
| 1094 | { "ftoi", 0xfb400000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, | |
| 1095 | { "itof", 0xfb420000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, | |
| 1096 | { "ftod", 0xfb520000, 0xffff0f15, 0, FMT_D10,AM33_2, {FSN3, FDN1}}, | |
| 1097 | { "dtof", 0xfb560000, 0xffff1f05, 0, FMT_D10,AM33_2, {FDN3, FSN1}}, | |
| 1098 | /* END of FIXME */ | |
| 1099 | ||
| 1100 | { "fabs", 0xfb440000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, | |
| 1101 | { "fabs", 0xfbc40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, | |
| 1102 | { "fabs", 0xf94400, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, | |
| 1103 | { "fabs", 0xf9c400, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, | |
| 1104 | ||
| 1105 | { "fneg", 0xfb460000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, | |
| 1106 | { "fneg", 0xfbc60000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, | |
| 1107 | { "fneg", 0xf94600, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, | |
| 1108 | { "fneg", 0xf9c600, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, | |
| 1109 | ||
| 1110 | { "frsqrt", 0xfb500000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, | |
| 1111 | { "frsqrt", 0xfbd00000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, | |
| 1112 | { "frsqrt", 0xf95000, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, | |
| 1113 | { "frsqrt", 0xf9d000, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, | |
| 1114 | ||
| 1115 | /* FIXME: this is documented in the instruction bitmap, but not in | |
| 1116 | * the instruction manual. */ | |
| 1117 | { "fsqrt", 0xfb540000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, | |
| 1118 | { "fsqrt", 0xfbd40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, | |
| 1119 | { "fsqrt", 0xf95200, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, | |
| 1120 | { "fsqrt", 0xf9d200, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, | |
| 1121 | /* END of FIXME */ | |
| 1122 | ||
| 1123 | { "fcmp", 0xf95400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, | |
| 1124 | { "fcmp", 0xf9d400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, | |
| 1125 | { "fcmp", 0xfe350000, 0xfffd0f00, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3}}, | |
| 1126 | ||
| 1127 | { "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, | |
| 1128 | { "fadd", 0xfbe00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, | |
| 1129 | { "fadd", 0xf96000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, | |
| 1130 | { "fadd", 0xf9e000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, | |
| 1131 | { "fadd", 0xfe600000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, | |
| 1132 | ||
| 1133 | { "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, | |
| 1134 | { "fsub", 0xfbe40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, | |
| 1135 | { "fsub", 0xf96400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, | |
| 1136 | { "fsub", 0xf9e400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, | |
| 1137 | { "fsub", 0xfe640000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, | |
| 1138 | ||
| 1139 | { "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, | |
| 1140 | { "fmul", 0xfbf00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, | |
| 1141 | { "fmul", 0xf97000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, | |
| 1142 | { "fmul", 0xf9f000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, | |
| 1143 | { "fmul", 0xfe700000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, | |
| 1144 | ||
| 1145 | { "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, | |
| 1146 | { "fdiv", 0xfbf40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, | |
| 1147 | { "fdiv", 0xf97400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, | |
| 1148 | { "fdiv", 0xf9f400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, | |
| 1149 | { "fdiv", 0xfe740000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, | |
| 1150 | ||
| 1151 | { "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, | |
| 1152 | { "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, | |
| 1153 | { "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, | |
| 1154 | { "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, | |
| 1155 | ||
| 252b5132 RH |
1156 | /* UDF instructions. */ |
| 1157 | { "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1158 | { "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1159 | { "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1160 | { "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1161 | { "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1162 | { "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1163 | { "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1164 | { "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1165 | { "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1166 | { "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1167 | { "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1168 | { "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1169 | { "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1170 | { "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1171 | { "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1172 | { "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1173 | { "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1174 | { "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1175 | { "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1176 | { "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1177 | { "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1178 | { "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1179 | { "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1180 | { "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1181 | { "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1182 | { "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1183 | { "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1184 | { "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1185 | { "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1186 | { "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1187 | { "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1188 | { "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1189 | { "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1190 | { "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1191 | { "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1192 | { "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1193 | { "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1194 | { "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1195 | { "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1196 | { "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1197 | { "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1198 | { "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1199 | { "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1200 | { "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1201 | { "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1202 | { "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1203 | { "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1204 | { "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1205 | { "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1206 | { "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1207 | { "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1208 | { "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1209 | { "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1210 | { "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1211 | { "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1212 | { "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1213 | { "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1214 | { "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1215 | { "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1216 | { "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1217 | { "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1218 | { "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, | |
| 1219 | { "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, | |
| 1220 | { "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1221 | { "udf20", 0xf500, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1222 | { "udf21", 0xf510, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1223 | { "udf22", 0xf520, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1224 | { "udf23", 0xf530, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1225 | { "udf24", 0xf540, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1226 | { "udf25", 0xf550, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1227 | { "udf26", 0xf560, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1228 | { "udf27", 0xf570, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1229 | { "udf28", 0xf580, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1230 | { "udf29", 0xf590, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1231 | { "udf30", 0xf5a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1232 | { "udf31", 0xf5b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1233 | { "udf32", 0xf5c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1234 | { "udf33", 0xf5d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1235 | { "udf34", 0xf5e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1236 | { "udf35", 0xf5f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, | |
| 1237 | { "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1238 | { "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1239 | { "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1240 | { "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1241 | { "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1242 | { "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1243 | { "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1244 | { "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1245 | { "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1246 | { "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1247 | { "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1248 | { "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1249 | { "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1250 | { "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1251 | { "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1252 | { "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1253 | { "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1254 | { "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1255 | { "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1256 | { "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1257 | { "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1258 | { "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1259 | { "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1260 | { "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1261 | { "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1262 | { "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1263 | { "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1264 | { "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1265 | { "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1266 | { "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1267 | { "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1268 | { "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1269 | { "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1270 | { "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1271 | { "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1272 | { "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1273 | { "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1274 | { "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1275 | { "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1276 | { "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1277 | { "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1278 | { "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1279 | { "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1280 | { "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1281 | { "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1282 | { "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, | |
| 1283 | { "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, | |
| 1284 | { "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, | |
| 1285 | ||
| 1286 | { "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}}, | |
| 1287 | { "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}}, | |
| 1288 | { "mulq", 0xf600, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, | |
| 1289 | { "mulq", 0xf90000, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, | |
| 1290 | { "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, | |
| 1291 | { "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, | |
| 1292 | { "mulqu", 0xf610, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, | |
| 1293 | { "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, | |
| 1294 | { "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, | |
| 1295 | { "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, | |
| 1296 | { "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, | |
| a9af5e04 | 1297 | { "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 RH |
1298 | |
| 1299 | { "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, | |
| a9af5e04 | 1300 | { "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}}, |
| 252b5132 | 1301 | |
| a9af5e04 | 1302 | { "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, |
| 252b5132 | 1303 | { "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, |
| a9af5e04 | 1304 | { "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, |
| 252b5132 RH |
1305 | |
| 1306 | /* Extension. We need some instruction to trigger "emulated syscalls" | |
| 1307 | for our simulator. */ | |
| a9af5e04 | 1308 | { "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}}, |
| 252b5132 RH |
1309 | { "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}}, |
| 1310 | ||
| 1311 | /* Extension. When talking to the simulator, gdb requires some instruction | |
| 1312 | that will trigger a "breakpoint" (really just an instruction that isn't | |
| 1313 | otherwise used by the tools. This instruction must be the same size | |
| 1314 | as the smallest instruction on the target machine. In the case of the | |
| 1315 | mn10x00 the "break" instruction must be one byte. 0xff is available on | |
| 1316 | both mn10x00 architectures. */ | |
| 1317 | { "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}}, | |
| 1318 | ||
| a9af5e04 JL |
1319 | { "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, |
| 1320 | { "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1321 | { "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1322 | { "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1323 | { "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1324 | { "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1325 | { "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1326 | { "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1327 | { "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1328 | { "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1329 | { "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1330 | { "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1331 | { "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1332 | { "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1333 | { "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1334 | { "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1335 | { "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1336 | { "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1337 | { "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1338 | { "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1339 | { "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1340 | { "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1341 | { "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1342 | { "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1343 | { "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1344 | { "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1345 | { "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1346 | { "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1347 | { "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1348 | { "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1349 | { "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1350 | { "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1351 | { "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1352 | { "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1353 | { "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1354 | { "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1355 | { "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1356 | { "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1357 | { "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1358 | { "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1359 | { "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1360 | { "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1361 | { "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1362 | { "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1363 | { "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1364 | { "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1365 | { "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1366 | { "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1367 | { "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1368 | { "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1369 | { "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1370 | { "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1371 | { "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1372 | { "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1373 | { "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1374 | { "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1375 | { "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1376 | { "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1377 | { "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1378 | { "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1379 | { "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1380 | { "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1381 | { "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1382 | { "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1383 | { "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1384 | { "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1385 | { "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1386 | { "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1387 | { "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1388 | { "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1389 | { "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1390 | { "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1391 | { "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1392 | { "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1393 | { "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1394 | { "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1395 | { "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1396 | { "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1397 | { "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1398 | { "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1399 | { "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1400 | { "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1401 | { "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1402 | { "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1403 | { "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1404 | { "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1405 | { "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1406 | { "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1407 | { "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1408 | { "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1409 | { "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1410 | { "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1411 | { "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1412 | { "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1413 | { "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1414 | { "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, | |
| 1415 | { "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1416 | { "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1417 | { "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1418 | { "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1419 | { "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1420 | { "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1421 | { "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1422 | { "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1423 | { "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1424 | { "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1425 | { "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, | |
| 1426 | { "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, | |
| 1427 | { "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1428 | { "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1429 | { "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1430 | { "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1431 | { "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1432 | { "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1433 | { "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1434 | { "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1435 | { "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1436 | { "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1437 | { "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1438 | { "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1439 | { "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1440 | { "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1441 | { "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1442 | { "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1443 | { "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1444 | { "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1445 | { "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1446 | { "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1447 | { "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1448 | { "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1449 | { "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1450 | { "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1451 | { "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1452 | { "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1453 | { "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1454 | { "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1455 | { "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1456 | { "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1457 | { "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1458 | { "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1459 | { "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1460 | { "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1461 | { "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1462 | { "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1463 | { "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1464 | { "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1465 | { "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1466 | { "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1467 | { "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1468 | { "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1469 | { "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1470 | { "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1471 | { "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1472 | { "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1473 | { "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1474 | { "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1475 | { "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1476 | { "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1477 | { "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1478 | { "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1479 | { "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1480 | { "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1481 | { "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1482 | { "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1483 | { "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1484 | { "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1485 | { "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1486 | { "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1487 | { "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1488 | { "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1489 | { "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1490 | { "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1491 | { "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1492 | { "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1493 | { "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1494 | { "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1495 | { "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1496 | { "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1497 | { "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1498 | { "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1499 | { "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1500 | { "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1501 | { "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1502 | { "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1503 | { "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1504 | { "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, | |
| 1505 | { "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1506 | { "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1507 | { "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1508 | { "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1509 | { "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, | |
| 1510 | { "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, | |
| 1511 | /* Ugh. Synthetic instructions. */ | |
| 1512 | { "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1513 | { "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1514 | { "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1515 | { "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1516 | { "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1517 | { "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1518 | { "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1519 | { "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1520 | { "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1521 | { "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1522 | { "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1523 | { "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1524 | { "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1525 | { "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1526 | { "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1527 | { "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1528 | { "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1529 | { "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1530 | { "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1531 | { "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, | |
| 1532 | { "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1533 | { "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1534 | { "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1535 | { "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1536 | { "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1537 | { "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1538 | { "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1539 | { "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1540 | { "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1541 | { "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1542 | { "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1543 | { "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1544 | { "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1545 | { "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1546 | { "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1547 | { "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1548 | { "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1549 | { "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1550 | { "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1551 | { "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1552 | { "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1553 | { "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1554 | { "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1555 | { "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1556 | { "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1557 | { "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1558 | { "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1559 | { "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, | |
| 1560 | { "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1561 | { "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1562 | { "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1563 | { "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1564 | { "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1565 | { "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1566 | { "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1567 | { "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1568 | { "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1569 | { "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1570 | { "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1571 | { "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1572 | { "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1573 | { "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1574 | { "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1575 | { "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1576 | { "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1577 | { "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1578 | { "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1579 | { "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1580 | { "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1581 | { "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1582 | { "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1583 | { "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1584 | { "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1585 | { "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1586 | { "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1587 | { "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1588 | { "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1589 | { "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1590 | { "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1591 | { "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1592 | { "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1593 | { "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1594 | { "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1595 | { "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1596 | { "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1597 | { "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1598 | { "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1599 | { "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, | |
| 1600 | { "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1601 | { "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1602 | { "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1603 | { "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1604 | { "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1605 | { "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1606 | { "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1607 | { "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1608 | { "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1609 | { "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1610 | { "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1611 | { "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1612 | { "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1613 | { "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1614 | { "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, | |
| 1615 | { "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, | |
| 1616 | { "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1617 | { "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1618 | { "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1619 | { "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, | |
| 1620 | { "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1621 | { "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1622 | { "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1623 | { "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1624 | { "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1625 | { "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1626 | { "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1627 | { "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1628 | { "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1629 | { "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1630 | { "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1631 | { "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1632 | { "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1633 | { "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1634 | { "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1635 | { "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1636 | { "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1637 | { "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1638 | { "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1639 | { "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1640 | { "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1641 | { "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1642 | { "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, | |
| 1643 | { "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, | |
| 1644 | { "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1645 | { "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1646 | { "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1647 | { "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1648 | { "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1649 | { "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1650 | { "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1651 | { "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1652 | { "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1653 | { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1654 | { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1655 | { "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1656 | { "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1657 | { "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1658 | { "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1659 | { "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1660 | { "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1661 | { "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1662 | { "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1663 | { "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1664 | { "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 1665 | { "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, | |
| 252b5132 RH |
1666 | |
| 1667 | { 0, 0, 0, 0, 0, 0, {0}}, | |
| 1668 | ||
| 1669 | } ; | |
| 1670 | ||
| 1671 | const int mn10300_num_opcodes = | |
| 1672 | sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]); | |
| 1673 | ||
| 1674 | \f |