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[AArch64] Reject invalid immediate operands to MSR PAN
[deliverable/binutils-gdb.git] / opcodes / m10300-opc.c
CommitLineData
252b5132 1/* Assemble Matsushita MN10300 instructions.
b90efa5b 2 Copyright (C) 1996-2015 Free Software Foundation, Inc.
252b5132 3
9b201bb5 4 This file is part of the GNU opcodes library.
252b5132 5
9b201bb5
NC		 6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
252b5132 10
9b201bb5
NC		 11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
252b5132 15
9b201bb5
NC		 16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21/* This file is formatted at > 80 columns. Attempting to read it
22 on a screeen with less than 80 columns will be difficult. */
0d8dfecf 23#include "sysdep.h"
252b5132
RH		 24#include "opcode/mn10300.h"
25
26\f
27const struct mn10300_operand mn10300_operands[] = {
28#define UNUSED 0
43e65147 29 {0, 0, 0},
252b5132
RH		 30
31/* dn register in the first register operand position. */
32#define DN0 (UNUSED+1)
33 {2, 0, MN10300_OPERAND_DREG},
34
35/* dn register in the second register operand position. */
36#define DN1 (DN0+1)
37 {2, 2, MN10300_OPERAND_DREG},
38
39/* dn register in the third register operand position. */
40#define DN2 (DN1+1)
41 {2, 4, MN10300_OPERAND_DREG},
42
43/* dm register in the first register operand position. */
44#define DM0 (DN2+1)
45 {2, 0, MN10300_OPERAND_DREG},
46
47/* dm register in the second register operand position. */
48#define DM1 (DM0+1)
49 {2, 2, MN10300_OPERAND_DREG},
50
51/* dm register in the third register operand position. */
52#define DM2 (DM1+1)
53 {2, 4, MN10300_OPERAND_DREG},
54
55/* an register in the first register operand position. */
56#define AN0 (DM2+1)
57 {2, 0, MN10300_OPERAND_AREG},
58
59/* an register in the second register operand position. */
60#define AN1 (AN0+1)
61 {2, 2, MN10300_OPERAND_AREG},
62
63/* an register in the third register operand position. */
64#define AN2 (AN1+1)
65 {2, 4, MN10300_OPERAND_AREG},
66
67/* am register in the first register operand position. */
68#define AM0 (AN2+1)
69 {2, 0, MN10300_OPERAND_AREG},
70
71/* am register in the second register operand position. */
72#define AM1 (AM0+1)
73 {2, 2, MN10300_OPERAND_AREG},
74
75/* am register in the third register operand position. */
76#define AM2 (AM1+1)
77 {2, 4, MN10300_OPERAND_AREG},
78
79/* 8 bit unsigned immediate which may promote to a 16bit
80 unsigned immediate. */
81#define IMM8 (AM2+1)
82 {8, 0, MN10300_OPERAND_PROMOTE},
83
84/* 16 bit unsigned immediate which may promote to a 32bit
85 unsigned immediate. */
86#define IMM16 (IMM8+1)
87 {16, 0, MN10300_OPERAND_PROMOTE},
88
89/* 16 bit pc-relative immediate which may promote to a 16bit
90 pc-relative immediate. */
91#define IMM16_PCREL (IMM16+1)
92 {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
93
fa5e0d8d 94/* 16bit unsigned displacement in a memory operation which
252b5132
RH		 95 may promote to a 32bit displacement. */
96#define IMM16_MEM (IMM16_PCREL+1)
97 {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
98
99/* 32bit immediate, high 16 bits in the main instruction
43e65147 100 word, 16bits in the extension word.
252b5132
RH		 101
102 The "bits" field indicates how many bits are in the
103 main instruction word for MN10300_OPERAND_SPLIT! */
104#define IMM32 (IMM16_MEM+1)
105 {16, 0, MN10300_OPERAND_SPLIT},
106
107/* 32bit pc-relative offset. */
108#define IMM32_PCREL (IMM32+1)
109 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
110
111/* 32bit memory offset. */
112#define IMM32_MEM (IMM32_PCREL+1)
113 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
114
115/* 32bit immediate, high 16 bits in the main instruction
116 word, 16bits in the extension word, low 16bits are left
43e65147 117 shifted 8 places.
252b5132
RH		 118
119 The "bits" field indicates how many bits are in the
120 main instruction word for MN10300_OPERAND_SPLIT! */
121#define IMM32_LOWSHIFT8 (IMM32_MEM+1)
122 {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
123
124/* 32bit immediate, high 24 bits in the main instruction
125 word, 8 in the extension word.
126
127 The "bits" field indicates how many bits are in the
128 main instruction word for MN10300_OPERAND_SPLIT! */
129#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
130 {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
131
132/* 32bit immediate, high 24 bits in the main instruction
133 word, 8 in the extension word, low 8 bits are left
43e65147 134 shifted 16 places.
252b5132
RH		 135
136 The "bits" field indicates how many bits are in the
137 main instruction word for MN10300_OPERAND_SPLIT! */
138#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
139 {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
140
141/* Stack pointer. */
142#define SP (IMM32_HIGH24_LOWSHIFT16+1)
143 {8, 0, MN10300_OPERAND_SP},
144
145/* Processor status word. */
146#define PSW (SP+1)
147 {0, 0, MN10300_OPERAND_PSW},
148
149/* MDR register. */
150#define MDR (PSW+1)
151 {0, 0, MN10300_OPERAND_MDR},
152
153/* Index register. */
154#define DI (MDR+1)
155 {2, 2, MN10300_OPERAND_DREG},
156
fa5e0d8d 157/* 8 bit signed displacement, may promote to 16bit signed displacement. */
252b5132
RH		 158#define SD8 (DI+1)
159 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
160
fa5e0d8d 161/* 16 bit signed displacement, may promote to 32bit displacement. */
252b5132
RH		 162#define SD16 (SD8+1)
163 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
164
165/* 8 bit signed displacement that can not promote. */
166#define SD8N (SD16+1)
167 {8, 0, MN10300_OPERAND_SIGNED},
168
169/* 8 bit pc-relative displacement. */
170#define SD8N_PCREL (SD8N+1)
171 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
172
173/* 8 bit signed displacement shifted left 8 bits in the instruction. */
174#define SD8N_SHIFT8 (SD8N_PCREL+1)
175 {8, 8, MN10300_OPERAND_SIGNED},
176
177/* 8 bit signed immediate which may promote to 16bit signed immediate. */
178#define SIMM8 (SD8N_SHIFT8+1)
179 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
180
181/* 16 bit signed immediate which may promote to 32bit immediate. */
182#define SIMM16 (SIMM8+1)
183 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
184
185/* Either an open paren or close paren. */
186#define PAREN (SIMM16+1)
43e65147 187 {0, 0, MN10300_OPERAND_PAREN},
252b5132
RH		 188
189/* dn register that appears in the first and second register positions. */
190#define DN01 (PAREN+1)
191 {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
192
193/* an register that appears in the first and second register positions. */
194#define AN01 (DN01+1)
195 {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
196
197/* 16bit pc-relative displacement which may promote to 32bit pc-relative
198 displacement. */
199#define D16_SHIFT (AN01+1)
200 {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
201
202/* 8 bit immediate found in the extension word. */
203#define IMM8E (D16_SHIFT+1)
204 {8, 0, MN10300_OPERAND_EXTENDED},
205
206/* Register list found in the extension word shifted 8 bits left. */
207#define REGSE_SHIFT8 (IMM8E+1)
208 {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
209
210/* Register list shifted 8 bits left. */
211#define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
212 {8, 8, MN10300_OPERAND_REG_LIST},
213
214/* Reigster list. */
215#define REGS (REGS_SHIFT8+1)
216 {8, 0, MN10300_OPERAND_REG_LIST},
217
a9af5e04
JL		 218/* UStack pointer. */
219#define USP (REGS+1)
220 {0, 0, MN10300_OPERAND_USP},
221
222/* SStack pointer. */
223#define SSP (USP+1)
224 {0, 0, MN10300_OPERAND_SSP},
225
226/* MStack pointer. */
227#define MSP (SSP+1)
228 {0, 0, MN10300_OPERAND_MSP},
229
230/* PC . */
231#define PC (MSP+1)
232 {0, 0, MN10300_OPERAND_PC},
233
234/* 4 bit immediate for syscall. */
235#define IMM4 (PC+1)
236 {4, 0, 0},
237
238/* Processor status word. */
239#define EPSW (IMM4+1)
240 {0, 0, MN10300_OPERAND_EPSW},
241
242/* rn register in the first register operand position. */
243#define RN0 (EPSW+1)
244 {4, 0, MN10300_OPERAND_RREG},
245
246/* rn register in the fourth register operand position. */
247#define RN2 (RN0+1)
248 {4, 4, MN10300_OPERAND_RREG},
249
250/* rm register in the first register operand position. */
251#define RM0 (RN2+1)
252 {4, 0, MN10300_OPERAND_RREG},
253
254/* rm register in the second register operand position. */
255#define RM1 (RM0+1)
256 {4, 2, MN10300_OPERAND_RREG},
257
258/* rm register in the third register operand position. */
259#define RM2 (RM1+1)
260 {4, 4, MN10300_OPERAND_RREG},
261
262#define RN02 (RM2+1)
263 {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
264
265#define XRN0 (RN02+1)
266 {4, 0, MN10300_OPERAND_XRREG},
267
268#define XRM2 (XRN0+1)
269 {4, 4, MN10300_OPERAND_XRREG},
270
271/* + for autoincrement */
272#define PLUS (XRM2+1)
43e65147 273 {0, 0, MN10300_OPERAND_PLUS},
a9af5e04
JL		 274
275#define XRN02 (PLUS+1)
276 {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
277
278/* Ick */
279#define RD0 (XRN02+1)
280 {4, -8, MN10300_OPERAND_RREG},
281
282#define RD2 (RD0+1)
283 {4, -4, MN10300_OPERAND_RREG},
284
fa5e0d8d 285/* 8 unsigned displacement in a memory operation which
a9af5e04
JL		 286 may promote to a 32bit displacement. */
287#define IMM8_MEM (RD2+1)
288 {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
289
290/* Index register. */
291#define RI (IMM8_MEM+1)
292 {4, 4, MN10300_OPERAND_RREG},
293
fa5e0d8d 294/* 24 bit signed displacement, may promote to 32bit displacement. */
a9af5e04
JL		 295#define SD24 (RI+1)
296 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
297
298/* 24 bit unsigned immediate which may promote to a 32bit
299 unsigned immediate. */
300#define IMM24 (SD24+1)
301 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
302
303/* 24 bit signed immediate which may promote to a 32bit
304 signed immediate. */
305#define SIMM24 (IMM24+1)
306 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
307
fa5e0d8d 308/* 24bit unsigned displacement in a memory operation which
a9af5e04
JL		 309 may promote to a 32bit displacement. */
310#define IMM24_MEM (SIMM24+1)
311 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
fa5e0d8d
AO		 312/* 32bit immediate, high 8 bits in the main instruction
313 word, 24 in the extension word.
a9af5e04
JL		 314
315 The "bits" field indicates how many bits are in the
316 main instruction word for MN10300_OPERAND_SPLIT! */
317#define IMM32_HIGH8 (IMM24_MEM+1)
318 {8, 0, MN10300_OPERAND_SPLIT},
319
320/* Similarly, but a memory address. */
321#define IMM32_HIGH8_MEM (IMM32_HIGH8+1)
322 {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
323
324/* rm register in the seventh register operand position. */
325#define RM6 (IMM32_HIGH8_MEM+1)
326 {4, 12, MN10300_OPERAND_RREG},
327
328/* rm register in the fifth register operand position. */
329#define RN4 (RM6+1)
330 {4, 8, MN10300_OPERAND_RREG},
331
332/* 4 bit immediate for dsp instructions. */
333#define IMM4_2 (RN4+1)
334 {4, 4, 0},
335
336/* 4 bit immediate for dsp instructions. */
337#define SIMM4_2 (IMM4_2+1)
338 {4, 4, MN10300_OPERAND_SIGNED},
339
340/* 4 bit immediate for dsp instructions. */
341#define SIMM4_6 (SIMM4_2+1)
342 {4, 12, MN10300_OPERAND_SIGNED},
252b5132 343
40fa0207
AO		 344#define FPCR (SIMM4_6+1)
345 {0, 0, MN10300_OPERAND_FPCR},
346
347/* We call f[sd]m registers those whose most significant bit is stored
348 * within the opcode half-word, i.e., in a bit on the left of the 4
349 * least significant bits, and f[sd]n registers those whose most
350 * significant bit is stored at the end of the full word, after the 4
351 * least significant bits. They're not numbered after their position
352 * in the mnemonic asm instruction, but after their position in the
353 * opcode word, i.e., depending on the amount of shift they need.
354 *
355 * The additional bit is shifted as follows: for `n' registers, it
356 * will be shifted by (|shift|/4); for `m' registers, it will be
357 * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose
358 * specifications are only 3-bits long, the two least-significant bits
359 * are shifted by 16, and the most-significant bit is shifted by -2
360 * (i.e., it's stored in the least significant bit of the full
361 * word). */
362
363/* fsm register in the first register operand position. */
364#define FSM0 (FPCR+1)
365 {5, 0, MN10300_OPERAND_FSREG },
366
367/* fsm register in the second register operand position. */
368#define FSM1 (FSM0+1)
369 {5, 4, MN10300_OPERAND_FSREG },
370
371/* fsm register in the third register operand position. */
372#define FSM2 (FSM1+1)
373 {5, 8, MN10300_OPERAND_FSREG },
374
375/* fsm register in the fourth register operand position. */
376#define FSM3 (FSM2+1)
377 {5, 12, MN10300_OPERAND_FSREG },
378
379/* fsn register in the first register operand position. */
380#define FSN1 (FSM3+1)
381 {5, -4, MN10300_OPERAND_FSREG },
382
383/* fsn register in the second register operand position. */
384#define FSN2 (FSN1+1)
385 {5, -8, MN10300_OPERAND_FSREG },
386
387/* fsm register in the third register operand position. */
388#define FSN3 (FSN2+1)
389 {5, -12, MN10300_OPERAND_FSREG },
390
391/* fsm accumulator, in the fourth register operand position. */
392#define FSACC (FSN3+1)
393 {3, -16, MN10300_OPERAND_FSREG },
394
395/* fdm register in the first register operand position. */
396#define FDM0 (FSACC+1)
397 {5, 0, MN10300_OPERAND_FDREG },
398
399/* fdm register in the second register operand position. */
400#define FDM1 (FDM0+1)
401 {5, 4, MN10300_OPERAND_FDREG },
402
403/* fdm register in the third register operand position. */
404#define FDM2 (FDM1+1)
405 {5, 8, MN10300_OPERAND_FDREG },
406
407/* fdm register in the fourth register operand position. */
408#define FDM3 (FDM2+1)
409 {5, 12, MN10300_OPERAND_FDREG },
410
411/* fdn register in the first register operand position. */
412#define FDN1 (FDM3+1)
413 {5, -4, MN10300_OPERAND_FDREG },
414
415/* fdn register in the second register operand position. */
416#define FDN2 (FDN1+1)
417 {5, -8, MN10300_OPERAND_FDREG },
418
419/* fdn register in the third register operand position. */
420#define FDN3 (FDN2+1)
421 {5, -12, MN10300_OPERAND_FDREG },
422
43e65147 423} ;
252b5132 424
43e65147
L		 425#define MEM(ADDR) PAREN, ADDR, PAREN
426#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
427#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
428#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
252b5132
RH		 429\f
430/* The opcode table.
431
432 The format of the opcode table is:
433
434 NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS }
435
436 NAME is the name of the instruction.
437 OPCODE is the instruction opcode.
438 MASK is the opcode mask; this is used to tell the disassembler
439 which bits in the actual opcode must match OPCODE.
440 OPERANDS is the list of operands.
441
442 The disassembler reads the table in order and prints the first
443 instruction which matches, so this table is sorted to put more
444 specific instructions before more general instructions. It is also
445 sorted by major opcode. */
446
447const struct mn10300_opcode mn10300_opcodes[] = {
448{ "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
449{ "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}},
450{ "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
451{ "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
452{ "mov", 0x9000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}},
453{ "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
454{ "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
455{ "mov", 0xf2f0, 0xfff3, 0, FMT_D0, 0, {AM1, SP}},
456{ "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
457{ "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}},
458{ "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}},
459{ "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}},
460{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
461{ "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}},
462{ "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
463{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
464{ "mov", 0x5c00, 0xfcff, 0, FMT_S1, 0, {MEM(SP), AN0}},
465{ "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2, 0, {MEM(IMM16_MEM), AN0}},
466{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
467{ "mov", 0x4200, 0xf3ff, 0, FMT_S1, 0, {DM1, MEM(SP)}},
468{ "mov", 0x010000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
469{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
470{ "mov", 0x4300, 0xf3ff, 0, FMT_S1, 0, {AM1, MEM(SP)}},
471{ "mov", 0xfa800000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}},
472{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
473{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
474{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
475{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
476{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
477{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
478{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
479{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
480{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
481{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
482{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
483{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
484{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
485{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
486{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
487{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
488{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
489{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
490{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
491{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
492
a9af5e04
JL		 493{ "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}},
494{ "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}},
495{ "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}},
496{ "mov", 0xf02c, 0xfffc, 0, FMT_D0, AM33, {PC, AN0}},
497{ "mov", 0xf030, 0xfff3, 0, FMT_D0, AM33, {AN1, USP}},
498{ "mov", 0xf031, 0xfff3, 0, FMT_D0, AM33, {AN1, SSP}},
499{ "mov", 0xf032, 0xfff3, 0, FMT_D0, AM33, {AN1, MSP}},
500{ "mov", 0xf2ec, 0xfffc, 0, FMT_D0, AM33, {EPSW, DN0}},
501{ "mov", 0xf2f1, 0xfff3, 0, FMT_D0, AM33, {DM1, EPSW}},
502{ "mov", 0xf500, 0xffc0, 0, FMT_D0, AM33, {AM2, RN0}},
503{ "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}},
504{ "mov", 0xf580, 0xffc0, 0, FMT_D0, AM33, {RM1, AN0}},
505{ "mov", 0xf5c0, 0xffc0, 0, FMT_D0, AM33, {RM1, DN0}},
506{ "mov", 0xf90800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
507{ "mov", 0xf9e800, 0xffff00, 0, FMT_D6, AM33, {XRM2, RN0}},
508{ "mov", 0xf9f800, 0xffff00, 0, FMT_D6, AM33, {RM2, XRN0}},
509{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
510{ "mov", 0xf98a00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
511{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
512{ "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
513{ "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
514{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
515{ "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
516{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
517{ "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
518{ "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
519{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
520{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
521{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
522{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
523{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
5728a7d7
AO		 524{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
525{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
526{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
527{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
a9af5e04
JL		 528{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
529{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
530{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
531{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
532{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
533{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
534{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
252b5132
RH		 535/* These must come after most of the other move instructions to avoid matching
536 a symbolic name with IMMxx operands. Ugh. */
537{ "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}},
538{ "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
539{ "mov", 0x240000, 0xfc0000, 0, FMT_S2, 0, {IMM16, AN0}},
540{ "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
541{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
542{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
543{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
544{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
545{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
546{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
547{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
548{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
549{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
550{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
551{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
552{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
553/* These non-promoting variants need to come after all the other memory
554 moves. */
555{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}},
556{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}},
a9af5e04
JL		 557/* These are the same as the previous non-promoting versions. The am33
558 does not have restrictions on the offsets used to load/store the stack
559 pointer. */
560{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
561{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
562/* These must come last so that we favor shorter move instructions for
563 loading immediates into d0-d3/a0-a3. */
564{ "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
565{ "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
566{ "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
d164ea7f
AO		 567{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, XRN02}},
568{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}},
a9af5e04
JL		 569{ "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}},
570{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
571{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
572{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
573{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
574{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
575{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
576
577{ "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
578{ "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
579{ "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
580
581{ "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}},
582{ "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}},
583{ "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}},
584{ "swap", 0xf9cb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
585{ "swaph", 0xf690, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}},
586{ "swaph", 0xf9db00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
587{ "getchx", 0xf6c0, 0xfff0, 0, FMT_D0, AM33, {DN01}},
588{ "getclx", 0xf6d0, 0xfff0, 0, FMT_D0, AM33, {DN01}},
589{ "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
590{ "mac", 0xf90b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
591{ "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
592{ "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
593{ "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
594{ "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
595{ "macu", 0xf91b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
596{ "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
597{ "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
598{ "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
599{ "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
600{ "macb", 0xf92b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
601{ "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
602{ "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
603{ "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
604{ "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
605{ "macbu", 0xf93b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
606{ "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
607{ "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
608{ "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
609{ "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
610{ "mach", 0xf94b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
611{ "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
612{ "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
613{ "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
614{ "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
615{ "machu", 0xf95b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
616{ "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
617{ "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
618{ "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
619{ "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
620{ "dmach", 0xf96b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
621{ "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
622{ "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
623{ "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
624{ "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
625{ "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
626{ "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
627{ "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
628{ "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
629{ "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
630{ "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
631{ "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
632{ "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
633{ "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 634
635{ "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
636{ "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
637{ "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
638{ "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}},
639{ "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
640{ "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
641{ "movbu", 0xf400, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
642{ "movbu", 0x340000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
643{ "movbu", 0xf050, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
644{ "movbu", 0xf85000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
645{ "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
646{ "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}},
647{ "movbu", 0xf89200, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
648{ "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
649{ "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
650{ "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
a9af5e04
JL		 651{ "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
652{ "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
653{ "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
654{ "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
655{ "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
656{ "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
657{ "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
658{ "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
5728a7d7
AO		 659{ "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
660{ "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
661{ "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
662{ "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
a9af5e04
JL		 663{ "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
664{ "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
665{ "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
666{ "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
667{ "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
668{ "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
252b5132
RH		 669{ "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
670{ "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
671{ "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
672{ "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
673{ "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
674{ "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
a9af5e04
JL		 675{ "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
676{ "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
677{ "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}},
678{ "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
679{ "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
680{ "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
252b5132
RH		 681
682{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
683{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
684{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
685{ "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}},
686{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
687{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
688{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
689{ "movhu", 0x380000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
690{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
691{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
692{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
693{ "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}},
694{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
695{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
696{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
697{ "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
a9af5e04
JL		 698{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
699{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
700{ "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
701{ "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
702{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
703{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
704{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
705{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
706{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
707{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
5728a7d7
AO		 708{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
709{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
710{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
711{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
a9af5e04
JL		 712{ "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
713{ "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
714{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
715{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
252b5132
RH		 716{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
717{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
718{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
719{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
720{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
721{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
a9af5e04
JL		 722{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
723{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
724{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
725{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
726{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
727{ "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
728{ "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
729{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
730{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
731{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
732{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
733{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
734{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
735{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
252b5132
RH		 736
737{ "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}},
a9af5e04 738{ "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132 739
a9af5e04 740{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132 741{ "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}},
a9af5e04 742{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132 743
a9af5e04 744{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132 745{ "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}},
a9af5e04 746{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132 747
a9af5e04 748{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132 749{ "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}},
a9af5e04 750{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132 751
a9af5e04 752{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132 753{ "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}},
a9af5e04 754{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132
RH		 755
756{ "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}},
757{ "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}},
a9af5e04
JL		 758{ "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}},
759{ "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}},
252b5132
RH		 760
761{ "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}},
a9af5e04 762{ "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132 763
a9af5e04 764{ "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 765{ "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}},
766{ "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
767{ "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
768{ "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
769{ "add", 0x2800, 0xfc00, 0, FMT_S1, 0, {SIMM8, DN0}},
770{ "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
771{ "add", 0x2000, 0xfc00, 0, FMT_S1, 0, {SIMM8, AN0}},
772{ "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}},
773{ "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}},
774{ "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}},
a9af5e04 775{ "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 776{ "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
777{ "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
778{ "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}},
a9af5e04
JL		 779{ "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
780{ "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
781{ "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 782
a9af5e04 783{ "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132 784{ "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
a9af5e04
JL		 785{ "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
786{ "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
787{ "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
788{ "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 789
a9af5e04 790{ "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 791{ "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
792{ "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
793{ "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
794{ "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
a9af5e04 795{ "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 796{ "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
797{ "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
a9af5e04
JL		 798{ "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
799{ "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
800{ "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 801
cb87eaaf 802{ "subc", 0xfbac0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132 803{ "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
a9af5e04
JL		 804{ "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
805{ "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
806{ "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
807{ "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 808
a9af5e04 809{ "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
252b5132 810{ "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
a9af5e04
JL		 811{ "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
812{ "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
813{ "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
814{ "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 815
a9af5e04 816{ "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
252b5132 817{ "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
a9af5e04
JL		 818{ "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
819{ "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
820{ "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
821{ "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132
RH		 822
823{ "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
a9af5e04 824{ "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 825
826{ "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
a9af5e04 827{ "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 828
829{ "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}},
830{ "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}},
a9af5e04 831{ "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132
RH		 832
833{ "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
a9af5e04 834{ "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132
RH		 835
836{ "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
837{ "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}},
838{ "cmp", 0xf1a0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
839{ "cmp", 0xf190, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
840{ "cmp", 0xb000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}},
841{ "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
842{ "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
843{ "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}},
a9af5e04 844{ "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 845{ "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
846{ "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
a9af5e04
JL		 847{ "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
848{ "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
849{ "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 850
a9af5e04 851{ "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 852{ "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
853{ "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
854{ "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
855{ "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
a9af5e04
JL		 856{ "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}},
857{ "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132 858{ "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
a9af5e04
JL		 859{ "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
860{ "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
861{ "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 862
a9af5e04 863{ "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 864{ "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
865{ "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
866{ "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
867{ "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
a9af5e04
JL		 868{ "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}},
869{ "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132 870{ "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
a9af5e04
JL		 871{ "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
872{ "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
873{ "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 874
a9af5e04 875{ "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 876{ "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
877{ "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
a9af5e04 878{ "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132 879{ "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
a9af5e04
JL		 880{ "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
881{ "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
882{ "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132
RH		 883
884{ "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}},
a9af5e04 885{ "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132
RH		 886
887{ "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
888{ "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
889{ "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
a9af5e04
JL		 890/* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
891 them to match last since they do not promote. */
892{ "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
893{ "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
894{ "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
40fa0207 895{ "btst", 0xfe820000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
252b5132
RH		 896{ "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
897{ "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
898
899{ "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
40fa0207 900{ "bset", 0xfe800000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
252b5132
RH		 901{ "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
902{ "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
903
904{ "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
40fa0207 905{ "bclr", 0xfe810000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
252b5132
RH		 906{ "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
907{ "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
908
a9af5e04 909{ "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 910{ "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
911{ "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
a9af5e04
JL		 912{ "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
913{ "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
914{ "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
915{ "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 916{ "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}},
a9af5e04 917{ "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
252b5132 918
a9af5e04 919{ "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 920{ "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
921{ "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
a9af5e04
JL		 922{ "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
923{ "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
924{ "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
925{ "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 926{ "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}},
a9af5e04 927{ "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
252b5132 928
a9af5e04 929{ "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132
RH		 930{ "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
931{ "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
a9af5e04
JL		 932{ "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
933{ "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
934{ "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
935{ "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
252b5132 936{ "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}},
a9af5e04 937{ "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
252b5132
RH		 938
939{ "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}},
a9af5e04 940{ "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132
RH		 941
942{ "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}},
a9af5e04 943{ "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132
RH		 944
945{ "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}},
a9af5e04 946{ "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
252b5132
RH		 947
948{ "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
949{ "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
950{ "bgt", 0xc100, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
951{ "bge", 0xc200, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
952{ "ble", 0xc300, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
953{ "blt", 0xc000, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
954{ "bhi", 0xc500, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
955{ "bcc", 0xc600, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
956{ "bls", 0xc700, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
957{ "bcs", 0xc400, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
958{ "bvc", 0xf8e800, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
959{ "bvs", 0xf8e900, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
960{ "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
961{ "bns", 0xf8eb00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
962{ "bra", 0xca00, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
963
964{ "leq", 0xd8, 0xff, 0, FMT_S0, 0, {UNUSED}},
965{ "lne", 0xd9, 0xff, 0, FMT_S0, 0, {UNUSED}},
966{ "lgt", 0xd1, 0xff, 0, FMT_S0, 0, {UNUSED}},
967{ "lge", 0xd2, 0xff, 0, FMT_S0, 0, {UNUSED}},
968{ "lle", 0xd3, 0xff, 0, FMT_S0, 0, {UNUSED}},
969{ "llt", 0xd0, 0xff, 0, FMT_S0, 0, {UNUSED}},
970{ "lhi", 0xd5, 0xff, 0, FMT_S0, 0, {UNUSED}},
971{ "lcc", 0xd6, 0xff, 0, FMT_S0, 0, {UNUSED}},
972{ "lls", 0xd7, 0xff, 0, FMT_S0, 0, {UNUSED}},
973{ "lcs", 0xd4, 0xff, 0, FMT_S0, 0, {UNUSED}},
974{ "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}},
975{ "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}},
976
40fa0207
AO		 977{ "fbeq", 0xf8d000, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
978{ "fbne", 0xf8d100, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
979{ "fbgt", 0xf8d200, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
980{ "fbge", 0xf8d300, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
981{ "fblt", 0xf8d400, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
982{ "fble", 0xf8d500, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
983{ "fbuo", 0xf8d600, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
984{ "fblg", 0xf8d700, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
985{ "fbleg", 0xf8d800, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
986{ "fbug", 0xf8d900, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
987{ "fbuge", 0xf8da00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
988{ "fbul", 0xf8db00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
989{ "fbule", 0xf8dc00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
990{ "fbue", 0xf8dd00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
991
992{ "fleq", 0xf0d0, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
993{ "flne", 0xf0d1, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
994{ "flgt", 0xf0d2, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
995{ "flge", 0xf0d3, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
996{ "fllt", 0xf0d4, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
997{ "flle", 0xf0d5, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
998{ "fluo", 0xf0d6, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
999{ "fllg", 0xf0d7, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
1000{ "flleg", 0xf0d8, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
1001{ "flug", 0xf0d9, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
1002{ "fluge", 0xf0da, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
1003{ "flul", 0xf0db, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
1004{ "flule", 0xf0dc, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
1005{ "flue", 0xf0dd, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
1006
252b5132
RH		 1007{ "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}},
1008{ "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}},
1009{ "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}},
1010{ "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},
1011{ "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
1012{ "calls", 0xf0f0, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}},
1013{ "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2, 0, {IMM16_PCREL}},
1014{ "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4, 0, {IMM32_PCREL}},
1015
1016{ "ret", 0xdf0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
1017{ "retf", 0xde0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
1018{ "rets", 0xf0fc, 0xffff, 0, FMT_D0, 0, {UNUSED}},
1019{ "rti", 0xf0fd, 0xffff, 0, FMT_D0, 0, {UNUSED}},
1020{ "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}},
1021{ "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}},
1022{ "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}},
1023
40fa0207
AO		 1024{ "dcpf", 0xf9a600, 0xffff0f, 0, FMT_D6, AM33_2, {MEM (RM2)}},
1025{ "dcpf", 0xf9a700, 0xffffff, 0, FMT_D6, AM33_2, {MEM (SP)}},
1026{ "dcpf", 0xfba60000, 0xffff00ff, 0, FMT_D7, AM33_2, {MEM2 (RI,RM0)}},
1027{ "dcpf", 0xfba70000, 0xffff0f00, 0, FMT_D7, AM33_2, {MEM2 (SD8,RM2)}},
1028{ "dcpf", 0xfda70000, 0xffff0f00, 0, FMT_D8, AM33_2, {MEM2 (SD24,RM2)}},
1029{ "dcpf", 0xfe460000, 0xffff0f00, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8,RM2)}},
1030
1031{ "fmov", 0xf92000, 0xfffe00, 0, FMT_D6, AM33_2, {MEM (RM2), FSM0}},
1032{ "fmov", 0xf92200, 0xfffe00, 0, FMT_D6, AM33_2, {MEMINC (RM2), FSM0}},
1033{ "fmov", 0xf92400, 0xfffef0, 0, FMT_D6, AM33_2, {MEM (SP), FSM0}},
1034{ "fmov", 0xf92600, 0xfffe00, 0, FMT_D6, AM33_2, {RM2, FSM0}},
1035{ "fmov", 0xf93000, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEM (RM0)}},
1036{ "fmov", 0xf93100, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEMINC (RM0)}},
1037{ "fmov", 0xf93400, 0xfffd0f, 0, FMT_D6, AM33_2, {FSM1, MEM (SP)}},
1038{ "fmov", 0xf93500, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, RM0}},
1039{ "fmov", 0xf94000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
1040{ "fmov", 0xf9a000, 0xfffe01, 0, FMT_D6, AM33_2, {MEM (RM2), FDM0}},
1041{ "fmov", 0xf9a200, 0xfffe01, 0, FMT_D6, AM33_2, {MEMINC (RM2), FDM0}},
1042{ "fmov", 0xf9a400, 0xfffef1, 0, FMT_D6, AM33_2, {MEM (SP), FDM0}},
1043{ "fmov", 0xf9b000, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEM (RM0)}},
1044{ "fmov", 0xf9b100, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEMINC (RM0)}},
1045{ "fmov", 0xf9b400, 0xfffd1f, 0, FMT_D6, AM33_2, {FDM1, MEM (SP)}},
1046{ "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}},
1047{ "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}},
1048{ "fmov", 0xf9c000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
1049{ "fmov", 0xfb200000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FSM2}},
1050{ "fmov", 0xfb220000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FSM2}},
1051{ "fmov", 0xfb240000, 0xfffef000, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FSM2}},
1052{ "fmov", 0xfb270000, 0xffff000d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FSN1}},
1053{ "fmov", 0xfb300000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEM2 (SD8, RM0)}},
1054{ "fmov", 0xfb310000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEMINC2 (RM0, SIMM8)}},
1055{ "fmov", 0xfb340000, 0xfffd0f00, 0, FMT_D7, AM33_2, {FSM3, MEM2 (IMM8, SP)}},
1056{ "fmov", 0xfb370000, 0xffff000d, 0, FMT_D7, AM33_2, {FSN1, MEM2(RI, RM0)}},
1057 /* FIXME: the spec doesn't say the fd register must be even for the
1058 * next two insns. Assuming it was a mistake in the spec. */
1059{ "fmov", 0xfb470000, 0xffff001d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FDN1}},
1060{ "fmov", 0xfb570000, 0xffff001d, 0, FMT_D7, AM33_2, {FDN1, MEM2(RI, RM0)}},
1061 /* END of FIXME */
1062{ "fmov", 0xfba00000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FDM2}},
1063{ "fmov", 0xfba20000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FDM2}},
1064{ "fmov", 0xfba40000, 0xfffef100, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FDM2}},
1065{ "fmov", 0xfbb00000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEM2 (SD8, RM0)}},
1066{ "fmov", 0xfbb10000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEMINC2 (RM0, SIMM8)}},
1067{ "fmov", 0xfbb40000, 0xfffd1f00, 0, FMT_D7, AM33_2, {FDM3, MEM2 (IMM8, SP)}},
1068{ "fmov", 0xfd200000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FSM2}},
1069{ "fmov", 0xfd220000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FSM2}},
1070{ "fmov", 0xfd240000, 0xfffef000, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FSM2}},
1071{ "fmov", 0xfd300000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEM2 (SIMM24, RM0)}},
1072{ "fmov", 0xfd310000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEMINC2 (RM0, SIMM24)}},
1073{ "fmov", 0xfd340000, 0xfffd0f00, 0, FMT_D8, AM33_2, {FSM3, MEM2 (IMM24, SP)}},
1074{ "fmov", 0xfda00000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FDM2}},
1075{ "fmov", 0xfda20000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FDM2}},
1076{ "fmov", 0xfda40000, 0xfffef100, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FDM2}},
1077{ "fmov", 0xfdb00000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEM2 (SIMM24, RM0)}},
1078{ "fmov", 0xfdb10000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEMINC2 (RM0, SIMM24)}},
1079{ "fmov", 0xfdb40000, 0xfffd1f00, 0, FMT_D8, AM33_2, {FDM3, MEM2 (IMM24, SP)}},
1080{ "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}},
1081{ "fmov", 0xfe200000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FSM2}},
1082{ "fmov", 0xfe220000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FSM2}},
1083{ "fmov", 0xfe240000, 0xfffef000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FSM2}},
1084{ "fmov", 0xfe260000, 0xfffef000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM2}},
1085{ "fmov", 0xfe300000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, RM0)}},
1086{ "fmov", 0xfe310000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEMINC2 (RM0, IMM32_HIGH8)}},
1087{ "fmov", 0xfe340000, 0xfffd0f00, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, SP)}},
1088{ "fmov", 0xfe400000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FDM2}},
1089{ "fmov", 0xfe420000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FDM2}},
1090{ "fmov", 0xfe440000, 0xfffef100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FDM2}},
1091{ "fmov", 0xfe500000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, RM0)}},
1092{ "fmov", 0xfe510000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEMINC2 (RM0, IMM32_HIGH8)}},
1093{ "fmov", 0xfe540000, 0xfffd1f00, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, SP)}},
1094
1095 /* FIXME: these are documented in the instruction bitmap, but not in
1096 * the instruction manual. */
1097{ "ftoi", 0xfb400000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
1098{ "itof", 0xfb420000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
1099{ "ftod", 0xfb520000, 0xffff0f15, 0, FMT_D10,AM33_2, {FSN3, FDN1}},
1100{ "dtof", 0xfb560000, 0xffff1f05, 0, FMT_D10,AM33_2, {FDN3, FSN1}},
1101 /* END of FIXME */
1102
1103{ "fabs", 0xfb440000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
1104{ "fabs", 0xfbc40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
1105{ "fabs", 0xf94400, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
1106{ "fabs", 0xf9c400, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
1107
1108{ "fneg", 0xfb460000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
1109{ "fneg", 0xfbc60000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
1110{ "fneg", 0xf94600, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
1111{ "fneg", 0xf9c600, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
1112
1113{ "frsqrt", 0xfb500000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
1114{ "frsqrt", 0xfbd00000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
1115{ "frsqrt", 0xf95000, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
1116{ "frsqrt", 0xf9d000, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
1117
1118 /* FIXME: this is documented in the instruction bitmap, but not in
1119 * the instruction manual. */
1120{ "fsqrt", 0xfb540000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
1121{ "fsqrt", 0xfbd40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
1122{ "fsqrt", 0xf95200, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
1123{ "fsqrt", 0xf9d200, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
1124 /* END of FIXME */
1125
1126{ "fcmp", 0xf95400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
1127{ "fcmp", 0xf9d400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
1128{ "fcmp", 0xfe350000, 0xfffd0f00, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3}},
1129
1130{ "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
1131{ "fadd", 0xfbe00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
1132{ "fadd", 0xf96000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
1133{ "fadd", 0xf9e000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
1134{ "fadd", 0xfe600000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
1135
1136{ "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
1137{ "fsub", 0xfbe40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
1138{ "fsub", 0xf96400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
1139{ "fsub", 0xf9e400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
1140{ "fsub", 0xfe640000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
1141
1142{ "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
1143{ "fmul", 0xfbf00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
1144{ "fmul", 0xf97000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
1145{ "fmul", 0xf9f000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
1146{ "fmul", 0xfe700000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
1147
1148{ "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
1149{ "fdiv", 0xfbf40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
1150{ "fdiv", 0xf97400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
1151{ "fdiv", 0xf9f400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
1152{ "fdiv", 0xfe740000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
1153
1154{ "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
1155{ "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
1156{ "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
1157{ "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
1158
252b5132
RH		 1159/* UDF instructions. */
1160{ "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1161{ "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1162{ "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1163{ "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1164{ "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1165{ "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1166{ "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1167{ "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1168{ "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1169{ "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1170{ "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1171{ "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1172{ "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1173{ "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1174{ "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1175{ "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1176{ "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1177{ "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1178{ "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1179{ "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1180{ "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1181{ "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1182{ "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1183{ "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1184{ "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1185{ "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1186{ "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1187{ "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1188{ "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1189{ "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1190{ "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1191{ "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1192{ "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1193{ "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1194{ "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1195{ "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1196{ "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1197{ "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1198{ "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1199{ "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1200{ "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1201{ "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1202{ "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1203{ "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1204{ "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1205{ "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1206{ "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1207{ "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1208{ "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1209{ "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1210{ "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1211{ "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1212{ "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1213{ "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1214{ "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1215{ "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1216{ "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1217{ "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1218{ "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1219{ "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1220{ "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1221{ "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
1222{ "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
1223{ "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1224{ "udf20", 0xf500, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1225{ "udf21", 0xf510, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1226{ "udf22", 0xf520, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1227{ "udf23", 0xf530, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1228{ "udf24", 0xf540, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1229{ "udf25", 0xf550, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1230{ "udf26", 0xf560, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1231{ "udf27", 0xf570, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1232{ "udf28", 0xf580, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1233{ "udf29", 0xf590, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1234{ "udf30", 0xf5a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1235{ "udf31", 0xf5b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1236{ "udf32", 0xf5c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1237{ "udf33", 0xf5d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1238{ "udf34", 0xf5e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1239{ "udf35", 0xf5f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
1240{ "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1241{ "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1242{ "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1243{ "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1244{ "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1245{ "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1246{ "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1247{ "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1248{ "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1249{ "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1250{ "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1251{ "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1252{ "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1253{ "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1254{ "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1255{ "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1256{ "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1257{ "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1258{ "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1259{ "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1260{ "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1261{ "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1262{ "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1263{ "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1264{ "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1265{ "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1266{ "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1267{ "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1268{ "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1269{ "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1270{ "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1271{ "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1272{ "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1273{ "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1274{ "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1275{ "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1276{ "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1277{ "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1278{ "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1279{ "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1280{ "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1281{ "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1282{ "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1283{ "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1284{ "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1285{ "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
1286{ "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
1287{ "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
1288
1289{ "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}},
1290{ "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}},
1291{ "mulq", 0xf600, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
1292{ "mulq", 0xf90000, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}},
1293{ "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}},
1294{ "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}},
1295{ "mulqu", 0xf610, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
1296{ "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}},
1297{ "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}},
1298{ "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}},
1299{ "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
a9af5e04 1300{ "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 1301
1302{ "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
a9af5e04 1303{ "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}},
252b5132 1304
a9af5e04 1305{ "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
252b5132 1306{ "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
a9af5e04 1307{ "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
252b5132
RH		 1308
1309/* Extension. We need some instruction to trigger "emulated syscalls"
1310 for our simulator. */
a9af5e04 1311{ "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}},
252b5132
RH		 1312{ "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}},
1313
1314/* Extension. When talking to the simulator, gdb requires some instruction
1315 that will trigger a "breakpoint" (really just an instruction that isn't
1316 otherwise used by the tools. This instruction must be the same size
1317 as the smallest instruction on the target machine. In the case of the
1318 mn10x00 the "break" instruction must be one byte. 0xff is available on
1319 both mn10x00 architectures. */
1320{ "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}},
1321
a9af5e04
JL		 1322{ "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1323{ "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1324{ "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1325{ "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1326{ "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1327{ "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1328{ "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1329{ "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1330{ "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1331{ "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1332{ "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1333{ "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1334{ "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1335{ "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1336{ "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1337{ "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1338{ "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1339{ "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1340{ "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1341{ "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1342{ "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1343{ "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1344{ "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1345{ "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1346{ "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1347{ "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1348{ "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1349{ "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1350{ "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1351{ "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1352{ "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1353{ "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1354{ "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1355{ "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1356{ "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1357{ "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1358{ "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1359{ "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1360{ "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1361{ "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1362{ "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1363{ "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1364{ "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1365{ "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1366{ "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1367{ "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1368{ "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1369{ "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1370{ "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1371{ "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1372{ "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1373{ "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1374{ "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1375{ "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1376{ "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1377{ "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1378{ "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1379{ "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1380{ "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1381{ "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1382{ "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1383{ "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1384{ "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1385{ "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1386{ "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1387{ "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1388{ "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1389{ "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1390{ "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1391{ "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1392{ "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1393{ "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1394{ "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1395{ "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1396{ "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1397{ "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1398{ "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1399{ "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1400{ "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1401{ "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1402{ "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1403{ "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1404{ "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1405{ "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1406{ "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1407{ "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1408{ "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1409{ "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1410{ "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1411{ "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1412{ "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1413{ "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1414{ "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1415{ "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1416{ "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1417{ "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
1418{ "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1419{ "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1420{ "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1421{ "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1422{ "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1423{ "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1424{ "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1425{ "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1426{ "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1427{ "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1428{ "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
1429{ "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
1430{ "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1431{ "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1432{ "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1433{ "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1434{ "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1435{ "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1436{ "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1437{ "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1438{ "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1439{ "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1440{ "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1441{ "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1442{ "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1443{ "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1444{ "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1445{ "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1446{ "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1447{ "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1448{ "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1449{ "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1450{ "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1451{ "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1452{ "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1453{ "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1454{ "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1455{ "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1456{ "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1457{ "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1458{ "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1459{ "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1460{ "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1461{ "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1462{ "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1463{ "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1464{ "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1465{ "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1466{ "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1467{ "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1468{ "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1469{ "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1470{ "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1471{ "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1472{ "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1473{ "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1474{ "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1475{ "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1476{ "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1477{ "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1478{ "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1479{ "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1480{ "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1481{ "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1482{ "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1483{ "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1484{ "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1485{ "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1486{ "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1487{ "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1488{ "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1489{ "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1490{ "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1491{ "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1492{ "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1493{ "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1494{ "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1495{ "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1496{ "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1497{ "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1498{ "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1499{ "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1500{ "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1501{ "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1502{ "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1503{ "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1504{ "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1505{ "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1506{ "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1507{ "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
1508{ "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1509{ "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1510{ "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1511{ "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1512{ "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1513{ "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1514/* Ugh. Synthetic instructions. */
1515{ "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1516{ "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1517{ "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1518{ "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1519{ "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1520{ "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1521{ "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1522{ "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1523{ "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1524{ "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1525{ "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1526{ "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1527{ "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1528{ "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1529{ "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1530{ "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1531{ "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1532{ "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1533{ "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1534{ "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }},
1535{ "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1536{ "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1537{ "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1538{ "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1539{ "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1540{ "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1541{ "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1542{ "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1543{ "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1544{ "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1545{ "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1546{ "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1547{ "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1548{ "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1549{ "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1550{ "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1551{ "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1552{ "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1553{ "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1554{ "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1555{ "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1556{ "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1557{ "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1558{ "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1559{ "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1560{ "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1561{ "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1562{ "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }},
1563{ "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1564{ "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1565{ "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1566{ "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1567{ "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1568{ "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1569{ "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1570{ "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1571{ "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1572{ "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1573{ "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1574{ "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1575{ "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1576{ "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1577{ "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1578{ "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1579{ "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1580{ "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1581{ "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1582{ "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1583{ "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1584{ "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1585{ "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1586{ "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1587{ "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1588{ "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1589{ "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1590{ "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1591{ "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1592{ "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1593{ "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1594{ "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1595{ "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1596{ "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1597{ "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1598{ "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1599{ "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1600{ "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1601{ "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1602{ "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }},
1603{ "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1604{ "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1605{ "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1606{ "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1607{ "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1608{ "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1609{ "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1610{ "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1611{ "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1612{ "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1613{ "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1614{ "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1615{ "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1616{ "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1617{ "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
1618{ "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
1619{ "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1620{ "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1621{ "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1622{ "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
1623{ "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1624{ "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1625{ "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1626{ "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1627{ "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1628{ "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1629{ "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1630{ "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1631{ "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1632{ "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1633{ "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1634{ "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1635{ "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1636{ "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1637{ "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1638{ "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1639{ "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1640{ "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1641{ "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1642{ "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1643{ "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1644{ "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1645{ "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
1646{ "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
1647{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1648{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1649{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1650{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1651{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1652{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1653{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1654{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1655{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1656{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1657{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1658{ "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1659{ "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1660{ "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1661{ "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1662{ "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1663{ "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1664{ "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1665{ "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1666{ "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1667{ "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
1668{ "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
43e65147 1669
252b5132
RH		 1670{ 0, 0, 0, 0, 0, 0, {0}},
1671
1672} ;
1673
1674const int mn10300_num_opcodes =
1675 sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
1676
1677\f
GDB Binutils - Deliverables
This page took 0.769994 seconds and 4 git commands to generate.