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[include/elf]
[deliverable/binutils-gdb.git] / opcodes / m32c-desc.c
CommitLineData
49f58d10
JB		 1/* CPU data for m32c.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996-2005 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2151 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "m32c-desc.h"
32#include "m32c-opc.h"
33#include "opintl.h"
34#include "libiberty.h"
35#include "xregex.h"
36
37/* Attributes. */
38
39static const CGEN_ATTR_ENTRY bool_attr[] =
40{
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44};
45
46static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47{
48 { "base", MACH_BASE },
49 { "m16c", MACH_M16C },
50 { "m32c", MACH_M32C },
51 { "max", MACH_MAX },
52 { 0, 0 }
53};
54
55static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
56{
57 { "m16c", ISA_M16C },
58 { "m32c", ISA_M32C },
59 { "max", ISA_MAX },
60 { 0, 0 }
61};
62
6772dd07
DD		 63static const CGEN_ATTR_ENTRY RL_TYPE_attr[] ATTRIBUTE_UNUSED =
64{
65 { "NONE", RL_TYPE_NONE },
66 { "JUMP", RL_TYPE_JUMP },
67 { "1ADDR", RL_TYPE_1ADDR },
68 { "2ADDR", RL_TYPE_2ADDR },
69 { 0, 0 }
70};
71
49f58d10
JB		 72const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] =
73{
74 { "MACH", & MACH_attr[0], & MACH_attr[0] },
75 { "ISA", & ISA_attr[0], & ISA_attr[0] },
6772dd07 76 { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
49f58d10
JB		 77 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
78 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
79 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
80 { "RESERVED", &bool_attr[0], &bool_attr[0] },
81 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
82 { "SIGNED", &bool_attr[0], &bool_attr[0] },
83 { 0, 0, 0 }
84};
85
86const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] =
87{
88 { "MACH", & MACH_attr[0], & MACH_attr[0] },
89 { "ISA", & ISA_attr[0], & ISA_attr[0] },
6772dd07 90 { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
49f58d10
JB		 91 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
92 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
93 { "PC", &bool_attr[0], &bool_attr[0] },
94 { "PROFILE", &bool_attr[0], &bool_attr[0] },
95 { 0, 0, 0 }
96};
97
98const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] =
99{
100 { "MACH", & MACH_attr[0], & MACH_attr[0] },
101 { "ISA", & ISA_attr[0], & ISA_attr[0] },
6772dd07 102 { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
49f58d10
JB		 103 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
104 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
105 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
106 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
107 { "SIGNED", &bool_attr[0], &bool_attr[0] },
108 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
109 { "RELAX", &bool_attr[0], &bool_attr[0] },
110 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
111 { 0, 0, 0 }
112};
113
114const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] =
115{
116 { "MACH", & MACH_attr[0], & MACH_attr[0] },
117 { "ISA", & ISA_attr[0], & ISA_attr[0] },
6772dd07 118 { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
49f58d10
JB		 119 { "ALIAS", &bool_attr[0], &bool_attr[0] },
120 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
121 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
122 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
123 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
124 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
125 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
126 { "RELAXED", &bool_attr[0], &bool_attr[0] },
127 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
128 { "PBB", &bool_attr[0], &bool_attr[0] },
129 { 0, 0, 0 }
130};
131
132/* Instruction set variants. */
133
134static const CGEN_ISA m32c_cgen_isa_table[] = {
135 { "m16c", 32, 32, 8, 56 },
136 { "m32c", 32, 32, 8, 80 },
137 { 0, 0, 0, 0, 0 }
138};
139
140/* Machine variants. */
141
142static const CGEN_MACH m32c_cgen_mach_table[] = {
143 { "m16c", "m16c", MACH_M16C, 0 },
144 { "m32c", "m32c", MACH_M32C, 0 },
145 { 0, 0, 0, 0 }
146};
147
148static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] =
149{
fb53f5a8
DB		 150 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
151 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
152 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
153 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 154};
155
156CGEN_KEYWORD m32c_cgen_opval_h_gr =
157{
158 & m32c_cgen_opval_h_gr_entries[0],
159 4,
160 0, 0, 0, 0, ""
161};
162
163static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] =
164{
fb53f5a8
DB		 165 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
166 { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 },
167 { "r1l", 2, {0, {{{0, 0}}}}, 0, 0 },
168 { "r1h", 3, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 169};
170
171CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
172{
173 & m32c_cgen_opval_h_gr_QI_entries[0],
174 4,
175 0, 0, 0, 0, ""
176};
177
178static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] =
179{
fb53f5a8
DB		 180 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
181 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
182 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
183 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 184};
185
186CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
187{
188 & m32c_cgen_opval_h_gr_HI_entries[0],
189 4,
190 0, 0, 0, 0, ""
191};
192
193static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] =
194{
fb53f5a8
DB		 195 { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 },
196 { "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 197};
198
199CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
200{
201 & m32c_cgen_opval_h_gr_SI_entries[0],
202 2,
203 0, 0, 0, 0, ""
204};
205
206static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] =
207{
fb53f5a8
DB		 208 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
209 { "r1l", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 210};
211
212CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
213{
214 & m32c_cgen_opval_h_gr_ext_QI_entries[0],
215 2,
216 0, 0, 0, 0, ""
217};
218
219static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] =
220{
fb53f5a8
DB		 221 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
222 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 223};
224
225CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
226{
227 & m32c_cgen_opval_h_gr_ext_HI_entries[0],
228 2,
229 0, 0, 0, 0, ""
230};
231
232static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] =
233{
fb53f5a8 234 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 235};
236
237CGEN_KEYWORD m32c_cgen_opval_h_r0l =
238{
239 & m32c_cgen_opval_h_r0l_entries[0],
240 1,
241 0, 0, 0, 0, ""
242};
243
244static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] =
245{
fb53f5a8 246 { "r0h", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 247};
248
249CGEN_KEYWORD m32c_cgen_opval_h_r0h =
250{
251 & m32c_cgen_opval_h_r0h_entries[0],
252 1,
253 0, 0, 0, 0, ""
254};
255
256static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] =
257{
fb53f5a8 258 { "r1l", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 259};
260
261CGEN_KEYWORD m32c_cgen_opval_h_r1l =
262{
263 & m32c_cgen_opval_h_r1l_entries[0],
264 1,
265 0, 0, 0, 0, ""
266};
267
268static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] =
269{
fb53f5a8 270 { "r1h", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 271};
272
273CGEN_KEYWORD m32c_cgen_opval_h_r1h =
274{
275 & m32c_cgen_opval_h_r1h_entries[0],
276 1,
277 0, 0, 0, 0, ""
278};
279
280static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] =
281{
fb53f5a8 282 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 283};
284
285CGEN_KEYWORD m32c_cgen_opval_h_r0 =
286{
287 & m32c_cgen_opval_h_r0_entries[0],
288 1,
289 0, 0, 0, 0, ""
290};
291
292static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] =
293{
fb53f5a8 294 { "r1", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 295};
296
297CGEN_KEYWORD m32c_cgen_opval_h_r1 =
298{
299 & m32c_cgen_opval_h_r1_entries[0],
300 1,
301 0, 0, 0, 0, ""
302};
303
304static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] =
305{
fb53f5a8 306 { "r2", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 307};
308
309CGEN_KEYWORD m32c_cgen_opval_h_r2 =
310{
311 & m32c_cgen_opval_h_r2_entries[0],
312 1,
313 0, 0, 0, 0, ""
314};
315
316static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] =
317{
fb53f5a8 318 { "r3", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 319};
320
321CGEN_KEYWORD m32c_cgen_opval_h_r3 =
322{
323 & m32c_cgen_opval_h_r3_entries[0],
324 1,
325 0, 0, 0, 0, ""
326};
327
328static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] =
329{
fb53f5a8
DB		 330 { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
331 { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 332};
333
334CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
335{
336 & m32c_cgen_opval_h_r0l_r0h_entries[0],
337 2,
338 0, 0, 0, 0, ""
339};
340
341static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] =
342{
fb53f5a8 343 { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 344};
345
346CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
347{
348 & m32c_cgen_opval_h_r2r0_entries[0],
349 1,
350 0, 0, 0, 0, ""
351};
352
353static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] =
354{
fb53f5a8 355 { "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 356};
357
358CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
359{
360 & m32c_cgen_opval_h_r3r1_entries[0],
361 1,
362 0, 0, 0, 0, ""
363};
364
365static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] =
366{
fb53f5a8 367 { "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 368};
369
370CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
371{
372 & m32c_cgen_opval_h_r1r2r0_entries[0],
373 1,
374 0, 0, 0, 0, ""
375};
376
377static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] =
378{
fb53f5a8
DB		 379 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
380 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 381};
382
383CGEN_KEYWORD m32c_cgen_opval_h_ar =
384{
385 & m32c_cgen_opval_h_ar_entries[0],
386 2,
387 0, 0, 0, 0, ""
388};
389
390static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] =
391{
fb53f5a8
DB		 392 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
393 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 394};
395
396CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
397{
398 & m32c_cgen_opval_h_ar_QI_entries[0],
399 2,
400 0, 0, 0, 0, ""
401};
402
403static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] =
404{
fb53f5a8
DB		 405 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
406 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 407};
408
409CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
410{
411 & m32c_cgen_opval_h_ar_HI_entries[0],
412 2,
413 0, 0, 0, 0, ""
414};
415
416static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] =
417{
fb53f5a8 418 { "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 419};
420
421CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
422{
423 & m32c_cgen_opval_h_ar_SI_entries[0],
424 1,
425 0, 0, 0, 0, ""
426};
427
428static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] =
429{
fb53f5a8 430 { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 431};
432
433CGEN_KEYWORD m32c_cgen_opval_h_a0 =
434{
435 & m32c_cgen_opval_h_a0_entries[0],
436 1,
437 0, 0, 0, 0, ""
438};
439
440static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] =
441{
fb53f5a8 442 { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 443};
444
445CGEN_KEYWORD m32c_cgen_opval_h_a1 =
446{
447 & m32c_cgen_opval_h_a1_entries[0],
448 1,
449 0, 0, 0, 0, ""
450};
451
452static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] =
453{
fb53f5a8
DB		 454 { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
455 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
456 { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
457 { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
458 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
459 { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
460 { "le", 4, {0, {{{0, 0}}}}, 0, 0 },
461 { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
462 { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
463 { "ltu", 248, {0, {{{0, 0}}}}, 0, 0 },
464 { "nc", 248, {0, {{{0, 0}}}}, 0, 0 },
465 { "leu", 249, {0, {{{0, 0}}}}, 0, 0 },
466 { "ne", 250, {0, {{{0, 0}}}}, 0, 0 },
467 { "nz", 250, {0, {{{0, 0}}}}, 0, 0 },
468 { "pz", 251, {0, {{{0, 0}}}}, 0, 0 },
469 { "gt", 252, {0, {{{0, 0}}}}, 0, 0 },
470 { "no", 253, {0, {{{0, 0}}}}, 0, 0 },
471 { "lt", 254, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 472};
473
474CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
475{
476 & m32c_cgen_opval_h_cond16_entries[0],
477 18,
478 0, 0, 0, 0, ""
479};
480
481static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] =
482{
fb53f5a8
DB		 483 { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
484 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
485 { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
486 { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
487 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
488 { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
489 { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
490 { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
491 { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
492 { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
493 { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
494 { "pz", 7, {0, {{{0, 0}}}}, 0, 0 },
495 { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
496 { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
497 { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
498 { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
499 { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
500 { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 501};
502
503CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
504{
505 & m32c_cgen_opval_h_cond16c_entries[0],
506 18,
507 0, 0, 0, 0, ""
508};
509
510static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] =
511{
fb53f5a8
DB		 512 { "le", 8, {0, {{{0, 0}}}}, 0, 0 },
513 { "o", 9, {0, {{{0, 0}}}}, 0, 0 },
514 { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
515 { "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
516 { "no", 13, {0, {{{0, 0}}}}, 0, 0 },
517 { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 518};
519
520CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
521{
522 & m32c_cgen_opval_h_cond16j_entries[0],
523 6,
524 0, 0, 0, 0, ""
525};
526
527static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] =
528{
fb53f5a8
DB		 529 { "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
530 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
531 { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
532 { "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
533 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
534 { "n", 3, {0, {{{0, 0}}}}, 0, 0 },
535 { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
536 { "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
537 { "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
538 { "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
539 { "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
540 { "pz", 7, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 541};
542
543CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
544{
545 & m32c_cgen_opval_h_cond16j_5_entries[0],
546 12,
547 0, 0, 0, 0, ""
548};
549
550static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] =
551{
fb53f5a8
DB		 552 { "ltu", 0, {0, {{{0, 0}}}}, 0, 0 },
553 { "nc", 0, {0, {{{0, 0}}}}, 0, 0 },
554 { "leu", 1, {0, {{{0, 0}}}}, 0, 0 },
555 { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
556 { "nz", 2, {0, {{{0, 0}}}}, 0, 0 },
557 { "pz", 3, {0, {{{0, 0}}}}, 0, 0 },
558 { "no", 4, {0, {{{0, 0}}}}, 0, 0 },
559 { "gt", 5, {0, {{{0, 0}}}}, 0, 0 },
560 { "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
561 { "geu", 8, {0, {{{0, 0}}}}, 0, 0 },
562 { "c", 8, {0, {{{0, 0}}}}, 0, 0 },
563 { "gtu", 9, {0, {{{0, 0}}}}, 0, 0 },
564 { "eq", 10, {0, {{{0, 0}}}}, 0, 0 },
565 { "z", 10, {0, {{{0, 0}}}}, 0, 0 },
566 { "n", 11, {0, {{{0, 0}}}}, 0, 0 },
567 { "o", 12, {0, {{{0, 0}}}}, 0, 0 },
568 { "le", 13, {0, {{{0, 0}}}}, 0, 0 },
569 { "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 570};
571
572CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
573{
574 & m32c_cgen_opval_h_cond32_entries[0],
575 18,
576 0, 0, 0, 0, ""
577};
578
579static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] =
580{
fb53f5a8
DB		 581 { "dct0", 0, {0, {{{0, 0}}}}, 0, 0 },
582 { "dct1", 1, {0, {{{0, 0}}}}, 0, 0 },
583 { "flg", 2, {0, {{{0, 0}}}}, 0, 0 },
584 { "svf", 3, {0, {{{0, 0}}}}, 0, 0 },
585 { "drc0", 4, {0, {{{0, 0}}}}, 0, 0 },
586 { "drc1", 5, {0, {{{0, 0}}}}, 0, 0 },
587 { "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 },
588 { "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 589};
590
591CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
592{
593 & m32c_cgen_opval_h_cr1_32_entries[0],
594 8,
595 0, 0, 0, 0, ""
596};
597
598static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] =
599{
fb53f5a8
DB		 600 { "intb", 0, {0, {{{0, 0}}}}, 0, 0 },
601 { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
602 { "sb", 2, {0, {{{0, 0}}}}, 0, 0 },
603 { "fb", 3, {0, {{{0, 0}}}}, 0, 0 },
604 { "svp", 4, {0, {{{0, 0}}}}, 0, 0 },
605 { "vct", 5, {0, {{{0, 0}}}}, 0, 0 },
606 { "isp", 7, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 607};
608
609CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
610{
611 & m32c_cgen_opval_h_cr2_32_entries[0],
612 7,
613 0, 0, 0, 0, ""
614};
615
616static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] =
617{
fb53f5a8
DB		 618 { "dma0", 2, {0, {{{0, 0}}}}, 0, 0 },
619 { "dma1", 3, {0, {{{0, 0}}}}, 0, 0 },
620 { "dra0", 4, {0, {{{0, 0}}}}, 0, 0 },
621 { "dra1", 5, {0, {{{0, 0}}}}, 0, 0 },
622 { "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 },
623 { "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 624};
625
626CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
627{
628 & m32c_cgen_opval_h_cr3_32_entries[0],
629 6,
630 0, 0, 0, 0, ""
631};
632
633static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] =
634{
fb53f5a8
DB		 635 { "intbl", 1, {0, {{{0, 0}}}}, 0, 0 },
636 { "intbh", 2, {0, {{{0, 0}}}}, 0, 0 },
637 { "flg", 3, {0, {{{0, 0}}}}, 0, 0 },
638 { "isp", 4, {0, {{{0, 0}}}}, 0, 0 },
639 { "sp", 5, {0, {{{0, 0}}}}, 0, 0 },
640 { "sb", 6, {0, {{{0, 0}}}}, 0, 0 },
641 { "fb", 7, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 642};
643
644CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
645{
646 & m32c_cgen_opval_h_cr_16_entries[0],
647 7,
648 0, 0, 0, 0, ""
649};
650
651static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] =
652{
fb53f5a8
DB		 653 { "c", 0, {0, {{{0, 0}}}}, 0, 0 },
654 { "d", 1, {0, {{{0, 0}}}}, 0, 0 },
655 { "z", 2, {0, {{{0, 0}}}}, 0, 0 },
656 { "s", 3, {0, {{{0, 0}}}}, 0, 0 },
657 { "b", 4, {0, {{{0, 0}}}}, 0, 0 },
658 { "o", 5, {0, {{{0, 0}}}}, 0, 0 },
659 { "i", 6, {0, {{{0, 0}}}}, 0, 0 },
660 { "u", 7, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 661};
662
663CGEN_KEYWORD m32c_cgen_opval_h_flags =
664{
665 & m32c_cgen_opval_h_flags_entries[0],
666 8,
667 0, 0, 0, 0, ""
668};
669
670static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] =
671{
fb53f5a8
DB		 672 { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
673 { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
674 { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
675 { "4", 3, {0, {{{0, 0}}}}, 0, 0 },
676 { "5", 4, {0, {{{0, 0}}}}, 0, 0 },
677 { "6", 5, {0, {{{0, 0}}}}, 0, 0 },
678 { "7", 6, {0, {{{0, 0}}}}, 0, 0 },
679 { "8", 7, {0, {{{0, 0}}}}, 0, 0 },
680 { "-1", -8, {0, {{{0, 0}}}}, 0, 0 },
681 { "-2", -7, {0, {{{0, 0}}}}, 0, 0 },
682 { "-3", -6, {0, {{{0, 0}}}}, 0, 0 },
683 { "-4", -5, {0, {{{0, 0}}}}, 0, 0 },
684 { "-5", -4, {0, {{{0, 0}}}}, 0, 0 },
685 { "-6", -3, {0, {{{0, 0}}}}, 0, 0 },
686 { "-7", -2, {0, {{{0, 0}}}}, 0, 0 },
687 { "-8", -1, {0, {{{0, 0}}}}, 0, 0 }
49f58d10
JB		 688};
689
690CGEN_KEYWORD m32c_cgen_opval_h_shimm =
691{
692 & m32c_cgen_opval_h_shimm_entries[0],
693 16,
694 0, 0, 0, 0, ""
695};
696
697
698/* The hardware table. */
699
700#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
701#define A(a) (1 << CGEN_HW_##a)
702#else
703#define A(a) (1 << CGEN_HW_/**/a)
704#endif
705
706const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
707{
6772dd07
DD		 708 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
709 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
710 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
711 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
712 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
713 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
714 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
715 { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
716 { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
717 { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
718 { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
719 { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
720 { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
721 { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
722 { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
723 { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
724 { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
725 { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
726 { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
727 { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
728 { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
729 { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
730 { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
731 { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
732 { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
733 { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
734 { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
735 { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
736 { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
737 { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
738 { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
739 { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
740 { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
741 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
742 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
743 { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
744 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
745 { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
746 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
747 { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
748 { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
749 { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
750 { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
751 { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
752 { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
753 { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
754 { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
755 { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
756 { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
757 { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
758 { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
759 { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
760 { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
761 { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
762 { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
763 { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
764 { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
765 { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
766 { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
767 { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
768 { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
769 { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
770 { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
771 { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
772 { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
773 { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
774 { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
775 { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
776 { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
777 { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
778 { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
779 { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
780 { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
781 { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
782 { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
783 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } }
49f58d10
JB		 784};
785
786#undef A
787
788
789/* The instruction field table. */
790
791#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
792#define A(a) (1 << CGEN_IFLD_##a)
793#else
794#define A(a) (1 << CGEN_IFLD_/**/a)
795#endif
796
797const CGEN_IFLD m32c_cgen_ifld_table[] =
798{
6772dd07
DD		 799 { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
800 { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
801 { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
802 { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
803 { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
804 { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
805 { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
806 { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
807 { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
808 { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
809 { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
810 { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
811 { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
812 { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
813 { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
814 { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
815 { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
816 { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
817 { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
818 { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
819 { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
820 { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
821 { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
822 { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
823 { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
824 { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
825 { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
826 { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
827 { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
828 { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
829 { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
830 { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
831 { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
832 { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
833 { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
834 { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
835 { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
836 { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
837 { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
838 { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
839 { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
840 { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
841 { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
842 { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
843 { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
844 { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
845 { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
846 { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
847 { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
848 { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
849 { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
850 { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
851 { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
852 { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
853 { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
854 { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
855 { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
856 { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
857 { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
858 { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
859 { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
860 { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
861 { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
862 { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
863 { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
864 { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
865 { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
866 { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
867 { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
868 { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
869 { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
870 { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
871 { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
872 { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
873 { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
874 { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
875 { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
876 { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
877 { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
878 { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
879 { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
880 { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
881 { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
882 { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
883 { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
884 { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
885 { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
886 { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
887 { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
888 { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
889 { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
890 { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
891 { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
892 { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
893 { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
894 { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
895 { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
896 { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
897 { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
898 { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
899 { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
900 { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
901 { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
902 { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
903 { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
904 { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
905 { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
906 { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
907 { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
908 { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
909 { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
910 { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
911 { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
912 { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
913 { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
914 { M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
915 { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
916 { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
917 { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
918 { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
919 { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
920 { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
921 { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
922 { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
923 { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
924 { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
925 { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
926 { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
927 { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
928 { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
929 { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
930 { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
931 { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
932 { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
933 { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
934 { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
935 { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
936 { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
937 { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
938 { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
939 { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
940 { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
941 { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
942 { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
943 { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
944 { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
945 { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
946 { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
947 { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
948 { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
949 { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
950 { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
951 { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
952 { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
953 { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
954 { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
955 { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
956 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } }
49f58d10
JB		 957};
958
959#undef A
960
961
962
963/* multi ifield declarations */
964
965const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [];
966const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [];
967const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [];
968const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [];
969const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [];
970const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [];
971const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [];
972const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [];
973const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [];
974const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [];
975const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [];
976const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [];
977const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [];
978const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [];
979const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [];
980const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [];
981const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [];
982const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [];
983const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [];
984const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [];
985const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [];
986const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [];
987const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [];
988const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [];
989const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [];
990const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [];
991
992
993/* multi ifield definitions */
994
995const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [] =
996{
997 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
998 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
999 { 0, { (const PTR) 0 } }
1000};
1001const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [] =
1002{
1003 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1004 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1005 { 0, { (const PTR) 0 } }
1006};
1007const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [] =
1008{
1009 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1010 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1011 { 0, { (const PTR) 0 } }
1012};
1013const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [] =
1014{
1015 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1016 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1017 { 0, { (const PTR) 0 } }
1018};
1019const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [] =
1020{
1021 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1022 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1023 { 0, { (const PTR) 0 } }
1024};
1025const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] =
1026{
1027 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1028 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1029 { 0, { (const PTR) 0 } }
1030};
1031const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] =
1032{
1033 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1034 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1035 { 0, { (const PTR) 0 } }
1036};
1037const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [] =
1038{
1039 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1040 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1041 { 0, { (const PTR) 0 } }
1042};
1043const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [] =
1044{
1045 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1046 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1047 { 0, { (const PTR) 0 } }
1048};
1049const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [] =
1050{
1051 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1052 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1053 { 0, { (const PTR) 0 } }
1054};
1055const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [] =
1056{
1057 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1058 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1059 { 0, { (const PTR) 0 } }
1060};
1061const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [] =
1062{
1063 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } },
1064 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1065 { 0, { (const PTR) 0 } }
1066};
1067const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [] =
1068{
1069 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } },
1070 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1071 { 0, { (const PTR) 0 } }
1072};
1073const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [] =
1074{
1075 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1076 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1077 { 0, { (const PTR) 0 } }
1078};
1079const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [] =
1080{
1081 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1082 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1083 { 0, { (const PTR) 0 } }
1084};
1085const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [] =
1086{
1087 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1088 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1089 { 0, { (const PTR) 0 } }
1090};
1091const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [] =
1092{
1093 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1094 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1095 { 0, { (const PTR) 0 } }
1096};
1097const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [] =
1098{
1099 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1100 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1101 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1102 { 0, { (const PTR) 0 } }
1103};
1104const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [] =
1105{
1106 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1107 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1108 { 0, { (const PTR) 0 } }
1109};
1110const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [] =
1111{
1112 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1113 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1114 { 0, { (const PTR) 0 } }
1115};
1116const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [] =
1117{
1118 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1119 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1120 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1121 { 0, { (const PTR) 0 } }
1122};
1123const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [] =
1124{
1125 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1126 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1127 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1128 { 0, { (const PTR) 0 } }
1129};
1130const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [] =
1131{
1132 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1133 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1134 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1135 { 0, { (const PTR) 0 } }
1136};
1137const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [] =
1138{
1139 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
1140 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1141 { 0, { (const PTR) 0 } }
1142};
1143const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [] =
1144{
1145 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } },
1146 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1147 { 0, { (const PTR) 0 } }
1148};
1149const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [] =
1150{
1151 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } },
1152 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1153 { 0, { (const PTR) 0 } }
1154};
1155
1156/* The operand table. */
1157
1158#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1159#define A(a) (1 << CGEN_OPERAND_##a)
1160#else
1161#define A(a) (1 << CGEN_OPERAND_/**/a)
1162#endif
1163#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1164#define OPERAND(op) M32C_OPERAND_##op
1165#else
1166#define OPERAND(op) M32C_OPERAND_/**/op
1167#endif
1168
1169const CGEN_OPERAND m32c_cgen_operand_table[] =
1170{
1171/* pc: program counter */
1172 { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
1173 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
6772dd07 1174 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1175/* Src16RnQI: general register QI view */
1176 { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
1177 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
6772dd07 1178 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1179/* Src16RnHI: general register QH view */
1180 { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
1181 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
6772dd07 1182 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1183/* Src32RnUnprefixedQI: general register QI view */
1184 { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
1185 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
6772dd07 1186 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1187/* Src32RnUnprefixedHI: general register HI view */
1188 { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
1189 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
6772dd07 1190 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1191/* Src32RnUnprefixedSI: general register SI view */
1192 { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
1193 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
6772dd07 1194 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1195/* Src32RnPrefixedQI: general register QI view */
1196 { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
1197 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
6772dd07 1198 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1199/* Src32RnPrefixedHI: general register HI view */
1200 { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
1201 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
6772dd07 1202 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1203/* Src32RnPrefixedSI: general register SI view */
1204 { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
1205 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
6772dd07 1206 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1207/* Src16An: address register */
1208 { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
1209 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
6772dd07 1210 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1211/* Src16AnQI: address register QI view */
1212 { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
1213 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
6772dd07 1214 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1215/* Src16AnHI: address register HI view */
1216 { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
1217 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
6772dd07 1218 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1219/* Src32AnUnprefixed: address register */
1220 { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
1221 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
6772dd07 1222 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1223/* Src32AnUnprefixedQI: address register QI view */
1224 { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
1225 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
6772dd07 1226 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1227/* Src32AnUnprefixedHI: address register HI view */
1228 { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
1229 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
6772dd07 1230 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1231/* Src32AnUnprefixedSI: address register SI view */
1232 { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
1233 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
6772dd07 1234 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1235/* Src32AnPrefixed: address register */
1236 { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
1237 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
6772dd07 1238 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1239/* Src32AnPrefixedQI: address register QI view */
1240 { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
1241 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
6772dd07 1242 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1243/* Src32AnPrefixedHI: address register HI view */
1244 { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
1245 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
6772dd07 1246 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1247/* Src32AnPrefixedSI: address register SI view */
1248 { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
1249 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
6772dd07 1250 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1251/* Dst16RnQI: general register QI view */
1252 { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
1253 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
6772dd07 1254 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1255/* Dst16RnHI: general register HI view */
1256 { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
1257 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
6772dd07 1258 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1259/* Dst16RnSI: general register SI view */
1260 { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
1261 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
6772dd07 1262 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1263/* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
1264 { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
1265 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
6772dd07 1266 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1267/* Dst32R0QI-S: general register QI view */
1268 { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
1269 { 0, { (const PTR) 0 } },
6772dd07 1270 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1271/* Dst32R0HI-S: general register HI view */
1272 { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
1273 { 0, { (const PTR) 0 } },
6772dd07 1274 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1275/* Dst32RnUnprefixedQI: general register QI view */
1276 { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
1277 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
6772dd07 1278 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1279/* Dst32RnUnprefixedHI: general register HI view */
1280 { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
1281 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
6772dd07 1282 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1283/* Dst32RnUnprefixedSI: general register SI view */
1284 { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
1285 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
6772dd07 1286 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1287/* Dst32RnExtUnprefixedQI: general register QI view */
1288 { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
1289 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
6772dd07 1290 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1291/* Dst32RnExtUnprefixedHI: general register HI view */
1292 { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
1293 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
6772dd07 1294 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1295/* Dst32RnPrefixedQI: general register QI view */
1296 { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
1297 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
6772dd07 1298 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1299/* Dst32RnPrefixedHI: general register HI view */
1300 { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
1301 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
6772dd07 1302 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1303/* Dst32RnPrefixedSI: general register SI view */
1304 { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
1305 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
6772dd07 1306 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1307/* Dst16RnQI-S: general register QI view */
1308 { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
1309 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
6772dd07 1310 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1311/* Dst16AnQI-S: address register QI view */
1312 { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
1313 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
6772dd07 1314 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1315/* Bit16Rn: general register bit view */
1316 { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
1317 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
6772dd07 1318 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1319/* Bit32RnPrefixed: general register bit view */
1320 { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
1321 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
6772dd07 1322 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1323/* Bit32RnUnprefixed: general register bit view */
1324 { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
1325 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
6772dd07 1326 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1327/* R0: r0 */
1328 { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
1329 { 0, { (const PTR) 0 } },
6772dd07 1330 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1331/* R1: r1 */
1332 { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
1333 { 0, { (const PTR) 0 } },
6772dd07 1334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1335/* R2: r2 */
1336 { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
1337 { 0, { (const PTR) 0 } },
6772dd07 1338 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1339/* R3: r3 */
1340 { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
1341 { 0, { (const PTR) 0 } },
6772dd07 1342 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1343/* R0l: r0l */
1344 { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
1345 { 0, { (const PTR) 0 } },
6772dd07 1346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1347/* R0h: r0h */
1348 { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
1349 { 0, { (const PTR) 0 } },
6772dd07 1350 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1351/* R2R0: r2r0 */
1352 { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
1353 { 0, { (const PTR) 0 } },
6772dd07 1354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1355/* R3R1: r3r1 */
1356 { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
1357 { 0, { (const PTR) 0 } },
6772dd07 1358 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1359/* R1R2R0: r1r2r0 */
1360 { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
1361 { 0, { (const PTR) 0 } },
6772dd07 1362 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1363/* Dst16An: address register */
1364 { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
1365 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
6772dd07 1366 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1367/* Dst16AnQI: address register QI view */
1368 { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
1369 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
6772dd07 1370 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1371/* Dst16AnHI: address register HI view */
1372 { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
1373 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
6772dd07 1374 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1375/* Dst16AnSI: address register SI view */
1376 { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
1377 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
6772dd07 1378 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1379/* Dst16An-S: address register HI view */
1380 { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
1381 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
6772dd07 1382 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1383/* Dst32AnUnprefixed: address register */
1384 { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
1385 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
6772dd07 1386 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1387/* Dst32AnUnprefixedQI: address register QI view */
1388 { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
1389 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
6772dd07 1390 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1391/* Dst32AnUnprefixedHI: address register HI view */
1392 { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
1393 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
6772dd07 1394 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1395/* Dst32AnUnprefixedSI: address register SI view */
1396 { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
1397 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
6772dd07 1398 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1399/* Dst32AnExtUnprefixed: address register */
1400 { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
1401 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
6772dd07 1402 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1403/* Dst32AnPrefixed: address register */
1404 { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
1405 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
6772dd07 1406 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1407/* Dst32AnPrefixedQI: address register QI view */
1408 { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
1409 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
6772dd07 1410 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1411/* Dst32AnPrefixedHI: address register HI view */
1412 { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
1413 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
6772dd07 1414 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1415/* Dst32AnPrefixedSI: address register SI view */
1416 { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
1417 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
6772dd07 1418 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1419/* Bit16An: address register bit view */
1420 { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
1421 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
6772dd07 1422 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1423/* Bit32AnPrefixed: address register bit */
1424 { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
1425 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
6772dd07 1426 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1427/* Bit32AnUnprefixed: address register bit */
1428 { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
1429 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
6772dd07 1430 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1431/* A0: a0 */
1432 { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
1433 { 0, { (const PTR) 0 } },
6772dd07 1434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1435/* A1: a1 */
1436 { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
1437 { 0, { (const PTR) 0 } },
6772dd07 1438 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1439/* sb: SB register */
1440 { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
1441 { 0, { (const PTR) 0 } },
6772dd07 1442 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1443/* fb: FB register */
1444 { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
1445 { 0, { (const PTR) 0 } },
6772dd07 1446 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1447/* sp: SP register */
1448 { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
1449 { 0, { (const PTR) 0 } },
6772dd07 1450 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1451/* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
1452 { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
1453 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
6772dd07 1454 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1455/* Regsetpop: popm regset */
1456 { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
1457 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
6772dd07 1458 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1459/* Regsetpush: pushm regset */
1460 { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
1461 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
6772dd07 1462 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1463/* Rn16-push-S: r0[lh] */
1464 { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
1465 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
6772dd07 1466 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1467/* An16-push-S: a[01] */
1468 { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
1469 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
6772dd07 1470 { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1471/* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
1472 { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
1473 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
6772dd07 1474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1475/* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
1476 { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
1477 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
6772dd07 1478 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1479/* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
1480 { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
1481 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
6772dd07 1482 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1483/* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
1484 { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
1485 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
6772dd07 1486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
f75eb1c0
DD		 1487/* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */
1488 { "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24,
1489 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } },
6772dd07 1490 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
e729279b
NC		 1491/* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
1492 { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
1493 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
6772dd07 1494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1495/* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
1496 { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
1497 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
6772dd07 1498 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1499/* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
1500 { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
1501 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
6772dd07 1502 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1503/* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
1504 { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
1505 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
6772dd07 1506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1507/* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
1508 { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
1509 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
6772dd07 1510 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1511/* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
1512 { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
1513 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
6772dd07 1514 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1515/* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
1516 { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
1517 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
6772dd07 1518 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1519/* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
1520 { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
1521 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
6772dd07 1522 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1523/* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
1524 { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
1525 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
6772dd07 1526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1527/* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
1528 { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
1529 { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
6772dd07 1530 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1531/* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
1532 { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
1533 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
6772dd07 1534 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1535/* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
1536 { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
1537 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
6772dd07 1538 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1539/* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
1540 { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
1541 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
6772dd07 1542 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1543/* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
1544 { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
1545 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
6772dd07 1546 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1547/* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
1548 { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
1549 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
6772dd07 1550 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1551/* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
1552 { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
1553 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
6772dd07 1554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1555/* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
1556 { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
1557 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
6772dd07 1558 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1559/* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
1560 { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
1561 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
6772dd07 1562 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1563/* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
1564 { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
1565 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
6772dd07 1566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1567/* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
1568 { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
1569 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
6772dd07 1570 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1571/* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
1572 { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
1573 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
6772dd07 1574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10 1575/* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
e729279b 1576 { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
49f58d10 1577 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
6772dd07 1578 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1579/* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
1580 { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
1581 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
6772dd07 1582 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10 1583/* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
e729279b 1584 { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
49f58d10 1585 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
6772dd07 1586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1587/* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
1588 { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
1589 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
6772dd07 1590 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1591/* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
1592 { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
1593 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
6772dd07 1594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10 1595/* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
e729279b 1596 { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
49f58d10 1597 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
6772dd07 1598 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1599/* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
1600 { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
1601 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
6772dd07 1602 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10 1603/* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
e729279b 1604 { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
49f58d10 1605 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
6772dd07 1606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1607/* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
1608 { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
1609 { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
6772dd07 1610 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1611/* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
1612 { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
1613 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
6772dd07 1614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
c6552317
DD		 1615/* Imm-8-s4n: negated 4 bit immediate at offset 8 bits */
1616 { "Imm-8-s4n", M32C_OPERAND_IMM_8_S4N, HW_H_SINT, 8, 4,
1617 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
6772dd07 1618 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1619/* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
1620 { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
1621 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
6772dd07 1622 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1623/* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
1624 { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
1625 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
6772dd07 1626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1627/* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
1628 { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
1629 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
6772dd07 1630 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1631/* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
1632 { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
1633 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
6772dd07 1634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
c6552317
DD		 1635/* Imm-12-s4n: negated 4 bit immediate at offset 12 bits */
1636 { "Imm-12-s4n", M32C_OPERAND_IMM_12_S4N, HW_H_SINT, 12, 4,
1637 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
6772dd07 1638 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1639/* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
1640 { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
1641 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
6772dd07 1642 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10 1643/* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
e729279b 1644 { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
49f58d10 1645 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
6772dd07 1646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1647/* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
1648 { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
1649 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
6772dd07 1650 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1651/* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
1652 { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
1653 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
6772dd07 1654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1655/* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
1656 { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
1657 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
6772dd07 1658 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1659/* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
1660 { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
1661 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
6772dd07 1662 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1663/* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
1664 { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
1665 { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
6772dd07 1666 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1667/* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
1668 { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
1669 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
6772dd07 1670 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1671/* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
1672 { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
1673 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
6772dd07 1674 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1675/* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
1676 { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
1677 { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
6772dd07 1678 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1679/* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
1680 { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
1681 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
6772dd07 1682 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1683/* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
1684 { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
1685 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
6772dd07 1686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1687/* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
1688 { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
1689 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
6772dd07 1690 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1691/* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
1692 { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
1693 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
6772dd07 1694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1695/* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
1696 { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
1697 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
6772dd07 1698 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1699/* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
1700 { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
1701 { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
6772dd07 1702 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1703/* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
1704 { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
1705 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
6772dd07 1706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1707/* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
1708 { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
1709 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
6772dd07 1710 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1711/* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
1712 { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
1713 { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
6772dd07 1714 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1715/* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
1716 { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
1717 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
6772dd07 1718 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1719/* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
1720 { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
1721 { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
6772dd07 1722 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1723/* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
1724 { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
1725 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
6772dd07 1726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1727/* Imm1-S: signed 1 bit immediate for short format binary insns */
1728 { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
1729 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
6772dd07 1730 { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1731/* Imm3-S: signed 3 bit immediate for short format binary insns */
1732 { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
1733 { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
6772dd07 1734 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1735/* Bitno16R: bit number for indexing registers */
1736 { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
1737 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
6772dd07 1738 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1739/* Bitno32Prefixed: bit number for indexing objects */
1740 { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
1741 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
6772dd07 1742 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1743/* Bitno32Unprefixed: bit number for indexing objects */
1744 { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
1745 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
6772dd07 1746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1747/* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
1748 { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
1749 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
6772dd07 1750 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10 1751/* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
e729279b 1752 { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
49f58d10 1753 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
6772dd07 1754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1755/* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
1756 { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
1757 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
6772dd07 1758 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10 1759/* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
e729279b 1760 { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
49f58d10 1761 { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
6772dd07 1762 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1763/* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
1764 { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
1765 { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
6772dd07 1766 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1767/* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
1768 { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
1769 { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
6772dd07 1770 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1771/* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
1772 { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
1773 { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
6772dd07 1774 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1775/* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
1776 { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
1777 { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
6772dd07 1778 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1779/* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
1780 { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
1781 { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
6772dd07 1782 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1783/* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
1784 { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
1785 { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
6772dd07 1786 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1787/* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
1788 { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
1789 { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
6772dd07 1790 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1791/* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
1792 { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
1793 { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
6772dd07 1794 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1795/* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
1796 { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
1797 { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
6772dd07 1798 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1799/* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
1800 { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
1801 { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
6772dd07 1802 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1803/* Lab-5-3: 3 bit label */
1804 { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
1805 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
6772dd07 1806 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1807/* Lab32-jmp-s: 3 bit label */
1808 { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
1809 { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
6772dd07 1810 { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1811/* Lab-8-8: 8 bit label */
1812 { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
1813 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
6772dd07 1814 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1815/* Lab-8-16: 16 bit label */
1816 { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
1817 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
6772dd07 1818 { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1819/* Lab-8-24: 24 bit label */
1820 { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
1821 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
6772dd07 1822 { 0|A(RELAX)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1823/* Lab-16-8: 8 bit label */
1824 { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
1825 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
6772dd07 1826 { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1827/* Lab-24-8: 8 bit label */
1828 { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
1829 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
6772dd07 1830 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1831/* Lab-32-8: 8 bit label */
1832 { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
1833 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
6772dd07 1834 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1835/* Lab-40-8: 8 bit label */
1836 { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
1837 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
6772dd07 1838 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1839/* sbit: negative bit */
1840 { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
1841 { 0, { (const PTR) 0 } },
6772dd07 1842 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1843/* obit: overflow bit */
1844 { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
1845 { 0, { (const PTR) 0 } },
6772dd07 1846 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1847/* zbit: zero bit */
1848 { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
1849 { 0, { (const PTR) 0 } },
6772dd07 1850 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1851/* cbit: carry bit */
1852 { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
1853 { 0, { (const PTR) 0 } },
6772dd07 1854 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1855/* ubit: stack ptr select bit */
1856 { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
1857 { 0, { (const PTR) 0 } },
6772dd07 1858 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1859/* ibit: interrupt enable bit */
1860 { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
1861 { 0, { (const PTR) 0 } },
6772dd07 1862 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1863/* bbit: reg bank select bit */
1864 { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
1865 { 0, { (const PTR) 0 } },
6772dd07 1866 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1867/* dbit: debug bit */
1868 { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
1869 { 0, { (const PTR) 0 } },
6772dd07 1870 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1871/* cond16-16: condition */
1872 { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
1873 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
6772dd07 1874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1875/* cond16-24: condition */
1876 { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
1877 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
6772dd07 1878 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1879/* cond16-32: condition */
1880 { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
1881 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
6772dd07 1882 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1883/* cond32-16: condition */
1884 { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
1885 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
6772dd07 1886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1887/* cond32-24: condition */
1888 { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
1889 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
6772dd07 1890 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1891/* cond32-32: condition */
1892 { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
1893 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
6772dd07 1894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1895/* cond32-40: condition */
1896 { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
1897 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
6772dd07 1898 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1899/* cond16c: condition */
1900 { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
1901 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
6772dd07 1902 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1903/* cond16j: condition */
1904 { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
1905 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
6772dd07 1906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1907/* cond16j5: condition */
1908 { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
1909 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
6772dd07 1910 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1911/* cond32: condition */
1912 { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
1913 { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
6772dd07 1914 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1915/* cond32j: condition */
1916 { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
1917 { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
6772dd07 1918 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1919/* sccond32: scCND condition */
1920 { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
1921 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
6772dd07 1922 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1923/* flags16: flags */
1924 { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
1925 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
6772dd07 1926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1927/* flags32: flags */
1928 { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
1929 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
6772dd07 1930 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1931/* cr16: control */
1932 { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
1933 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
6772dd07 1934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1935/* cr1-Unprefixed-32: control */
1936 { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
1937 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
6772dd07 1938 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1939/* cr1-Prefixed-32: control */
1940 { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
1941 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
6772dd07 1942 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1943/* cr2-32: control */
1944 { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
1945 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
6772dd07 1946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1947/* cr3-Unprefixed-32: control */
1948 { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
1949 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
6772dd07 1950 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1951/* cr3-Prefixed-32: control */
1952 { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
1953 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
6772dd07 1954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1955/* Z: Suffix for zero format insns */
1956 { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
1957 { 0, { (const PTR) 0 } },
6772dd07 1958 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1959/* S: Suffix for short format insns */
1960 { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
1961 { 0, { (const PTR) 0 } },
6772dd07 1962 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1963/* Q: Suffix for quick format insns */
1964 { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
1965 { 0, { (const PTR) 0 } },
6772dd07 1966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1967/* G: Suffix for general format insns */
1968 { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
1969 { 0, { (const PTR) 0 } },
6772dd07 1970 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1971/* X: Empty suffix */
1972 { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
1973 { 0, { (const PTR) 0 } },
6772dd07 1974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1975/* size: any size specifier */
1976 { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
1977 { 0, { (const PTR) 0 } },
6772dd07 1978 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1979/* BitIndex: Bit Index for the next insn */
1980 { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
1981 { 0, { (const PTR) 0 } },
6772dd07 1982 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1983/* SrcIndex: Source Index for the next insn */
1984 { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
1985 { 0, { (const PTR) 0 } },
6772dd07 1986 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1987/* DstIndex: Destination Index for the next insn */
1988 { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
1989 { 0, { (const PTR) 0 } },
6772dd07 1990 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1991/* NoRemainder: Place holder for when the remainder is not kept */
1992 { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
1993 { 0, { (const PTR) 0 } },
6772dd07 1994 { 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 1995/* src16-Rn-direct-QI: m16c Rn direct source QI */
1996/* src16-Rn-direct-HI: m16c Rn direct source HI */
1997/* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */
1998/* src32-Rn-direct-Prefixed-QI: m32c Rn direct source QI */
1999/* src32-Rn-direct-Unprefixed-HI: m32c Rn direct source HI */
2000/* src32-Rn-direct-Prefixed-HI: m32c Rn direct source HI */
2001/* src32-Rn-direct-Unprefixed-SI: m32c Rn direct source SI */
2002/* src32-Rn-direct-Prefixed-SI: m32c Rn direct source SI */
2003/* src16-An-direct-QI: m16c An direct destination QI */
2004/* src16-An-direct-HI: m16c An direct destination HI */
2005/* src32-An-direct-Unprefixed-QI: m32c An direct destination QI */
2006/* src32-An-direct-Unprefixed-HI: m32c An direct destination HI */
2007/* src32-An-direct-Unprefixed-SI: m32c An direct destination SI */
2008/* src32-An-direct-Prefixed-QI: m32c An direct destination QI */
2009/* src32-An-direct-Prefixed-HI: m32c An direct destination HI */
2010/* src32-An-direct-Prefixed-SI: m32c An direct destination SI */
2011/* src16-An-indirect-QI: m16c An indirect destination QI */
2012/* src16-An-indirect-HI: m16c An indirect destination HI */
2013/* src32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
2014/* src32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
2015/* src32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
2016/* src32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
2017/* src32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
2018/* src32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
2019/* src16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2020/* src16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2021/* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2022/* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2023/* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2024/* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2025/* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2026/* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2027/* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2028/* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2029/* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2030/* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2031/* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2032/* src32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2033/* src32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2034/* src32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2035/* src32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2036/* src32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2037/* src32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2038/* src32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2039/* src32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2040/* src32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2041/* src32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2042/* src32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2043/* src32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2044/* src32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2045/* src32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2046/* src32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2047/* src32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2048/* src32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2049/* src32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2050/* src32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2051/* src32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2052/* src32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2053/* src32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2054/* src32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2055/* src32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2056/* src32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2057/* src32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2058/* src32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2059/* src32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2060/* src32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2061/* src32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2062/* src32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2063/* src32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2064/* src32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2065/* src32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2066/* src32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2067/* src32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2068/* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2069/* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2070/* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2071/* src16-16-16-absolute-QI: m16c absolute address QI */
2072/* src16-16-16-absolute-HI: m16c absolute address HI */
2073/* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2074/* src32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2075/* src32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2076/* src32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2077/* src32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2078/* src32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2079/* src32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2080/* src32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2081/* src32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2082/* src32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2083/* src32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2084/* src32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2085/* src16-2-S-8-SB-relative-QI: m16c SB relative address */
2086/* src16-2-S-8-FB-relative-QI: m16c FB relative address */
2087/* src16-2-S-16-absolute-QI: m16c absolute address */
2088/* src32-2-S-8-SB-relative-QI: m32c SB relative address */
2089/* src32-2-S-8-FB-relative-QI: m32c FB relative address */
2090/* src32-2-S-16-absolute-QI: m32c absolute address */
2091/* src32-2-S-8-SB-relative-HI: m32c SB relative address */
2092/* src32-2-S-8-FB-relative-HI: m32c FB relative address */
2093/* src32-2-S-16-absolute-HI: m32c absolute address */
2094/* dst16-Rn-direct-QI: m16c Rn direct destination QI */
2095/* dst16-Rn-direct-HI: m16c Rn direct destination HI */
2096/* dst16-Rn-direct-SI: m16c Rn direct destination SI */
2097/* dst16-Rn-direct-Ext-QI: m16c Rn direct destination QI */
2098/* dst32-Rn-direct-Unprefixed-QI: m32c Rn direct destination QI */
2099/* dst32-Rn-direct-Prefixed-QI: m32c Rn direct destination QI */
2100/* dst32-Rn-direct-Unprefixed-HI: m32c Rn direct destination HI */
2101/* dst32-Rn-direct-Prefixed-HI: m32c Rn direct destination HI */
2102/* dst32-Rn-direct-Unprefixed-SI: m32c Rn direct destination SI */
2103/* dst32-Rn-direct-Prefixed-SI: m32c Rn direct destination SI */
2104/* dst32-Rn-direct-ExtUnprefixed-QI: m32c Rn direct destination QI */
2105/* dst32-Rn-direct-ExtUnprefixed-HI: m32c Rn direct destination HI */
2106/* dst32-R3-direct-Unprefixed-HI: m32c R3 direct HI */
2107/* dst16-An-direct-QI: m16c An direct destination QI */
2108/* dst16-An-direct-HI: m16c An direct destination HI */
2109/* dst16-An-direct-SI: m16c An direct destination SI */
2110/* dst32-An-direct-Unprefixed-QI: m32c An direct destination QI */
2111/* dst32-An-direct-Prefixed-QI: m32c An direct destination QI */
2112/* dst32-An-direct-Unprefixed-HI: m32c An direct destination HI */
2113/* dst32-An-direct-Prefixed-HI: m32c An direct destination HI */
2114/* dst32-An-direct-Unprefixed-SI: m32c An direct destination SI */
2115/* dst32-An-direct-Prefixed-SI: m32c An direct destination SI */
2116/* dst16-An-indirect-QI: m16c An indirect destination QI */
2117/* dst16-An-indirect-HI: m16c An indirect destination HI */
2118/* dst16-An-indirect-SI: m16c An indirect destination SI */
2119/* dst16-An-indirect-Ext-QI: m16c An indirect destination QI */
2120/* dst32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
2121/* dst32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
2122/* dst32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
2123/* dst32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
2124/* dst32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
2125/* dst32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
2126/* dst32-An-indirect-ExtUnprefixed-QI: m32c An indirect destination QI */
2127/* dst32-An-indirect-ExtUnprefixed-HI: m32c An indirect destination HI */
2128/* dst16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2129/* dst16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2130/* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2131/* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2132/* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2133/* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2134/* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2135/* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2136/* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2137/* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2138/* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2139/* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2140/* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2141/* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2142/* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2143/* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2144/* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2145/* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2146/* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2147/* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2148/* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2149/* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2150/* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2151/* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2152/* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2153/* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2154/* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2155/* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2156/* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2157/* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2158/* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2159/* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2160/* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2161/* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2162/* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2163/* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2164/* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2165/* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2166/* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2167/* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2168/* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2169/* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2170/* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2171/* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2172/* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2173/* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2174/* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2175/* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2176/* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2177/* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2178/* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2179/* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2180/* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2181/* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2182/* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2183/* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2184/* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2185/* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2186/* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2187/* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2188/* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2189/* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2190/* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2191/* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2192/* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2193/* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2194/* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2195/* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2196/* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2197/* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2198/* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2199/* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2200/* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2201/* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2202/* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2203/* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */
2204/* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */
2205/* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */
2206/* dst16-16-8-An-relative-Ext-QI: m16c dsp:8[An] relative destination QI */
2207/* dst16-16-16-An-relative-Ext-QI: m16c dsp:16[An] relative destination QI */
2208/* dst32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2209/* dst32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2210/* dst32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2211/* dst32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2212/* dst32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2213/* dst32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2214/* dst32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2215/* dst32-24-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2216/* dst32-24-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2217/* dst32-24-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2218/* dst32-24-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2219/* dst32-24-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2220/* dst32-24-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2221/* dst32-24-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2222/* dst32-32-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2223/* dst32-32-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2224/* dst32-32-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2225/* dst32-32-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2226/* dst32-32-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2227/* dst32-32-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2228/* dst32-32-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2229/* dst32-40-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2230/* dst32-40-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2231/* dst32-40-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2232/* dst32-40-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2233/* dst32-40-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2234/* dst32-40-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2235/* dst32-40-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2236/* dst32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2237/* dst32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2238/* dst32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2239/* dst32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2240/* dst32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2241/* dst32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2242/* dst32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2243/* dst32-24-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2244/* dst32-24-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2245/* dst32-24-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2246/* dst32-24-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2247/* dst32-24-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2248/* dst32-24-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2249/* dst32-24-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2250/* dst32-32-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2251/* dst32-32-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2252/* dst32-32-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2253/* dst32-32-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2254/* dst32-32-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2255/* dst32-32-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2256/* dst32-32-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2257/* dst32-40-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2258/* dst32-40-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2259/* dst32-40-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2260/* dst32-40-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2261/* dst32-40-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2262/* dst32-40-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2263/* dst32-40-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2264/* dst32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2265/* dst32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2266/* dst32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2267/* dst32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2268/* dst32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2269/* dst32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2270/* dst32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2271/* dst32-24-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2272/* dst32-24-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2273/* dst32-24-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2274/* dst32-24-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2275/* dst32-24-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2276/* dst32-24-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2277/* dst32-24-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2278/* dst32-32-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2279/* dst32-32-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2280/* dst32-32-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2281/* dst32-32-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2282/* dst32-32-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2283/* dst32-32-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2284/* dst32-32-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2285/* dst32-40-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2286/* dst32-40-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2287/* dst32-40-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2288/* dst32-40-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2289/* dst32-40-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2290/* dst32-40-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2291/* dst32-40-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2292/* dst32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2293/* dst32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2294/* dst32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2295/* dst32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2296/* dst32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2297/* dst32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2298/* dst32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2299/* dst32-32-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2300/* dst32-32-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2301/* dst32-32-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2302/* dst32-32-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2303/* dst32-32-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2304/* dst32-32-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2305/* dst32-32-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2306/* dst32-40-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2307/* dst32-40-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2308/* dst32-40-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2309/* dst32-40-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2310/* dst32-40-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2311/* dst32-40-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2312/* dst32-40-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2313/* dst32-48-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2314/* dst32-48-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2315/* dst32-48-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2316/* dst32-48-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2317/* dst32-48-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2318/* dst32-48-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2319/* dst32-48-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2320/* dst32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2321/* dst32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2322/* dst32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2323/* dst32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2324/* dst32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2325/* dst32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2326/* dst32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2327/* dst32-32-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2328/* dst32-32-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2329/* dst32-32-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2330/* dst32-32-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2331/* dst32-32-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2332/* dst32-32-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2333/* dst32-32-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2334/* dst32-40-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2335/* dst32-40-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2336/* dst32-40-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2337/* dst32-40-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2338/* dst32-40-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2339/* dst32-40-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2340/* dst32-40-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2341/* dst32-48-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2342/* dst32-48-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2343/* dst32-48-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2344/* dst32-48-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2345/* dst32-48-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2346/* dst32-48-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2347/* dst32-48-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2348/* dst32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2349/* dst32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2350/* dst32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2351/* dst32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2352/* dst32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2353/* dst32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2354/* dst32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2355/* dst32-32-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2356/* dst32-32-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2357/* dst32-32-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2358/* dst32-32-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2359/* dst32-32-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2360/* dst32-32-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2361/* dst32-32-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2362/* dst32-40-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2363/* dst32-40-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2364/* dst32-40-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2365/* dst32-40-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2366/* dst32-40-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2367/* dst32-40-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2368/* dst32-40-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2369/* dst32-48-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2370/* dst32-48-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2371/* dst32-48-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2372/* dst32-48-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2373/* dst32-48-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2374/* dst32-48-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2375/* dst32-48-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2376/* dst32-16-8-SB-relative-ExtUnprefixed-QI: m32c dsp:8[sb] relative destination QI */
2377/* dst32-16-16-SB-relative-ExtUnprefixed-QI: m32c dsp:16[sb] relative destination QI */
2378/* dst32-16-8-FB-relative-ExtUnprefixed-QI: m32c dsp:8[fb] relative destination QI */
2379/* dst32-16-16-FB-relative-ExtUnprefixed-QI: m32c dsp:16[fb] relative destination QI */
2380/* dst32-16-8-An-relative-ExtUnprefixed-QI: m32c dsp:8[An] relative destination QI */
2381/* dst32-16-16-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2382/* dst32-16-24-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2383/* dst32-16-8-SB-relative-ExtUnprefixed-HI: m32c dsp:8[sb] relative destination HI */
2384/* dst32-16-16-SB-relative-ExtUnprefixed-HI: m32c dsp:16[sb] relative destination HI */
2385/* dst32-16-8-FB-relative-ExtUnprefixed-HI: m32c dsp:8[fb] relative destination HI */
2386/* dst32-16-16-FB-relative-ExtUnprefixed-HI: m32c dsp:16[fb] relative destination HI */
2387/* dst32-16-8-An-relative-ExtUnprefixed-HI: m32c dsp:8[An] relative destination HI */
2388/* dst32-16-16-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2389/* dst32-16-24-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2390/* dst16-16-16-absolute-QI: m16c absolute address QI */
2391/* dst16-24-16-absolute-QI: m16c absolute address QI */
2392/* dst16-32-16-absolute-QI: m16c absolute address QI */
2393/* dst16-40-16-absolute-QI: m16c absolute address QI */
2394/* dst16-48-16-absolute-QI: m16c absolute address QI */
2395/* dst16-16-16-absolute-HI: m16c absolute address HI */
2396/* dst16-24-16-absolute-HI: m16c absolute address HI */
2397/* dst16-32-16-absolute-HI: m16c absolute address HI */
2398/* dst16-40-16-absolute-HI: m16c absolute address HI */
2399/* dst16-48-16-absolute-HI: m16c absolute address HI */
2400/* dst16-16-16-absolute-SI: m16c absolute address SI */
2401/* dst16-24-16-absolute-SI: m16c absolute address SI */
2402/* dst16-32-16-absolute-SI: m16c absolute address SI */
2403/* dst16-40-16-absolute-SI: m16c absolute address SI */
2404/* dst16-48-16-absolute-SI: m16c absolute address SI */
2405/* dst16-16-16-absolute-Ext-QI: m16c absolute address QI */
2406/* dst32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2407/* dst32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2408/* dst32-24-16-absolute-Unprefixed-QI: m32c absolute address QI */
2409/* dst32-24-24-absolute-Unprefixed-QI: m32c absolute address QI */
2410/* dst32-32-16-absolute-Unprefixed-QI: m32c absolute address QI */
2411/* dst32-32-24-absolute-Unprefixed-QI: m32c absolute address QI */
2412/* dst32-40-16-absolute-Unprefixed-QI: m32c absolute address QI */
2413/* dst32-40-24-absolute-Unprefixed-QI: m32c absolute address QI */
2414/* dst32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2415/* dst32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2416/* dst32-24-16-absolute-Unprefixed-HI: m32c absolute address HI */
2417/* dst32-24-24-absolute-Unprefixed-HI: m32c absolute address HI */
2418/* dst32-32-16-absolute-Unprefixed-HI: m32c absolute address HI */
2419/* dst32-32-24-absolute-Unprefixed-HI: m32c absolute address HI */
2420/* dst32-40-16-absolute-Unprefixed-HI: m32c absolute address HI */
2421/* dst32-40-24-absolute-Unprefixed-HI: m32c absolute address HI */
2422/* dst32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2423/* dst32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2424/* dst32-24-16-absolute-Unprefixed-SI: m32c absolute address SI */
2425/* dst32-24-24-absolute-Unprefixed-SI: m32c absolute address SI */
2426/* dst32-32-16-absolute-Unprefixed-SI: m32c absolute address SI */
2427/* dst32-32-24-absolute-Unprefixed-SI: m32c absolute address SI */
2428/* dst32-40-16-absolute-Unprefixed-SI: m32c absolute address SI */
2429/* dst32-40-24-absolute-Unprefixed-SI: m32c absolute address SI */
2430/* dst32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2431/* dst32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2432/* dst32-32-16-absolute-Prefixed-QI: m32c absolute address QI */
2433/* dst32-32-24-absolute-Prefixed-QI: m32c absolute address QI */
2434/* dst32-40-16-absolute-Prefixed-QI: m32c absolute address QI */
2435/* dst32-40-24-absolute-Prefixed-QI: m32c absolute address QI */
2436/* dst32-48-16-absolute-Prefixed-QI: m32c absolute address QI */
2437/* dst32-48-24-absolute-Prefixed-QI: m32c absolute address QI */
2438/* dst32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2439/* dst32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2440/* dst32-32-16-absolute-Prefixed-HI: m32c absolute address HI */
2441/* dst32-32-24-absolute-Prefixed-HI: m32c absolute address HI */
2442/* dst32-40-16-absolute-Prefixed-HI: m32c absolute address HI */
2443/* dst32-40-24-absolute-Prefixed-HI: m32c absolute address HI */
2444/* dst32-48-16-absolute-Prefixed-HI: m32c absolute address HI */
2445/* dst32-48-24-absolute-Prefixed-HI: m32c absolute address HI */
2446/* dst32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2447/* dst32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2448/* dst32-32-16-absolute-Prefixed-SI: m32c absolute address SI */
2449/* dst32-32-24-absolute-Prefixed-SI: m32c absolute address SI */
2450/* dst32-40-16-absolute-Prefixed-SI: m32c absolute address SI */
2451/* dst32-40-24-absolute-Prefixed-SI: m32c absolute address SI */
2452/* dst32-48-16-absolute-Prefixed-SI: m32c absolute address SI */
2453/* dst32-48-24-absolute-Prefixed-SI: m32c absolute address SI */
2454/* dst32-16-16-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2455/* dst32-16-24-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2456/* dst32-16-16-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2457/* dst32-16-24-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2458/* bit16-Rn-direct: m16c Rn direct bit */
2459/* bit32-Rn-direct-Unprefixed: m32c Rn direct bit */
2460/* bit32-Rn-direct-Prefixed: m32c Rn direct bit */
2461/* bit16-An-direct: m16c An direct bit */
2462/* bit32-An-direct-Unprefixed: m32c An direct bit */
2463/* bit32-An-direct-Prefixed: m32c An direct bit */
2464/* bit16-An-indirect: m16c An indirect bit */
2465/* bit32-An-indirect-Unprefixed: m32c An indirect destination */
2466/* bit32-An-indirect-Prefixed: m32c An indirect destination */
2467/* bit16-16-8-SB-relative: m16c dsp:8[sb] relative bit xmode */
2468/* bit16-16-16-SB-relative: m16c dsp:16[sb] relative bit xmode */
2469/* bit16-16-8-FB-relative: m16c dsp:8[fb] relative bit xmode */
2470/* bit16-16-8-An-relative: m16c dsp:8[An] relative bit xmode */
2471/* bit16-16-16-An-relative: m16c dsp:16[An] relative bit xmode */
2472/* bit32-16-11-SB-relative-Unprefixed: m32c bit,base:11[sb] relative bit */
2473/* bit32-16-19-SB-relative-Unprefixed: m32c bit,base:19[sb] relative bit */
2474/* bit32-16-11-FB-relative-Unprefixed: m32c bit,base:11[fb] relative bit */
2475/* bit32-16-19-FB-relative-Unprefixed: m32c bit,base:19[fb] relative bit */
2476/* bit32-16-11-An-relative-Unprefixed: m32c bit,base:11[An] relative bit */
2477/* bit32-16-19-An-relative-Unprefixed: m32c bit,base:19[An] relative bit */
2478/* bit32-16-27-An-relative-Unprefixed: m32c bit,base:27[An] relative bit */
2479/* bit32-24-11-SB-relative-Prefixed: m32c bit,base:11[sb] relative bit */
2480/* bit32-24-19-SB-relative-Prefixed: m32c bit,base:19[sb] relative bit */
2481/* bit32-24-11-FB-relative-Prefixed: m32c bit,base:11[fb] relative bit */
2482/* bit32-24-19-FB-relative-Prefixed: m32c bit,base:19[fb] relative bit */
2483/* bit32-24-11-An-relative-Prefixed: m32c bit,base:11[An] relative bit */
2484/* bit32-24-19-An-relative-Prefixed: m32c bit,base:19[An] relative bit */
2485/* bit32-24-27-An-relative-Prefixed: m32c bit,base:27[An] relative bit */
2486/* bit16-11-SB-relative-S: m16c bit,base:11[sb] relative bit */
2487/* Rn16-push-S-derived: m16c r0[lh] for push,pop short version */
2488/* An16-push-S-derived: m16c r0[lh] for push,pop short version */
2489/* bit16-16-16-absolute: m16c absolute address */
2490/* bit32-16-19-absolute-Unprefixed: m32c absolute address bit */
2491/* bit32-16-27-absolute-Unprefixed: m32c absolute address bit */
2492/* bit32-24-19-absolute-Prefixed: m32c absolute address bit */
2493/* bit32-24-27-absolute-Prefixed: m32c absolute address bit */
2494/* dst16-3-S-R0l-direct-QI: m16c R0l direct QI */
2495/* dst16-3-S-R0h-direct-QI: m16c R0h direct QI */
2496/* dst16-3-S-8-8-SB-relative-QI: m16c SB relative QI */
2497/* dst16-3-S-8-8-FB-relative-QI: m16c FB relative QI */
2498/* dst16-3-S-8-16-absolute-QI: m16c absolute address QI */
2499/* dst16-3-S-16-8-SB-relative-QI: m16c SB relative QI */
2500/* dst16-3-S-16-8-FB-relative-QI: m16c FB relative QI */
2501/* dst16-3-S-16-16-absolute-QI: m16c absolute address QI */
2502/* srcdst16-r0l-r0h-S-derived: m16c r0l/r0h operand for short format insns */
2503/* dst32-2-S-R0l-direct-QI: m32c R0l direct QI */
2504/* dst32-2-S-R0-direct-HI: m32c R0 direct HI */
2505/* dst32-1-S-A0-direct-HI: m32c A0 direct HI */
2506/* dst32-1-S-A1-direct-HI: m32c A1 direct HI */
2507/* dst32-2-S-8-SB-relative-QI: m32c SB relative for short binary insns */
2508/* dst32-2-S-8-FB-relative-QI: m32c FB relative for short binary insns */
2509/* dst32-2-S-16-absolute-QI: m32c absolute address for short binary insns */
2510/* dst32-2-S-8-SB-relative-HI: m32c SB relative for short binary insns */
2511/* dst32-2-S-8-FB-relative-HI: m32c FB relative for short binary insns */
2512/* dst32-2-S-16-absolute-HI: m32c absolute address for short binary insns */
2513/* dst32-2-S-8-SB-relative-SI: m32c SB relative for short binary insns */
2514/* dst32-2-S-8-FB-relative-SI: m32c FB relative for short binary insns */
2515/* dst32-2-S-16-absolute-SI: m32c absolute address for short binary insns */
2516/* src16-basic-QI: m16c source operand of size QI with no additional fields */
2517/* src16-basic-HI: m16c source operand of size HI with no additional fields */
2518/* src32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2519/* src32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2520/* src32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2521/* src32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2522/* src32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2523/* src32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2524/* src32-basic-ExtPrefixed-QI: m32c source operand of size QI with no additional fields */
2525/* src16-16-8-QI: m16c source operand of size QI with additional 8 bit fields at offset 16 */
2526/* src16-16-16-QI: m16c source operand of size QI with additional 16 bit fields at offset 16 */
2527/* src16-16-8-HI: m16c source operand of size HI with additional 8 bit fields at offset 16 */
2528/* src16-16-16-HI: m16c source operand of size HI with additional 16 bit fields at offset 16 */
2529/* src32-16-8-Unprefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 16 */
2530/* src32-16-16-Unprefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2531/* src32-16-24-Unprefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2532/* src32-16-8-Unprefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 16 */
2533/* src32-16-16-Unprefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2534/* src32-16-24-Unprefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2535/* src32-16-8-Unprefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 16 */
2536/* src32-16-16-Unprefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2537/* src32-16-24-Unprefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2538/* src32-24-8-Prefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 24 */
2539/* src32-24-16-Prefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2540/* src32-24-24-Prefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2541/* src32-24-8-Prefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 24 */
2542/* src32-24-16-Prefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2543/* src32-24-24-Prefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2544/* src32-24-8-Prefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 24 */
2545/* src32-24-16-Prefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2546/* src32-24-24-Prefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2547/* dst16-basic-QI: m16c destination operand of size QI with no additional fields */
2548/* dst16-basic-HI: m16c destination operand of size HI with no additional fields */
2549/* dst16-basic-SI: m16c destination operand of size SI with no additional fields */
2550/* dst32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2551/* dst32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2552/* dst32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2553/* dst32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2554/* dst32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2555/* dst32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2556/* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2557/* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */
2558/* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2559/* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2560/* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */
2561/* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2562/* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2563/* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */
2564/* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2565/* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */
2566/* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */
2567/* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */
2568/* dst16-16-16-An-relative-Mova-HI: m16c addressof dsp:16[An] relative destination HI */
2569/* dst16-16-8-SB-relative-Mova-HI: m16c addressof dsp:8[sb] relative destination HI */
2570/* dst16-16-16-SB-relative-Mova-HI: m16c addressof dsp:16[sb] relative destination HI */
2571/* dst16-16-8-FB-relative-Mova-HI: m16c addressof dsp:8[fb] relative destination HI */
2572/* dst16-16-16-absolute-Mova-HI: m16c addressof absolute address HI */
2573/* dst16-16-Mova-HI: m16c addressof destination operand of size HI with additional fields at offset 16 */
2574/* dst32-An-indirect-Unprefixed-Mova-SI: m32c addressof An indirect destination SI */
2575/* dst32-16-8-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[An] relative destination SI */
2576/* dst32-16-16-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[An] relative destination SI */
2577/* dst32-16-24-An-relative-Unprefixed-Mova-SI: addressof m32c dsp:16[An] relative destination SI */
2578/* dst32-16-8-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[sb] relative destination SI */
2579/* dst32-16-16-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[sb] relative destination SI */
2580/* dst32-16-8-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[fb] relative destination SI */
2581/* dst32-16-16-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[fb] relative destination SI */
2582/* dst32-16-16-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2583/* dst32-16-24-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2584/* dst32-16-Unprefixed-Mova-SI: m32c addressof destination operand of size SI with additional fields at offset 16 */
2585/* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2586/* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2587/* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2588/* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2589/* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2590/* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2591/* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2592/* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2593/* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2594/* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2595/* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2596/* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2597/* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2598/* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2599/* dst32-16-Unprefixed-Mulex-HI: m32c destination operand of size HI with additional fields at offset 16 */
2600/* dst16-24-QI: m16c destination operand of size QI with additional fields at offset 24 */
2601/* dst16-24-HI: m16c destination operand of size HI with additional fields at offset 24 */
2602/* dst32-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2603/* dst32-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2604/* dst32-24-8-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2605/* dst32-24-16-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2606/* dst32-24-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2607/* dst32-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2608/* dst32-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2609/* dst32-24-8-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2610/* dst32-24-16-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2611/* dst32-24-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2612/* dst32-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2613/* dst32-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2614/* dst32-24-8-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2615/* dst32-24-16-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2616/* dst32-24-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2617/* dst16-32-QI: m16c destination operand of size QI with additional fields at offset 32 */
2618/* dst16-32-HI: m16c destination operand of size HI with additional fields at offset 32 */
2619/* dst32-32-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2620/* dst32-32-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2621/* dst32-32-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2622/* dst32-32-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2623/* dst32-32-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2624/* dst32-32-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2625/* dst32-40-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2626/* dst32-40-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2627/* dst32-40-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2628/* dst32-40-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2629/* dst32-40-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2630/* dst32-40-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2631/* dst32-48-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2632/* dst32-48-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2633/* dst32-48-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2634/* bit16-16: m16c bit operand with possible additional fields at offset 24 */
2635/* bit16-16-basic: m16c bit operand with no additional fields */
2636/* bit16-16-8: m16c bit operand with possible additional fields at offset 24 */
2637/* bit16-16-16: m16c bit operand with possible additional fields at offset 24 */
2638/* bit32-16-Unprefixed: m32c bit operand with possible additional fields at offset 24 */
2639/* bit32-24-Prefixed: m32c bit operand with possible additional fields at offset 24 */
2640/* bit32-basic-Unprefixed: m32c bit operand with no additional fields */
2641/* bit32-16-8-Unprefixed: m32c bit operand with 8 bit additional fields */
2642/* bit32-16-16-Unprefixed: m32c bit operand with 16 bit additional fields */
2643/* bit32-16-24-Unprefixed: m32c bit operand with 24 bit additional fields */
2644/* src16-2-S: m16c source operand of size QI for short format insns */
2645/* src32-2-S-QI: m32c source operand of size QI for short format insns */
2646/* src32-2-S-HI: m32c source operand of size QI for short format insns */
2647/* Dst16-3-S-8: m16c destination operand of size QI for short format insns */
2648/* Dst16-3-S-16: m16c destination operand of size QI for short format insns */
2649/* srcdst16-r0l-r0h-S: m16c r0l/r0h operand of size QI for short format insns */
2650/* dst32-2-S-basic-QI: m32c r0l operand of size QI for short format binary insns */
2651/* dst32-2-S-basic-HI: m32c r0 operand of size HI for short format binary insns */
2652/* dst32-2-S-8-QI: m32c operand of size */
2653/* dst32-2-S-16-QI: m32c operand of size */
2654/* dst32-2-S-8-HI: m32c operand of size */
2655/* dst32-2-S-16-HI: m32c operand of size */
2656/* dst32-2-S-8-SI: m32c operand of size */
2657/* dst32-2-S-16-SI: m32c operand of size */
2658/* dst32-an-S: m32c An operand for short format binary insns */
2659/* bit16-11-S: m16c bit operand for short format insns */
2660/* Rn16-push-S-anyof: m16c bit operand for short format insns */
2661/* An16-push-S-anyof: m16c bit operand for short format insns */
2662/* sentinel */
2663 { 0, 0, 0, 0, 0,
2664 { 0, { (const PTR) 0 } },
6772dd07 2665 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } }
49f58d10
JB		 2666};
2667
2668#undef A
2669
2670
2671/* The instruction table. */
2672
2673#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2674#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2675#define A(a) (1 << CGEN_INSN_##a)
2676#else
2677#define A(a) (1 << CGEN_INSN_/**/a)
2678#endif
2679
2680static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
2681{
2682 /* Special null first entry.
2683 A `num' value of zero is thus invalid.
2684 Also, the special `invalid' insn resides here. */
6772dd07 2685 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
49f58d10
JB		 2686/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2687 {
2688 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
6772dd07 2689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2690 },
2691/* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
2692 {
2693 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
6772dd07 2694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2695 },
2696/* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
2697 {
2698 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
6772dd07 2699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2700 },
2701/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2702 {
2703 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
6772dd07 2704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2705 },
2706/* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
2707 {
2708 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
6772dd07 2709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2710 },
2711/* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
2712 {
2713 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
6772dd07 2714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2715 },
2716/* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2717 {
2718 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
6772dd07 2719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2720 },
2721/* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
2722 {
2723 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
6772dd07 2724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2725 },
2726/* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
2727 {
2728 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
6772dd07 2729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2730 },
2731/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
2732 {
2733 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
6772dd07 2734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2735 },
2736/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2737 {
2738 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
6772dd07 2739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2740 },
2741/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2742 {
2743 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
6772dd07 2744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2745 },
2746/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
2747 {
2748 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
6772dd07 2749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2750 },
2751/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2752 {
2753 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
6772dd07 2754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2755 },
2756/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2757 {
2758 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
6772dd07 2759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2760 },
2761/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
2762 {
2763 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
6772dd07 2764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2765 },
2766/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2767 {
2768 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
6772dd07 2769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2770 },
2771/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2772 {
2773 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
6772dd07 2774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2775 },
2776/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
2777 {
2778 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
6772dd07 2779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2780 },
2781/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
2782 {
2783 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
6772dd07 2784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2785 },
2786/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
2787 {
2788 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
6772dd07 2789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2790 },
2791/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
2792 {
2793 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
6772dd07 2794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2795 },
2796/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
2797 {
2798 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
6772dd07 2799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2800 },
2801/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
2802 {
2803 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
6772dd07 2804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2805 },
2806/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
2807 {
2808 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
6772dd07 2809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2810 },
2811/* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
2812 {
2813 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
6772dd07 2814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2815 },
2816/* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
2817 {
2818 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
6772dd07 2819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2820 },
2821/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
2822 {
2823 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
6772dd07 2824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2825 },
2826/* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
2827 {
2828 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
6772dd07 2829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2830 },
2831/* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
2832 {
2833 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
6772dd07 2834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2835 },
2836/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
2837 {
2838 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
6772dd07 2839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2840 },
2841/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
2842 {
2843 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
6772dd07 2844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2845 },
2846/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
2847 {
2848 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
6772dd07 2849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2850 },
2851/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
2852 {
2853 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
6772dd07 2854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2855 },
2856/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
2857 {
2858 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
6772dd07 2859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2860 },
2861/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
2862 {
2863 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
6772dd07 2864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2865 },
2866/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2867 {
2868 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
6772dd07 2869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2870 },
2871/* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
2872 {
2873 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
6772dd07 2874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2875 },
2876/* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
2877 {
2878 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
6772dd07 2879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2880 },
2881/* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
2882 {
2883 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
6772dd07 2884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2885 },
2886/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2887 {
2888 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
6772dd07 2889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2890 },
2891/* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
2892 {
2893 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
6772dd07 2894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2895 },
2896/* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
2897 {
2898 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
6772dd07 2899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2900 },
2901/* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
2902 {
2903 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
6772dd07 2904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2905 },
2906/* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2907 {
2908 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
6772dd07 2909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2910 },
2911/* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
2912 {
2913 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
6772dd07 2914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2915 },
2916/* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
2917 {
2918 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
6772dd07 2919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2920 },
2921/* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
2922 {
2923 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
6772dd07 2924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2925 },
2926/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
2927 {
2928 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
6772dd07 2929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2930 },
2931/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2932 {
2933 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
6772dd07 2934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2935 },
2936/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2937 {
2938 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
6772dd07 2939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2940 },
2941/* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
2942 {
2943 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
6772dd07 2944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2945 },
2946/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
2947 {
2948 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
6772dd07 2949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2950 },
2951/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2952 {
2953 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
6772dd07 2954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2955 },
2956/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2957 {
2958 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
6772dd07 2959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2960 },
2961/* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
2962 {
2963 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
6772dd07 2964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2965 },
2966/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
2967 {
2968 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
6772dd07 2969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2970 },
2971/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2972 {
2973 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
6772dd07 2974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2975 },
2976/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2977 {
2978 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
6772dd07 2979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2980 },
2981/* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
2982 {
2983 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
6772dd07 2984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2985 },
2986/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
2987 {
2988 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
6772dd07 2989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2990 },
2991/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
2992 {
2993 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
6772dd07 2994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 2995 },
2996/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
2997 {
2998 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
6772dd07 2999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3000 },
3001/* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
3002 {
3003 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
6772dd07 3004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3005 },
3006/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
3007 {
3008 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
6772dd07 3009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3010 },
3011/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3012 {
3013 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
6772dd07 3014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3015 },
3016/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3017 {
3018 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
6772dd07 3019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3020 },
3021/* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3022 {
3023 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
6772dd07 3024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3025 },
3026/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3027 {
3028 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
6772dd07 3029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3030 },
3031/* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3032 {
3033 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
6772dd07 3034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3035 },
3036/* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3037 {
3038 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
6772dd07 3039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3040 },
3041/* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3042 {
3043 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
6772dd07 3044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3045 },
3046/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3047 {
3048 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
6772dd07 3049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3050 },
3051/* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3052 {
3053 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
6772dd07 3054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3055 },
3056/* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3057 {
3058 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
6772dd07 3059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3060 },
3061/* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3062 {
3063 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
6772dd07 3064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3065 },
3066/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3067 {
3068 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
6772dd07 3069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3070 },
3071/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3072 {
3073 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
6772dd07 3074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3075 },
3076/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3077 {
3078 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
6772dd07 3079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3080 },
3081/* extz ${Dsp-24-u16},${Dsp-40-u16} */
3082 {
3083 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
6772dd07 3084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3085 },
3086/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3087 {
3088 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
6772dd07 3089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3090 },
3091/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3092 {
3093 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
6772dd07 3094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3095 },
3096/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3097 {
3098 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
6772dd07 3099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3100 },
3101/* extz ${Dsp-24-u16},${Dsp-40-u24} */
3102 {
3103 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
6772dd07 3104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3105 },
3106/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3107 {
3108 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
6772dd07 3109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3110 },
3111/* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
3112 {
3113 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
6772dd07 3114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3115 },
3116/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3117 {
3118 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
6772dd07 3119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3120 },
3121/* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
3122 {
3123 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
6772dd07 3124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3125 },
3126/* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3127 {
3128 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
6772dd07 3129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3130 },
3131/* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
3132 {
3133 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
6772dd07 3134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3135 },
3136/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3137 {
3138 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
6772dd07 3139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3140 },
3141/* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3142 {
3143 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
6772dd07 3144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3145 },
3146/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3147 {
3148 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
6772dd07 3149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3150 },
3151/* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3152 {
3153 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
6772dd07 3154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3155 },
3156/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3157 {
3158 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
6772dd07 3159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3160 },
3161/* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3162 {
3163 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
6772dd07 3164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3165 },
3166/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3167 {
3168 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
6772dd07 3169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3170 },
3171/* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3172 {
3173 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
6772dd07 3174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3175 },
3176/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3177 {
3178 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
6772dd07 3179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3180 },
3181/* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3182 {
3183 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
6772dd07 3184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3185 },
3186/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3187 {
3188 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
6772dd07 3189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3190 },
3191/* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3192 {
3193 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
6772dd07 3194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3195 },
3196/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3197 {
3198 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
6772dd07 3199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3200 },
3201/* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3202 {
3203 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
6772dd07 3204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3205 },
3206/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3207 {
3208 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
6772dd07 3209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3210 },
3211/* extz ${Dsp-24-u24},${Dsp-48-u16} */
3212 {
3213 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
6772dd07 3214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3215 },
3216/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3217 {
3218 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
6772dd07 3219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3220 },
3221/* extz ${Dsp-24-u24},${Dsp-48-u24} */
3222 {
3223 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
6772dd07 3224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3225 },
3226/* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3227 {
3228 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
6772dd07 3229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3230 },
3231/* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3232 {
3233 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
6772dd07 3234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3235 },
3236/* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3237 {
3238 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
6772dd07 3239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3240 },
3241/* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3242 {
3243 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
6772dd07 3244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3245 },
3246/* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3247 {
3248 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
6772dd07 3249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3250 },
3251/* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3252 {
3253 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
6772dd07 3254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3255 },
3256/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3257 {
3258 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
6772dd07 3259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3260 },
3261/* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3262 {
3263 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
6772dd07 3264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3265 },
3266/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3267 {
3268 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
6772dd07 3269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3270 },
3271/* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3272 {
3273 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
6772dd07 3274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3275 },
3276/* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3277 {
3278 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
6772dd07 3279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3280 },
3281/* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3282 {
3283 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
6772dd07 3284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3285 },
3286/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3287 {
3288 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
6772dd07 3289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3290 },
3291/* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3292 {
3293 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
6772dd07 3294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3295 },
3296/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3297 {
3298 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
6772dd07 3299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3300 },
3301/* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3302 {
3303 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
6772dd07 3304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3305 },
3306/* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3307 {
3308 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
6772dd07 3309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3310 },
3311/* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3312 {
3313 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
6772dd07 3314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3315 },
3316/* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3317 {
3318 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
6772dd07 3319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3320 },
3321/* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3322 {
3323 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
6772dd07 3324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3325 },
3326/* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
3327 {
3328 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
6772dd07 3329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3330 },
3331/* extz [$Src32AnPrefixed],${Dsp-24-u16} */
3332 {
3333 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
6772dd07 3334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3335 },
3336/* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
3337 {
3338 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
6772dd07 3339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3340 },
3341/* extz [$Src32AnPrefixed],${Dsp-24-u24} */
3342 {
3343 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
6772dd07 3344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3345 },
3346/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3347 {
3348 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
6772dd07 3349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3350 },
3351/* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
3352 {
3353 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
6772dd07 3354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3355 },
3356/* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
3357 {
3358 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
6772dd07 3359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3360 },
3361/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3362 {
3363 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
6772dd07 3364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3365 },
3366/* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
3367 {
3368 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
6772dd07 3369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3370 },
3371/* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
3372 {
3373 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
6772dd07 3374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3375 },
3376/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3377 {
3378 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
6772dd07 3379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3380 },
3381/* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
3382 {
3383 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
6772dd07 3384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3385 },
3386/* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
3387 {
3388 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
6772dd07 3389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3390 },
3391/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
3392 {
3393 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3395 },
3396/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3397 {
3398 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3400 },
3401/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3402 {
3403 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3405 },
3406/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
3407 {
3408 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3410 },
3411/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3412 {
3413 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3415 },
3416/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3417 {
3418 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3420 },
3421/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
3422 {
3423 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3425 },
3426/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3427 {
3428 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3430 },
3431/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3432 {
3433 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3435 },
3436/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
3437 {
3438 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3440 },
3441/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
3442 {
3443 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3445 },
3446/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
3447 {
3448 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3450 },
3451/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
3452 {
3453 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3455 },
3456/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
3457 {
3458 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3460 },
3461/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
3462 {
3463 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3465 },
3466/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
3467 {
3468 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3470 },
3471/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
3472 {
3473 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3475 },
3476/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
3477 {
3478 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3480 },
3481/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
3482 {
3483 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3485 },
3486/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
3487 {
3488 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3490 },
3491/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
3492 {
3493 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3495 },
3496/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
3497 {
3498 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
6772dd07 3499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3500 },
3501/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
3502 {
3503 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
6772dd07 3504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3505 },
3506/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
3507 {
3508 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
6772dd07 3509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3510 },
3511/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
3512 {
3513 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
6772dd07 3514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3515 },
3516/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
3517 {
3518 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
6772dd07 3519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3520 },
3521/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
3522 {
3523 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
6772dd07 3524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3525 },
3526/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3527 {
3528 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3530 },
3531/* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
3532 {
3533 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3535 },
3536/* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
3537 {
3538 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3540 },
3541/* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
3542 {
3543 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3545 },
3546/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3547 {
3548 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3550 },
3551/* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
3552 {
3553 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3555 },
3556/* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
3557 {
3558 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3560 },
3561/* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
3562 {
3563 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
6772dd07 3564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3565 },
3566/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3567 {
3568 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
6772dd07 3569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3570 },
3571/* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
3572 {
3573 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
6772dd07 3574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3575 },
3576/* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
3577 {
3578 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
6772dd07 3579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3580 },
3581/* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
3582 {
3583 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
6772dd07 3584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3585 },
3586/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
3587 {
3588 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3590 },
3591/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3592 {
3593 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3595 },
3596/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3597 {
3598 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3600 },
3601/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
3602 {
3603 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3605 },
3606/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
3607 {
3608 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3610 },
3611/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3612 {
3613 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3615 },
3616/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3617 {
3618 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3620 },
3621/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
3622 {
3623 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3625 },
3626/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
3627 {
3628 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3630 },
3631/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3632 {
3633 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3635 },
3636/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3637 {
3638 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3640 },
3641/* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
3642 {
3643 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3645 },
3646/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
3647 {
3648 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3650 },
3651/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
3652 {
3653 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3655 },
3656/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
3657 {
3658 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3660 },
3661/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
3662 {
3663 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3665 },
3666/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
3667 {
3668 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3670 },
3671/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3672 {
3673 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3675 },
3676/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3677 {
3678 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3680 },
3681/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3682 {
3683 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3685 },
3686/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3687 {
3688 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3690 },
3691/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3692 {
3693 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3695 },
3696/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3697 {
3698 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3700 },
3701/* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3702 {
3703 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3705 },
3706/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3707 {
3708 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3710 },
3711/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3712 {
3713 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3715 },
3716/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3717 {
3718 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3720 },
3721/* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3722 {
3723 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3725 },
3726/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3727 {
3728 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
6772dd07 3729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3730 },
3731/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3732 {
3733 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
6772dd07 3734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3735 },
3736/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3737 {
3738 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
6772dd07 3739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3740 },
3741/* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
3742 {
3743 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
6772dd07 3744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3745 },
3746/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3747 {
3748 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
6772dd07 3749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3750 },
3751/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3752 {
3753 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
6772dd07 3754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3755 },
3756/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3757 {
3758 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
6772dd07 3759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3760 },
3761/* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
3762 {
3763 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
6772dd07 3764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3765 },
3766/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3767 {
3768 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
6772dd07 3769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3770 },
3771/* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
3772 {
3773 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
6772dd07 3774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3775 },
3776/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3777 {
3778 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
6772dd07 3779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3780 },
3781/* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
3782 {
3783 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
6772dd07 3784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3785 },
3786/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3787 {
3788 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
6772dd07 3789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3790 },
3791/* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
3792 {
3793 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
6772dd07 3794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3795 },
3796/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3797 {
3798 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3800 },
3801/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3802 {
3803 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3805 },
3806/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3807 {
3808 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3810 },
3811/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3812 {
3813 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3815 },
3816/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3817 {
3818 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
6772dd07 3819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3820 },
3821/* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3822 {
3823 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
6772dd07 3824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3825 },
3826/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3827 {
3828 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3830 },
3831/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3832 {
3833 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3835 },
3836/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3837 {
3838 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3840 },
3841/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3842 {
3843 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3845 },
3846/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3847 {
3848 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3850 },
3851/* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3852 {
3853 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
6772dd07 3854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3855 },
3856/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3857 {
3858 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3860 },
3861/* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3862 {
3863 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
6772dd07 3864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3865 },
3866/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3867 {
3868 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
6772dd07 3869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3870 },
3871/* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
3872 {
3873 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
6772dd07 3874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3875 },
3876/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3877 {
3878 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
6772dd07 3879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3880 },
3881/* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
3882 {
3883 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
6772dd07 3884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3885 },
3886/* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3887 {
3888 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
6772dd07 3889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3890 },
3891/* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3892 {
3893 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
6772dd07 3894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3895 },
3896/* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3897 {
3898 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
6772dd07 3899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3900 },
3901/* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3902 {
3903 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
6772dd07 3904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3905 },
3906/* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3907 {
3908 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
6772dd07 3909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3910 },
3911/* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3912 {
3913 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
6772dd07 3914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3915 },
3916/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3917 {
3918 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
6772dd07 3919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3920 },
3921/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3922 {
3923 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
6772dd07 3924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3925 },
3926/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3927 {
3928 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3930 },
3931/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3932 {
3933 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3935 },
3936/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3937 {
3938 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3940 },
3941/* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3942 {
3943 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
6772dd07 3944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3945 },
3946/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3947 {
3948 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
6772dd07 3949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3950 },
3951/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3952 {
3953 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
6772dd07 3954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3955 },
3956/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3957 {
3958 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3960 },
3961/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3962 {
3963 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3965 },
3966/* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3967 {
3968 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
6772dd07 3969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3970 },
3971/* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3972 {
3973 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
6772dd07 3974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3975 },
3976/* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3977 {
3978 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3980 },
3981/* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3982 {
3983 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
6772dd07 3984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3985 },
3986/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
3987 {
3988 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
6772dd07 3989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3990 },
3991/* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
3992 {
3993 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
6772dd07 3994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 3995 },
3996/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
3997 {
3998 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
6772dd07 3999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4000 },
4001/* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
4002 {
4003 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
6772dd07 4004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4005 },
4006/* exts.w $Dst32RnExtUnprefixedHI */
4007 {
4008 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16,
6772dd07 4009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4010 },
4011/* exts.w $Dst32AnUnprefixedSI */
4012 {
4013 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16,
6772dd07 4014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4015 },
4016/* exts.w [$Dst32AnExtUnprefixed] */
4017 {
4018 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16,
6772dd07 4019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4020 },
4021/* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4022 {
4023 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24,
6772dd07 4024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4025 },
4026/* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4027 {
4028 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32,
6772dd07 4029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4030 },
4031/* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4032 {
4033 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40,
6772dd07 4034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4035 },
4036/* exts.w ${Dsp-16-u8}[sb] */
4037 {
4038 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24,
6772dd07 4039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4040 },
4041/* exts.w ${Dsp-16-u16}[sb] */
4042 {
4043 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32,
6772dd07 4044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4045 },
4046/* exts.w ${Dsp-16-s8}[fb] */
4047 {
4048 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24,
6772dd07 4049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4050 },
4051/* exts.w ${Dsp-16-s16}[fb] */
4052 {
4053 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32,
6772dd07 4054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4055 },
4056/* exts.w ${Dsp-16-u16} */
4057 {
4058 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32,
6772dd07 4059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4060 },
4061/* exts.w ${Dsp-16-u24} */
4062 {
4063 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40,
6772dd07 4064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4065 },
4066/* exts.b $Dst32RnExtUnprefixedQI */
4067 {
4068 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16,
6772dd07 4069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4070 },
4071/* exts.b $Dst32AnUnprefixedHI */
4072 {
4073 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16,
6772dd07 4074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4075 },
4076/* exts.b [$Dst32AnExtUnprefixed] */
4077 {
4078 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16,
6772dd07 4079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4080 },
4081/* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4082 {
4083 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24,
6772dd07 4084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4085 },
4086/* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4087 {
4088 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32,
6772dd07 4089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4090 },
4091/* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4092 {
4093 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40,
6772dd07 4094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4095 },
4096/* exts.b ${Dsp-16-u8}[sb] */
4097 {
4098 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24,
6772dd07 4099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4100 },
4101/* exts.b ${Dsp-16-u16}[sb] */
4102 {
4103 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32,
6772dd07 4104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4105 },
4106/* exts.b ${Dsp-16-s8}[fb] */
4107 {
4108 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24,
6772dd07 4109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4110 },
4111/* exts.b ${Dsp-16-s16}[fb] */
4112 {
4113 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32,
6772dd07 4114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4115 },
4116/* exts.b ${Dsp-16-u16} */
4117 {
4118 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32,
6772dd07 4119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4120 },
4121/* exts.b ${Dsp-16-u24} */
4122 {
4123 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40,
6772dd07 4124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4125 },
4126/* exts.b $Dst16RnExtQI */
4127 {
4128 M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16,
6772dd07 4129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4130 },
4131/* exts.b [$Dst16An] */
4132 {
4133 M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16,
6772dd07 4134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4135 },
4136/* exts.b ${Dsp-16-u8}[$Dst16An] */
4137 {
4138 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24,
6772dd07 4139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4140 },
4141/* exts.b ${Dsp-16-u16}[$Dst16An] */
4142 {
4143 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32,
6772dd07 4144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4145 },
4146/* exts.b ${Dsp-16-u8}[sb] */
4147 {
4148 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24,
6772dd07 4149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4150 },
4151/* exts.b ${Dsp-16-u16}[sb] */
4152 {
4153 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32,
6772dd07 4154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4155 },
4156/* exts.b ${Dsp-16-s8}[fb] */
4157 {
4158 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24,
6772dd07 4159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4160 },
4161/* exts.b ${Dsp-16-u16} */
4162 {
4163 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32,
6772dd07 4164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 4165 },
4166/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4167 {
4168 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
6772dd07 4169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4170 },
4171/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
4172 {
4173 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
6772dd07 4174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4175 },
4176/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
4177 {
4178 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
6772dd07 4179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4180 },
4181/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4182 {
4183 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
6772dd07 4184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4185 },
4186/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
4187 {
4188 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
6772dd07 4189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4190 },
4191/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
4192 {
4193 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
6772dd07 4194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4195 },
4196/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4197 {
4198 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
6772dd07 4199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4200 },
4201/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4202 {
4203 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
6772dd07 4204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4205 },
4206/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4207 {
4208 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
6772dd07 4209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4210 },
4211/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4212 {
4213 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4215 },
4216/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4217 {
4218 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4220 },
4221/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4222 {
4223 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4225 },
4226/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4227 {
4228 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4230 },
4231/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4232 {
4233 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4235 },
4236/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4237 {
4238 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4240 },
4241/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4242 {
4243 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4245 },
4246/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4247 {
4248 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4250 },
4251/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4252 {
4253 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4255 },
4256/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4257 {
4258 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4260 },
4261/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4262 {
4263 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4265 },
4266/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4267 {
4268 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4270 },
4271/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4272 {
4273 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4275 },
4276/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4277 {
4278 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4280 },
4281/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4282 {
4283 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4285 },
4286/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4287 {
4288 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4290 },
4291/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
4292 {
4293 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4295 },
4296/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
4297 {
4298 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4300 },
4301/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
4302 {
4303 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4305 },
4306/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
4307 {
4308 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4310 },
4311/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
4312 {
4313 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4315 },
4316/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
4317 {
4318 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
6772dd07 4319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4320 },
4321/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
4322 {
4323 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
6772dd07 4324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4325 },
4326/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
4327 {
4328 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
6772dd07 4329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4330 },
4331/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
4332 {
4333 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 4334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4335 },
4336/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
4337 {
4338 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 4339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4340 },
4341/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
4342 {
4343 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 4344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4345 },
4346/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4347 {
4348 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4350 },
4351/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
4352 {
4353 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4355 },
4356/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
4357 {
4358 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4360 },
4361/* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
4362 {
4363 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4365 },
4366/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4367 {
4368 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4370 },
4371/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
4372 {
4373 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4375 },
4376/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
4377 {
4378 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4380 },
4381/* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
4382 {
4383 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 4384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4385 },
4386/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4387 {
4388 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6772dd07 4389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4390 },
4391/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
4392 {
4393 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6772dd07 4394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4395 },
4396/* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
4397 {
4398 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6772dd07 4399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4400 },
4401/* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
4402 {
4403 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6772dd07 4404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4405 },
4406/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4407 {
4408 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4410 },
4411/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4412 {
4413 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4415 },
4416/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4417 {
4418 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4420 },
4421/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
4422 {
4423 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4425 },
4426/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4427 {
4428 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4430 },
4431/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4432 {
4433 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4435 },
4436/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4437 {
4438 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4440 },
4441/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
4442 {
4443 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4445 },
4446/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4447 {
4448 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4450 },
4451/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4452 {
4453 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4455 },
4456/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4457 {
4458 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4460 },
4461/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
4462 {
4463 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4465 },
4466/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
4467 {
4468 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4470 },
4471/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
4472 {
4473 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4475 },
4476/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
4477 {
4478 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4480 },
4481/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
4482 {
4483 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4485 },
4486/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
4487 {
4488 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4490 },
4491/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
4492 {
4493 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4495 },
4496/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
4497 {
4498 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4500 },
4501/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
4502 {
4503 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4505 },
4506/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
4507 {
4508 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4510 },
4511/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
4512 {
4513 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4515 },
4516/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
4517 {
4518 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4520 },
4521/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
4522 {
4523 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4525 },
4526/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
4527 {
4528 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4530 },
4531/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
4532 {
4533 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4535 },
4536/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
4537 {
4538 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4540 },
4541/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
4542 {
4543 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4545 },
4546/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
4547 {
4548 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 4549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4550 },
4551/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
4552 {
4553 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 4554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4555 },
4556/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
4557 {
4558 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 4559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4560 },
4561/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
4562 {
4563 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 4564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4565 },
4566/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
4567 {
4568 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
6772dd07 4569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4570 },
4571/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
4572 {
4573 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
6772dd07 4574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4575 },
4576/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
4577 {
4578 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
6772dd07 4579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4580 },
4581/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
4582 {
4583 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
6772dd07 4584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4585 },
4586/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4587 {
4588 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
6772dd07 4589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4590 },
4591/* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
4592 {
4593 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
6772dd07 4594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4595 },
4596/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4597 {
4598 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
6772dd07 4599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4600 },
4601/* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
4602 {
4603 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
6772dd07 4604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4605 },
4606/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4607 {
4608 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
6772dd07 4609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4610 },
4611/* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
4612 {
4613 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
6772dd07 4614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4615 },
4616/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
4617 {
4618 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4620 },
4621/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
4622 {
4623 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4625 },
4626/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
4627 {
4628 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4630 },
4631/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
4632 {
4633 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4635 },
4636/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
4637 {
4638 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
6772dd07 4639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4640 },
4641/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
4642 {
4643 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
6772dd07 4644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4645 },
4646/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
4647 {
4648 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4650 },
4651/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
4652 {
4653 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4655 },
4656/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
4657 {
4658 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4660 },
4661/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
4662 {
4663 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4665 },
4666/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
4667 {
4668 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4670 },
4671/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
4672 {
4673 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 4674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4675 },
4676/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
4677 {
4678 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4680 },
4681/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
4682 {
4683 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 4684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4685 },
4686/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
4687 {
4688 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
6772dd07 4689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4690 },
4691/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
4692 {
4693 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
6772dd07 4694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4695 },
4696/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
4697 {
4698 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
6772dd07 4699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4700 },
4701/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
4702 {
4703 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
6772dd07 4704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4705 },
4706/* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
4707 {
4708 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
6772dd07 4709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4710 },
4711/* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
4712 {
4713 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
6772dd07 4714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4715 },
4716/* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4717 {
4718 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
6772dd07 4719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4720 },
4721/* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
4722 {
4723 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
6772dd07 4724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4725 },
4726/* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
4727 {
4728 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
6772dd07 4729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4730 },
4731/* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4732 {
4733 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
6772dd07 4734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4735 },
4736/* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
4737 {
4738 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
6772dd07 4739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4740 },
4741/* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
4742 {
4743 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
6772dd07 4744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4745 },
4746/* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4747 {
4748 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
6772dd07 4749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4750 },
4751/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4752 {
4753 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4755 },
4756/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4757 {
4758 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4760 },
4761/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
4762 {
4763 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4765 },
4766/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4767 {
4768 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4770 },
4771/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4772 {
4773 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4775 },
4776/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
4777 {
4778 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4780 },
4781/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4782 {
4783 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4785 },
4786/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4787 {
4788 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4790 },
4791/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
4792 {
4793 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 4794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4795 },
4796/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
4797 {
4798 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4800 },
4801/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
4802 {
4803 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4805 },
4806/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
4807 {
4808 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4810 },
4811/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
4812 {
4813 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4815 },
4816/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
4817 {
4818 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4820 },
4821/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
4822 {
4823 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4825 },
4826/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
4827 {
4828 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4830 },
4831/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
4832 {
4833 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4835 },
4836/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
4837 {
4838 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
6772dd07 4839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4840 },
4841/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
4842 {
4843 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4845 },
4846/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
4847 {
4848 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4850 },
4851/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
4852 {
4853 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
6772dd07 4854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4855 },
4856/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
4857 {
4858 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
6772dd07 4859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4860 },
4861/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
4862 {
4863 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
6772dd07 4864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4865 },
4866/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
4867 {
4868 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
6772dd07 4869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4870 },
4871/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
4872 {
4873 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
6772dd07 4874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4875 },
4876/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
4877 {
4878 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
6772dd07 4879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4880 },
4881/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
4882 {
4883 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
6772dd07 4884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4885 },
4886/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
4887 {
4888 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 4889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4890 },
4891/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
4892 {
4893 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 4894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4895 },
4896/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
4897 {
4898 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 4899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4900 },
4901/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
4902 {
4903 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 4904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4905 },
4906/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
4907 {
4908 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 4909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4910 },
4911/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
4912 {
4913 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 4914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4915 },
4916/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4917 {
4918 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6772dd07 4919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4920 },
4921/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4922 {
4923 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6772dd07 4924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4925 },
4926/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4927 {
4928 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6772dd07 4929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4930 },
4931/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4932 {
4933 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 4934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4935 },
4936/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4937 {
4938 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 4939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4940 },
4941/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4942 {
4943 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 4944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4945 },
4946/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4947 {
4948 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 4949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4950 },
4951/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4952 {
4953 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 4954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4955 },
4956/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4957 {
4958 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 4959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4960 },
4961/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4962 {
4963 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 4964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4965 },
4966/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4967 {
4968 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 4969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4970 },
4971/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4972 {
4973 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 4974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4975 },
4976/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4977 {
4978 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 4979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4980 },
4981/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4982 {
4983 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 4984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4985 },
4986/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4987 {
4988 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 4989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4990 },
4991/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4992 {
4993 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 4994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 4995 },
4996/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4997 {
4998 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 4999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5000 },
5001/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
5002 {
5003 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5005 },
5006/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
5007 {
5008 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5010 },
5011/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5012 {
5013 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5015 },
5016/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5017 {
5018 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5020 },
5021/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
5022 {
5023 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5025 },
5026/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
5027 {
5028 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5030 },
5031/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
5032 {
5033 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5035 },
5036/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
5037 {
5038 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
6772dd07 5039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5040 },
5041/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5042 {
5043 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
6772dd07 5044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5045 },
5046/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5047 {
5048 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
6772dd07 5049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5050 },
5051/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
5052 {
5053 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 5054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5055 },
5056/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
5057 {
5058 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 5059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5060 },
5061/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
5062 {
5063 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 5064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5065 },
5066/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5067 {
5068 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5070 },
5071/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
5072 {
5073 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5075 },
5076/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
5077 {
5078 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5080 },
5081/* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
5082 {
5083 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5085 },
5086/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5087 {
5088 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5090 },
5091/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
5092 {
5093 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5095 },
5096/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
5097 {
5098 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5100 },
5101/* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
5102 {
5103 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
6772dd07 5104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5105 },
5106/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5107 {
5108 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
6772dd07 5109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5110 },
5111/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
5112 {
5113 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
6772dd07 5114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5115 },
5116/* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
5117 {
5118 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
6772dd07 5119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5120 },
5121/* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
5122 {
5123 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
6772dd07 5124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5125 },
5126/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5127 {
5128 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5130 },
5131/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5132 {
5133 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5135 },
5136/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5137 {
5138 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5140 },
5141/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
5142 {
5143 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5145 },
5146/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5147 {
5148 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5150 },
5151/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5152 {
5153 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5155 },
5156/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5157 {
5158 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5160 },
5161/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
5162 {
5163 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5165 },
5166/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5167 {
5168 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5170 },
5171/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5172 {
5173 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5175 },
5176/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5177 {
5178 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5180 },
5181/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
5182 {
5183 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5185 },
5186/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
5187 {
5188 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5190 },
5191/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5192 {
5193 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5195 },
5196/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
5197 {
5198 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5200 },
5201/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5202 {
5203 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5205 },
5206/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
5207 {
5208 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5210 },
5211/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5212 {
5213 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5215 },
5216/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
5217 {
5218 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5220 },
5221/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5222 {
5223 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5225 },
5226/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
5227 {
5228 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5230 },
5231/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5232 {
5233 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5235 },
5236/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
5237 {
5238 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5240 },
5241/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5242 {
5243 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5245 },
5246/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
5247 {
5248 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5250 },
5251/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
5252 {
5253 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5255 },
5256/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
5257 {
5258 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5260 },
5261/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
5262 {
5263 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5265 },
5266/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
5267 {
5268 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 5269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5270 },
5271/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5272 {
5273 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 5274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5275 },
5276/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
5277 {
5278 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 5279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5280 },
5281/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
5282 {
5283 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 5284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5285 },
5286/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
5287 {
5288 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
6772dd07 5289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5290 },
5291/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
5292 {
5293 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
6772dd07 5294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5295 },
5296/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
5297 {
5298 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
6772dd07 5299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5300 },
5301/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
5302 {
5303 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
6772dd07 5304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5305 },
5306/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5307 {
5308 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
6772dd07 5309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5310 },
5311/* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
5312 {
5313 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
6772dd07 5314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5315 },
5316/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5317 {
5318 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
6772dd07 5319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5320 },
5321/* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
5322 {
5323 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
6772dd07 5324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5325 },
5326/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5327 {
5328 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
6772dd07 5329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5330 },
5331/* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
5332 {
5333 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
6772dd07 5334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5335 },
5336/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
5337 {
5338 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5340 },
5341/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
5342 {
5343 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5345 },
5346/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
5347 {
5348 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5350 },
5351/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
5352 {
5353 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5355 },
5356/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
5357 {
5358 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
6772dd07 5359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5360 },
5361/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
5362 {
5363 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
6772dd07 5364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5365 },
5366/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
5367 {
5368 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5370 },
5371/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
5372 {
5373 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5375 },
5376/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
5377 {
5378 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5380 },
5381/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
5382 {
5383 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5385 },
5386/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
5387 {
5388 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5390 },
5391/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
5392 {
5393 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 5394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5395 },
5396/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
5397 {
5398 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5400 },
5401/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
5402 {
5403 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
6772dd07 5404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5405 },
5406/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
5407 {
5408 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
6772dd07 5409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5410 },
5411/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
5412 {
5413 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
6772dd07 5414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5415 },
5416/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
5417 {
5418 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
6772dd07 5419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5420 },
5421/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
5422 {
5423 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
6772dd07 5424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5425 },
5426/* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
5427 {
5428 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
6772dd07 5429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5430 },
5431/* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
5432 {
5433 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
6772dd07 5434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5435 },
5436/* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5437 {
5438 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
6772dd07 5439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5440 },
5441/* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
5442 {
5443 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
6772dd07 5444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5445 },
5446/* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
5447 {
5448 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
6772dd07 5449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5450 },
5451/* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5452 {
5453 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
6772dd07 5454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5455 },
5456/* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
5457 {
5458 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
6772dd07 5459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5460 },
5461/* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
5462 {
5463 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
6772dd07 5464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5465 },
5466/* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5467 {
5468 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
6772dd07 5469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5470 },
5471/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5472 {
5473 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5475 },
5476/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5477 {
5478 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5480 },
5481/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
5482 {
5483 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5485 },
5486/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5487 {
5488 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5490 },
5491/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5492 {
5493 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5495 },
5496/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
5497 {
5498 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5500 },
5501/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5502 {
5503 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5505 },
5506/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5507 {
5508 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5510 },
5511/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
5512 {
5513 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 5514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5515 },
5516/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
5517 {
5518 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5520 },
5521/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
5522 {
5523 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5525 },
5526/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
5527 {
5528 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5530 },
5531/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
5532 {
5533 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5535 },
5536/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
5537 {
5538 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5540 },
5541/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
5542 {
5543 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5545 },
5546/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
5547 {
5548 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5550 },
5551/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
5552 {
5553 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5555 },
5556/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
5557 {
5558 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
6772dd07 5559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5560 },
5561/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
5562 {
5563 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5565 },
5566/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
5567 {
5568 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5570 },
5571/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
5572 {
5573 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 5574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5575 },
5576/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
5577 {
5578 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
6772dd07 5579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5580 },
5581/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
5582 {
5583 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
6772dd07 5584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5585 },
5586/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
5587 {
5588 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
6772dd07 5589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5590 },
5591/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
5592 {
5593 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
6772dd07 5594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5595 },
5596/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
5597 {
5598 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
6772dd07 5599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5600 },
5601/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
5602 {
5603 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
6772dd07 5604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5605 },
5606/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
5607 {
5608 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
6772dd07 5609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5610 },
5611/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
5612 {
5613 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
6772dd07 5614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5615 },
5616/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
5617 {
5618 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
6772dd07 5619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5620 },
5621/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
5622 {
5623 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24,
6772dd07 5624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5625 },
5626/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
5627 {
5628 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
6772dd07 5629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5630 },
5631/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
5632 {
5633 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
6772dd07 5634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5635 },
5636/* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
5637 {
5638 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
6772dd07 5639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5640 },
5641/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
5642 {
5643 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
6772dd07 5644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5645 },
5646/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
5647 {
5648 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
6772dd07 5649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5650 },
5651/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
5652 {
5653 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
6772dd07 5654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5655 },
5656/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
5657 {
5658 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
6772dd07 5659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5660 },
5661/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
5662 {
5663 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
6772dd07 5664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5665 },
5666/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
5667 {
5668 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
6772dd07 5669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5670 },
5671/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
5672 {
5673 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
6772dd07 5674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5675 },
5676/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
5677 {
5678 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
6772dd07 5679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5680 },
5681/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
5682 {
5683 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
6772dd07 5684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5685 },
5686/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
5687 {
5688 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
6772dd07 5689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5690 },
5691/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
5692 {
5693 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
6772dd07 5694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5695 },
5696/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
5697 {
5698 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
6772dd07 5699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5700 },
5701/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
5702 {
5703 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
6772dd07 5704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5705 },
5706/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
5707 {
5708 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
6772dd07 5709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5710 },
5711/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
5712 {
5713 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
6772dd07 5714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5715 },
5716/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5717 {
5718 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
6772dd07 5719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5720 },
5721/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5722 {
5723 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
6772dd07 5724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5725 },
5726/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
5727 {
5728 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
6772dd07 5729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5730 },
5731/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5732 {
5733 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
6772dd07 5734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5735 },
5736/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5737 {
5738 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
6772dd07 5739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5740 },
5741/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
5742 {
5743 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
6772dd07 5744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5745 },
5746/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
5747 {
5748 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
6772dd07 5749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5750 },
5751/* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
5752 {
5753 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32,
6772dd07 5754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5755 },
5756/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
5757 {
5758 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32,
6772dd07 5759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5760 },
5761/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
5762 {
5763 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32,
6772dd07 5764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5765 },
5766/* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
5767 {
5768 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32,
6772dd07 5769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5770 },
5771/* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
5772 {
5773 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
6772dd07 5774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5775 },
5776/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
5777 {
5778 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
6772dd07 5779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5780 },
5781/* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
5782 {
5783 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32,
6772dd07 5784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5785 },
5786/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
5787 {
5788 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
6772dd07 5789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5790 },
5791/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
5792 {
5793 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
6772dd07 5794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5795 },
5796/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
5797 {
5798 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
6772dd07 5799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5800 },
5801/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
5802 {
5803 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
6772dd07 5804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5805 },
5806/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
5807 {
5808 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
6772dd07 5809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5810 },
5811/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
5812 {
5813 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
6772dd07 5814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5815 },
5816/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
5817 {
5818 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
6772dd07 5819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5820 },
5821/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5822 {
5823 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
6772dd07 5824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5825 },
5826/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5827 {
5828 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
6772dd07 5829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5830 },
5831/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
5832 {
5833 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
6772dd07 5834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5835 },
5836/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5837 {
5838 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
6772dd07 5839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5840 },
5841/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5842 {
5843 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
6772dd07 5844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5845 },
5846/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
5847 {
5848 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
6772dd07 5849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5850 },
5851/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5852 {
5853 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
6772dd07 5854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5855 },
5856/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5857 {
5858 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
6772dd07 5859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5860 },
5861/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
5862 {
5863 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
6772dd07 5864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5865 },
5866/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5867 {
5868 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
6772dd07 5869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5870 },
5871/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
5872 {
5873 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48,
6772dd07 5874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5875 },
5876/* xor.w${G} $Src16RnHI,$Dst16RnHI */
5877 {
5878 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
6772dd07 5879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5880 },
5881/* xor.w${G} $Src16AnHI,$Dst16RnHI */
5882 {
5883 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
6772dd07 5884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5885 },
5886/* xor.w${G} [$Src16An],$Dst16RnHI */
5887 {
5888 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16,
6772dd07 5889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5890 },
5891/* xor.w${G} $Src16RnHI,$Dst16AnHI */
5892 {
5893 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16,
6772dd07 5894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5895 },
5896/* xor.w${G} $Src16AnHI,$Dst16AnHI */
5897 {
5898 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16,
6772dd07 5899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5900 },
5901/* xor.w${G} [$Src16An],$Dst16AnHI */
5902 {
5903 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16,
6772dd07 5904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5905 },
5906/* xor.w${G} $Src16RnHI,[$Dst16An] */
5907 {
5908 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
6772dd07 5909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5910 },
5911/* xor.w${G} $Src16AnHI,[$Dst16An] */
5912 {
5913 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
6772dd07 5914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5915 },
5916/* xor.w${G} [$Src16An],[$Dst16An] */
5917 {
5918 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16,
6772dd07 5919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5920 },
5921/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
5922 {
5923 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
6772dd07 5924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5925 },
5926/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
5927 {
5928 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
6772dd07 5929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5930 },
5931/* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
5932 {
5933 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
6772dd07 5934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5935 },
5936/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
5937 {
5938 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
6772dd07 5939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5940 },
5941/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
5942 {
5943 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
6772dd07 5944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5945 },
5946/* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
5947 {
5948 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
6772dd07 5949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5950 },
5951/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
5952 {
5953 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
6772dd07 5954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5955 },
5956/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
5957 {
5958 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
6772dd07 5959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5960 },
5961/* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
5962 {
5963 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
6772dd07 5964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5965 },
5966/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
5967 {
5968 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
6772dd07 5969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5970 },
5971/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
5972 {
5973 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
6772dd07 5974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5975 },
5976/* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
5977 {
5978 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
6772dd07 5979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5980 },
5981/* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
5982 {
5983 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
6772dd07 5984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5985 },
5986/* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
5987 {
5988 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
6772dd07 5989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5990 },
5991/* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
5992 {
5993 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
6772dd07 5994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 5995 },
5996/* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
5997 {
5998 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
6772dd07 5999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6000 },
6001/* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
6002 {
6003 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
6772dd07 6004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6005 },
6006/* xor.w${G} [$Src16An],${Dsp-16-u16} */
6007 {
6008 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32,
6772dd07 6009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6010 },
6011/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
6012 {
6013 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6772dd07 6014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6015 },
6016/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
6017 {
6018 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6772dd07 6019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6020 },
6021/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
6022 {
6023 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6772dd07 6024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6025 },
6026/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
6027 {
6028 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6772dd07 6029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6030 },
6031/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
6032 {
6033 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6772dd07 6034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6035 },
6036/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
6037 {
6038 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6772dd07 6039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6040 },
6041/* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
6042 {
6043 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6772dd07 6044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6045 },
6046/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
6047 {
6048 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6772dd07 6049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6050 },
6051/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
6052 {
6053 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6772dd07 6054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6055 },
6056/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
6057 {
6058 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6772dd07 6059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6060 },
6061/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
6062 {
6063 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6772dd07 6064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6065 },
6066/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
6067 {
6068 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6772dd07 6069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6070 },
6071/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
6072 {
6073 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6772dd07 6074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6075 },
6076/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
6077 {
6078 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6772dd07 6079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6080 },
6081/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
6082 {
6083 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6772dd07 6084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6085 },
6086/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
6087 {
6088 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6772dd07 6089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6090 },
6091/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
6092 {
6093 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6772dd07 6094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6095 },
6096/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
6097 {
6098 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6772dd07 6099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6100 },
6101/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
6102 {
6103 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6772dd07 6104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6105 },
6106/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
6107 {
6108 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6772dd07 6109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6110 },
6111/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
6112 {
6113 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6772dd07 6114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6115 },
6116/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
6117 {
6118 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6772dd07 6119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6120 },
6121/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
6122 {
6123 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6772dd07 6124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6125 },
6126/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
6127 {
6128 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6772dd07 6129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6130 },
6131/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
6132 {
6133 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6772dd07 6134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6135 },
6136/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
6137 {
6138 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6772dd07 6139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6140 },
6141/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
6142 {
6143 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6772dd07 6144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6145 },
6146/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
6147 {
6148 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6772dd07 6149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6150 },
6151/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
6152 {
6153 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6772dd07 6154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6155 },
6156/* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
6157 {
6158 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32,
6772dd07 6159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6160 },
6161/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
6162 {
6163 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6772dd07 6164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6165 },
6166/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
6167 {
6168 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6772dd07 6169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6170 },
6171/* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
6172 {
6173 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32,
6772dd07 6174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6175 },
6176/* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
6177 {
6178 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6772dd07 6179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6180 },
6181/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
6182 {
6183 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6772dd07 6184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6185 },
6186/* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
6187 {
6188 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32,
6772dd07 6189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6190 },
6191/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
6192 {
6193 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6772dd07 6194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6195 },
6196/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
6197 {
6198 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6772dd07 6199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6200 },
6201/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
6202 {
6203 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6772dd07 6204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6205 },
6206/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
6207 {
6208 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6772dd07 6209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6210 },
6211/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
6212 {
6213 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6772dd07 6214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6215 },
6216/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
6217 {
6218 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6772dd07 6219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6220 },
6221/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
6222 {
6223 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6772dd07 6224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6225 },
6226/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
6227 {
6228 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6772dd07 6229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6230 },
6231/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
6232 {
6233 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6772dd07 6234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6235 },
6236/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
6237 {
6238 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6772dd07 6239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6240 },
6241/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
6242 {
6243 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6772dd07 6244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6245 },
6246/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
6247 {
6248 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6772dd07 6249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6250 },
6251/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
6252 {
6253 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6772dd07 6254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6255 },
6256/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
6257 {
6258 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6772dd07 6259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6260 },
6261/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
6262 {
6263 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6772dd07 6264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6265 },
6266/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
6267 {
6268 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6772dd07 6269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6270 },
6271/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
6272 {
6273 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6772dd07 6274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6275 },
6276/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
6277 {
6278 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6772dd07 6279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6280 },
6281/* xor.b${G} $Src16RnQI,$Dst16RnQI */
6282 {
6283 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6772dd07 6284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6285 },
6286/* xor.b${G} $Src16AnQI,$Dst16RnQI */
6287 {
6288 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6772dd07 6289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6290 },
6291/* xor.b${G} [$Src16An],$Dst16RnQI */
6292 {
6293 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16,
6772dd07 6294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6295 },
6296/* xor.b${G} $Src16RnQI,$Dst16AnQI */
6297 {
6298 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6772dd07 6299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6300 },
6301/* xor.b${G} $Src16AnQI,$Dst16AnQI */
6302 {
6303 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6772dd07 6304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6305 },
6306/* xor.b${G} [$Src16An],$Dst16AnQI */
6307 {
6308 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16,
6772dd07 6309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6310 },
6311/* xor.b${G} $Src16RnQI,[$Dst16An] */
6312 {
6313 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6772dd07 6314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6315 },
6316/* xor.b${G} $Src16AnQI,[$Dst16An] */
6317 {
6318 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6772dd07 6319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6320 },
6321/* xor.b${G} [$Src16An],[$Dst16An] */
6322 {
6323 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16,
6772dd07 6324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6325 },
6326/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
6327 {
6328 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6772dd07 6329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6330 },
6331/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
6332 {
6333 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6772dd07 6334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6335 },
6336/* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
6337 {
6338 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6772dd07 6339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6340 },
6341/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
6342 {
6343 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6772dd07 6344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6345 },
6346/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
6347 {
6348 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6772dd07 6349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6350 },
6351/* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
6352 {
6353 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6772dd07 6354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6355 },
6356/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
6357 {
6358 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6772dd07 6359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6360 },
6361/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
6362 {
6363 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6772dd07 6364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6365 },
6366/* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
6367 {
6368 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6772dd07 6369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6370 },
6371/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
6372 {
6373 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6772dd07 6374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6375 },
6376/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
6377 {
6378 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6772dd07 6379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6380 },
6381/* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
6382 {
6383 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6772dd07 6384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6385 },
6386/* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
6387 {
6388 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6772dd07 6389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6390 },
6391/* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
6392 {
6393 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6772dd07 6394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6395 },
6396/* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
6397 {
6398 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6772dd07 6399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6400 },
6401/* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
6402 {
6403 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6772dd07 6404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6405 },
6406/* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
6407 {
6408 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6772dd07 6409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6410 },
6411/* xor.b${G} [$Src16An],${Dsp-16-u16} */
6412 {
6413 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6772dd07 6414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 6415 },
6416/* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
6417 {
6418 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 6419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6420 },
6421/* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
6422 {
6423 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6772dd07 6424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6425 },
6426/* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
6427 {
6428 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6772dd07 6429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6430 },
6431/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6432 {
6433 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 6434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6435 },
6436/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6437 {
6438 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 6439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6440 },
6441/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6442 {
6443 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6772dd07 6444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6445 },
6446/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6447 {
6448 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 6449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6450 },
6451/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6452 {
6453 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 6454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6455 },
6456/* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
6457 {
6458 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6772dd07 6459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6460 },
6461/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6462 {
6463 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48,
6772dd07 6464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6465 },
6466/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6467 {
6468 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56,
6772dd07 6469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6470 },
6471/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
6472 {
6473 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56,
6772dd07 6474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6475 },
6476/* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
6477 {
6478 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 6479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6480 },
6481/* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
6482 {
6483 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6772dd07 6484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6485 },
6486/* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
6487 {
6488 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6772dd07 6489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6490 },
6491/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6492 {
6493 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 6494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6495 },
6496/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6497 {
6498 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 6499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6500 },
6501/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6502 {
6503 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6772dd07 6504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6505 },
6506/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6507 {
6508 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 6509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6510 },
6511/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6512 {
6513 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 6514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6515 },
6516/* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
6517 {
6518 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6772dd07 6519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6520 },
6521/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6522 {
6523 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40,
6772dd07 6524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6525 },
6526/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6527 {
6528 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48,
6772dd07 6529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6530 },
6531/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
6532 {
6533 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48,
6772dd07 6534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6535 },
6536/* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
6537 {
6538 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32,
6772dd07 6539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6540 },
6541/* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
6542 {
6543 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32,
6772dd07 6544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6545 },
6546/* xor.w${G} #${Imm-16-HI},[$Dst16An] */
6547 {
6548 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32,
6772dd07 6549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6550 },
6551/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
6552 {
6553 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40,
6772dd07 6554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6555 },
6556/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6557 {
6558 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40,
6772dd07 6559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6560 },
6561/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6562 {
6563 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40,
6772dd07 6564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6565 },
6566/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
6567 {
6568 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48,
6772dd07 6569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6570 },
6571/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6572 {
6573 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48,
6772dd07 6574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6575 },
6576/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6577 {
6578 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48,
6772dd07 6579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6580 },
6581/* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
6582 {
6583 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24,
6772dd07 6584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6585 },
6586/* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
6587 {
6588 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24,
6772dd07 6589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6590 },
6591/* xor.b${G} #${Imm-16-QI},[$Dst16An] */
6592 {
6593 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24,
6772dd07 6594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6595 },
6596/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
6597 {
6598 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32,
6772dd07 6599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6600 },
6601/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6602 {
6603 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32,
6772dd07 6604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6605 },
6606/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6607 {
6608 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32,
6772dd07 6609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6610 },
6611/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
6612 {
6613 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40,
6772dd07 6614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6615 },
6616/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6617 {
6618 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40,
6772dd07 6619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6620 },
6621/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6622 {
6623 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40,
6772dd07 6624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 6625 },
6626/* xchg.w r3,$Dst32RnUnprefixedHI */
6627 {
6628 M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6630 },
6631/* xchg.w r3,$Dst32AnUnprefixedHI */
6632 {
6633 M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6635 },
6636/* xchg.w r3,[$Dst32AnUnprefixed] */
6637 {
6638 M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6772dd07 6639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6640 },
6641/* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6642 {
6643 M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6645 },
6646/* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6647 {
6648 M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6650 },
6651/* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6652 {
6653 M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6772dd07 6654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6655 },
6656/* xchg.w r3,${Dsp-16-u8}[sb] */
6657 {
6658 M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6660 },
6661/* xchg.w r3,${Dsp-16-u16}[sb] */
6662 {
6663 M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6665 },
6666/* xchg.w r3,${Dsp-16-s8}[fb] */
6667 {
6668 M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6670 },
6671/* xchg.w r3,${Dsp-16-s16}[fb] */
6672 {
6673 M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6675 },
6676/* xchg.w r3,${Dsp-16-u16} */
6677 {
6678 M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6772dd07 6679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6680 },
6681/* xchg.w r3,${Dsp-16-u24} */
6682 {
6683 M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6772dd07 6684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6685 },
6686/* xchg.w r2,$Dst32RnUnprefixedHI */
6687 {
6688 M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6690 },
6691/* xchg.w r2,$Dst32AnUnprefixedHI */
6692 {
6693 M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6695 },
6696/* xchg.w r2,[$Dst32AnUnprefixed] */
6697 {
6698 M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6772dd07 6699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6700 },
6701/* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6702 {
6703 M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6705 },
6706/* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6707 {
6708 M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6710 },
6711/* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6712 {
6713 M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6772dd07 6714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6715 },
6716/* xchg.w r2,${Dsp-16-u8}[sb] */
6717 {
6718 M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6720 },
6721/* xchg.w r2,${Dsp-16-u16}[sb] */
6722 {
6723 M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6725 },
6726/* xchg.w r2,${Dsp-16-s8}[fb] */
6727 {
6728 M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6730 },
6731/* xchg.w r2,${Dsp-16-s16}[fb] */
6732 {
6733 M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6735 },
6736/* xchg.w r2,${Dsp-16-u16} */
6737 {
6738 M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6772dd07 6739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6740 },
6741/* xchg.w r2,${Dsp-16-u24} */
6742 {
6743 M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6772dd07 6744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6745 },
6746/* xchg.w a1,$Dst32RnUnprefixedHI */
6747 {
6748 M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6750 },
6751/* xchg.w a1,$Dst32AnUnprefixedHI */
6752 {
6753 M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6755 },
6756/* xchg.w a1,[$Dst32AnUnprefixed] */
6757 {
6758 M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6772dd07 6759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6760 },
6761/* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6762 {
6763 M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6765 },
6766/* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6767 {
6768 M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6770 },
6771/* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6772 {
6773 M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6772dd07 6774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6775 },
6776/* xchg.w a1,${Dsp-16-u8}[sb] */
6777 {
6778 M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6780 },
6781/* xchg.w a1,${Dsp-16-u16}[sb] */
6782 {
6783 M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6785 },
6786/* xchg.w a1,${Dsp-16-s8}[fb] */
6787 {
6788 M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6790 },
6791/* xchg.w a1,${Dsp-16-s16}[fb] */
6792 {
6793 M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6795 },
6796/* xchg.w a1,${Dsp-16-u16} */
6797 {
6798 M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6772dd07 6799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6800 },
6801/* xchg.w a1,${Dsp-16-u24} */
6802 {
6803 M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6772dd07 6804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6805 },
6806/* xchg.w a0,$Dst32RnUnprefixedHI */
6807 {
6808 M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6810 },
6811/* xchg.w a0,$Dst32AnUnprefixedHI */
6812 {
6813 M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6815 },
6816/* xchg.w a0,[$Dst32AnUnprefixed] */
6817 {
6818 M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6772dd07 6819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6820 },
6821/* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6822 {
6823 M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6825 },
6826/* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6827 {
6828 M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6830 },
6831/* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6832 {
6833 M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6772dd07 6834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6835 },
6836/* xchg.w a0,${Dsp-16-u8}[sb] */
6837 {
6838 M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6840 },
6841/* xchg.w a0,${Dsp-16-u16}[sb] */
6842 {
6843 M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6845 },
6846/* xchg.w a0,${Dsp-16-s8}[fb] */
6847 {
6848 M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6850 },
6851/* xchg.w a0,${Dsp-16-s16}[fb] */
6852 {
6853 M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6855 },
6856/* xchg.w a0,${Dsp-16-u16} */
6857 {
6858 M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6772dd07 6859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6860 },
6861/* xchg.w a0,${Dsp-16-u24} */
6862 {
6863 M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6772dd07 6864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6865 },
6866/* xchg.w r1,$Dst32RnUnprefixedHI */
6867 {
6868 M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6870 },
6871/* xchg.w r1,$Dst32AnUnprefixedHI */
6872 {
6873 M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6875 },
6876/* xchg.w r1,[$Dst32AnUnprefixed] */
6877 {
6878 M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6772dd07 6879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6880 },
6881/* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6882 {
6883 M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6885 },
6886/* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6887 {
6888 M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6890 },
6891/* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6892 {
6893 M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6772dd07 6894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6895 },
6896/* xchg.w r1,${Dsp-16-u8}[sb] */
6897 {
6898 M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6900 },
6901/* xchg.w r1,${Dsp-16-u16}[sb] */
6902 {
6903 M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6905 },
6906/* xchg.w r1,${Dsp-16-s8}[fb] */
6907 {
6908 M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6910 },
6911/* xchg.w r1,${Dsp-16-s16}[fb] */
6912 {
6913 M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6915 },
6916/* xchg.w r1,${Dsp-16-u16} */
6917 {
6918 M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6772dd07 6919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6920 },
6921/* xchg.w r1,${Dsp-16-u24} */
6922 {
6923 M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6772dd07 6924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6925 },
6926/* xchg.w r0,$Dst32RnUnprefixedHI */
6927 {
6928 M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6930 },
6931/* xchg.w r0,$Dst32AnUnprefixedHI */
6932 {
6933 M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6772dd07 6934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6935 },
6936/* xchg.w r0,[$Dst32AnUnprefixed] */
6937 {
6938 M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6772dd07 6939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6940 },
6941/* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6942 {
6943 M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6945 },
6946/* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6947 {
6948 M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6950 },
6951/* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6952 {
6953 M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6772dd07 6954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6955 },
6956/* xchg.w r0,${Dsp-16-u8}[sb] */
6957 {
6958 M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6960 },
6961/* xchg.w r0,${Dsp-16-u16}[sb] */
6962 {
6963 M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6965 },
6966/* xchg.w r0,${Dsp-16-s8}[fb] */
6967 {
6968 M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6772dd07 6969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6970 },
6971/* xchg.w r0,${Dsp-16-s16}[fb] */
6972 {
6973 M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6772dd07 6974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6975 },
6976/* xchg.w r0,${Dsp-16-u16} */
6977 {
6978 M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6772dd07 6979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6980 },
6981/* xchg.w r0,${Dsp-16-u24} */
6982 {
6983 M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6772dd07 6984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6985 },
6986/* xchg.b r1h,$Dst32RnUnprefixedQI */
6987 {
6988 M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 6989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6990 },
6991/* xchg.b r1h,$Dst32AnUnprefixedQI */
6992 {
6993 M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 6994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 6995 },
6996/* xchg.b r1h,[$Dst32AnUnprefixed] */
6997 {
6998 M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6772dd07 6999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7000 },
7001/* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7002 {
7003 M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7005 },
7006/* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7007 {
7008 M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7010 },
7011/* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7012 {
7013 M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6772dd07 7014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7015 },
7016/* xchg.b r1h,${Dsp-16-u8}[sb] */
7017 {
7018 M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7020 },
7021/* xchg.b r1h,${Dsp-16-u16}[sb] */
7022 {
7023 M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7025 },
7026/* xchg.b r1h,${Dsp-16-s8}[fb] */
7027 {
7028 M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7030 },
7031/* xchg.b r1h,${Dsp-16-s16}[fb] */
7032 {
7033 M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7035 },
7036/* xchg.b r1h,${Dsp-16-u16} */
7037 {
7038 M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
6772dd07 7039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7040 },
7041/* xchg.b r1h,${Dsp-16-u24} */
7042 {
7043 M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
6772dd07 7044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7045 },
7046/* xchg.b r0h,$Dst32RnUnprefixedQI */
7047 {
7048 M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7050 },
7051/* xchg.b r0h,$Dst32AnUnprefixedQI */
7052 {
7053 M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7055 },
7056/* xchg.b r0h,[$Dst32AnUnprefixed] */
7057 {
7058 M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6772dd07 7059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7060 },
7061/* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7062 {
7063 M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7065 },
7066/* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7067 {
7068 M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7070 },
7071/* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7072 {
7073 M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6772dd07 7074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7075 },
7076/* xchg.b r0h,${Dsp-16-u8}[sb] */
7077 {
7078 M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7080 },
7081/* xchg.b r0h,${Dsp-16-u16}[sb] */
7082 {
7083 M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7085 },
7086/* xchg.b r0h,${Dsp-16-s8}[fb] */
7087 {
7088 M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7090 },
7091/* xchg.b r0h,${Dsp-16-s16}[fb] */
7092 {
7093 M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7095 },
7096/* xchg.b r0h,${Dsp-16-u16} */
7097 {
7098 M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
6772dd07 7099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7100 },
7101/* xchg.b r0h,${Dsp-16-u24} */
7102 {
7103 M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
6772dd07 7104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7105 },
7106/* xchg.b a1,$Dst32RnUnprefixedQI */
7107 {
7108 M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7110 },
7111/* xchg.b a1,$Dst32AnUnprefixedQI */
7112 {
7113 M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7115 },
7116/* xchg.b a1,[$Dst32AnUnprefixed] */
7117 {
7118 M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6772dd07 7119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7120 },
7121/* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7122 {
7123 M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7125 },
7126/* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7127 {
7128 M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7130 },
7131/* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7132 {
7133 M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6772dd07 7134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7135 },
7136/* xchg.b a1,${Dsp-16-u8}[sb] */
7137 {
7138 M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7140 },
7141/* xchg.b a1,${Dsp-16-u16}[sb] */
7142 {
7143 M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7145 },
7146/* xchg.b a1,${Dsp-16-s8}[fb] */
7147 {
7148 M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7150 },
7151/* xchg.b a1,${Dsp-16-s16}[fb] */
7152 {
7153 M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7155 },
7156/* xchg.b a1,${Dsp-16-u16} */
7157 {
7158 M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
6772dd07 7159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7160 },
7161/* xchg.b a1,${Dsp-16-u24} */
7162 {
7163 M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
6772dd07 7164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7165 },
7166/* xchg.b a0,$Dst32RnUnprefixedQI */
7167 {
7168 M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7170 },
7171/* xchg.b a0,$Dst32AnUnprefixedQI */
7172 {
7173 M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7175 },
7176/* xchg.b a0,[$Dst32AnUnprefixed] */
7177 {
7178 M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6772dd07 7179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7180 },
7181/* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7182 {
7183 M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7185 },
7186/* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7187 {
7188 M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7190 },
7191/* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7192 {
7193 M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6772dd07 7194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7195 },
7196/* xchg.b a0,${Dsp-16-u8}[sb] */
7197 {
7198 M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7200 },
7201/* xchg.b a0,${Dsp-16-u16}[sb] */
7202 {
7203 M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7205 },
7206/* xchg.b a0,${Dsp-16-s8}[fb] */
7207 {
7208 M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7210 },
7211/* xchg.b a0,${Dsp-16-s16}[fb] */
7212 {
7213 M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7215 },
7216/* xchg.b a0,${Dsp-16-u16} */
7217 {
7218 M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
6772dd07 7219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7220 },
7221/* xchg.b a0,${Dsp-16-u24} */
7222 {
7223 M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
6772dd07 7224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7225 },
7226/* xchg.b r1l,$Dst32RnUnprefixedQI */
7227 {
7228 M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7230 },
7231/* xchg.b r1l,$Dst32AnUnprefixedQI */
7232 {
7233 M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7235 },
7236/* xchg.b r1l,[$Dst32AnUnprefixed] */
7237 {
7238 M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6772dd07 7239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7240 },
7241/* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7242 {
7243 M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7245 },
7246/* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7247 {
7248 M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7250 },
7251/* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7252 {
7253 M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6772dd07 7254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7255 },
7256/* xchg.b r1l,${Dsp-16-u8}[sb] */
7257 {
7258 M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7260 },
7261/* xchg.b r1l,${Dsp-16-u16}[sb] */
7262 {
7263 M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7265 },
7266/* xchg.b r1l,${Dsp-16-s8}[fb] */
7267 {
7268 M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7270 },
7271/* xchg.b r1l,${Dsp-16-s16}[fb] */
7272 {
7273 M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7275 },
7276/* xchg.b r1l,${Dsp-16-u16} */
7277 {
7278 M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
6772dd07 7279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7280 },
7281/* xchg.b r1l,${Dsp-16-u24} */
7282 {
7283 M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
6772dd07 7284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7285 },
7286/* xchg.b r0l,$Dst32RnUnprefixedQI */
7287 {
7288 M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7290 },
7291/* xchg.b r0l,$Dst32AnUnprefixedQI */
7292 {
7293 M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6772dd07 7294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7295 },
7296/* xchg.b r0l,[$Dst32AnUnprefixed] */
7297 {
7298 M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6772dd07 7299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7300 },
7301/* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7302 {
7303 M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7305 },
7306/* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7307 {
7308 M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7310 },
7311/* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7312 {
7313 M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6772dd07 7314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7315 },
7316/* xchg.b r0l,${Dsp-16-u8}[sb] */
7317 {
7318 M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7320 },
7321/* xchg.b r0l,${Dsp-16-u16}[sb] */
7322 {
7323 M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7325 },
7326/* xchg.b r0l,${Dsp-16-s8}[fb] */
7327 {
7328 M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
6772dd07 7329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7330 },
7331/* xchg.b r0l,${Dsp-16-s16}[fb] */
7332 {
7333 M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
6772dd07 7334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7335 },
7336/* xchg.b r0l,${Dsp-16-u16} */
7337 {
7338 M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
6772dd07 7339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7340 },
7341/* xchg.b r0l,${Dsp-16-u24} */
7342 {
7343 M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
6772dd07 7344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7345 },
7346/* xchg.w r3,$Dst16RnHI */
7347 {
7348 M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16,
6772dd07 7349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7350 },
7351/* xchg.w r3,$Dst16AnHI */
7352 {
7353 M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16,
6772dd07 7354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7355 },
7356/* xchg.w r3,[$Dst16An] */
7357 {
7358 M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16,
6772dd07 7359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7360 },
7361/* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
7362 {
7363 M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24,
6772dd07 7364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7365 },
7366/* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
7367 {
7368 M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32,
6772dd07 7369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7370 },
7371/* xchg.w r3,${Dsp-16-u8}[sb] */
7372 {
7373 M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24,
6772dd07 7374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7375 },
7376/* xchg.w r3,${Dsp-16-u16}[sb] */
7377 {
7378 M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32,
6772dd07 7379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7380 },
7381/* xchg.w r3,${Dsp-16-s8}[fb] */
7382 {
7383 M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24,
6772dd07 7384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7385 },
7386/* xchg.w r3,${Dsp-16-u16} */
7387 {
7388 M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32,
6772dd07 7389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7390 },
7391/* xchg.w r2,$Dst16RnHI */
7392 {
7393 M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16,
6772dd07 7394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7395 },
7396/* xchg.w r2,$Dst16AnHI */
7397 {
7398 M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16,
6772dd07 7399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7400 },
7401/* xchg.w r2,[$Dst16An] */
7402 {
7403 M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16,
6772dd07 7404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7405 },
7406/* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
7407 {
7408 M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24,
6772dd07 7409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7410 },
7411/* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
7412 {
7413 M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32,
6772dd07 7414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7415 },
7416/* xchg.w r2,${Dsp-16-u8}[sb] */
7417 {
7418 M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24,
6772dd07 7419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7420 },
7421/* xchg.w r2,${Dsp-16-u16}[sb] */
7422 {
7423 M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32,
6772dd07 7424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7425 },
7426/* xchg.w r2,${Dsp-16-s8}[fb] */
7427 {
7428 M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24,
6772dd07 7429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7430 },
7431/* xchg.w r2,${Dsp-16-u16} */
7432 {
7433 M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32,
6772dd07 7434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7435 },
7436/* xchg.w r1,$Dst16RnHI */
7437 {
7438 M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16,
6772dd07 7439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7440 },
7441/* xchg.w r1,$Dst16AnHI */
7442 {
7443 M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16,
6772dd07 7444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7445 },
7446/* xchg.w r1,[$Dst16An] */
7447 {
7448 M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16,
6772dd07 7449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7450 },
7451/* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
7452 {
7453 M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24,
6772dd07 7454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7455 },
7456/* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
7457 {
7458 M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32,
6772dd07 7459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7460 },
7461/* xchg.w r1,${Dsp-16-u8}[sb] */
7462 {
7463 M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24,
6772dd07 7464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7465 },
7466/* xchg.w r1,${Dsp-16-u16}[sb] */
7467 {
7468 M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32,
6772dd07 7469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7470 },
7471/* xchg.w r1,${Dsp-16-s8}[fb] */
7472 {
7473 M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24,
6772dd07 7474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7475 },
7476/* xchg.w r1,${Dsp-16-u16} */
7477 {
7478 M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
6772dd07 7479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 7480 },
a1a280bb 7481/* xchg.w r0,$Dst16RnHI */
49f58d10 7482 {
a1a280bb 7483 M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16,
6772dd07 7484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 7485 },
a1a280bb 7486/* xchg.w r0,$Dst16AnHI */
49f58d10 7487 {
a1a280bb 7488 M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16,
6772dd07 7489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7490 },
7491/* xchg.w r0,[$Dst16An] */
7492 {
a1a280bb 7493 M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16,
6772dd07 7494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7495 },
7496/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
7497 {
a1a280bb 7498 M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24,
6772dd07 7499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7500 },
7501/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
7502 {
a1a280bb 7503 M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32,
6772dd07 7504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7505 },
7506/* xchg.w r0,${Dsp-16-u8}[sb] */
7507 {
a1a280bb 7508 M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24,
6772dd07 7509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7510 },
7511/* xchg.w r0,${Dsp-16-u16}[sb] */
7512 {
a1a280bb 7513 M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32,
6772dd07 7514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7515 },
7516/* xchg.w r0,${Dsp-16-s8}[fb] */
7517 {
a1a280bb 7518 M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24,
6772dd07 7519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7520 },
7521/* xchg.w r0,${Dsp-16-u16} */
7522 {
a1a280bb 7523 M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32,
6772dd07 7524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7525 },
7526/* xchg.b r1h,$Dst16RnQI */
7527 {
7528 M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16,
6772dd07 7529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7530 },
7531/* xchg.b r1h,$Dst16AnQI */
7532 {
7533 M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16,
6772dd07 7534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7535 },
7536/* xchg.b r1h,[$Dst16An] */
7537 {
7538 M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16,
6772dd07 7539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7540 },
7541/* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
7542 {
7543 M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24,
6772dd07 7544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7545 },
7546/* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
7547 {
7548 M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32,
6772dd07 7549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7550 },
7551/* xchg.b r1h,${Dsp-16-u8}[sb] */
7552 {
7553 M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
6772dd07 7554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7555 },
7556/* xchg.b r1h,${Dsp-16-u16}[sb] */
7557 {
7558 M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
6772dd07 7559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7560 },
7561/* xchg.b r1h,${Dsp-16-s8}[fb] */
7562 {
7563 M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
6772dd07 7564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7565 },
7566/* xchg.b r1h,${Dsp-16-u16} */
7567 {
7568 M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32,
6772dd07 7569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7570 },
7571/* xchg.b r1l,$Dst16RnQI */
7572 {
7573 M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16,
6772dd07 7574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7575 },
7576/* xchg.b r1l,$Dst16AnQI */
7577 {
7578 M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16,
6772dd07 7579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7580 },
7581/* xchg.b r1l,[$Dst16An] */
7582 {
7583 M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16,
6772dd07 7584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7585 },
7586/* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
7587 {
7588 M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24,
6772dd07 7589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7590 },
7591/* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
7592 {
7593 M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32,
6772dd07 7594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7595 },
7596/* xchg.b r1l,${Dsp-16-u8}[sb] */
7597 {
7598 M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
6772dd07 7599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7600 },
7601/* xchg.b r1l,${Dsp-16-u16}[sb] */
7602 {
7603 M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
6772dd07 7604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7605 },
7606/* xchg.b r1l,${Dsp-16-s8}[fb] */
7607 {
7608 M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
6772dd07 7609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7610 },
7611/* xchg.b r1l,${Dsp-16-u16} */
7612 {
7613 M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32,
6772dd07 7614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7615 },
7616/* xchg.b r0h,$Dst16RnQI */
7617 {
7618 M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16,
6772dd07 7619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7620 },
7621/* xchg.b r0h,$Dst16AnQI */
7622 {
7623 M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16,
6772dd07 7624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7625 },
7626/* xchg.b r0h,[$Dst16An] */
7627 {
7628 M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16,
6772dd07 7629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7630 },
7631/* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
7632 {
7633 M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24,
6772dd07 7634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7635 },
7636/* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
7637 {
7638 M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32,
6772dd07 7639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7640 },
7641/* xchg.b r0h,${Dsp-16-u8}[sb] */
7642 {
7643 M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
6772dd07 7644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7645 },
7646/* xchg.b r0h,${Dsp-16-u16}[sb] */
7647 {
7648 M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
6772dd07 7649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7650 },
7651/* xchg.b r0h,${Dsp-16-s8}[fb] */
7652 {
7653 M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
6772dd07 7654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7655 },
7656/* xchg.b r0h,${Dsp-16-u16} */
7657 {
7658 M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32,
6772dd07 7659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7660 },
7661/* xchg.b r0l,$Dst16RnQI */
7662 {
7663 M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16,
6772dd07 7664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7665 },
7666/* xchg.b r0l,$Dst16AnQI */
7667 {
7668 M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16,
6772dd07 7669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7670 },
7671/* xchg.b r0l,[$Dst16An] */
7672 {
7673 M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16,
6772dd07 7674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7675 },
7676/* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
7677 {
7678 M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24,
6772dd07 7679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7680 },
7681/* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
7682 {
7683 M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32,
6772dd07 7684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7685 },
7686/* xchg.b r0l,${Dsp-16-u8}[sb] */
7687 {
7688 M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
6772dd07 7689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7690 },
7691/* xchg.b r0l,${Dsp-16-u16}[sb] */
7692 {
7693 M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
6772dd07 7694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7695 },
7696/* xchg.b r0l,${Dsp-16-s8}[fb] */
7697 {
7698 M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
6772dd07 7699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7700 },
7701/* xchg.b r0l,${Dsp-16-u16} */
7702 {
7703 M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32,
6772dd07 7704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7705 },
7706/* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
7707 {
7708 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32,
6772dd07 7709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7710 },
7711/* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
7712 {
7713 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32,
6772dd07 7714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7715 },
7716/* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
7717 {
7718 M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40,
6772dd07 7719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7720 },
7721/* tst.w${S} #${Imm-8-HI},r0 */
7722 {
7723 M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24,
6772dd07 7724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7725 },
7726/* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
7727 {
7728 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24,
6772dd07 7729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7730 },
7731/* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
7732 {
7733 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24,
6772dd07 7734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7735 },
7736/* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
7737 {
7738 M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32,
6772dd07 7739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 7740 },
7741/* tst.b${S} #${Imm-8-QI},r0l */
7742 {
7743 M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16,
6772dd07 7744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 7745 },
f75eb1c0 7746/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 7747 {
7748 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
6772dd07 7749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7750 },
f75eb1c0 7751/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
49f58d10
JB		 7752 {
7753 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
6772dd07 7754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7755 },
f75eb1c0 7756/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
49f58d10
JB		 7757 {
7758 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
6772dd07 7759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7760 },
f75eb1c0 7761/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 7762 {
7763 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
6772dd07 7764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7765 },
f75eb1c0 7766/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
49f58d10
JB		 7767 {
7768 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
6772dd07 7769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7770 },
f75eb1c0 7771/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
49f58d10
JB		 7772 {
7773 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
6772dd07 7774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7775 },
f75eb1c0 7776/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 7777 {
7778 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
6772dd07 7779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7780 },
f75eb1c0 7781/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 7782 {
7783 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
6772dd07 7784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7785 },
f75eb1c0 7786/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 7787 {
7788 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
6772dd07 7789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7790 },
f75eb1c0 7791/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 7792 {
7793 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7795 },
f75eb1c0 7796/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 7797 {
7798 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7800 },
f75eb1c0 7801/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 7802 {
7803 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7805 },
f75eb1c0 7806/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 7807 {
7808 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7810 },
f75eb1c0 7811/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 7812 {
7813 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7815 },
f75eb1c0 7816/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 7817 {
7818 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7820 },
f75eb1c0 7821/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 7822 {
7823 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 7824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7825 },
f75eb1c0 7826/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 7827 {
7828 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 7829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7830 },
f75eb1c0 7831/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 7832 {
7833 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 7834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7835 },
f75eb1c0 7836/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
49f58d10
JB		 7837 {
7838 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7840 },
f75eb1c0 7841/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
49f58d10
JB		 7842 {
7843 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7845 },
f75eb1c0 7846/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
49f58d10
JB		 7847 {
7848 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7850 },
f75eb1c0 7851/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
49f58d10
JB		 7852 {
7853 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7855 },
f75eb1c0 7856/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
49f58d10
JB		 7857 {
7858 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7860 },
f75eb1c0 7861/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
49f58d10
JB		 7862 {
7863 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7865 },
f75eb1c0 7866/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
49f58d10
JB		 7867 {
7868 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7870 },
f75eb1c0 7871/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
49f58d10
JB		 7872 {
7873 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7875 },
f75eb1c0 7876/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
49f58d10
JB		 7877 {
7878 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 7879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7880 },
f75eb1c0 7881/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
49f58d10
JB		 7882 {
7883 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7885 },
f75eb1c0 7886/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
49f58d10
JB		 7887 {
7888 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7890 },
f75eb1c0 7891/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
49f58d10
JB		 7892 {
7893 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7895 },
f75eb1c0 7896/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
49f58d10
JB		 7897 {
7898 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
6772dd07 7899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7900 },
f75eb1c0 7901/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
49f58d10
JB		 7902 {
7903 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
6772dd07 7904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7905 },
f75eb1c0 7906/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
49f58d10
JB		 7907 {
7908 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
6772dd07 7909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7910 },
f75eb1c0 7911/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
49f58d10
JB		 7912 {
7913 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
6772dd07 7914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7915 },
f75eb1c0 7916/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
49f58d10
JB		 7917 {
7918 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
6772dd07 7919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7920 },
f75eb1c0 7921/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
49f58d10
JB		 7922 {
7923 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
6772dd07 7924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7925 },
f75eb1c0 7926/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 7927 {
7928 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7930 },
f75eb1c0 7931/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
49f58d10
JB		 7932 {
7933 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7935 },
f75eb1c0 7936/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
49f58d10
JB		 7937 {
7938 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7940 },
f75eb1c0 7941/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
49f58d10
JB		 7942 {
7943 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7945 },
f75eb1c0 7946/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 7947 {
7948 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7950 },
f75eb1c0 7951/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
49f58d10
JB		 7952 {
7953 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7955 },
f75eb1c0 7956/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
49f58d10
JB		 7957 {
7958 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7960 },
f75eb1c0 7961/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
49f58d10
JB		 7962 {
7963 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
6772dd07 7964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7965 },
f75eb1c0 7966/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 7967 {
7968 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
6772dd07 7969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7970 },
f75eb1c0 7971/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 7972 {
7973 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
6772dd07 7974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7975 },
f75eb1c0 7976/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 7977 {
7978 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
6772dd07 7979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7980 },
f75eb1c0 7981/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
49f58d10
JB		 7982 {
7983 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
6772dd07 7984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7985 },
f75eb1c0 7986/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 7987 {
7988 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7990 },
f75eb1c0 7991/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 7992 {
7993 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 7995 },
f75eb1c0 7996/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 7997 {
7998 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 7999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8000 },
f75eb1c0 8001/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8002 {
8003 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8005 },
f75eb1c0 8006/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8007 {
8008 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8010 },
f75eb1c0 8011/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8012 {
8013 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8015 },
f75eb1c0 8016/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8017 {
8018 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8020 },
f75eb1c0 8021/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8022 {
8023 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8025 },
f75eb1c0 8026/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8027 {
8028 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8030 },
f75eb1c0 8031/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8032 {
8033 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8035 },
f75eb1c0 8036/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8037 {
8038 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8040 },
f75eb1c0 8041/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8042 {
8043 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8045 },
f75eb1c0 8046/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
49f58d10
JB		 8047 {
8048 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8050 },
f75eb1c0 8051/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
49f58d10
JB		 8052 {
8053 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8055 },
f75eb1c0 8056/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
49f58d10
JB		 8057 {
8058 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8060 },
f75eb1c0 8061/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
49f58d10
JB		 8062 {
8063 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8065 },
f75eb1c0 8066/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
49f58d10
JB		 8067 {
8068 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8070 },
f75eb1c0 8071/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
49f58d10
JB		 8072 {
8073 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8075 },
f75eb1c0 8076/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
49f58d10
JB		 8077 {
8078 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8080 },
f75eb1c0 8081/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
49f58d10
JB		 8082 {
8083 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8085 },
f75eb1c0 8086/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
49f58d10
JB		 8087 {
8088 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8090 },
f75eb1c0 8091/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
49f58d10
JB		 8092 {
8093 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8095 },
f75eb1c0 8096/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
49f58d10
JB		 8097 {
8098 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8100 },
f75eb1c0 8101/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
49f58d10
JB		 8102 {
8103 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8105 },
f75eb1c0 8106/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
49f58d10
JB		 8107 {
8108 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8110 },
f75eb1c0 8111/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
49f58d10
JB		 8112 {
8113 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8115 },
f75eb1c0 8116/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
49f58d10
JB		 8117 {
8118 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8120 },
f75eb1c0 8121/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
49f58d10
JB		 8122 {
8123 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8125 },
f75eb1c0 8126/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
49f58d10
JB		 8127 {
8128 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
6772dd07 8129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8130 },
f75eb1c0 8131/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
49f58d10
JB		 8132 {
8133 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
6772dd07 8134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8135 },
f75eb1c0 8136/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
49f58d10
JB		 8137 {
8138 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
6772dd07 8139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8140 },
f75eb1c0 8141/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
49f58d10
JB		 8142 {
8143 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
6772dd07 8144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8145 },
f75eb1c0 8146/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
49f58d10
JB		 8147 {
8148 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
6772dd07 8149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8150 },
f75eb1c0 8151/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
49f58d10
JB		 8152 {
8153 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
6772dd07 8154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8155 },
f75eb1c0 8156/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
49f58d10
JB		 8157 {
8158 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
6772dd07 8159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8160 },
f75eb1c0 8161/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
49f58d10
JB		 8162 {
8163 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
6772dd07 8164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8165 },
f75eb1c0 8166/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 8167 {
8168 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
6772dd07 8169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8170 },
f75eb1c0 8171/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
49f58d10
JB		 8172 {
8173 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
6772dd07 8174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8175 },
f75eb1c0 8176/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 8177 {
8178 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
6772dd07 8179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8180 },
f75eb1c0 8181/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
49f58d10
JB		 8182 {
8183 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
6772dd07 8184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8185 },
f75eb1c0 8186/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 8187 {
8188 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
6772dd07 8189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8190 },
f75eb1c0 8191/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
49f58d10
JB		 8192 {
8193 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
6772dd07 8194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8195 },
f75eb1c0 8196/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8197 {
8198 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8200 },
f75eb1c0 8201/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8202 {
8203 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8205 },
f75eb1c0 8206/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8207 {
8208 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8210 },
f75eb1c0 8211/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8212 {
8213 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8215 },
f75eb1c0 8216/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8217 {
8218 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
6772dd07 8219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8220 },
f75eb1c0 8221/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8222 {
8223 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
6772dd07 8224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8225 },
f75eb1c0 8226/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
49f58d10
JB		 8227 {
8228 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8230 },
f75eb1c0 8231/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
49f58d10
JB		 8232 {
8233 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8235 },
f75eb1c0 8236/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
49f58d10
JB		 8237 {
8238 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8240 },
f75eb1c0 8241/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
49f58d10
JB		 8242 {
8243 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8245 },
f75eb1c0 8246/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
49f58d10
JB		 8247 {
8248 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8250 },
f75eb1c0 8251/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
49f58d10
JB		 8252 {
8253 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
6772dd07 8254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8255 },
f75eb1c0 8256/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
49f58d10
JB		 8257 {
8258 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8260 },
f75eb1c0 8261/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
49f58d10
JB		 8262 {
8263 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
6772dd07 8264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8265 },
f75eb1c0 8266/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
49f58d10
JB		 8267 {
8268 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
6772dd07 8269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8270 },
f75eb1c0 8271/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
49f58d10
JB		 8272 {
8273 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
6772dd07 8274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8275 },
f75eb1c0 8276/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
49f58d10
JB		 8277 {
8278 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
6772dd07 8279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8280 },
f75eb1c0 8281/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
49f58d10
JB		 8282 {
8283 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
6772dd07 8284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8285 },
f75eb1c0 8286/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
49f58d10
JB		 8287 {
8288 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
6772dd07 8289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8290 },
f75eb1c0 8291/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
49f58d10
JB		 8292 {
8293 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
6772dd07 8294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8295 },
f75eb1c0 8296/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
49f58d10
JB		 8297 {
8298 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
6772dd07 8299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8300 },
f75eb1c0 8301/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
49f58d10
JB		 8302 {
8303 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
6772dd07 8304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8305 },
f75eb1c0 8306/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
49f58d10
JB		 8307 {
8308 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
6772dd07 8309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8310 },
f75eb1c0 8311/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
49f58d10
JB		 8312 {
8313 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
6772dd07 8314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8315 },
f75eb1c0 8316/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
49f58d10
JB		 8317 {
8318 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
6772dd07 8319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8320 },
f75eb1c0 8321/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
49f58d10
JB		 8322 {
8323 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
6772dd07 8324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8325 },
f75eb1c0 8326/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 8327 {
8328 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
6772dd07 8329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8330 },
f75eb1c0 8331/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8332 {
8333 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8335 },
f75eb1c0 8336/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8337 {
8338 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8340 },
f75eb1c0 8341/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8342 {
8343 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8345 },
f75eb1c0 8346/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8347 {
8348 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8350 },
f75eb1c0 8351/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8352 {
8353 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8355 },
f75eb1c0 8356/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8357 {
8358 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8360 },
f75eb1c0 8361/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8362 {
8363 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8365 },
f75eb1c0 8366/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8367 {
8368 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8370 },
f75eb1c0 8371/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8372 {
8373 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
6772dd07 8374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8375 },
f75eb1c0 8376/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
49f58d10
JB		 8377 {
8378 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8380 },
f75eb1c0 8381/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
49f58d10
JB		 8382 {
8383 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8385 },
f75eb1c0 8386/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
49f58d10
JB		 8387 {
8388 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8390 },
f75eb1c0 8391/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
49f58d10
JB		 8392 {
8393 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8395 },
f75eb1c0 8396/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
49f58d10
JB		 8397 {
8398 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8400 },
f75eb1c0 8401/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
49f58d10
JB		 8402 {
8403 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8405 },
f75eb1c0 8406/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
49f58d10
JB		 8407 {
8408 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8410 },
f75eb1c0 8411/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
49f58d10
JB		 8412 {
8413 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8415 },
f75eb1c0 8416/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
49f58d10
JB		 8417 {
8418 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
6772dd07 8419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8420 },
f75eb1c0 8421/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
49f58d10
JB		 8422 {
8423 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8425 },
f75eb1c0 8426/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
49f58d10
JB		 8427 {
8428 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8430 },
f75eb1c0 8431/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
49f58d10
JB		 8432 {
8433 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
6772dd07 8434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8435 },
f75eb1c0 8436/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
49f58d10
JB		 8437 {
8438 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
6772dd07 8439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8440 },
f75eb1c0 8441/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
49f58d10
JB		 8442 {
8443 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
6772dd07 8444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8445 },
f75eb1c0 8446/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
49f58d10
JB		 8447 {
8448 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
6772dd07 8449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8450 },
f75eb1c0 8451/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
49f58d10
JB		 8452 {
8453 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
6772dd07 8454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8455 },
f75eb1c0 8456/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
49f58d10
JB		 8457 {
8458 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
6772dd07 8459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8460 },
f75eb1c0 8461/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
49f58d10
JB		 8462 {
8463 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
6772dd07 8464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8465 },
f75eb1c0 8466/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 8467 {
8468 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
6772dd07 8469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8470 },
f75eb1c0 8471/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
49f58d10
JB		 8472 {
8473 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
6772dd07 8474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8475 },
f75eb1c0 8476/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
49f58d10
JB		 8477 {
8478 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
6772dd07 8479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8480 },
f75eb1c0 8481/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 8482 {
8483 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
6772dd07 8484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8485 },
f75eb1c0 8486/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
49f58d10
JB		 8487 {
8488 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
6772dd07 8489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8490 },
f75eb1c0 8491/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
49f58d10
JB		 8492 {
8493 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
6772dd07 8494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8495 },
f75eb1c0 8496/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 8497 {
8498 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
6772dd07 8499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8500 },
f75eb1c0 8501/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 8502 {
8503 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
6772dd07 8504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8505 },
f75eb1c0 8506/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 8507 {
8508 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
6772dd07 8509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8510 },
f75eb1c0 8511/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8512 {
8513 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8515 },
f75eb1c0 8516/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8517 {
8518 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8520 },
f75eb1c0 8521/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8522 {
8523 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8525 },
f75eb1c0 8526/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8527 {
8528 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8530 },
f75eb1c0 8531/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8532 {
8533 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8535 },
f75eb1c0 8536/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8537 {
8538 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8540 },
f75eb1c0 8541/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8542 {
8543 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8545 },
f75eb1c0 8546/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8547 {
8548 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8550 },
f75eb1c0 8551/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8552 {
8553 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8555 },
f75eb1c0 8556/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
49f58d10
JB		 8557 {
8558 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8560 },
f75eb1c0 8561/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
49f58d10
JB		 8562 {
8563 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8565 },
f75eb1c0 8566/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
49f58d10
JB		 8567 {
8568 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8570 },
f75eb1c0 8571/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
49f58d10
JB		 8572 {
8573 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8575 },
f75eb1c0 8576/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
49f58d10
JB		 8577 {
8578 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8580 },
f75eb1c0 8581/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
49f58d10
JB		 8582 {
8583 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8585 },
f75eb1c0 8586/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
49f58d10
JB		 8587 {
8588 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8590 },
f75eb1c0 8591/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
49f58d10
JB		 8592 {
8593 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8595 },
f75eb1c0 8596/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
49f58d10
JB		 8597 {
8598 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 8599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8600 },
f75eb1c0 8601/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
49f58d10
JB		 8602 {
8603 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8605 },
f75eb1c0 8606/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
49f58d10
JB		 8607 {
8608 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8610 },
f75eb1c0 8611/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
49f58d10
JB		 8612 {
8613 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8615 },
f75eb1c0 8616/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
49f58d10
JB		 8617 {
8618 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
6772dd07 8619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8620 },
f75eb1c0 8621/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
49f58d10
JB		 8622 {
8623 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
6772dd07 8624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8625 },
f75eb1c0 8626/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
49f58d10
JB		 8627 {
8628 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
6772dd07 8629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8630 },
f75eb1c0 8631/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
49f58d10
JB		 8632 {
8633 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
6772dd07 8634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8635 },
f75eb1c0 8636/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
49f58d10
JB		 8637 {
8638 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
6772dd07 8639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8640 },
f75eb1c0 8641/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
49f58d10
JB		 8642 {
8643 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
6772dd07 8644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8645 },
f75eb1c0 8646/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 8647 {
8648 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8650 },
f75eb1c0 8651/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
49f58d10
JB		 8652 {
8653 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8655 },
f75eb1c0 8656/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
49f58d10
JB		 8657 {
8658 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8660 },
f75eb1c0 8661/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
49f58d10
JB		 8662 {
8663 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8665 },
f75eb1c0 8666/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 8667 {
8668 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8670 },
f75eb1c0 8671/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
49f58d10
JB		 8672 {
8673 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8675 },
f75eb1c0 8676/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
49f58d10
JB		 8677 {
8678 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8680 },
f75eb1c0 8681/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
49f58d10
JB		 8682 {
8683 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
6772dd07 8684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8685 },
f75eb1c0 8686/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 8687 {
8688 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
6772dd07 8689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8690 },
f75eb1c0 8691/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
49f58d10
JB		 8692 {
8693 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
6772dd07 8694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8695 },
f75eb1c0 8696/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
49f58d10
JB		 8697 {
8698 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
6772dd07 8699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8700 },
f75eb1c0 8701/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
49f58d10
JB		 8702 {
8703 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
6772dd07 8704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8705 },
f75eb1c0 8706/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8707 {
8708 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8710 },
f75eb1c0 8711/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8712 {
8713 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8715 },
f75eb1c0 8716/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8717 {
8718 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8720 },
f75eb1c0 8721/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8722 {
8723 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8725 },
f75eb1c0 8726/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8727 {
8728 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8730 },
f75eb1c0 8731/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8732 {
8733 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8735 },
f75eb1c0 8736/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8737 {
8738 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8740 },
f75eb1c0 8741/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8742 {
8743 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8745 },
f75eb1c0 8746/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8747 {
8748 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8750 },
f75eb1c0 8751/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8752 {
8753 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8755 },
f75eb1c0 8756/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8757 {
8758 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8760 },
f75eb1c0 8761/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8762 {
8763 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8765 },
f75eb1c0 8766/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
49f58d10
JB		 8767 {
8768 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8770 },
f75eb1c0 8771/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
49f58d10
JB		 8772 {
8773 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8775 },
f75eb1c0 8776/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
49f58d10
JB		 8777 {
8778 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8780 },
f75eb1c0 8781/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
49f58d10
JB		 8782 {
8783 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8785 },
f75eb1c0 8786/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
49f58d10
JB		 8787 {
8788 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8790 },
f75eb1c0 8791/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
49f58d10
JB		 8792 {
8793 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8795 },
f75eb1c0 8796/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
49f58d10
JB		 8797 {
8798 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8800 },
f75eb1c0 8801/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
49f58d10
JB		 8802 {
8803 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8805 },
f75eb1c0 8806/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
49f58d10
JB		 8807 {
8808 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8810 },
f75eb1c0 8811/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
49f58d10
JB		 8812 {
8813 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8815 },
f75eb1c0 8816/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
49f58d10
JB		 8817 {
8818 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8820 },
f75eb1c0 8821/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
49f58d10
JB		 8822 {
8823 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
6772dd07 8824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8825 },
f75eb1c0 8826/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
49f58d10
JB		 8827 {
8828 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8830 },
f75eb1c0 8831/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
49f58d10
JB		 8832 {
8833 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8835 },
f75eb1c0 8836/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
49f58d10
JB		 8837 {
8838 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8840 },
f75eb1c0 8841/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
49f58d10
JB		 8842 {
8843 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8845 },
f75eb1c0 8846/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
49f58d10
JB		 8847 {
8848 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
6772dd07 8849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8850 },
f75eb1c0 8851/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
49f58d10
JB		 8852 {
8853 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
6772dd07 8854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8855 },
f75eb1c0 8856/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
49f58d10
JB		 8857 {
8858 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
6772dd07 8859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8860 },
f75eb1c0 8861/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
49f58d10
JB		 8862 {
8863 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
6772dd07 8864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8865 },
f75eb1c0 8866/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
49f58d10
JB		 8867 {
8868 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
6772dd07 8869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8870 },
f75eb1c0 8871/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
49f58d10
JB		 8872 {
8873 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
6772dd07 8874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8875 },
f75eb1c0 8876/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
49f58d10
JB		 8877 {
8878 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
6772dd07 8879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8880 },
f75eb1c0 8881/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
49f58d10
JB		 8882 {
8883 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
6772dd07 8884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8885 },
f75eb1c0 8886/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 8887 {
8888 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
6772dd07 8889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8890 },
f75eb1c0 8891/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
49f58d10
JB		 8892 {
8893 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
6772dd07 8894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8895 },
f75eb1c0 8896/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 8897 {
8898 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
6772dd07 8899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8900 },
f75eb1c0 8901/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
49f58d10
JB		 8902 {
8903 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
6772dd07 8904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8905 },
f75eb1c0 8906/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 8907 {
8908 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
6772dd07 8909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8910 },
f75eb1c0 8911/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
49f58d10
JB		 8912 {
8913 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
6772dd07 8914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8915 },
f75eb1c0 8916/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8917 {
8918 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8920 },
f75eb1c0 8921/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 8922 {
8923 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8925 },
f75eb1c0 8926/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8927 {
8928 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8930 },
f75eb1c0 8931/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 8932 {
8933 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8935 },
f75eb1c0 8936/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8937 {
8938 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
6772dd07 8939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8940 },
f75eb1c0 8941/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 8942 {
8943 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
6772dd07 8944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8945 },
f75eb1c0 8946/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
49f58d10
JB		 8947 {
8948 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8950 },
f75eb1c0 8951/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
49f58d10
JB		 8952 {
8953 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8955 },
f75eb1c0 8956/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
49f58d10
JB		 8957 {
8958 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8960 },
f75eb1c0 8961/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
49f58d10
JB		 8962 {
8963 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8965 },
f75eb1c0 8966/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
49f58d10
JB		 8967 {
8968 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8970 },
f75eb1c0 8971/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
49f58d10
JB		 8972 {
8973 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
6772dd07 8974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8975 },
f75eb1c0 8976/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
49f58d10
JB		 8977 {
8978 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8980 },
f75eb1c0 8981/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
49f58d10
JB		 8982 {
8983 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
6772dd07 8984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8985 },
f75eb1c0 8986/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
49f58d10
JB		 8987 {
8988 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
6772dd07 8989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8990 },
f75eb1c0 8991/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
49f58d10
JB		 8992 {
8993 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
6772dd07 8994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 8995 },
f75eb1c0 8996/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
49f58d10
JB		 8997 {
8998 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
6772dd07 8999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9000 },
f75eb1c0 9001/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
49f58d10
JB		 9002 {
9003 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
6772dd07 9004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9005 },
f75eb1c0 9006/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
49f58d10
JB		 9007 {
9008 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
6772dd07 9009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9010 },
f75eb1c0 9011/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
49f58d10
JB		 9012 {
9013 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
6772dd07 9014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9015 },
f75eb1c0 9016/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
49f58d10
JB		 9017 {
9018 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
6772dd07 9019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9020 },
f75eb1c0 9021/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
49f58d10
JB		 9022 {
9023 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
6772dd07 9024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9025 },
f75eb1c0 9026/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
49f58d10
JB		 9027 {
9028 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
6772dd07 9029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9030 },
f75eb1c0 9031/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
49f58d10
JB		 9032 {
9033 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
6772dd07 9034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9035 },
f75eb1c0 9036/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
49f58d10
JB		 9037 {
9038 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
6772dd07 9039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9040 },
f75eb1c0 9041/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
49f58d10
JB		 9042 {
9043 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
6772dd07 9044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9045 },
f75eb1c0 9046/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
49f58d10
JB		 9047 {
9048 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
6772dd07 9049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9050 },
f75eb1c0 9051/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 9052 {
9053 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9055 },
f75eb1c0 9056/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 9057 {
9058 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9060 },
f75eb1c0 9061/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
49f58d10
JB		 9062 {
9063 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9065 },
f75eb1c0 9066/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 9067 {
9068 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9070 },
f75eb1c0 9071/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 9072 {
9073 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9075 },
f75eb1c0 9076/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
49f58d10
JB		 9077 {
9078 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9080 },
f75eb1c0 9081/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 9082 {
9083 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 9084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9085 },
f75eb1c0 9086/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 9087 {
9088 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 9089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9090 },
f75eb1c0 9091/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
49f58d10
JB		 9092 {
9093 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
6772dd07 9094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9095 },
f75eb1c0 9096/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
49f58d10
JB		 9097 {
9098 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9100 },
f75eb1c0 9101/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
49f58d10
JB		 9102 {
9103 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9105 },
f75eb1c0 9106/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
49f58d10
JB		 9107 {
9108 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9110 },
f75eb1c0 9111/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
49f58d10
JB		 9112 {
9113 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9115 },
f75eb1c0 9116/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
49f58d10
JB		 9117 {
9118 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9120 },
f75eb1c0 9121/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
49f58d10
JB		 9122 {
9123 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9125 },
f75eb1c0 9126/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
49f58d10
JB		 9127 {
9128 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9130 },
f75eb1c0 9131/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
49f58d10
JB		 9132 {
9133 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9135 },
f75eb1c0 9136/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
49f58d10
JB		 9137 {
9138 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
6772dd07 9139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9140 },
f75eb1c0 9141/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
49f58d10
JB		 9142 {
9143 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9145 },
f75eb1c0 9146/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
49f58d10
JB		 9147 {
9148 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9150 },
f75eb1c0 9151/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
49f58d10
JB		 9152 {
9153 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
6772dd07 9154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9155 },
f75eb1c0 9156/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
49f58d10
JB		 9157 {
9158 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
6772dd07 9159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9160 },
f75eb1c0 9161/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
49f58d10
JB		 9162 {
9163 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
6772dd07 9164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9165 },
f75eb1c0 9166/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
49f58d10
JB		 9167 {
9168 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
6772dd07 9169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9170 },
f75eb1c0 9171/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
49f58d10
JB		 9172 {
9173 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
6772dd07 9174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9175 },
f75eb1c0 9176/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
49f58d10
JB		 9177 {
9178 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
6772dd07 9179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9180 },
f75eb1c0 9181/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
49f58d10
JB		 9182 {
9183 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
6772dd07 9184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9185 },
9186/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
9187 {
9188 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
6772dd07 9189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9190 },
9191/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
9192 {
9193 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
6772dd07 9194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9195 },
9196/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
9197 {
9198 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
6772dd07 9199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9200 },
9201/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
9202 {
9203 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24,
6772dd07 9204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9205 },
9206/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
9207 {
9208 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
6772dd07 9209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9210 },
9211/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
9212 {
9213 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
6772dd07 9214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9215 },
9216/* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9217 {
9218 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
6772dd07 9219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9220 },
9221/* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9222 {
9223 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
6772dd07 9224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9225 },
9226/* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9227 {
9228 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
6772dd07 9229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9230 },
9231/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9232 {
9233 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
6772dd07 9234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9235 },
9236/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9237 {
9238 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
6772dd07 9239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9240 },
9241/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9242 {
9243 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
6772dd07 9244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9245 },
9246/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9247 {
9248 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
6772dd07 9249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9250 },
9251/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9252 {
9253 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
6772dd07 9254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9255 },
9256/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9257 {
9258 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
6772dd07 9259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9260 },
9261/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9262 {
9263 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
6772dd07 9264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9265 },
9266/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9267 {
9268 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
6772dd07 9269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9270 },
9271/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9272 {
9273 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
6772dd07 9274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9275 },
9276/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9277 {
9278 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
6772dd07 9279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9280 },
9281/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9282 {
9283 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
6772dd07 9284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9285 },
9286/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9287 {
9288 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
6772dd07 9289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9290 },
9291/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9292 {
9293 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
6772dd07 9294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9295 },
9296/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9297 {
9298 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
6772dd07 9299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9300 },
9301/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9302 {
9303 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
6772dd07 9304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9305 },
9306/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9307 {
9308 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
6772dd07 9309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9310 },
9311/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9312 {
9313 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
6772dd07 9314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9315 },
9316/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9317 {
9318 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
6772dd07 9319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9320 },
9321/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
9322 {
9323 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
6772dd07 9324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9325 },
9326/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
9327 {
9328 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
6772dd07 9329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9330 },
9331/* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
9332 {
9333 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32,
6772dd07 9334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9335 },
9336/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
9337 {
9338 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32,
6772dd07 9339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9340 },
9341/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
9342 {
9343 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32,
6772dd07 9344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9345 },
9346/* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
9347 {
9348 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32,
6772dd07 9349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9350 },
9351/* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9352 {
9353 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
6772dd07 9354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9355 },
9356/* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9357 {
9358 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
6772dd07 9359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9360 },
9361/* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
9362 {
9363 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32,
6772dd07 9364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9365 },
9366/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9367 {
9368 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
6772dd07 9369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9370 },
9371/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9372 {
9373 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
6772dd07 9374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9375 },
9376/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9377 {
9378 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
6772dd07 9379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9380 },
9381/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9382 {
9383 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
6772dd07 9384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9385 },
9386/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9387 {
9388 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
6772dd07 9389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9390 },
9391/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9392 {
9393 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
6772dd07 9394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9395 },
9396/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9397 {
9398 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
6772dd07 9399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9400 },
9401/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9402 {
9403 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
6772dd07 9404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9405 },
9406/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9407 {
9408 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
6772dd07 9409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9410 },
9411/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9412 {
9413 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
6772dd07 9414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9415 },
9416/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9417 {
9418 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
6772dd07 9419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9420 },
9421/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9422 {
9423 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
6772dd07 9424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9425 },
9426/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9427 {
9428 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
6772dd07 9429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9430 },
9431/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9432 {
9433 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
6772dd07 9434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9435 },
9436/* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9437 {
9438 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
6772dd07 9439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9440 },
9441/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9442 {
9443 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
6772dd07 9444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9445 },
9446/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9447 {
9448 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
6772dd07 9449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9450 },
9451/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
9452 {
9453 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48,
6772dd07 9454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9455 },
9456/* tst.w${X} $Src16RnHI,$Dst16RnHI */
9457 {
9458 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
6772dd07 9459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9460 },
9461/* tst.w${X} $Src16AnHI,$Dst16RnHI */
9462 {
9463 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
6772dd07 9464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9465 },
9466/* tst.w${X} [$Src16An],$Dst16RnHI */
9467 {
9468 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16,
6772dd07 9469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9470 },
9471/* tst.w${X} $Src16RnHI,$Dst16AnHI */
9472 {
9473 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16,
6772dd07 9474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9475 },
9476/* tst.w${X} $Src16AnHI,$Dst16AnHI */
9477 {
9478 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16,
6772dd07 9479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9480 },
9481/* tst.w${X} [$Src16An],$Dst16AnHI */
9482 {
9483 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16,
6772dd07 9484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9485 },
9486/* tst.w${X} $Src16RnHI,[$Dst16An] */
9487 {
9488 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
6772dd07 9489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9490 },
9491/* tst.w${X} $Src16AnHI,[$Dst16An] */
9492 {
9493 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
6772dd07 9494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9495 },
9496/* tst.w${X} [$Src16An],[$Dst16An] */
9497 {
9498 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16,
6772dd07 9499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9500 },
9501/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
9502 {
9503 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
6772dd07 9504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9505 },
9506/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
9507 {
9508 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
6772dd07 9509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9510 },
9511/* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9512 {
9513 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
6772dd07 9514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9515 },
9516/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
9517 {
9518 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
6772dd07 9519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9520 },
9521/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
9522 {
9523 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
6772dd07 9524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9525 },
9526/* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9527 {
9528 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
6772dd07 9529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9530 },
9531/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
9532 {
9533 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
6772dd07 9534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9535 },
9536/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
9537 {
9538 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
6772dd07 9539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9540 },
9541/* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
9542 {
9543 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
6772dd07 9544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9545 },
9546/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
9547 {
9548 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
6772dd07 9549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9550 },
9551/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
9552 {
9553 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
6772dd07 9554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9555 },
9556/* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
9557 {
9558 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
6772dd07 9559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9560 },
9561/* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
9562 {
9563 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
6772dd07 9564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9565 },
9566/* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
9567 {
9568 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
6772dd07 9569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9570 },
9571/* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
9572 {
9573 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
6772dd07 9574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9575 },
9576/* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
9577 {
9578 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
6772dd07 9579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9580 },
9581/* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
9582 {
9583 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
6772dd07 9584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9585 },
9586/* tst.w${X} [$Src16An],${Dsp-16-u16} */
9587 {
9588 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32,
6772dd07 9589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9590 },
9591/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
9592 {
9593 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
6772dd07 9594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9595 },
9596/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
9597 {
9598 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
6772dd07 9599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9600 },
9601/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
9602 {
9603 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
6772dd07 9604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9605 },
9606/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
9607 {
9608 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24,
6772dd07 9609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9610 },
9611/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
9612 {
9613 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
6772dd07 9614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9615 },
9616/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
9617 {
9618 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
6772dd07 9619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9620 },
9621/* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9622 {
9623 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
6772dd07 9624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9625 },
9626/* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9627 {
9628 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
6772dd07 9629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9630 },
9631/* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9632 {
9633 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
6772dd07 9634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9635 },
9636/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9637 {
9638 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
6772dd07 9639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9640 },
9641/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9642 {
9643 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
6772dd07 9644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9645 },
9646/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9647 {
9648 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
6772dd07 9649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9650 },
9651/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9652 {
9653 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
6772dd07 9654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9655 },
9656/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9657 {
9658 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
6772dd07 9659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9660 },
9661/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9662 {
9663 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
6772dd07 9664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9665 },
9666/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9667 {
9668 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
6772dd07 9669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9670 },
9671/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9672 {
9673 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
6772dd07 9674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9675 },
9676/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9677 {
9678 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
6772dd07 9679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9680 },
9681/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9682 {
9683 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
6772dd07 9684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9685 },
9686/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9687 {
9688 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
6772dd07 9689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9690 },
9691/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9692 {
9693 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
6772dd07 9694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9695 },
9696/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9697 {
9698 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
6772dd07 9699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9700 },
9701/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9702 {
9703 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
6772dd07 9704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9705 },
9706/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9707 {
9708 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
6772dd07 9709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9710 },
9711/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9712 {
9713 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
6772dd07 9714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9715 },
9716/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9717 {
9718 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
6772dd07 9719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9720 },
9721/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9722 {
9723 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
6772dd07 9724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9725 },
9726/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
9727 {
9728 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
6772dd07 9729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9730 },
9731/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
9732 {
9733 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
6772dd07 9734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9735 },
9736/* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
9737 {
9738 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32,
6772dd07 9739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9740 },
9741/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
9742 {
9743 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32,
6772dd07 9744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9745 },
9746/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
9747 {
9748 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32,
6772dd07 9749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9750 },
9751/* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
9752 {
9753 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32,
6772dd07 9754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9755 },
9756/* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9757 {
9758 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
6772dd07 9759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9760 },
9761/* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9762 {
9763 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
6772dd07 9764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9765 },
9766/* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
9767 {
9768 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32,
6772dd07 9769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9770 },
9771/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9772 {
9773 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
6772dd07 9774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9775 },
9776/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9777 {
9778 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
6772dd07 9779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9780 },
9781/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9782 {
9783 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
6772dd07 9784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9785 },
9786/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9787 {
9788 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
6772dd07 9789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9790 },
9791/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9792 {
9793 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
6772dd07 9794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9795 },
9796/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9797 {
9798 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
6772dd07 9799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9800 },
9801/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9802 {
9803 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
6772dd07 9804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9805 },
9806/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9807 {
9808 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
6772dd07 9809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9810 },
9811/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9812 {
9813 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
6772dd07 9814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9815 },
9816/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9817 {
9818 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
6772dd07 9819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9820 },
9821/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9822 {
9823 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
6772dd07 9824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9825 },
9826/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9827 {
9828 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
6772dd07 9829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9830 },
9831/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9832 {
9833 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
6772dd07 9834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9835 },
9836/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9837 {
9838 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
6772dd07 9839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9840 },
9841/* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9842 {
9843 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
6772dd07 9844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9845 },
9846/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9847 {
9848 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
6772dd07 9849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9850 },
9851/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9852 {
9853 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
6772dd07 9854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9855 },
9856/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
9857 {
9858 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48,
6772dd07 9859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9860 },
9861/* tst.b${X} $Src16RnQI,$Dst16RnQI */
9862 {
9863 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
6772dd07 9864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9865 },
9866/* tst.b${X} $Src16AnQI,$Dst16RnQI */
9867 {
9868 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
6772dd07 9869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9870 },
9871/* tst.b${X} [$Src16An],$Dst16RnQI */
9872 {
9873 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16,
6772dd07 9874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9875 },
9876/* tst.b${X} $Src16RnQI,$Dst16AnQI */
9877 {
9878 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16,
6772dd07 9879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9880 },
9881/* tst.b${X} $Src16AnQI,$Dst16AnQI */
9882 {
9883 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16,
6772dd07 9884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9885 },
9886/* tst.b${X} [$Src16An],$Dst16AnQI */
9887 {
9888 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16,
6772dd07 9889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9890 },
9891/* tst.b${X} $Src16RnQI,[$Dst16An] */
9892 {
9893 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
6772dd07 9894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9895 },
9896/* tst.b${X} $Src16AnQI,[$Dst16An] */
9897 {
9898 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
6772dd07 9899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9900 },
9901/* tst.b${X} [$Src16An],[$Dst16An] */
9902 {
9903 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16,
6772dd07 9904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9905 },
9906/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
9907 {
9908 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
6772dd07 9909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9910 },
9911/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
9912 {
9913 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
6772dd07 9914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9915 },
9916/* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9917 {
9918 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
6772dd07 9919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9920 },
9921/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
9922 {
9923 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
6772dd07 9924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9925 },
9926/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
9927 {
9928 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
6772dd07 9929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9930 },
9931/* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9932 {
9933 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
6772dd07 9934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9935 },
9936/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
9937 {
9938 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
6772dd07 9939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9940 },
9941/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
9942 {
9943 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
6772dd07 9944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9945 },
9946/* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
9947 {
9948 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
6772dd07 9949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9950 },
9951/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
9952 {
9953 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
6772dd07 9954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9955 },
9956/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
9957 {
9958 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
6772dd07 9959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9960 },
9961/* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
9962 {
9963 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
6772dd07 9964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9965 },
9966/* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
9967 {
9968 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
6772dd07 9969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9970 },
9971/* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
9972 {
9973 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
6772dd07 9974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9975 },
9976/* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
9977 {
9978 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
6772dd07 9979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9980 },
9981/* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
9982 {
9983 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
6772dd07 9984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9985 },
9986/* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
9987 {
9988 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
6772dd07 9989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 9990 },
9991/* tst.b${X} [$Src16An],${Dsp-16-u16} */
9992 {
9993 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32,
6772dd07 9994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10 9995 },
f75eb1c0 9996/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
49f58d10
JB		 9997 {
9998 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32,
6772dd07 9999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10000 },
f75eb1c0 10001/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
49f58d10
JB		 10002 {
10003 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32,
6772dd07 10004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10005 },
f75eb1c0 10006/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
49f58d10
JB		 10007 {
10008 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32,
6772dd07 10009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10010 },
f75eb1c0 10011/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 10012 {
10013 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40,
6772dd07 10014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10015 },
f75eb1c0 10016/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
49f58d10
JB		 10017 {
10018 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40,
6772dd07 10019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10020 },
f75eb1c0 10021/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
49f58d10
JB		 10022 {
10023 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40,
6772dd07 10024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10025 },
f75eb1c0 10026/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 10027 {
10028 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48,
6772dd07 10029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10030 },
f75eb1c0 10031/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
49f58d10
JB		 10032 {
10033 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48,
6772dd07 10034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10035 },
f75eb1c0 10036/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
49f58d10
JB		 10037 {
10038 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48,
6772dd07 10039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10040 },
f75eb1c0 10041/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
49f58d10
JB		 10042 {
10043 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48,
6772dd07 10044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10045 },
f75eb1c0 10046/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 10047 {
10048 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56,
6772dd07 10049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10050 },
f75eb1c0 10051/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
49f58d10
JB		 10052 {
10053 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56,
6772dd07 10054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10055 },
f75eb1c0 10056/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
49f58d10
JB		 10057 {
10058 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24,
6772dd07 10059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10060 },
f75eb1c0 10061/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
49f58d10
JB		 10062 {
10063 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24,
6772dd07 10064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10065 },
f75eb1c0 10066/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
49f58d10
JB		 10067 {
10068 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24,
6772dd07 10069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10070 },
f75eb1c0 10071/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 10072 {
10073 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32,
6772dd07 10074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10075 },
f75eb1c0 10076/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 10077 {
10078 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32,
6772dd07 10079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10080 },
f75eb1c0 10081/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 10082 {
10083 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32,
6772dd07 10084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10085 },
f75eb1c0 10086/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 10087 {
10088 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40,
6772dd07 10089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10090 },
f75eb1c0 10091/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
49f58d10
JB		 10092 {
10093 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40,
6772dd07 10094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10095 },
f75eb1c0 10096/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
49f58d10
JB		 10097 {
10098 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40,
6772dd07 10099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10100 },
f75eb1c0 10101/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 10102 {
10103 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40,
6772dd07 10104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10105 },
f75eb1c0 10106/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 10107 {
10108 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48,
6772dd07 10109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10110 },
f75eb1c0 10111/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
49f58d10
JB		 10112 {
10113 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48,
6772dd07 10114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10115 },
f75eb1c0 10116/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
49f58d10
JB		 10117 {
10118 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32,
6772dd07 10119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10120 },
f75eb1c0 10121/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
49f58d10
JB		 10122 {
10123 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32,
6772dd07 10124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10125 },
f75eb1c0 10126/* tst.w${G} #${Imm-16-HI},[$Dst16An] */
49f58d10
JB		 10127 {
10128 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32,
6772dd07 10129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10130 },
f75eb1c0 10131/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 10132 {
10133 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40,
6772dd07 10134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10135 },
f75eb1c0 10136/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
49f58d10
JB		 10137 {
10138 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40,
6772dd07 10139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10140 },
f75eb1c0 10141/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
49f58d10
JB		 10142 {
10143 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40,
6772dd07 10144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10145 },
f75eb1c0 10146/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 10147 {
10148 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48,
6772dd07 10149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10150 },
f75eb1c0 10151/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
49f58d10
JB		 10152 {
10153 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48,
6772dd07 10154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10155 },
f75eb1c0 10156/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
49f58d10
JB		 10157 {
10158 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48,
6772dd07 10159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10160 },
f75eb1c0 10161/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
49f58d10
JB		 10162 {
10163 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24,
6772dd07 10164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10165 },
f75eb1c0 10166/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
49f58d10
JB		 10167 {
10168 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24,
6772dd07 10169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10170 },
f75eb1c0 10171/* tst.b${G} #${Imm-16-QI},[$Dst16An] */
49f58d10
JB		 10172 {
10173 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24,
6772dd07 10174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10175 },
f75eb1c0 10176/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 10177 {
10178 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32,
6772dd07 10179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10180 },
f75eb1c0 10181/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 10182 {
10183 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32,
6772dd07 10184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10185 },
f75eb1c0 10186/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 10187 {
10188 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32,
6772dd07 10189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10190 },
f75eb1c0 10191/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 10192 {
10193 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40,
6772dd07 10194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10195 },
f75eb1c0 10196/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
49f58d10
JB		 10197 {
10198 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40,
6772dd07 10199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 10200 },
f75eb1c0 10201/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 10202 {
10203 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40,
6772dd07 10204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10205 },
10206/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10207 {
10208 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
6772dd07 10209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10210 },
10211/* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
10212 {
10213 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
6772dd07 10214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10215 },
10216/* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
10217 {
10218 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
6772dd07 10219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10220 },
10221/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10222 {
10223 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
6772dd07 10224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10225 },
10226/* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
10227 {
10228 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
6772dd07 10229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10230 },
10231/* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
10232 {
10233 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
6772dd07 10234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10235 },
10236/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10237 {
10238 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
6772dd07 10239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10240 },
10241/* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10242 {
10243 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
6772dd07 10244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10245 },
10246/* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10247 {
10248 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
6772dd07 10249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10250 },
10251/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10252 {
10253 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
6772dd07 10254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10255 },
10256/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10257 {
10258 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
6772dd07 10259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10260 },
10261/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10262 {
10263 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
6772dd07 10264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10265 },
10266/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10267 {
10268 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10270 },
10271/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10272 {
10273 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10275 },
10276/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10277 {
10278 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10280 },
10281/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10282 {
10283 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10285 },
10286/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10287 {
10288 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10290 },
10291/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10292 {
10293 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10295 },
10296/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10297 {
10298 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10300 },
10301/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10302 {
10303 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10305 },
10306/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10307 {
10308 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10310 },
10311/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10312 {
10313 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10315 },
10316/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10317 {
10318 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10320 },
10321/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10322 {
10323 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10325 },
10326/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10327 {
10328 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10330 },
10331/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10332 {
10333 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10335 },
10336/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10337 {
10338 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10340 },
10341/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10342 {
10343 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10345 },
10346/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10347 {
10348 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10350 },
10351/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10352 {
10353 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10355 },
10356/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10357 {
10358 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
6772dd07 10359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10360 },
10361/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10362 {
10363 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
6772dd07 10364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10365 },
10366/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10367 {
10368 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
6772dd07 10369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10370 },
10371/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10372 {
10373 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10375 },
10376/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10377 {
10378 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10380 },
10381/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10382 {
10383 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10385 },
10386/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10387 {
10388 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
6772dd07 10389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10390 },
10391/* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
10392 {
10393 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
6772dd07 10394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10395 },
10396/* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
10397 {
10398 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
6772dd07 10399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10400 },
10401/* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
10402 {
10403 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
6772dd07 10404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10405 },
10406/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10407 {
10408 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
6772dd07 10409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10410 },
10411/* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
10412 {
10413 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
6772dd07 10414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10415 },
10416/* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
10417 {
10418 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
6772dd07 10419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10420 },
10421/* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
10422 {
10423 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
6772dd07 10424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10425 },
10426/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10427 {
10428 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
6772dd07 10429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10430 },
10431/* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10432 {
10433 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
6772dd07 10434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10435 },
10436/* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10437 {
10438 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
6772dd07 10439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10440 },
10441/* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10442 {
10443 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
6772dd07 10444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10445 },
10446/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10447 {
10448 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10450 },
10451/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10452 {
10453 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10455 },
10456/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10457 {
10458 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10460 },
10461/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10462 {
10463 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10465 },
10466/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10467 {
10468 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10470 },
10471/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10472 {
10473 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10475 },
10476/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10477 {
10478 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10480 },
10481/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10482 {
10483 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10485 },
10486/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10487 {
10488 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
6772dd07 10489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10490 },
10491/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10492 {
10493 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
6772dd07 10494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10495 },
10496/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10497 {
10498 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
6772dd07 10499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10500 },
10501/* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10502 {
10503 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
6772dd07 10504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10505 },
10506/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10507 {
10508 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10510 },
10511/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10512 {
10513 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10515 },
10516/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10517 {
10518 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10520 },
10521/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10522 {
10523 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10525 },
10526/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10527 {
10528 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10530 },
10531/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10532 {
10533 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10535 },
10536/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10537 {
10538 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10540 },
10541/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10542 {
10543 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10545 },
10546/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10547 {
10548 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10550 },
10551/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10552 {
10553 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10555 },
10556/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10557 {
10558 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10560 },
10561/* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10562 {
10563 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10565 },
10566/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10567 {
10568 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10570 },
10571/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10572 {
10573 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10575 },
10576/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10577 {
10578 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10580 },
10581/* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10582 {
10583 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10585 },
10586/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10587 {
10588 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10590 },
10591/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10592 {
10593 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10595 },
10596/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10597 {
10598 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10600 },
10601/* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
10602 {
10603 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10605 },
10606/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10607 {
10608 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
6772dd07 10609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10610 },
10611/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10612 {
10613 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
6772dd07 10614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10615 },
10616/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10617 {
10618 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
6772dd07 10619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10620 },
10621/* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
10622 {
10623 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
6772dd07 10624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10625 },
10626/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10627 {
10628 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
6772dd07 10629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10630 },
10631/* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
10632 {
10633 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
6772dd07 10634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10635 },
10636/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10637 {
10638 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
6772dd07 10639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10640 },
10641/* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
10642 {
10643 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
6772dd07 10644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10645 },
10646/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10647 {
10648 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
6772dd07 10649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10650 },
10651/* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10652 {
10653 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
6772dd07 10654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10655 },
10656/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10657 {
10658 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10660 },
10661/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10662 {
10663 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10665 },
10666/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10667 {
10668 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
6772dd07 10669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10670 },
10671/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10672 {
10673 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
6772dd07 10674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10675 },
10676/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10677 {
10678 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
6772dd07 10679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10680 },
10681/* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10682 {
10683 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
6772dd07 10684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10685 },
10686/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10687 {
10688 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10690 },
10691/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10692 {
10693 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10695 },
10696/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10697 {
10698 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
6772dd07 10699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10700 },
10701/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10702 {
10703 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
6772dd07 10704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10705 },
10706/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10707 {
10708 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10710 },
10711/* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10712 {
10713 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
6772dd07 10714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10715 },
10716/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10717 {
10718 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
6772dd07 10719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10720 },
10721/* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10722 {
10723 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
6772dd07 10724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10725 },
10726/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10727 {
10728 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
6772dd07 10729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10730 },
10731/* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
10732 {
10733 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
6772dd07 10734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10735 },
10736/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10737 {
10738 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
6772dd07 10739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10740 },
10741/* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
10742 {
10743 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
6772dd07 10744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10745 },
10746/* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
10747 {
10748 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
6772dd07 10749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10750 },
10751/* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
10752 {
10753 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
6772dd07 10754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10755 },
10756/* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10757 {
10758 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
6772dd07 10759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10760 },
10761/* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
10762 {
10763 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
6772dd07 10764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10765 },
10766/* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
10767 {
10768 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
6772dd07 10769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10770 },
10771/* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10772 {
10773 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
6772dd07 10774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10775 },
10776/* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
10777 {
10778 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
6772dd07 10779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10780 },
10781/* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
10782 {
10783 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
6772dd07 10784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10785 },
10786/* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10787 {
10788 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
6772dd07 10789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10790 },
10791/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10792 {
10793 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
6772dd07 10794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10795 },
10796/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10797 {
10798 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
6772dd07 10799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10800 },
10801/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10802 {
10803 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
6772dd07 10804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10805 },
10806/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10807 {
10808 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
6772dd07 10809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10810 },
10811/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10812 {
10813 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
6772dd07 10814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10815 },
10816/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10817 {
10818 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
6772dd07 10819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10820 },
10821/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10822 {
10823 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10825 },
10826/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10827 {
10828 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10830 },
10831/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10832 {
10833 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10835 },
10836/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
10837 {
10838 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
6772dd07 10839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10840 },
10841/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
10842 {
10843 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
6772dd07 10844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10845 },
10846/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10847 {
10848 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
6772dd07 10849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10850 },
10851/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
10852 {
10853 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10855 },
10856/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
10857 {
10858 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10860 },
10861/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10862 {
10863 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10865 },
10866/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
10867 {
10868 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
6772dd07 10869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10870 },
10871/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
10872 {
10873 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
6772dd07 10874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10875 },
10876/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10877 {
10878 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
6772dd07 10879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10880 },
10881/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
10882 {
10883 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10885 },
10886/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
10887 {
10888 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10890 },
10891/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10892 {
10893 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10895 },
10896/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
10897 {
10898 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
6772dd07 10899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10900 },
10901/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
10902 {
10903 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
6772dd07 10904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10905 },
10906/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10907 {
10908 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
6772dd07 10909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10910 },
10911/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
10912 {
10913 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
6772dd07 10914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10915 },
10916/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
10917 {
10918 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
6772dd07 10919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10920 },
10921/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10922 {
10923 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
6772dd07 10924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 10925 },
10926/* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
10927 {
10928 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
6772dd07 10929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10930 },
10931/* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
10932 {
10933 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24,
6772dd07 10934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10935 },
10936/* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10937 {
10938 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24,
6772dd07 10939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10940 },
10941/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10942 {
10943 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32,
6772dd07 10944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10945 },
10946/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10947 {
10948 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10950 },
10951/* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10952 {
10953 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32,
6772dd07 10954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10955 },
10956/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10957 {
10958 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40,
6772dd07 10959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10960 },
10961/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10962 {
10963 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10965 },
10966/* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10967 {
10968 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40,
6772dd07 10969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10970 },
10971/* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
10972 {
10973 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40,
6772dd07 10974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10975 },
10976/* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10977 {
10978 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48,
6772dd07 10979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10980 },
10981/* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
10982 {
10983 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48,
6772dd07 10984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 10985 },
10986/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
10987 {
10988 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48,
6772dd07 10989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 10990 },
10991/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
10992 {
10993 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48,
6772dd07 10994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 10995 },
10996/* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
10997 {
10998 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48,
6772dd07 10999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11000 },
11001/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11002 {
11003 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56,
6772dd07 11004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11005 },
11006/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
11007 {
11008 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56,
6772dd07 11009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11010 },
11011/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
11012 {
11013 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56,
6772dd07 11014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11015 },
11016/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11017 {
11018 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64,
6772dd07 11019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11020 },
11021/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
11022 {
11023 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64,
6772dd07 11024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11025 },
11026/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
11027 {
11028 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64,
6772dd07 11029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11030 },
11031/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
11032 {
11033 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64,
6772dd07 11034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11035 },
11036/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11037 {
11038 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72,
6772dd07 11039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11040 },
11041/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
11042 {
11043 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72,
6772dd07 11044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11045 },
11046/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
11047 {
11048 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32,
6772dd07 11049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11050 },
11051/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
11052 {
11053 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32,
6772dd07 11054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11055 },
11056/* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
11057 {
11058 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32,
6772dd07 11059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11060 },
11061/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11062 {
11063 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40,
6772dd07 11064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11065 },
11066/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
11067 {
11068 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40,
6772dd07 11069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11070 },
11071/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
11072 {
11073 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40,
6772dd07 11074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11075 },
11076/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11077 {
11078 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48,
6772dd07 11079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11080 },
11081/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
11082 {
11083 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48,
6772dd07 11084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11085 },
11086/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
11087 {
11088 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48,
6772dd07 11089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11090 },
11091/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
11092 {
11093 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48,
6772dd07 11094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11095 },
11096/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11097 {
11098 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56,
6772dd07 11099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11100 },
11101/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
11102 {
11103 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56,
6772dd07 11104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11105 },
11106/* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11107 {
11108 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32,
6772dd07 11109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11110 },
11111/* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11112 {
11113 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32,
6772dd07 11114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11115 },
11116/* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11117 {
11118 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32,
6772dd07 11119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11120 },
11121/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11122 {
11123 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40,
6772dd07 11124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11125 },
11126/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11127 {
11128 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40,
6772dd07 11129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11130 },
11131/* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11132 {
11133 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40,
6772dd07 11134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11135 },
11136/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11137 {
11138 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48,
6772dd07 11139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11140 },
11141/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11142 {
11143 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48,
6772dd07 11144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11145 },
11146/* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11147 {
11148 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48,
6772dd07 11149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11150 },
11151/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11152 {
11153 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48,
6772dd07 11154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11155 },
11156/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11157 {
11158 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56,
6772dd07 11159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11160 },
11161/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11162 {
11163 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56,
6772dd07 11164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11165 },
11166/* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11167 {
11168 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24,
6772dd07 11169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11170 },
11171/* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11172 {
11173 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24,
6772dd07 11174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11175 },
11176/* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11177 {
11178 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24,
6772dd07 11179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11180 },
11181/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11182 {
11183 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32,
6772dd07 11184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11185 },
11186/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11187 {
11188 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32,
6772dd07 11189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11190 },
11191/* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11192 {
11193 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32,
6772dd07 11194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11195 },
11196/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11197 {
11198 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40,
6772dd07 11199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11200 },
11201/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11202 {
11203 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40,
6772dd07 11204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11205 },
11206/* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11207 {
11208 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40,
6772dd07 11209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11210 },
11211/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11212 {
11213 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40,
6772dd07 11214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11215 },
11216/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11217 {
11218 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48,
6772dd07 11219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11220 },
11221/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11222 {
11223 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48,
6772dd07 11224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11225 },
11226/* stz${S} #${Imm-8-QI},r0l */
11227 {
11228 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16,
6772dd07 11229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11230 },
11231/* stz${S} #${Imm-8-QI},r0h */
11232 {
11233 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16,
6772dd07 11234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11235 },
11236/* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11237 {
11238 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24,
6772dd07 11239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11240 },
11241/* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11242 {
11243 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24,
6772dd07 11244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11245 },
11246/* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
11247 {
11248 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32,
6772dd07 11249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11250 },
11251/* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11252 {
11253 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32,
6772dd07 11254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11255 },
11256/* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11257 {
11258 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32,
6772dd07 11259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11260 },
11261/* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11262 {
11263 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32,
6772dd07 11264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11265 },
11266/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11267 {
11268 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40,
6772dd07 11269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11270 },
11271/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11272 {
11273 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40,
6772dd07 11274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11275 },
11276/* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11277 {
11278 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40,
6772dd07 11279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11280 },
11281/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11282 {
11283 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48,
6772dd07 11284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11285 },
11286/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11287 {
11288 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48,
6772dd07 11289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11290 },
11291/* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11292 {
11293 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48,
6772dd07 11294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11295 },
11296/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11297 {
11298 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48,
6772dd07 11299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11300 },
11301/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11302 {
11303 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56,
6772dd07 11304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11305 },
11306/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11307 {
11308 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56,
6772dd07 11309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11310 },
11311/* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11312 {
11313 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24,
6772dd07 11314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11315 },
11316/* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11317 {
11318 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24,
6772dd07 11319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11320 },
11321/* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11322 {
11323 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24,
6772dd07 11324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11325 },
11326/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11327 {
11328 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32,
6772dd07 11329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11330 },
11331/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11332 {
11333 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32,
6772dd07 11334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11335 },
11336/* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11337 {
11338 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32,
6772dd07 11339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11340 },
11341/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11342 {
11343 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40,
6772dd07 11344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11345 },
11346/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11347 {
11348 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40,
6772dd07 11349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11350 },
11351/* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11352 {
11353 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40,
6772dd07 11354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11355 },
11356/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11357 {
11358 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40,
6772dd07 11359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11360 },
11361/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11362 {
11363 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48,
6772dd07 11364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11365 },
11366/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11367 {
11368 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48,
6772dd07 11369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11370 },
11371/* stnz${S} #${Imm-8-QI},r0l */
11372 {
11373 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16,
6772dd07 11374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11375 },
11376/* stnz${S} #${Imm-8-QI},r0h */
11377 {
11378 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16,
6772dd07 11379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11380 },
11381/* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11382 {
11383 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24,
6772dd07 11384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11385 },
11386/* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11387 {
11388 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24,
6772dd07 11389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11390 },
11391/* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
11392 {
11393 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32,
6772dd07 11394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11395 },
11396/* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11397 {
11398 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24,
6772dd07 11399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11400 },
11401/* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11402 {
11403 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24,
6772dd07 11404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11405 },
11406/* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11407 {
11408 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24,
6772dd07 11409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11410 },
11411/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11412 {
11413 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32,
6772dd07 11414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11415 },
11416/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11417 {
11418 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32,
6772dd07 11419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11420 },
11421/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11422 {
11423 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32,
6772dd07 11424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11425 },
11426/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11427 {
11428 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40,
6772dd07 11429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11430 },
11431/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11432 {
11433 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40,
6772dd07 11434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11435 },
11436/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11437 {
11438 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40,
6772dd07 11439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11440 },
11441/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11442 {
11443 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40,
6772dd07 11444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11445 },
11446/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11447 {
11448 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48,
6772dd07 11449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11450 },
11451/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11452 {
11453 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48,
6772dd07 11454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11455 },
11456/* shl.l r1h,$Dst32RnUnprefixedSI */
11457 {
11458 M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16,
6772dd07 11459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11460 },
11461/* shl.l r1h,$Dst32AnUnprefixedSI */
11462 {
11463 M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16,
6772dd07 11464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11465 },
11466/* shl.l r1h,[$Dst32AnUnprefixed] */
11467 {
11468 M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16,
6772dd07 11469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11470 },
11471/* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11472 {
11473 M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24,
6772dd07 11474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11475 },
11476/* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11477 {
11478 M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32,
6772dd07 11479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11480 },
11481/* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11482 {
11483 M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40,
6772dd07 11484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11485 },
11486/* shl.l r1h,${Dsp-16-u8}[sb] */
11487 {
11488 M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24,
6772dd07 11489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11490 },
11491/* shl.l r1h,${Dsp-16-u16}[sb] */
11492 {
11493 M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32,
6772dd07 11494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11495 },
11496/* shl.l r1h,${Dsp-16-s8}[fb] */
11497 {
11498 M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24,
6772dd07 11499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11500 },
11501/* shl.l r1h,${Dsp-16-s16}[fb] */
11502 {
11503 M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32,
6772dd07 11504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11505 },
11506/* shl.l r1h,${Dsp-16-u16} */
11507 {
11508 M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32,
6772dd07 11509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11510 },
11511/* shl.l r1h,${Dsp-16-u24} */
11512 {
11513 M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40,
6772dd07 11514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11515 },
11516/* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11517 {
11518 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24,
6772dd07 11519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11520 },
11521/* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11522 {
11523 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24,
6772dd07 11524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11525 },
11526/* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11527 {
11528 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24,
6772dd07 11529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11530 },
11531/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11532 {
11533 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32,
6772dd07 11534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11535 },
11536/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11537 {
11538 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32,
6772dd07 11539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11540 },
11541/* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11542 {
11543 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32,
6772dd07 11544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11545 },
11546/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11547 {
11548 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40,
6772dd07 11549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11550 },
11551/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11552 {
11553 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40,
6772dd07 11554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11555 },
11556/* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11557 {
11558 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40,
6772dd07 11559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11560 },
11561/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11562 {
11563 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40,
6772dd07 11564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11565 },
11566/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11567 {
11568 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48,
6772dd07 11569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11570 },
11571/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11572 {
11573 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48,
6772dd07 11574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11575 },
11576/* shl.w r1h,$Dst32RnUnprefixedHI */
11577 {
11578 M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
6772dd07 11579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11580 },
11581/* shl.w r1h,$Dst32AnUnprefixedHI */
11582 {
11583 M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
6772dd07 11584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11585 },
11586/* shl.w r1h,[$Dst32AnUnprefixed] */
11587 {
11588 M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
6772dd07 11589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11590 },
11591/* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11592 {
11593 M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
6772dd07 11594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11595 },
11596/* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11597 {
11598 M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
6772dd07 11599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11600 },
11601/* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11602 {
11603 M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
6772dd07 11604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11605 },
11606/* shl.w r1h,${Dsp-16-u8}[sb] */
11607 {
11608 M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
6772dd07 11609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11610 },
11611/* shl.w r1h,${Dsp-16-u16}[sb] */
11612 {
11613 M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
6772dd07 11614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11615 },
11616/* shl.w r1h,${Dsp-16-s8}[fb] */
11617 {
11618 M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
6772dd07 11619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11620 },
11621/* shl.w r1h,${Dsp-16-s16}[fb] */
11622 {
11623 M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
6772dd07 11624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11625 },
11626/* shl.w r1h,${Dsp-16-u16} */
11627 {
11628 M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
6772dd07 11629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11630 },
11631/* shl.w r1h,${Dsp-16-u24} */
11632 {
11633 M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
6772dd07 11634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11635 },
11636/* shl.b r1h,$Dst32RnUnprefixedQI */
11637 {
11638 M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
6772dd07 11639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11640 },
11641/* shl.b r1h,$Dst32AnUnprefixedQI */
11642 {
11643 M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
6772dd07 11644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11645 },
11646/* shl.b r1h,[$Dst32AnUnprefixed] */
11647 {
11648 M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
6772dd07 11649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11650 },
11651/* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11652 {
11653 M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
6772dd07 11654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11655 },
11656/* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11657 {
11658 M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
6772dd07 11659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11660 },
11661/* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11662 {
11663 M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
6772dd07 11664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11665 },
11666/* shl.b r1h,${Dsp-16-u8}[sb] */
11667 {
11668 M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
6772dd07 11669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11670 },
11671/* shl.b r1h,${Dsp-16-u16}[sb] */
11672 {
11673 M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
6772dd07 11674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11675 },
11676/* shl.b r1h,${Dsp-16-s8}[fb] */
11677 {
11678 M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
6772dd07 11679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11680 },
11681/* shl.b r1h,${Dsp-16-s16}[fb] */
11682 {
11683 M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
6772dd07 11684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11685 },
11686/* shl.b r1h,${Dsp-16-u16} */
11687 {
11688 M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
6772dd07 11689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11690 },
11691/* shl.b r1h,${Dsp-16-u24} */
11692 {
11693 M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
6772dd07 11694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11695 },
11696/* shl.w r1h,$Dst16RnHI */
11697 {
11698 M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16,
6772dd07 11699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11700 },
11701/* shl.w r1h,$Dst16AnHI */
11702 {
11703 M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16,
6772dd07 11704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11705 },
11706/* shl.w r1h,[$Dst16An] */
11707 {
11708 M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16,
6772dd07 11709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11710 },
11711/* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
11712 {
11713 M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24,
6772dd07 11714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11715 },
11716/* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
11717 {
11718 M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32,
6772dd07 11719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11720 },
11721/* shl.w r1h,${Dsp-16-u8}[sb] */
11722 {
11723 M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24,
6772dd07 11724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11725 },
11726/* shl.w r1h,${Dsp-16-u16}[sb] */
11727 {
11728 M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32,
6772dd07 11729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11730 },
11731/* shl.w r1h,${Dsp-16-s8}[fb] */
11732 {
11733 M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24,
6772dd07 11734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11735 },
11736/* shl.w r1h,${Dsp-16-u16} */
11737 {
11738 M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32,
6772dd07 11739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11740 },
11741/* shl.b r1h,$Dst16RnQI */
11742 {
11743 M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16,
6772dd07 11744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11745 },
11746/* shl.b r1h,$Dst16AnQI */
11747 {
11748 M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16,
6772dd07 11749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11750 },
11751/* shl.b r1h,[$Dst16An] */
11752 {
11753 M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16,
6772dd07 11754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11755 },
11756/* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
11757 {
11758 M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24,
6772dd07 11759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11760 },
11761/* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
11762 {
11763 M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32,
6772dd07 11764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11765 },
11766/* shl.b r1h,${Dsp-16-u8}[sb] */
11767 {
11768 M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24,
6772dd07 11769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11770 },
11771/* shl.b r1h,${Dsp-16-u16}[sb] */
11772 {
11773 M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32,
6772dd07 11774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11775 },
11776/* shl.b r1h,${Dsp-16-s8}[fb] */
11777 {
11778 M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24,
6772dd07 11779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11780 },
11781/* shl.b r1h,${Dsp-16-u16} */
11782 {
11783 M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32,
6772dd07 11784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 11785 },
11786/* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
11787 {
11788 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
6772dd07 11789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11790 },
11791/* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
11792 {
11793 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
6772dd07 11794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11795 },
11796/* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11797 {
11798 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
6772dd07 11799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11800 },
11801/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11802 {
11803 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
6772dd07 11804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11805 },
11806/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11807 {
11808 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
6772dd07 11809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11810 },
11811/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11812 {
11813 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
6772dd07 11814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11815 },
11816/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11817 {
11818 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
6772dd07 11819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11820 },
11821/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11822 {
11823 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
6772dd07 11824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11825 },
11826/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11827 {
11828 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
6772dd07 11829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11830 },
11831/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11832 {
11833 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
6772dd07 11834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11835 },
11836/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11837 {
11838 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
6772dd07 11839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11840 },
11841/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11842 {
11843 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
6772dd07 11844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11845 },
11846/* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
11847 {
11848 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
6772dd07 11849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11850 },
11851/* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
11852 {
11853 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
6772dd07 11854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11855 },
11856/* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11857 {
11858 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
6772dd07 11859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11860 },
11861/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11862 {
11863 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
6772dd07 11864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11865 },
11866/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11867 {
11868 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
6772dd07 11869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11870 },
11871/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11872 {
11873 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
6772dd07 11874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11875 },
11876/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11877 {
11878 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
6772dd07 11879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11880 },
11881/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11882 {
11883 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
6772dd07 11884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11885 },
11886/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11887 {
11888 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
6772dd07 11889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11890 },
11891/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11892 {
11893 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
6772dd07 11894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11895 },
11896/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11897 {
11898 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
6772dd07 11899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11900 },
11901/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11902 {
11903 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
6772dd07 11904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11905 },
11906/* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
11907 {
11908 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16,
6772dd07 11909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11910 },
11911/* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
11912 {
11913 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16,
6772dd07 11914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11915 },
11916/* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
11917 {
11918 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16,
6772dd07 11919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11920 },
11921/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11922 {
11923 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24,
6772dd07 11924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11925 },
11926/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11927 {
11928 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32,
6772dd07 11929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11930 },
11931/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11932 {
11933 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24,
6772dd07 11934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11935 },
11936/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11937 {
11938 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32,
6772dd07 11939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11940 },
11941/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11942 {
11943 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24,
6772dd07 11944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11945 },
11946/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11947 {
11948 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32,
6772dd07 11949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11950 },
11951/* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
11952 {
11953 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16,
6772dd07 11954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11955 },
11956/* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
11957 {
11958 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16,
6772dd07 11959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11960 },
11961/* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
11962 {
11963 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16,
6772dd07 11964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11965 },
11966/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11967 {
11968 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24,
6772dd07 11969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11970 },
11971/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11972 {
11973 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32,
6772dd07 11974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11975 },
11976/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11977 {
11978 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24,
6772dd07 11979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11980 },
11981/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11982 {
11983 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32,
6772dd07 11984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11985 },
11986/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11987 {
11988 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24,
6772dd07 11989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11990 },
11991/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11992 {
11993 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32,
6772dd07 11994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 11995 },
11996/* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11997 {
11998 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24,
6772dd07 11999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12000 },
12001/* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
12002 {
12003 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24,
6772dd07 12004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12005 },
12006/* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12007 {
12008 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24,
6772dd07 12009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12010 },
12011/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12012 {
12013 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32,
6772dd07 12014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12015 },
12016/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12017 {
12018 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32,
6772dd07 12019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12020 },
12021/* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12022 {
12023 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32,
6772dd07 12024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12025 },
12026/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12027 {
12028 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40,
6772dd07 12029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12030 },
12031/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12032 {
12033 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40,
6772dd07 12034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12035 },
12036/* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12037 {
12038 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40,
6772dd07 12039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12040 },
12041/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12042 {
12043 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40,
6772dd07 12044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12045 },
12046/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12047 {
12048 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48,
6772dd07 12049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12050 },
12051/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12052 {
12053 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48,
6772dd07 12054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12055 },
12056/* sha.l r1h,$Dst32RnUnprefixedSI */
12057 {
12058 M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16,
6772dd07 12059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12060 },
12061/* sha.l r1h,$Dst32AnUnprefixedSI */
12062 {
12063 M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16,
6772dd07 12064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12065 },
12066/* sha.l r1h,[$Dst32AnUnprefixed] */
12067 {
12068 M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16,
6772dd07 12069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12070 },
12071/* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12072 {
12073 M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24,
6772dd07 12074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12075 },
12076/* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12077 {
12078 M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32,
6772dd07 12079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12080 },
12081/* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12082 {
12083 M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40,
6772dd07 12084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12085 },
12086/* sha.l r1h,${Dsp-16-u8}[sb] */
12087 {
12088 M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24,
6772dd07 12089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12090 },
12091/* sha.l r1h,${Dsp-16-u16}[sb] */
12092 {
12093 M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32,
6772dd07 12094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12095 },
12096/* sha.l r1h,${Dsp-16-s8}[fb] */
12097 {
12098 M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24,
6772dd07 12099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12100 },
12101/* sha.l r1h,${Dsp-16-s16}[fb] */
12102 {
12103 M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32,
6772dd07 12104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12105 },
12106/* sha.l r1h,${Dsp-16-u16} */
12107 {
12108 M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32,
6772dd07 12109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12110 },
12111/* sha.l r1h,${Dsp-16-u24} */
12112 {
12113 M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40,
6772dd07 12114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12115 },
12116/* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
12117 {
12118 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24,
6772dd07 12119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12120 },
12121/* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
12122 {
12123 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24,
6772dd07 12124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12125 },
12126/* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12127 {
12128 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24,
6772dd07 12129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12130 },
12131/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12132 {
12133 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32,
6772dd07 12134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12135 },
12136/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12137 {
12138 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32,
6772dd07 12139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12140 },
12141/* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12142 {
12143 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32,
6772dd07 12144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12145 },
12146/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12147 {
12148 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40,
6772dd07 12149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12150 },
12151/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12152 {
12153 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40,
6772dd07 12154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12155 },
12156/* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12157 {
12158 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40,
6772dd07 12159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12160 },
12161/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12162 {
12163 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40,
6772dd07 12164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12165 },
12166/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12167 {
12168 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48,
6772dd07 12169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12170 },
12171/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12172 {
12173 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48,
6772dd07 12174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12175 },
12176/* sha.w r1h,$Dst32RnUnprefixedHI */
12177 {
12178 M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
6772dd07 12179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12180 },
12181/* sha.w r1h,$Dst32AnUnprefixedHI */
12182 {
12183 M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
6772dd07 12184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12185 },
12186/* sha.w r1h,[$Dst32AnUnprefixed] */
12187 {
12188 M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
6772dd07 12189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12190 },
12191/* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12192 {
12193 M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
6772dd07 12194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12195 },
12196/* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12197 {
12198 M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
6772dd07 12199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12200 },
12201/* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12202 {
12203 M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
6772dd07 12204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12205 },
12206/* sha.w r1h,${Dsp-16-u8}[sb] */
12207 {
12208 M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
6772dd07 12209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12210 },
12211/* sha.w r1h,${Dsp-16-u16}[sb] */
12212 {
12213 M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
6772dd07 12214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12215 },
12216/* sha.w r1h,${Dsp-16-s8}[fb] */
12217 {
12218 M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
6772dd07 12219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12220 },
12221/* sha.w r1h,${Dsp-16-s16}[fb] */
12222 {
12223 M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
6772dd07 12224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12225 },
12226/* sha.w r1h,${Dsp-16-u16} */
12227 {
12228 M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
6772dd07 12229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12230 },
12231/* sha.w r1h,${Dsp-16-u24} */
12232 {
12233 M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
6772dd07 12234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12235 },
12236/* sha.b r1h,$Dst32RnUnprefixedQI */
12237 {
12238 M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
6772dd07 12239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12240 },
12241/* sha.b r1h,$Dst32AnUnprefixedQI */
12242 {
12243 M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
6772dd07 12244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12245 },
12246/* sha.b r1h,[$Dst32AnUnprefixed] */
12247 {
12248 M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
6772dd07 12249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12250 },
12251/* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12252 {
12253 M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
6772dd07 12254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12255 },
12256/* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12257 {
12258 M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
6772dd07 12259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12260 },
12261/* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12262 {
12263 M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
6772dd07 12264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12265 },
12266/* sha.b r1h,${Dsp-16-u8}[sb] */
12267 {
12268 M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
6772dd07 12269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12270 },
12271/* sha.b r1h,${Dsp-16-u16}[sb] */
12272 {
12273 M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
6772dd07 12274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12275 },
12276/* sha.b r1h,${Dsp-16-s8}[fb] */
12277 {
12278 M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
6772dd07 12279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12280 },
12281/* sha.b r1h,${Dsp-16-s16}[fb] */
12282 {
12283 M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
6772dd07 12284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12285 },
12286/* sha.b r1h,${Dsp-16-u16} */
12287 {
12288 M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
6772dd07 12289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12290 },
12291/* sha.b r1h,${Dsp-16-u24} */
12292 {
12293 M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
6772dd07 12294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12295 },
12296/* sha.w r1h,$Dst16RnHI */
12297 {
12298 M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16,
6772dd07 12299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12300 },
12301/* sha.w r1h,$Dst16AnHI */
12302 {
12303 M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16,
6772dd07 12304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12305 },
12306/* sha.w r1h,[$Dst16An] */
12307 {
12308 M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16,
6772dd07 12309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12310 },
12311/* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
12312 {
12313 M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24,
6772dd07 12314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12315 },
12316/* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
12317 {
12318 M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32,
6772dd07 12319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12320 },
12321/* sha.w r1h,${Dsp-16-u8}[sb] */
12322 {
12323 M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24,
6772dd07 12324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12325 },
12326/* sha.w r1h,${Dsp-16-u16}[sb] */
12327 {
12328 M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32,
6772dd07 12329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12330 },
12331/* sha.w r1h,${Dsp-16-s8}[fb] */
12332 {
12333 M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24,
6772dd07 12334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12335 },
12336/* sha.w r1h,${Dsp-16-u16} */
12337 {
12338 M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32,
6772dd07 12339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12340 },
12341/* sha.b r1h,$Dst16RnQI */
12342 {
12343 M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16,
6772dd07 12344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12345 },
12346/* sha.b r1h,$Dst16AnQI */
12347 {
12348 M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16,
6772dd07 12349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12350 },
12351/* sha.b r1h,[$Dst16An] */
12352 {
12353 M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16,
6772dd07 12354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12355 },
12356/* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
12357 {
12358 M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24,
6772dd07 12359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12360 },
12361/* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
12362 {
12363 M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32,
6772dd07 12364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12365 },
12366/* sha.b r1h,${Dsp-16-u8}[sb] */
12367 {
12368 M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24,
6772dd07 12369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12370 },
12371/* sha.b r1h,${Dsp-16-u16}[sb] */
12372 {
12373 M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32,
6772dd07 12374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12375 },
12376/* sha.b r1h,${Dsp-16-s8}[fb] */
12377 {
12378 M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24,
6772dd07 12379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12380 },
12381/* sha.b r1h,${Dsp-16-u16} */
12382 {
12383 M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32,
6772dd07 12384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12385 },
12386/* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
12387 {
12388 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
6772dd07 12389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12390 },
12391/* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
12392 {
12393 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
6772dd07 12394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12395 },
12396/* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12397 {
12398 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
6772dd07 12399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12400 },
12401/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12402 {
12403 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
6772dd07 12404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12405 },
12406/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12407 {
12408 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
6772dd07 12409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12410 },
12411/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12412 {
12413 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
6772dd07 12414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12415 },
12416/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12417 {
12418 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
6772dd07 12419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12420 },
12421/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12422 {
12423 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
6772dd07 12424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12425 },
12426/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12427 {
12428 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
6772dd07 12429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12430 },
12431/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12432 {
12433 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
6772dd07 12434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12435 },
12436/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12437 {
12438 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
6772dd07 12439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12440 },
12441/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12442 {
12443 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
6772dd07 12444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12445 },
12446/* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
12447 {
12448 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
6772dd07 12449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12450 },
12451/* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
12452 {
12453 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
6772dd07 12454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12455 },
12456/* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12457 {
12458 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
6772dd07 12459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12460 },
12461/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12462 {
12463 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
6772dd07 12464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12465 },
12466/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12467 {
12468 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
6772dd07 12469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12470 },
12471/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12472 {
12473 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
6772dd07 12474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12475 },
12476/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12477 {
12478 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
6772dd07 12479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12480 },
12481/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12482 {
12483 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
6772dd07 12484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12485 },
12486/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12487 {
12488 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
6772dd07 12489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12490 },
12491/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12492 {
12493 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
6772dd07 12494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12495 },
12496/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12497 {
12498 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
6772dd07 12499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12500 },
12501/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12502 {
12503 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
6772dd07 12504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12505 },
12506/* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
12507 {
12508 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16,
6772dd07 12509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12510 },
12511/* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
12512 {
12513 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16,
6772dd07 12514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12515 },
12516/* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
12517 {
12518 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16,
6772dd07 12519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12520 },
12521/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12522 {
12523 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24,
6772dd07 12524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12525 },
12526/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12527 {
12528 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32,
6772dd07 12529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12530 },
12531/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12532 {
12533 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24,
6772dd07 12534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12535 },
12536/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12537 {
12538 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32,
6772dd07 12539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12540 },
12541/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12542 {
12543 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24,
6772dd07 12544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12545 },
12546/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12547 {
12548 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32,
6772dd07 12549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12550 },
12551/* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
12552 {
12553 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16,
6772dd07 12554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12555 },
12556/* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
12557 {
12558 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16,
6772dd07 12559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12560 },
12561/* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
12562 {
12563 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16,
6772dd07 12564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12565 },
12566/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12567 {
12568 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24,
6772dd07 12569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12570 },
12571/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12572 {
12573 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32,
6772dd07 12574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12575 },
12576/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12577 {
12578 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24,
6772dd07 12579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12580 },
12581/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12582 {
12583 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32,
6772dd07 12584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12585 },
12586/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12587 {
12588 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24,
6772dd07 12589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12590 },
12591/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12592 {
12593 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32,
6772dd07 12594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 12595 },
12596/* sc${sccond32} $Dst32RnUnprefixedHI */
12597 {
12598 M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16,
6772dd07 12599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12600 },
12601/* sc${sccond32} $Dst32AnUnprefixedHI */
12602 {
12603 M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16,
6772dd07 12604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12605 },
12606/* sc${sccond32} [$Dst32AnUnprefixed] */
12607 {
12608 M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16,
6772dd07 12609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12610 },
12611/* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
12612 {
12613 M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24,
6772dd07 12614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12615 },
12616/* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
12617 {
12618 M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32,
6772dd07 12619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12620 },
12621/* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
12622 {
12623 M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40,
6772dd07 12624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12625 },
12626/* sc${sccond32} ${Dsp-16-u8}[sb] */
12627 {
12628 M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24,
6772dd07 12629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12630 },
12631/* sc${sccond32} ${Dsp-16-u16}[sb] */
12632 {
12633 M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32,
6772dd07 12634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12635 },
12636/* sc${sccond32} ${Dsp-16-s8}[fb] */
12637 {
12638 M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24,
6772dd07 12639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12640 },
12641/* sc${sccond32} ${Dsp-16-s16}[fb] */
12642 {
12643 M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32,
6772dd07 12644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12645 },
12646/* sc${sccond32} ${Dsp-16-u16} */
12647 {
12648 M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32,
6772dd07 12649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12650 },
12651/* sc${sccond32} ${Dsp-16-u24} */
12652 {
12653 M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
6772dd07 12654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12655 },
c6552317 12656/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
49f58d10
JB		 12657 {
12658 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
6772dd07 12659 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12660 },
c6552317 12661/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 12662 {
12663 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
6772dd07 12664 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12665 },
c6552317 12666/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 12667 {
12668 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
6772dd07 12669 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12670 },
c6552317 12671/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
49f58d10
JB		 12672 {
12673 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
6772dd07 12674 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12675 },
c6552317 12676/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 12677 {
12678 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
6772dd07 12679 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12680 },
c6552317 12681/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
49f58d10
JB		 12682 {
12683 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
6772dd07 12684 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12685 },
c6552317 12686/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 12687 {
12688 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
6772dd07 12689 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12690 },
c6552317 12691/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
49f58d10
JB		 12692 {
12693 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
6772dd07 12694 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12695 },
c6552317 12696/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
49f58d10
JB		 12697 {
12698 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
6772dd07 12699 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12700 },
c6552317 12701/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
49f58d10
JB		 12702 {
12703 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
6772dd07 12704 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12705 },
c6552317 12706/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
49f58d10
JB		 12707 {
12708 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
6772dd07 12709 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12710 },
c6552317 12711/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
49f58d10
JB		 12712 {
12713 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
6772dd07 12714 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12715 },
c6552317 12716/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
49f58d10
JB		 12717 {
12718 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
6772dd07 12719 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12720 },
c6552317 12721/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 12722 {
12723 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
6772dd07 12724 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12725 },
c6552317 12726/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 12727 {
12728 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
6772dd07 12729 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12730 },
c6552317 12731/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
49f58d10
JB		 12732 {
12733 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
6772dd07 12734 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12735 },
c6552317 12736/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 12737 {
12738 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
6772dd07 12739 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12740 },
c6552317 12741/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
49f58d10
JB		 12742 {
12743 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
6772dd07 12744 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12745 },
c6552317 12746/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 12747 {
12748 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
6772dd07 12749 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12750 },
c6552317 12751/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
49f58d10
JB		 12752 {
12753 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
6772dd07 12754 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12755 },
c6552317 12756/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
49f58d10
JB		 12757 {
12758 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
6772dd07 12759 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12760 },
c6552317 12761/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
49f58d10
JB		 12762 {
12763 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
6772dd07 12764 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12765 },
c6552317 12766/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
49f58d10
JB		 12767 {
12768 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
6772dd07 12769 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12770 },
c6552317 12771/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
49f58d10
JB		 12772 {
12773 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
6772dd07 12774 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12775 },
c6552317 12776/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
49f58d10
JB		 12777 {
12778 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
6772dd07 12779 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12780 },
c6552317 12781/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 12782 {
12783 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
6772dd07 12784 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12785 },
c6552317 12786/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 12787 {
12788 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
6772dd07 12789 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12790 },
c6552317 12791/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
49f58d10
JB		 12792 {
12793 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
6772dd07 12794 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12795 },
c6552317 12796/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 12797 {
12798 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
6772dd07 12799 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12800 },
c6552317 12801/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 12802 {
12803 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
6772dd07 12804 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12805 },
c6552317 12806/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
49f58d10
JB		 12807 {
12808 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
6772dd07 12809 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12810 },
c6552317 12811/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
49f58d10
JB		 12812 {
12813 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
6772dd07 12814 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12815 },
c6552317 12816/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
49f58d10
JB		 12817 {
12818 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
6772dd07 12819 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12820 },
c6552317 12821/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
49f58d10
JB		 12822 {
12823 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
6772dd07 12824 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12825 },
c6552317 12826/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
49f58d10
JB		 12827 {
12828 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
6772dd07 12829 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12830 },
c6552317 12831/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
49f58d10
JB		 12832 {
12833 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
6772dd07 12834 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12835 },
c6552317 12836/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
49f58d10
JB		 12837 {
12838 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
6772dd07 12839 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12840 },
c6552317 12841/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
49f58d10
JB		 12842 {
12843 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
6772dd07 12844 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12845 },
c6552317 12846/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
49f58d10
JB		 12847 {
12848 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
6772dd07 12849 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12850 },
c6552317 12851/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
49f58d10
JB		 12852 {
12853 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
6772dd07 12854 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12855 },
c6552317 12856/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
49f58d10
JB		 12857 {
12858 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
6772dd07 12859 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 12860 },
c6552317 12861/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
49f58d10
JB		 12862 {
12863 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
6772dd07 12864 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 12865 },
12866/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
12867 {
12868 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
6772dd07 12869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12870 },
12871/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
12872 {
12873 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
6772dd07 12874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12875 },
12876/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
12877 {
12878 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
6772dd07 12879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12880 },
12881/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
12882 {
12883 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
6772dd07 12884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12885 },
12886/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
12887 {
12888 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
6772dd07 12889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12890 },
12891/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
12892 {
12893 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
6772dd07 12894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12895 },
12896/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
12897 {
12898 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
6772dd07 12899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12900 },
12901/* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
12902 {
12903 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
6772dd07 12904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12905 },
12906/* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
12907 {
12908 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
6772dd07 12909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12910 },
12911/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
12912 {
12913 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12915 },
12916/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12917 {
12918 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12920 },
12921/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12922 {
12923 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12925 },
12926/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
12927 {
12928 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 12929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12930 },
12931/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12932 {
12933 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 12934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12935 },
12936/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12937 {
12938 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 12939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12940 },
12941/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
12942 {
12943 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 12944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12945 },
12946/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12947 {
12948 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 12949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12950 },
12951/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12952 {
12953 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 12954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12955 },
12956/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
12957 {
12958 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12960 },
12961/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
12962 {
12963 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12965 },
12966/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
12967 {
12968 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12970 },
12971/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
12972 {
12973 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 12974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12975 },
12976/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
12977 {
12978 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 12979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12980 },
12981/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
12982 {
12983 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 12984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12985 },
12986/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
12987 {
12988 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12990 },
12991/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
12992 {
12993 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 12995 },
12996/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
12997 {
12998 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 12999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13000 },
13001/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
13002 {
13003 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13005 },
13006/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
13007 {
13008 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13010 },
13011/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13012 {
13013 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13015 },
13016/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13017 {
13018 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
6772dd07 13019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13020 },
13021/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13022 {
13023 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
6772dd07 13024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13025 },
13026/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13027 {
13028 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
6772dd07 13029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13030 },
13031/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13032 {
13033 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 13034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13035 },
13036/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13037 {
13038 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 13039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13040 },
13041/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13042 {
13043 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 13044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13045 },
13046/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13047 {
13048 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13050 },
13051/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
13052 {
13053 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13055 },
13056/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
13057 {
13058 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13060 },
13061/* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
13062 {
13063 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13065 },
13066/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13067 {
13068 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13070 },
13071/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
13072 {
13073 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13075 },
13076/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
13077 {
13078 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13080 },
13081/* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
13082 {
13083 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 13084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13085 },
13086/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13087 {
13088 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
6772dd07 13089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13090 },
13091/* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13092 {
13093 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
6772dd07 13094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13095 },
13096/* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13097 {
13098 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
6772dd07 13099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13100 },
13101/* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13102 {
13103 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
6772dd07 13104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13105 },
13106/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13107 {
13108 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13110 },
13111/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13112 {
13113 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13115 },
13116/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13117 {
13118 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13120 },
13121/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13122 {
13123 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13125 },
13126/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13127 {
13128 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13130 },
13131/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13132 {
13133 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13135 },
13136/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13137 {
13138 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13140 },
13141/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13142 {
13143 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13145 },
13146/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13147 {
13148 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13150 },
13151/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13152 {
13153 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13155 },
13156/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13157 {
13158 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13160 },
13161/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13162 {
13163 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13165 },
13166/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13167 {
13168 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13170 },
13171/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13172 {
13173 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13175 },
13176/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13177 {
13178 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13180 },
13181/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13182 {
13183 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13185 },
13186/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13187 {
13188 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13190 },
13191/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13192 {
13193 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13195 },
13196/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13197 {
13198 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13200 },
13201/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13202 {
13203 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13205 },
13206/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13207 {
13208 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13210 },
13211/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13212 {
13213 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13215 },
13216/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13217 {
13218 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13220 },
13221/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13222 {
13223 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13225 },
13226/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13227 {
13228 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13230 },
13231/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13232 {
13233 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13235 },
13236/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13237 {
13238 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13240 },
13241/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13242 {
13243 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13245 },
13246/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13247 {
13248 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 13249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13250 },
13251/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13252 {
13253 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 13254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13255 },
13256/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13257 {
13258 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 13259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13260 },
13261/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
13262 {
13263 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 13264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13265 },
13266/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13267 {
13268 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
6772dd07 13269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13270 },
13271/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13272 {
13273 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
6772dd07 13274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13275 },
13276/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13277 {
13278 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
6772dd07 13279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13280 },
13281/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
13282 {
13283 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
6772dd07 13284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13285 },
13286/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13287 {
13288 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
6772dd07 13289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13290 },
13291/* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
13292 {
13293 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
6772dd07 13294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13295 },
13296/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13297 {
13298 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
6772dd07 13299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13300 },
13301/* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
13302 {
13303 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
6772dd07 13304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13305 },
13306/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13307 {
13308 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
6772dd07 13309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13310 },
13311/* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
13312 {
13313 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
6772dd07 13314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13315 },
13316/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
13317 {
13318 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13320 },
13321/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
13322 {
13323 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13325 },
13326/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
13327 {
13328 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13330 },
13331/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
13332 {
13333 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13335 },
13336/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
13337 {
13338 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
6772dd07 13339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13340 },
13341/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
13342 {
13343 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
6772dd07 13344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13345 },
13346/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
13347 {
13348 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13350 },
13351/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
13352 {
13353 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13355 },
13356/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
13357 {
13358 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13360 },
13361/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
13362 {
13363 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13365 },
13366/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
13367 {
13368 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13370 },
13371/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
13372 {
13373 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 13374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13375 },
13376/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
13377 {
13378 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13380 },
13381/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
13382 {
13383 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 13384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13385 },
13386/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
13387 {
13388 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
6772dd07 13389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13390 },
13391/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
13392 {
13393 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
6772dd07 13394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13395 },
13396/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
13397 {
13398 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
6772dd07 13399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13400 },
13401/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
13402 {
13403 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
6772dd07 13404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13405 },
13406/* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
13407 {
13408 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
6772dd07 13409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13410 },
13411/* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
13412 {
13413 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
6772dd07 13414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13415 },
13416/* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
13417 {
13418 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
6772dd07 13419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13420 },
13421/* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
13422 {
13423 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
6772dd07 13424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13425 },
13426/* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
13427 {
13428 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
6772dd07 13429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13430 },
13431/* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
13432 {
13433 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
6772dd07 13434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13435 },
13436/* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
13437 {
13438 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
6772dd07 13439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13440 },
13441/* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
13442 {
13443 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
6772dd07 13444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13445 },
13446/* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
13447 {
13448 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
6772dd07 13449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13450 },
13451/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13452 {
13453 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13455 },
13456/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13457 {
13458 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13460 },
13461/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
13462 {
13463 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13465 },
13466/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13467 {
13468 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13470 },
13471/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13472 {
13473 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13475 },
13476/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
13477 {
13478 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13480 },
13481/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13482 {
13483 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13485 },
13486/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13487 {
13488 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13490 },
13491/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
13492 {
13493 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 13494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13495 },
13496/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
13497 {
13498 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13500 },
13501/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
13502 {
13503 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13505 },
13506/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
13507 {
13508 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13510 },
13511/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
13512 {
13513 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13515 },
13516/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
13517 {
13518 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13520 },
13521/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
13522 {
13523 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13525 },
13526/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
13527 {
13528 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13530 },
13531/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
13532 {
13533 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13535 },
13536/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
13537 {
13538 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
6772dd07 13539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13540 },
13541/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
13542 {
13543 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13545 },
13546/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
13547 {
13548 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13550 },
13551/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
13552 {
13553 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
6772dd07 13554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13555 },
13556/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
13557 {
13558 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
6772dd07 13559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13560 },
13561/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
13562 {
13563 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
6772dd07 13564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13565 },
13566/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
13567 {
13568 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
6772dd07 13569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13570 },
13571/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
13572 {
13573 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
6772dd07 13574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13575 },
13576/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
13577 {
13578 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
6772dd07 13579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13580 },
13581/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
13582 {
13583 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
6772dd07 13584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13585 },
13586/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13587 {
13588 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 13589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13590 },
13591/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
13592 {
13593 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 13594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13595 },
13596/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
13597 {
13598 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 13599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13600 },
13601/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13602 {
13603 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 13604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13605 },
13606/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
13607 {
13608 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 13609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13610 },
13611/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
13612 {
13613 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 13614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13615 },
13616/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13617 {
13618 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
6772dd07 13619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13620 },
13621/* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
13622 {
13623 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
6772dd07 13624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13625 },
13626/* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
13627 {
13628 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
6772dd07 13629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13630 },
13631/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
13632 {
13633 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13635 },
13636/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13637 {
13638 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13640 },
13641/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13642 {
13643 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13645 },
13646/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
13647 {
13648 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13650 },
13651/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13652 {
13653 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13655 },
13656/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13657 {
13658 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13660 },
13661/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
13662 {
13663 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13665 },
13666/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13667 {
13668 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13670 },
13671/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13672 {
13673 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13675 },
13676/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
13677 {
13678 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13680 },
13681/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
13682 {
13683 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13685 },
13686/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
13687 {
13688 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13690 },
13691/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
13692 {
13693 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13695 },
13696/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
13697 {
13698 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13700 },
13701/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
13702 {
13703 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13705 },
13706/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
13707 {
13708 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13710 },
13711/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
13712 {
13713 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13715 },
13716/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
13717 {
13718 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 13719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13720 },
13721/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
13722 {
13723 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13725 },
13726/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
13727 {
13728 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13730 },
13731/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13732 {
13733 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13735 },
13736/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13737 {
13738 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
6772dd07 13739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13740 },
13741/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13742 {
13743 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
6772dd07 13744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13745 },
13746/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13747 {
13748 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
6772dd07 13749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13750 },
13751/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13752 {
13753 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 13754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13755 },
13756/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13757 {
13758 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 13759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13760 },
13761/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13762 {
13763 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 13764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13765 },
13766/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13767 {
13768 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13770 },
13771/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
13772 {
13773 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13775 },
13776/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
13777 {
13778 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13780 },
13781/* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
13782 {
13783 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13785 },
13786/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13787 {
13788 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13790 },
13791/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
13792 {
13793 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13795 },
13796/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
13797 {
13798 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13800 },
13801/* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
13802 {
13803 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
6772dd07 13804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13805 },
13806/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13807 {
13808 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
6772dd07 13809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13810 },
13811/* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13812 {
13813 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
6772dd07 13814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13815 },
13816/* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13817 {
13818 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
6772dd07 13819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13820 },
13821/* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13822 {
13823 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
6772dd07 13824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13825 },
13826/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13827 {
13828 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13830 },
13831/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13832 {
13833 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13835 },
13836/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13837 {
13838 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13840 },
13841/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13842 {
13843 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13845 },
13846/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13847 {
13848 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13850 },
13851/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13852 {
13853 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13855 },
13856/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13857 {
13858 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13860 },
13861/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13862 {
13863 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13865 },
13866/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13867 {
13868 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 13869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13870 },
13871/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13872 {
13873 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 13874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13875 },
13876/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13877 {
13878 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 13879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13880 },
13881/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13882 {
13883 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 13884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13885 },
13886/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13887 {
13888 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13890 },
13891/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13892 {
13893 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13895 },
13896/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13897 {
13898 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13900 },
13901/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13902 {
13903 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13905 },
13906/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13907 {
13908 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13910 },
13911/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13912 {
13913 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13915 },
13916/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13917 {
13918 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13920 },
13921/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13922 {
13923 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13925 },
13926/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13927 {
13928 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13930 },
13931/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13932 {
13933 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13935 },
13936/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13937 {
13938 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13940 },
13941/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13942 {
13943 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 13944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13945 },
13946/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13947 {
13948 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13950 },
13951/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13952 {
13953 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13955 },
13956/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13957 {
13958 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13960 },
13961/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13962 {
13963 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 13964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13965 },
13966/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13967 {
13968 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 13969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13970 },
13971/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13972 {
13973 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 13974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13975 },
13976/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13977 {
13978 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 13979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13980 },
13981/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
13982 {
13983 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 13984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13985 },
13986/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13987 {
13988 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
6772dd07 13989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13990 },
13991/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13992 {
13993 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
6772dd07 13994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 13995 },
13996/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13997 {
13998 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
6772dd07 13999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14000 },
14001/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
14002 {
14003 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
6772dd07 14004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14005 },
14006/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
14007 {
14008 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
6772dd07 14009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14010 },
14011/* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
14012 {
14013 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
6772dd07 14014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14015 },
14016/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
14017 {
14018 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
6772dd07 14019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14020 },
14021/* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
14022 {
14023 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
6772dd07 14024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14025 },
14026/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
14027 {
14028 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
6772dd07 14029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14030 },
14031/* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
14032 {
14033 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
6772dd07 14034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14035 },
14036/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
14037 {
14038 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 14039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14040 },
14041/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
14042 {
14043 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 14044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14045 },
14046/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
14047 {
14048 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 14049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14050 },
14051/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
14052 {
14053 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 14054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14055 },
14056/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
14057 {
14058 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
6772dd07 14059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14060 },
14061/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
14062 {
14063 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
6772dd07 14064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14065 },
14066/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
14067 {
14068 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 14069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14070 },
14071/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
14072 {
14073 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 14074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14075 },
14076/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
14077 {
14078 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 14079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14080 },
14081/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
14082 {
14083 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 14084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14085 },
14086/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
14087 {
14088 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 14089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14090 },
14091/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
14092 {
14093 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 14094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14095 },
14096/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
14097 {
14098 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 14099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14100 },
14101/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
14102 {
14103 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
6772dd07 14104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14105 },
14106/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
14107 {
14108 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
6772dd07 14109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14110 },
14111/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
14112 {
14113 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
6772dd07 14114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14115 },
14116/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
14117 {
14118 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
6772dd07 14119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14120 },
14121/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
14122 {
14123 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
6772dd07 14124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14125 },
14126/* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
14127 {
14128 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
6772dd07 14129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14130 },
14131/* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
14132 {
14133 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
6772dd07 14134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14135 },
14136/* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
14137 {
14138 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
6772dd07 14139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14140 },
14141/* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
14142 {
14143 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
6772dd07 14144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14145 },
14146/* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
14147 {
14148 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
6772dd07 14149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14150 },
14151/* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
14152 {
14153 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
6772dd07 14154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14155 },
14156/* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
14157 {
14158 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
6772dd07 14159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14160 },
14161/* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
14162 {
14163 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
6772dd07 14164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14165 },
14166/* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
14167 {
14168 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
6772dd07 14169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14170 },
14171/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14172 {
14173 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14175 },
14176/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14177 {
14178 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14180 },
14181/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
14182 {
14183 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14185 },
14186/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14187 {
14188 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14190 },
14191/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14192 {
14193 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14195 },
14196/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
14197 {
14198 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14200 },
14201/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14202 {
14203 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 14204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14205 },
14206/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14207 {
14208 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 14209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14210 },
14211/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
14212 {
14213 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 14214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14215 },
14216/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
14217 {
14218 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14220 },
14221/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
14222 {
14223 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14225 },
14226/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
14227 {
14228 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14230 },
14231/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
14232 {
14233 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14235 },
14236/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
14237 {
14238 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14240 },
14241/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
14242 {
14243 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14245 },
14246/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
14247 {
14248 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14250 },
14251/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
14252 {
14253 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14255 },
14256/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
14257 {
14258 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
6772dd07 14259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14260 },
14261/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
14262 {
14263 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14265 },
14266/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
14267 {
14268 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14270 },
14271/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
14272 {
14273 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 14274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14275 },
14276/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
14277 {
14278 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
6772dd07 14279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14280 },
14281/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
14282 {
14283 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
6772dd07 14284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14285 },
14286/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
14287 {
14288 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
6772dd07 14289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14290 },
14291/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
14292 {
14293 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
6772dd07 14294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14295 },
14296/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
14297 {
14298 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
6772dd07 14299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14300 },
14301/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
14302 {
14303 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
6772dd07 14304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14305 },
14306/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
14307 {
14308 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
6772dd07 14309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14310 },
14311/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
14312 {
14313 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
6772dd07 14314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14315 },
14316/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
14317 {
14318 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
6772dd07 14319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14320 },
14321/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
14322 {
14323 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
6772dd07 14324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14325 },
14326/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
14327 {
14328 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
6772dd07 14329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14330 },
14331/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
14332 {
14333 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
6772dd07 14334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14335 },
14336/* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14337 {
14338 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
6772dd07 14339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14340 },
14341/* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14342 {
14343 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
6772dd07 14344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14345 },
14346/* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14347 {
14348 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
6772dd07 14349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14350 },
14351/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14352 {
14353 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
6772dd07 14354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14355 },
14356/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14357 {
14358 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
6772dd07 14359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14360 },
14361/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14362 {
14363 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
6772dd07 14364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14365 },
14366/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14367 {
14368 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
6772dd07 14369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14370 },
14371/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14372 {
14373 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
6772dd07 14374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14375 },
14376/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14377 {
14378 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
6772dd07 14379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14380 },
14381/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14382 {
14383 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
6772dd07 14384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14385 },
14386/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14387 {
14388 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
6772dd07 14389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14390 },
14391/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14392 {
14393 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
6772dd07 14394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14395 },
14396/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14397 {
14398 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
6772dd07 14399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14400 },
14401/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14402 {
14403 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
6772dd07 14404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14405 },
14406/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14407 {
14408 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
6772dd07 14409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14410 },
14411/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14412 {
14413 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
6772dd07 14414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14415 },
14416/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14417 {
14418 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
6772dd07 14419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14420 },
14421/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14422 {
14423 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
6772dd07 14424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14425 },
14426/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14427 {
14428 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
6772dd07 14429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14430 },
14431/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14432 {
14433 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
6772dd07 14434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14435 },
14436/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14437 {
14438 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
6772dd07 14439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14440 },
14441/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
14442 {
14443 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
6772dd07 14444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14445 },
14446/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
14447 {
14448 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
6772dd07 14449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14450 },
14451/* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
14452 {
14453 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32,
6772dd07 14454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14455 },
14456/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
14457 {
14458 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
6772dd07 14459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14460 },
14461/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
14462 {
14463 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
6772dd07 14464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14465 },
14466/* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
14467 {
14468 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32,
6772dd07 14469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14470 },
14471/* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14472 {
14473 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
6772dd07 14474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14475 },
14476/* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14477 {
14478 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
6772dd07 14479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14480 },
14481/* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
14482 {
14483 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32,
6772dd07 14484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14485 },
14486/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14487 {
14488 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
6772dd07 14489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14490 },
14491/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14492 {
14493 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
6772dd07 14494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14495 },
14496/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14497 {
14498 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
6772dd07 14499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14500 },
14501/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14502 {
14503 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
6772dd07 14504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14505 },
14506/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14507 {
14508 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
6772dd07 14509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14510 },
14511/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14512 {
14513 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
6772dd07 14514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14515 },
14516/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14517 {
14518 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
6772dd07 14519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14520 },
14521/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14522 {
14523 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
6772dd07 14524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14525 },
14526/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14527 {
14528 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
6772dd07 14529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14530 },
14531/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14532 {
14533 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
6772dd07 14534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14535 },
14536/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14537 {
14538 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
6772dd07 14539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14540 },
14541/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14542 {
14543 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
6772dd07 14544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14545 },
14546/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14547 {
14548 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
6772dd07 14549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14550 },
14551/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14552 {
14553 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
6772dd07 14554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14555 },
14556/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14557 {
14558 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
6772dd07 14559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14560 },
14561/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14562 {
14563 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
6772dd07 14564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14565 },
14566/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14567 {
14568 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
6772dd07 14569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14570 },
14571/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
14572 {
14573 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
6772dd07 14574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14575 },
14576/* sbb.w${X} $Src16RnHI,$Dst16RnHI */
14577 {
14578 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
6772dd07 14579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14580 },
14581/* sbb.w${X} $Src16AnHI,$Dst16RnHI */
14582 {
14583 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
6772dd07 14584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14585 },
14586/* sbb.w${X} [$Src16An],$Dst16RnHI */
14587 {
14588 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16,
6772dd07 14589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14590 },
14591/* sbb.w${X} $Src16RnHI,$Dst16AnHI */
14592 {
14593 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
6772dd07 14594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14595 },
14596/* sbb.w${X} $Src16AnHI,$Dst16AnHI */
14597 {
14598 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
6772dd07 14599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14600 },
14601/* sbb.w${X} [$Src16An],$Dst16AnHI */
14602 {
14603 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16,
6772dd07 14604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14605 },
14606/* sbb.w${X} $Src16RnHI,[$Dst16An] */
14607 {
14608 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
6772dd07 14609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14610 },
14611/* sbb.w${X} $Src16AnHI,[$Dst16An] */
14612 {
14613 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
6772dd07 14614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14615 },
14616/* sbb.w${X} [$Src16An],[$Dst16An] */
14617 {
14618 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16,
6772dd07 14619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14620 },
14621/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
14622 {
14623 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
6772dd07 14624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14625 },
14626/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
14627 {
14628 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
6772dd07 14629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14630 },
14631/* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
14632 {
14633 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
6772dd07 14634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14635 },
14636/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
14637 {
14638 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
6772dd07 14639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14640 },
14641/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
14642 {
14643 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
6772dd07 14644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14645 },
14646/* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
14647 {
14648 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
6772dd07 14649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14650 },
14651/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
14652 {
14653 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
6772dd07 14654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14655 },
14656/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
14657 {
14658 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
6772dd07 14659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14660 },
14661/* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
14662 {
14663 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
6772dd07 14664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14665 },
14666/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
14667 {
14668 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
6772dd07 14669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14670 },
14671/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
14672 {
14673 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
6772dd07 14674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14675 },
14676/* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
14677 {
14678 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
6772dd07 14679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14680 },
14681/* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
14682 {
14683 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
6772dd07 14684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14685 },
14686/* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
14687 {
14688 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
6772dd07 14689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14690 },
14691/* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
14692 {
14693 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
6772dd07 14694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14695 },
14696/* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
14697 {
14698 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
6772dd07 14699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14700 },
14701/* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
14702 {
14703 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
6772dd07 14704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14705 },
14706/* sbb.w${X} [$Src16An],${Dsp-16-u16} */
14707 {
14708 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
6772dd07 14709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14710 },
14711/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
14712 {
14713 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
6772dd07 14714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14715 },
14716/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
14717 {
14718 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
6772dd07 14719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14720 },
14721/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
14722 {
14723 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
6772dd07 14724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14725 },
14726/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
14727 {
14728 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
6772dd07 14729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14730 },
14731/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
14732 {
14733 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
6772dd07 14734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14735 },
14736/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
14737 {
14738 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
6772dd07 14739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14740 },
14741/* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14742 {
14743 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
6772dd07 14744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14745 },
14746/* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14747 {
14748 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
6772dd07 14749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14750 },
14751/* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14752 {
14753 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
6772dd07 14754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14755 },
14756/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14757 {
14758 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
6772dd07 14759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14760 },
14761/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14762 {
14763 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
6772dd07 14764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14765 },
14766/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14767 {
14768 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
6772dd07 14769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14770 },
14771/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14772 {
14773 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
6772dd07 14774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14775 },
14776/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14777 {
14778 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
6772dd07 14779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14780 },
14781/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14782 {
14783 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
6772dd07 14784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14785 },
14786/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14787 {
14788 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
6772dd07 14789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14790 },
14791/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14792 {
14793 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
6772dd07 14794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14795 },
14796/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14797 {
14798 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
6772dd07 14799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14800 },
14801/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14802 {
14803 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
6772dd07 14804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14805 },
14806/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14807 {
14808 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
6772dd07 14809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14810 },
14811/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14812 {
14813 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
6772dd07 14814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14815 },
14816/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14817 {
14818 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
6772dd07 14819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14820 },
14821/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14822 {
14823 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
6772dd07 14824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14825 },
14826/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14827 {
14828 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
6772dd07 14829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14830 },
14831/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14832 {
14833 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
6772dd07 14834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14835 },
14836/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14837 {
14838 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
6772dd07 14839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14840 },
14841/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14842 {
14843 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
6772dd07 14844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14845 },
14846/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
14847 {
14848 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
6772dd07 14849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14850 },
14851/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
14852 {
14853 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
6772dd07 14854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14855 },
14856/* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
14857 {
14858 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32,
6772dd07 14859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14860 },
14861/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
14862 {
14863 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
6772dd07 14864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14865 },
14866/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
14867 {
14868 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
6772dd07 14869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14870 },
14871/* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
14872 {
14873 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32,
6772dd07 14874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14875 },
14876/* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14877 {
14878 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
6772dd07 14879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14880 },
14881/* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14882 {
14883 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
6772dd07 14884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14885 },
14886/* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
14887 {
14888 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32,
6772dd07 14889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14890 },
14891/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14892 {
14893 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
6772dd07 14894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14895 },
14896/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14897 {
14898 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
6772dd07 14899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14900 },
14901/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14902 {
14903 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
6772dd07 14904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14905 },
14906/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14907 {
14908 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
6772dd07 14909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14910 },
14911/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14912 {
14913 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
6772dd07 14914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14915 },
14916/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14917 {
14918 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
6772dd07 14919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14920 },
14921/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14922 {
14923 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
6772dd07 14924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14925 },
14926/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14927 {
14928 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
6772dd07 14929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14930 },
14931/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14932 {
14933 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
6772dd07 14934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14935 },
14936/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14937 {
14938 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
6772dd07 14939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14940 },
14941/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14942 {
14943 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
6772dd07 14944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14945 },
14946/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14947 {
14948 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
6772dd07 14949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14950 },
14951/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14952 {
14953 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
6772dd07 14954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14955 },
14956/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14957 {
14958 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
6772dd07 14959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14960 },
14961/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14962 {
14963 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
6772dd07 14964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14965 },
14966/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14967 {
14968 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
6772dd07 14969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14970 },
14971/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14972 {
14973 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
6772dd07 14974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14975 },
14976/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
14977 {
14978 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
6772dd07 14979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14980 },
14981/* sbb.b${X} $Src16RnQI,$Dst16RnQI */
14982 {
14983 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
6772dd07 14984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14985 },
14986/* sbb.b${X} $Src16AnQI,$Dst16RnQI */
14987 {
14988 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
6772dd07 14989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14990 },
14991/* sbb.b${X} [$Src16An],$Dst16RnQI */
14992 {
14993 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16,
6772dd07 14994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 14995 },
14996/* sbb.b${X} $Src16RnQI,$Dst16AnQI */
14997 {
14998 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
6772dd07 14999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15000 },
15001/* sbb.b${X} $Src16AnQI,$Dst16AnQI */
15002 {
15003 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
6772dd07 15004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15005 },
15006/* sbb.b${X} [$Src16An],$Dst16AnQI */
15007 {
15008 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16,
6772dd07 15009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15010 },
15011/* sbb.b${X} $Src16RnQI,[$Dst16An] */
15012 {
15013 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
6772dd07 15014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15015 },
15016/* sbb.b${X} $Src16AnQI,[$Dst16An] */
15017 {
15018 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
6772dd07 15019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15020 },
15021/* sbb.b${X} [$Src16An],[$Dst16An] */
15022 {
15023 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16,
6772dd07 15024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15025 },
15026/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
15027 {
15028 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
6772dd07 15029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15030 },
15031/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
15032 {
15033 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
6772dd07 15034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15035 },
15036/* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
15037 {
15038 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
6772dd07 15039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15040 },
15041/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
15042 {
15043 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
6772dd07 15044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15045 },
15046/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
15047 {
15048 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
6772dd07 15049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15050 },
15051/* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
15052 {
15053 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
6772dd07 15054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15055 },
15056/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
15057 {
15058 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
6772dd07 15059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15060 },
15061/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
15062 {
15063 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
6772dd07 15064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15065 },
15066/* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
15067 {
15068 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
6772dd07 15069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15070 },
15071/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
15072 {
15073 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
6772dd07 15074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15075 },
15076/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
15077 {
15078 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
6772dd07 15079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15080 },
15081/* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
15082 {
15083 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
6772dd07 15084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15085 },
15086/* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
15087 {
15088 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
6772dd07 15089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15090 },
15091/* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
15092 {
15093 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
6772dd07 15094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15095 },
15096/* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
15097 {
15098 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
6772dd07 15099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15100 },
15101/* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
15102 {
15103 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
6772dd07 15104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15105 },
15106/* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
15107 {
15108 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
6772dd07 15109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15110 },
15111/* sbb.b${X} [$Src16An],${Dsp-16-u16} */
15112 {
15113 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
6772dd07 15114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 15115 },
15116/* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
15117 {
15118 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 15119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15120 },
15121/* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
15122 {
15123 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
6772dd07 15124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15125 },
15126/* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
15127 {
15128 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
6772dd07 15129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15130 },
15131/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15132 {
15133 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 15134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15135 },
15136/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
15137 {
15138 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 15139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15140 },
15141/* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
15142 {
15143 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48,
6772dd07 15144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15145 },
15146/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15147 {
15148 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 15149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15150 },
15151/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
15152 {
15153 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 15154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15155 },
15156/* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
15157 {
15158 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56,
6772dd07 15159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15160 },
15161/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
15162 {
15163 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56,
6772dd07 15164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15165 },
15166/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15167 {
15168 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64,
6772dd07 15169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15170 },
15171/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
15172 {
15173 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64,
6772dd07 15174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15175 },
15176/* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
15177 {
15178 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 15179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15180 },
15181/* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
15182 {
15183 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
6772dd07 15184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15185 },
15186/* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
15187 {
15188 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
6772dd07 15189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15190 },
15191/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15192 {
15193 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 15194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15195 },
15196/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
15197 {
15198 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 15199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15200 },
15201/* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
15202 {
15203 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40,
6772dd07 15204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15205 },
15206/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15207 {
15208 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 15209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15210 },
15211/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
15212 {
15213 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 15214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15215 },
15216/* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
15217 {
15218 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48,
6772dd07 15219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15220 },
15221/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
15222 {
15223 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48,
6772dd07 15224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15225 },
15226/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15227 {
15228 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56,
6772dd07 15229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15230 },
15231/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
15232 {
15233 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56,
6772dd07 15234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15235 },
15236/* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
15237 {
15238 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32,
6772dd07 15239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15240 },
15241/* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
15242 {
15243 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32,
6772dd07 15244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15245 },
15246/* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
15247 {
15248 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32,
6772dd07 15249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15250 },
15251/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
15252 {
15253 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40,
6772dd07 15254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15255 },
15256/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
15257 {
15258 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40,
6772dd07 15259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15260 },
15261/* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
15262 {
15263 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40,
6772dd07 15264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15265 },
15266/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
15267 {
15268 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48,
6772dd07 15269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15270 },
15271/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
15272 {
15273 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48,
6772dd07 15274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15275 },
15276/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
15277 {
15278 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48,
6772dd07 15279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15280 },
15281/* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
15282 {
15283 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24,
6772dd07 15284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15285 },
15286/* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
15287 {
15288 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24,
6772dd07 15289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15290 },
15291/* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
15292 {
15293 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24,
6772dd07 15294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15295 },
15296/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
15297 {
15298 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32,
6772dd07 15299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15300 },
15301/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
15302 {
15303 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32,
6772dd07 15304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15305 },
15306/* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
15307 {
15308 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32,
6772dd07 15309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15310 },
15311/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
15312 {
15313 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40,
6772dd07 15314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15315 },
15316/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
15317 {
15318 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40,
6772dd07 15319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15320 },
15321/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
15322 {
15323 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
6772dd07 15324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 15325 },
a1a280bb 15326/* rot.w r1h,$Dst32RnUnprefixedHI */
49f58d10 15327 {
a1a280bb 15328 M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
6772dd07 15329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 15330 },
a1a280bb 15331/* rot.w r1h,$Dst32AnUnprefixedHI */
49f58d10 15332 {
a1a280bb 15333 M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
6772dd07 15334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15335 },
15336/* rot.w r1h,[$Dst32AnUnprefixed] */
15337 {
a1a280bb 15338 M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
6772dd07 15339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15340 },
15341/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15342 {
a1a280bb 15343 M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
6772dd07 15344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15345 },
15346/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15347 {
a1a280bb 15348 M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
6772dd07 15349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15350 },
15351/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15352 {
a1a280bb 15353 M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
6772dd07 15354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15355 },
15356/* rot.w r1h,${Dsp-16-u8}[sb] */
15357 {
a1a280bb 15358 M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
6772dd07 15359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15360 },
15361/* rot.w r1h,${Dsp-16-u16}[sb] */
15362 {
a1a280bb 15363 M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
6772dd07 15364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15365 },
15366/* rot.w r1h,${Dsp-16-s8}[fb] */
15367 {
a1a280bb 15368 M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
6772dd07 15369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15370 },
15371/* rot.w r1h,${Dsp-16-s16}[fb] */
15372 {
a1a280bb 15373 M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
6772dd07 15374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15375 },
15376/* rot.w r1h,${Dsp-16-u16} */
15377 {
a1a280bb 15378 M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
6772dd07 15379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15380 },
15381/* rot.w r1h,${Dsp-16-u24} */
15382 {
a1a280bb 15383 M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
6772dd07 15384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 15385 },
a1a280bb 15386/* rot.b r1h,$Dst32RnUnprefixedQI */
49f58d10 15387 {
a1a280bb 15388 M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
6772dd07 15389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 15390 },
a1a280bb 15391/* rot.b r1h,$Dst32AnUnprefixedQI */
49f58d10 15392 {
a1a280bb 15393 M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
6772dd07 15394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15395 },
15396/* rot.b r1h,[$Dst32AnUnprefixed] */
15397 {
a1a280bb 15398 M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
6772dd07 15399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15400 },
15401/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15402 {
a1a280bb 15403 M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
6772dd07 15404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15405 },
15406/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15407 {
a1a280bb 15408 M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
6772dd07 15409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15410 },
15411/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15412 {
a1a280bb 15413 M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
6772dd07 15414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15415 },
15416/* rot.b r1h,${Dsp-16-u8}[sb] */
15417 {
a1a280bb 15418 M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
6772dd07 15419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15420 },
15421/* rot.b r1h,${Dsp-16-u16}[sb] */
15422 {
a1a280bb 15423 M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
6772dd07 15424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15425 },
15426/* rot.b r1h,${Dsp-16-s8}[fb] */
15427 {
a1a280bb 15428 M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
6772dd07 15429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15430 },
15431/* rot.b r1h,${Dsp-16-s16}[fb] */
15432 {
a1a280bb 15433 M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
6772dd07 15434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15435 },
15436/* rot.b r1h,${Dsp-16-u16} */
15437 {
a1a280bb 15438 M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
6772dd07 15439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15440 },
15441/* rot.b r1h,${Dsp-16-u24} */
15442 {
a1a280bb 15443 M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
6772dd07 15444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15445 },
15446/* rot.w r1h,$Dst16RnHI */
15447 {
15448 M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16,
6772dd07 15449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15450 },
15451/* rot.w r1h,$Dst16AnHI */
15452 {
15453 M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16,
6772dd07 15454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15455 },
15456/* rot.w r1h,[$Dst16An] */
15457 {
15458 M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16,
6772dd07 15459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15460 },
15461/* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
15462 {
15463 M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24,
6772dd07 15464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15465 },
15466/* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
15467 {
15468 M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32,
6772dd07 15469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15470 },
15471/* rot.w r1h,${Dsp-16-u8}[sb] */
15472 {
15473 M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24,
6772dd07 15474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15475 },
15476/* rot.w r1h,${Dsp-16-u16}[sb] */
15477 {
15478 M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32,
6772dd07 15479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15480 },
15481/* rot.w r1h,${Dsp-16-s8}[fb] */
15482 {
15483 M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24,
6772dd07 15484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15485 },
15486/* rot.w r1h,${Dsp-16-u16} */
15487 {
15488 M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
6772dd07 15489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 15490 },
a1a280bb 15491/* rot.b r1h,$Dst16RnQI */
49f58d10 15492 {
a1a280bb 15493 M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16,
6772dd07 15494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 15495 },
a1a280bb 15496/* rot.b r1h,$Dst16AnQI */
49f58d10 15497 {
a1a280bb 15498 M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16,
6772dd07 15499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15500 },
15501/* rot.b r1h,[$Dst16An] */
15502 {
a1a280bb 15503 M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16,
6772dd07 15504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15505 },
15506/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
15507 {
a1a280bb 15508 M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24,
6772dd07 15509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15510 },
15511/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
15512 {
a1a280bb 15513 M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32,
6772dd07 15514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15515 },
15516/* rot.b r1h,${Dsp-16-u8}[sb] */
15517 {
a1a280bb 15518 M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24,
6772dd07 15519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15520 },
15521/* rot.b r1h,${Dsp-16-u16}[sb] */
15522 {
a1a280bb 15523 M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32,
6772dd07 15524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15525 },
15526/* rot.b r1h,${Dsp-16-s8}[fb] */
15527 {
a1a280bb 15528 M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24,
6772dd07 15529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15530 },
15531/* rot.b r1h,${Dsp-16-u16} */
15532 {
a1a280bb 15533 M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32,
6772dd07 15534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 15535 },
15536/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
15537 {
15538 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
6772dd07 15539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15540 },
15541/* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
15542 {
15543 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
6772dd07 15544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15545 },
15546/* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15547 {
15548 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
6772dd07 15549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15550 },
15551/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15552 {
15553 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
6772dd07 15554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15555 },
15556/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15557 {
15558 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
6772dd07 15559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15560 },
15561/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15562 {
15563 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
6772dd07 15564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15565 },
15566/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15567 {
15568 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
6772dd07 15569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15570 },
15571/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15572 {
15573 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
6772dd07 15574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15575 },
15576/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15577 {
15578 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
6772dd07 15579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15580 },
15581/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15582 {
15583 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
6772dd07 15584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15585 },
15586/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15587 {
15588 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
6772dd07 15589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15590 },
15591/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15592 {
15593 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
6772dd07 15594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15595 },
15596/* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
15597 {
15598 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
6772dd07 15599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15600 },
15601/* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
15602 {
15603 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
6772dd07 15604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15605 },
15606/* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15607 {
15608 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
6772dd07 15609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15610 },
15611/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15612 {
15613 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
6772dd07 15614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15615 },
15616/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15617 {
15618 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
6772dd07 15619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15620 },
15621/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15622 {
15623 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
6772dd07 15624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15625 },
15626/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15627 {
15628 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
6772dd07 15629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15630 },
15631/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15632 {
15633 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
6772dd07 15634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15635 },
15636/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15637 {
15638 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
6772dd07 15639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15640 },
15641/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15642 {
15643 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
6772dd07 15644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15645 },
15646/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15647 {
15648 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
6772dd07 15649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15650 },
15651/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15652 {
15653 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
6772dd07 15654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15655 },
15656/* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
15657 {
15658 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16,
6772dd07 15659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15660 },
15661/* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
15662 {
15663 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16,
6772dd07 15664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15665 },
15666/* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
15667 {
15668 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16,
6772dd07 15669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15670 },
15671/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15672 {
15673 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24,
6772dd07 15674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15675 },
15676/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15677 {
15678 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32,
6772dd07 15679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15680 },
15681/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15682 {
15683 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24,
6772dd07 15684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15685 },
15686/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15687 {
15688 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32,
6772dd07 15689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15690 },
15691/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15692 {
15693 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24,
6772dd07 15694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15695 },
15696/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15697 {
15698 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32,
6772dd07 15699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15700 },
15701/* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
15702 {
15703 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16,
6772dd07 15704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15705 },
15706/* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
15707 {
15708 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16,
6772dd07 15709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15710 },
15711/* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
15712 {
15713 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16,
6772dd07 15714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15715 },
15716/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15717 {
15718 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24,
6772dd07 15719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15720 },
15721/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15722 {
15723 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32,
6772dd07 15724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15725 },
15726/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15727 {
15728 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24,
6772dd07 15729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15730 },
15731/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15732 {
15733 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32,
6772dd07 15734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15735 },
15736/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15737 {
15738 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24,
6772dd07 15739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15740 },
15741/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15742 {
15743 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32,
6772dd07 15744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15745 },
15746/* rorc.w $Dst32RnUnprefixedHI */
15747 {
15748 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16,
6772dd07 15749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15750 },
15751/* rorc.w $Dst32AnUnprefixedHI */
15752 {
15753 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16,
6772dd07 15754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15755 },
15756/* rorc.w [$Dst32AnUnprefixed] */
15757 {
15758 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16,
6772dd07 15759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15760 },
15761/* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15762 {
15763 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24,
6772dd07 15764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15765 },
15766/* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15767 {
15768 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32,
6772dd07 15769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15770 },
15771/* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15772 {
15773 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40,
6772dd07 15774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15775 },
15776/* rorc.w ${Dsp-16-u8}[sb] */
15777 {
15778 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24,
6772dd07 15779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15780 },
15781/* rorc.w ${Dsp-16-u16}[sb] */
15782 {
15783 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32,
6772dd07 15784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15785 },
15786/* rorc.w ${Dsp-16-s8}[fb] */
15787 {
15788 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24,
6772dd07 15789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15790 },
15791/* rorc.w ${Dsp-16-s16}[fb] */
15792 {
15793 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32,
6772dd07 15794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15795 },
15796/* rorc.w ${Dsp-16-u16} */
15797 {
15798 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32,
6772dd07 15799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15800 },
15801/* rorc.w ${Dsp-16-u24} */
15802 {
15803 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40,
6772dd07 15804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15805 },
15806/* rorc.b $Dst32RnUnprefixedQI */
15807 {
15808 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16,
6772dd07 15809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15810 },
15811/* rorc.b $Dst32AnUnprefixedQI */
15812 {
15813 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16,
6772dd07 15814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15815 },
15816/* rorc.b [$Dst32AnUnprefixed] */
15817 {
15818 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16,
6772dd07 15819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15820 },
15821/* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15822 {
15823 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24,
6772dd07 15824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15825 },
15826/* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15827 {
15828 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32,
6772dd07 15829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15830 },
15831/* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15832 {
15833 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40,
6772dd07 15834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15835 },
15836/* rorc.b ${Dsp-16-u8}[sb] */
15837 {
15838 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24,
6772dd07 15839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15840 },
15841/* rorc.b ${Dsp-16-u16}[sb] */
15842 {
15843 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32,
6772dd07 15844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15845 },
15846/* rorc.b ${Dsp-16-s8}[fb] */
15847 {
15848 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24,
6772dd07 15849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15850 },
15851/* rorc.b ${Dsp-16-s16}[fb] */
15852 {
15853 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32,
6772dd07 15854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15855 },
15856/* rorc.b ${Dsp-16-u16} */
15857 {
15858 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32,
6772dd07 15859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15860 },
15861/* rorc.b ${Dsp-16-u24} */
15862 {
15863 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40,
6772dd07 15864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15865 },
15866/* rorc.w $Dst16RnHI */
15867 {
15868 M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16,
6772dd07 15869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15870 },
15871/* rorc.w $Dst16AnHI */
15872 {
15873 M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16,
6772dd07 15874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15875 },
15876/* rorc.w [$Dst16An] */
15877 {
15878 M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16,
6772dd07 15879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15880 },
15881/* rorc.w ${Dsp-16-u8}[$Dst16An] */
15882 {
15883 M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24,
6772dd07 15884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15885 },
15886/* rorc.w ${Dsp-16-u16}[$Dst16An] */
15887 {
15888 M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32,
6772dd07 15889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15890 },
15891/* rorc.w ${Dsp-16-u8}[sb] */
15892 {
15893 M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24,
6772dd07 15894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15895 },
15896/* rorc.w ${Dsp-16-u16}[sb] */
15897 {
15898 M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32,
6772dd07 15899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15900 },
15901/* rorc.w ${Dsp-16-s8}[fb] */
15902 {
15903 M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24,
6772dd07 15904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15905 },
15906/* rorc.w ${Dsp-16-u16} */
15907 {
15908 M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32,
6772dd07 15909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15910 },
15911/* rorc.b $Dst16RnQI */
15912 {
15913 M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16,
6772dd07 15914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15915 },
15916/* rorc.b $Dst16AnQI */
15917 {
15918 M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16,
6772dd07 15919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15920 },
15921/* rorc.b [$Dst16An] */
15922 {
15923 M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16,
6772dd07 15924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15925 },
15926/* rorc.b ${Dsp-16-u8}[$Dst16An] */
15927 {
15928 M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24,
6772dd07 15929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15930 },
15931/* rorc.b ${Dsp-16-u16}[$Dst16An] */
15932 {
15933 M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32,
6772dd07 15934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15935 },
15936/* rorc.b ${Dsp-16-u8}[sb] */
15937 {
15938 M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24,
6772dd07 15939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15940 },
15941/* rorc.b ${Dsp-16-u16}[sb] */
15942 {
15943 M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32,
6772dd07 15944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15945 },
15946/* rorc.b ${Dsp-16-s8}[fb] */
15947 {
15948 M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24,
6772dd07 15949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15950 },
15951/* rorc.b ${Dsp-16-u16} */
15952 {
15953 M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32,
6772dd07 15954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15955 },
15956/* rolc.w $Dst32RnUnprefixedHI */
15957 {
15958 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16,
6772dd07 15959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15960 },
15961/* rolc.w $Dst32AnUnprefixedHI */
15962 {
15963 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16,
6772dd07 15964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15965 },
15966/* rolc.w [$Dst32AnUnprefixed] */
15967 {
15968 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16,
6772dd07 15969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15970 },
15971/* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15972 {
15973 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24,
6772dd07 15974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15975 },
15976/* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15977 {
15978 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32,
6772dd07 15979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15980 },
15981/* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15982 {
15983 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40,
6772dd07 15984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15985 },
15986/* rolc.w ${Dsp-16-u8}[sb] */
15987 {
15988 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24,
6772dd07 15989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15990 },
15991/* rolc.w ${Dsp-16-u16}[sb] */
15992 {
15993 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32,
6772dd07 15994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 15995 },
15996/* rolc.w ${Dsp-16-s8}[fb] */
15997 {
15998 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24,
6772dd07 15999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16000 },
16001/* rolc.w ${Dsp-16-s16}[fb] */
16002 {
16003 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32,
6772dd07 16004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16005 },
16006/* rolc.w ${Dsp-16-u16} */
16007 {
16008 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32,
6772dd07 16009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16010 },
16011/* rolc.w ${Dsp-16-u24} */
16012 {
16013 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40,
6772dd07 16014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16015 },
16016/* rolc.b $Dst32RnUnprefixedQI */
16017 {
16018 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16,
6772dd07 16019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16020 },
16021/* rolc.b $Dst32AnUnprefixedQI */
16022 {
16023 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16,
6772dd07 16024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16025 },
16026/* rolc.b [$Dst32AnUnprefixed] */
16027 {
16028 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16,
6772dd07 16029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16030 },
16031/* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16032 {
16033 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24,
6772dd07 16034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16035 },
16036/* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16037 {
16038 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32,
6772dd07 16039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16040 },
16041/* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16042 {
16043 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40,
6772dd07 16044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16045 },
16046/* rolc.b ${Dsp-16-u8}[sb] */
16047 {
16048 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24,
6772dd07 16049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16050 },
16051/* rolc.b ${Dsp-16-u16}[sb] */
16052 {
16053 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32,
6772dd07 16054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16055 },
16056/* rolc.b ${Dsp-16-s8}[fb] */
16057 {
16058 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24,
6772dd07 16059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16060 },
16061/* rolc.b ${Dsp-16-s16}[fb] */
16062 {
16063 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32,
6772dd07 16064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16065 },
16066/* rolc.b ${Dsp-16-u16} */
16067 {
16068 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32,
6772dd07 16069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16070 },
16071/* rolc.b ${Dsp-16-u24} */
16072 {
16073 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40,
6772dd07 16074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16075 },
16076/* rolc.w $Dst16RnHI */
16077 {
16078 M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16,
6772dd07 16079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16080 },
16081/* rolc.w $Dst16AnHI */
16082 {
16083 M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16,
6772dd07 16084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16085 },
16086/* rolc.w [$Dst16An] */
16087 {
16088 M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16,
6772dd07 16089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16090 },
16091/* rolc.w ${Dsp-16-u8}[$Dst16An] */
16092 {
16093 M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24,
6772dd07 16094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16095 },
16096/* rolc.w ${Dsp-16-u16}[$Dst16An] */
16097 {
16098 M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32,
6772dd07 16099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16100 },
16101/* rolc.w ${Dsp-16-u8}[sb] */
16102 {
16103 M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24,
6772dd07 16104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16105 },
16106/* rolc.w ${Dsp-16-u16}[sb] */
16107 {
16108 M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32,
6772dd07 16109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16110 },
16111/* rolc.w ${Dsp-16-s8}[fb] */
16112 {
16113 M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24,
6772dd07 16114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16115 },
16116/* rolc.w ${Dsp-16-u16} */
16117 {
16118 M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32,
6772dd07 16119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16120 },
16121/* rolc.b $Dst16RnQI */
16122 {
16123 M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16,
6772dd07 16124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16125 },
16126/* rolc.b $Dst16AnQI */
16127 {
16128 M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16,
6772dd07 16129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16130 },
16131/* rolc.b [$Dst16An] */
16132 {
16133 M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16,
6772dd07 16134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16135 },
16136/* rolc.b ${Dsp-16-u8}[$Dst16An] */
16137 {
16138 M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24,
6772dd07 16139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16140 },
16141/* rolc.b ${Dsp-16-u16}[$Dst16An] */
16142 {
16143 M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32,
6772dd07 16144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16145 },
16146/* rolc.b ${Dsp-16-u8}[sb] */
16147 {
16148 M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24,
6772dd07 16149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16150 },
16151/* rolc.b ${Dsp-16-u16}[sb] */
16152 {
16153 M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32,
6772dd07 16154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16155 },
16156/* rolc.b ${Dsp-16-s8}[fb] */
16157 {
16158 M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24,
6772dd07 16159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16160 },
16161/* rolc.b ${Dsp-16-u16} */
16162 {
16163 M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32,
6772dd07 16164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16165 },
16166/* pusha [$Dst32AnUnprefixed] */
16167 {
16168 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16,
6772dd07 16169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16170 },
16171/* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16172 {
16173 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24,
6772dd07 16174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16175 },
16176/* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16177 {
16178 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32,
6772dd07 16179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16180 },
16181/* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16182 {
16183 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40,
6772dd07 16184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16185 },
16186/* pusha ${Dsp-16-u8}[sb] */
16187 {
16188 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24,
6772dd07 16189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16190 },
16191/* pusha ${Dsp-16-u16}[sb] */
16192 {
16193 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32,
6772dd07 16194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16195 },
16196/* pusha ${Dsp-16-s8}[fb] */
16197 {
16198 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24,
6772dd07 16199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16200 },
16201/* pusha ${Dsp-16-s16}[fb] */
16202 {
16203 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32,
6772dd07 16204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16205 },
16206/* pusha ${Dsp-16-u16} */
16207 {
16208 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32,
6772dd07 16209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16210 },
16211/* pusha ${Dsp-16-u24} */
16212 {
16213 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40,
6772dd07 16214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16215 },
16216/* pusha [$Dst16An] */
16217 {
16218 M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16,
6772dd07 16219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16220 },
16221/* pusha ${Dsp-16-u8}[$Dst16An] */
16222 {
16223 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24,
6772dd07 16224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16225 },
16226/* pusha ${Dsp-16-u16}[$Dst16An] */
16227 {
16228 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32,
6772dd07 16229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16230 },
16231/* pusha ${Dsp-16-u8}[sb] */
16232 {
16233 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24,
6772dd07 16234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16235 },
16236/* pusha ${Dsp-16-u16}[sb] */
16237 {
16238 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32,
6772dd07 16239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16240 },
16241/* pusha ${Dsp-16-s8}[fb] */
16242 {
16243 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24,
6772dd07 16244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16245 },
16246/* pusha ${Dsp-16-u16} */
16247 {
16248 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32,
6772dd07 16249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16250 },
16251/* push.l $Dst32RnUnprefixedSI */
16252 {
16253 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16,
6772dd07 16254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16255 },
16256/* push.l $Dst32AnUnprefixedSI */
16257 {
16258 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16,
6772dd07 16259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16260 },
16261/* push.l [$Dst32AnUnprefixed] */
16262 {
16263 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16,
6772dd07 16264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16265 },
16266/* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16267 {
16268 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24,
6772dd07 16269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16270 },
16271/* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16272 {
16273 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32,
6772dd07 16274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16275 },
16276/* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16277 {
16278 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40,
6772dd07 16279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16280 },
16281/* push.l ${Dsp-16-u8}[sb] */
16282 {
16283 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24,
6772dd07 16284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16285 },
16286/* push.l ${Dsp-16-u16}[sb] */
16287 {
16288 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32,
6772dd07 16289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16290 },
16291/* push.l ${Dsp-16-s8}[fb] */
16292 {
16293 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24,
6772dd07 16294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16295 },
16296/* push.l ${Dsp-16-s16}[fb] */
16297 {
16298 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32,
6772dd07 16299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16300 },
16301/* push.l ${Dsp-16-u16} */
16302 {
16303 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32,
6772dd07 16304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16305 },
16306/* push.l ${Dsp-16-u24} */
16307 {
16308 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40,
6772dd07 16309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16310 },
16311/* push.w${S} ${An16-push-S} */
16312 {
16313 M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8,
6772dd07 16314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 16315 },
16316/* push.b${S} ${Rn16-push-S} */
16317 {
16318 M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8,
6772dd07 16319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 16320 },
16321/* push.w $Dst32RnUnprefixedHI */
16322 {
16323 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16,
6772dd07 16324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16325 },
16326/* push.w $Dst32AnUnprefixedHI */
16327 {
16328 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16,
6772dd07 16329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16330 },
16331/* push.w [$Dst32AnUnprefixed] */
16332 {
16333 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16,
6772dd07 16334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16335 },
16336/* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16337 {
16338 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24,
6772dd07 16339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16340 },
16341/* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16342 {
16343 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32,
6772dd07 16344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16345 },
16346/* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16347 {
16348 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40,
6772dd07 16349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16350 },
16351/* push.w ${Dsp-16-u8}[sb] */
16352 {
16353 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24,
6772dd07 16354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16355 },
16356/* push.w ${Dsp-16-u16}[sb] */
16357 {
16358 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32,
6772dd07 16359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16360 },
16361/* push.w ${Dsp-16-s8}[fb] */
16362 {
16363 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24,
6772dd07 16364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16365 },
16366/* push.w ${Dsp-16-s16}[fb] */
16367 {
16368 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32,
6772dd07 16369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16370 },
16371/* push.w ${Dsp-16-u16} */
16372 {
16373 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32,
6772dd07 16374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16375 },
16376/* push.w ${Dsp-16-u24} */
16377 {
16378 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40,
6772dd07 16379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16380 },
16381/* push.b $Dst32RnUnprefixedQI */
16382 {
16383 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16,
6772dd07 16384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16385 },
16386/* push.b $Dst32AnUnprefixedQI */
16387 {
16388 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16,
6772dd07 16389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16390 },
16391/* push.b [$Dst32AnUnprefixed] */
16392 {
16393 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16,
6772dd07 16394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16395 },
16396/* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16397 {
16398 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24,
6772dd07 16399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16400 },
16401/* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16402 {
16403 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32,
6772dd07 16404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16405 },
16406/* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16407 {
16408 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40,
6772dd07 16409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16410 },
16411/* push.b ${Dsp-16-u8}[sb] */
16412 {
16413 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24,
6772dd07 16414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16415 },
16416/* push.b ${Dsp-16-u16}[sb] */
16417 {
16418 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32,
6772dd07 16419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16420 },
16421/* push.b ${Dsp-16-s8}[fb] */
16422 {
16423 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24,
6772dd07 16424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16425 },
16426/* push.b ${Dsp-16-s16}[fb] */
16427 {
16428 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32,
6772dd07 16429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16430 },
16431/* push.b ${Dsp-16-u16} */
16432 {
16433 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32,
6772dd07 16434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16435 },
16436/* push.b ${Dsp-16-u24} */
16437 {
16438 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
6772dd07 16439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16440 },
c6552317 16441/* push.w${G} $Dst16RnHI */
49f58d10
JB		 16442 {
16443 M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
6772dd07 16444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16445 },
c6552317 16446/* push.w${G} $Dst16AnHI */
49f58d10
JB		 16447 {
16448 M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
6772dd07 16449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16450 },
c6552317 16451/* push.w${G} [$Dst16An] */
49f58d10
JB		 16452 {
16453 M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
6772dd07 16454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16455 },
c6552317 16456/* push.w${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 16457 {
16458 M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
6772dd07 16459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16460 },
c6552317 16461/* push.w${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 16462 {
16463 M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
6772dd07 16464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16465 },
c6552317 16466/* push.w${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 16467 {
16468 M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
6772dd07 16469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16470 },
c6552317 16471/* push.w${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 16472 {
16473 M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
6772dd07 16474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16475 },
c6552317 16476/* push.w${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 16477 {
16478 M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
6772dd07 16479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16480 },
c6552317 16481/* push.w${G} ${Dsp-16-u16} */
49f58d10
JB		 16482 {
16483 M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
6772dd07 16484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16485 },
c6552317 16486/* push.b${G} $Dst16RnQI */
49f58d10
JB		 16487 {
16488 M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
6772dd07 16489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16490 },
c6552317 16491/* push.b${G} $Dst16AnQI */
49f58d10
JB		 16492 {
16493 M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
6772dd07 16494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16495 },
c6552317 16496/* push.b${G} [$Dst16An] */
49f58d10
JB		 16497 {
16498 M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
6772dd07 16499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16500 },
c6552317 16501/* push.b${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 16502 {
16503 M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
6772dd07 16504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16505 },
c6552317 16506/* push.b${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 16507 {
16508 M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
6772dd07 16509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16510 },
c6552317 16511/* push.b${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 16512 {
16513 M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
6772dd07 16514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16515 },
c6552317 16516/* push.b${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 16517 {
16518 M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
6772dd07 16519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16520 },
c6552317 16521/* push.b${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 16522 {
16523 M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
6772dd07 16524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 16525 },
c6552317 16526/* push.b${G} ${Dsp-16-u16} */
49f58d10
JB		 16527 {
16528 M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
6772dd07 16529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16530 },
16531/* pop.w${S} ${An16-push-S} */
16532 {
16533 M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8,
6772dd07 16534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 16535 },
16536/* pop.b${S} ${Rn16-push-S} */
16537 {
16538 M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8,
6772dd07 16539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 16540 },
16541/* pop.w $Dst32RnUnprefixedHI */
16542 {
16543 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16,
6772dd07 16544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16545 },
16546/* pop.w $Dst32AnUnprefixedHI */
16547 {
16548 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16,
6772dd07 16549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16550 },
16551/* pop.w [$Dst32AnUnprefixed] */
16552 {
16553 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16,
6772dd07 16554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16555 },
16556/* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16557 {
16558 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24,
6772dd07 16559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16560 },
16561/* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16562 {
16563 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32,
6772dd07 16564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16565 },
16566/* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16567 {
16568 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40,
6772dd07 16569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16570 },
16571/* pop.w ${Dsp-16-u8}[sb] */
16572 {
16573 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24,
6772dd07 16574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16575 },
16576/* pop.w ${Dsp-16-u16}[sb] */
16577 {
16578 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32,
6772dd07 16579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16580 },
16581/* pop.w ${Dsp-16-s8}[fb] */
16582 {
16583 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24,
6772dd07 16584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16585 },
16586/* pop.w ${Dsp-16-s16}[fb] */
16587 {
16588 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32,
6772dd07 16589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16590 },
16591/* pop.w ${Dsp-16-u16} */
16592 {
16593 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32,
6772dd07 16594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16595 },
16596/* pop.w ${Dsp-16-u24} */
16597 {
16598 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40,
6772dd07 16599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16600 },
16601/* pop.b $Dst32RnUnprefixedQI */
16602 {
16603 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16,
6772dd07 16604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16605 },
16606/* pop.b $Dst32AnUnprefixedQI */
16607 {
16608 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16,
6772dd07 16609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16610 },
16611/* pop.b [$Dst32AnUnprefixed] */
16612 {
16613 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16,
6772dd07 16614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16615 },
16616/* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16617 {
16618 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24,
6772dd07 16619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16620 },
16621/* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16622 {
16623 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32,
6772dd07 16624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16625 },
16626/* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16627 {
16628 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40,
6772dd07 16629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16630 },
16631/* pop.b ${Dsp-16-u8}[sb] */
16632 {
16633 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24,
6772dd07 16634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16635 },
16636/* pop.b ${Dsp-16-u16}[sb] */
16637 {
16638 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32,
6772dd07 16639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16640 },
16641/* pop.b ${Dsp-16-s8}[fb] */
16642 {
16643 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24,
6772dd07 16644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16645 },
16646/* pop.b ${Dsp-16-s16}[fb] */
16647 {
16648 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32,
6772dd07 16649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16650 },
16651/* pop.b ${Dsp-16-u16} */
16652 {
16653 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32,
6772dd07 16654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16655 },
16656/* pop.b ${Dsp-16-u24} */
16657 {
16658 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40,
6772dd07 16659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16660 },
16661/* pop.w $Dst16RnHI */
16662 {
16663 M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16,
6772dd07 16664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16665 },
16666/* pop.w $Dst16AnHI */
16667 {
16668 M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16,
6772dd07 16669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16670 },
16671/* pop.w [$Dst16An] */
16672 {
16673 M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16,
6772dd07 16674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16675 },
16676/* pop.w ${Dsp-16-u8}[$Dst16An] */
16677 {
16678 M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24,
6772dd07 16679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16680 },
16681/* pop.w ${Dsp-16-u16}[$Dst16An] */
16682 {
16683 M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32,
6772dd07 16684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16685 },
16686/* pop.w ${Dsp-16-u8}[sb] */
16687 {
16688 M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24,
6772dd07 16689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16690 },
16691/* pop.w ${Dsp-16-u16}[sb] */
16692 {
16693 M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32,
6772dd07 16694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16695 },
16696/* pop.w ${Dsp-16-s8}[fb] */
16697 {
16698 M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24,
6772dd07 16699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16700 },
16701/* pop.w ${Dsp-16-u16} */
16702 {
16703 M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32,
6772dd07 16704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16705 },
16706/* pop.b $Dst16RnQI */
16707 {
16708 M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16,
6772dd07 16709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16710 },
16711/* pop.b $Dst16AnQI */
16712 {
16713 M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16,
6772dd07 16714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16715 },
16716/* pop.b [$Dst16An] */
16717 {
16718 M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16,
6772dd07 16719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16720 },
16721/* pop.b ${Dsp-16-u8}[$Dst16An] */
16722 {
16723 M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24,
6772dd07 16724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16725 },
16726/* pop.b ${Dsp-16-u16}[$Dst16An] */
16727 {
16728 M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32,
6772dd07 16729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16730 },
16731/* pop.b ${Dsp-16-u8}[sb] */
16732 {
16733 M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24,
6772dd07 16734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16735 },
16736/* pop.b ${Dsp-16-u16}[sb] */
16737 {
16738 M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32,
6772dd07 16739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16740 },
16741/* pop.b ${Dsp-16-s8}[fb] */
16742 {
16743 M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24,
6772dd07 16744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16745 },
16746/* pop.b ${Dsp-16-u16} */
16747 {
16748 M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32,
6772dd07 16749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 16750 },
16751/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16752 {
16753 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
6772dd07 16754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16755 },
16756/* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
16757 {
16758 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
6772dd07 16759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16760 },
16761/* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
16762 {
16763 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
6772dd07 16764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16765 },
16766/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16767 {
16768 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
6772dd07 16769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16770 },
16771/* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
16772 {
16773 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
6772dd07 16774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16775 },
16776/* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
16777 {
16778 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
6772dd07 16779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16780 },
16781/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16782 {
16783 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
6772dd07 16784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16785 },
16786/* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16787 {
16788 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
6772dd07 16789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16790 },
16791/* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16792 {
16793 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
6772dd07 16794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16795 },
16796/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16797 {
16798 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16800 },
16801/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16802 {
16803 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16805 },
16806/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16807 {
16808 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16810 },
16811/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16812 {
16813 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16815 },
16816/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16817 {
16818 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16820 },
16821/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16822 {
16823 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16825 },
16826/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16827 {
16828 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 16829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16830 },
16831/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16832 {
16833 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 16834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16835 },
16836/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16837 {
16838 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 16839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16840 },
16841/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
16842 {
16843 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16845 },
16846/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16847 {
16848 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16850 },
16851/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16852 {
16853 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16855 },
16856/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
16857 {
16858 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16860 },
16861/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16862 {
16863 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16865 },
16866/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16867 {
16868 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16870 },
16871/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
16872 {
16873 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16875 },
16876/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16877 {
16878 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16880 },
16881/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16882 {
16883 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 16884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16885 },
16886/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
16887 {
16888 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16890 },
16891/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
16892 {
16893 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16895 },
16896/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
16897 {
16898 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16900 },
16901/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
16902 {
16903 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
6772dd07 16904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16905 },
16906/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16907 {
16908 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
6772dd07 16909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16910 },
16911/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16912 {
16913 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
6772dd07 16914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16915 },
16916/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
16917 {
16918 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 16919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16920 },
16921/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
16922 {
16923 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 16924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16925 },
16926/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
16927 {
16928 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 16929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16930 },
16931/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16932 {
16933 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16935 },
16936/* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
16937 {
16938 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16940 },
16941/* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
16942 {
16943 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16945 },
16946/* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
16947 {
16948 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16950 },
16951/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16952 {
16953 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16955 },
16956/* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
16957 {
16958 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16960 },
16961/* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
16962 {
16963 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16965 },
16966/* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
16967 {
16968 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
6772dd07 16969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16970 },
16971/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16972 {
16973 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
6772dd07 16974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16975 },
16976/* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
16977 {
16978 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
6772dd07 16979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16980 },
16981/* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
16982 {
16983 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
6772dd07 16984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16985 },
16986/* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
16987 {
16988 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
6772dd07 16989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16990 },
16991/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16992 {
16993 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 16995 },
16996/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16997 {
16998 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 16999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17000 },
17001/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17002 {
17003 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17005 },
17006/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17007 {
17008 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17010 },
17011/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17012 {
17013 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17015 },
17016/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17017 {
17018 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17020 },
17021/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17022 {
17023 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17025 },
17026/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17027 {
17028 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17030 },
17031/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17032 {
17033 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17035 },
17036/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17037 {
17038 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17040 },
17041/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17042 {
17043 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17045 },
17046/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17047 {
17048 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17050 },
17051/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17052 {
17053 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17055 },
17056/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17057 {
17058 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17060 },
17061/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17062 {
17063 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17065 },
17066/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17067 {
17068 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17070 },
17071/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17072 {
17073 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17075 },
17076/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17077 {
17078 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17080 },
17081/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17082 {
17083 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17085 },
17086/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17087 {
17088 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17090 },
17091/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17092 {
17093 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17095 },
17096/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17097 {
17098 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17100 },
17101/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17102 {
17103 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17105 },
17106/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17107 {
17108 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17110 },
17111/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17112 {
17113 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17115 },
17116/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17117 {
17118 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17120 },
17121/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17122 {
17123 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17125 },
17126/* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17127 {
17128 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17130 },
17131/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17132 {
17133 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 17134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17135 },
17136/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17137 {
17138 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 17139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17140 },
17141/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17142 {
17143 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 17144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17145 },
17146/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
17147 {
17148 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 17149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17150 },
17151/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17152 {
17153 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
6772dd07 17154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17155 },
17156/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17157 {
17158 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
6772dd07 17159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17160 },
17161/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17162 {
17163 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
6772dd07 17164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17165 },
17166/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
17167 {
17168 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
6772dd07 17169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17170 },
17171/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17172 {
17173 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
6772dd07 17174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17175 },
17176/* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
17177 {
17178 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
6772dd07 17179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17180 },
17181/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17182 {
17183 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
6772dd07 17184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17185 },
17186/* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
17187 {
17188 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
6772dd07 17189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17190 },
17191/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17192 {
17193 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
6772dd07 17194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17195 },
17196/* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17197 {
17198 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
6772dd07 17199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17200 },
17201/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17202 {
17203 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17205 },
17206/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17207 {
17208 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17210 },
17211/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17212 {
17213 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17215 },
17216/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17217 {
17218 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17220 },
17221/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17222 {
17223 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
6772dd07 17224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17225 },
17226/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17227 {
17228 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
6772dd07 17229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17230 },
17231/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17232 {
17233 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17235 },
17236/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17237 {
17238 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17240 },
17241/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17242 {
17243 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17245 },
17246/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17247 {
17248 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17250 },
17251/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17252 {
17253 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17255 },
17256/* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17257 {
17258 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 17259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17260 },
17261/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17262 {
17263 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17265 },
17266/* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17267 {
17268 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
6772dd07 17269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17270 },
17271/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17272 {
17273 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
6772dd07 17274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17275 },
17276/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
17277 {
17278 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
6772dd07 17279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17280 },
17281/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17282 {
17283 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
6772dd07 17284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17285 },
17286/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
17287 {
17288 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
6772dd07 17289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17290 },
17291/* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
17292 {
17293 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
6772dd07 17294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17295 },
17296/* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
17297 {
17298 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
6772dd07 17299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17300 },
17301/* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17302 {
17303 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
6772dd07 17304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17305 },
17306/* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
17307 {
17308 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
6772dd07 17309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17310 },
17311/* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
17312 {
17313 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
6772dd07 17314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17315 },
17316/* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17317 {
17318 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
6772dd07 17319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17320 },
17321/* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
17322 {
17323 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
6772dd07 17324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17325 },
17326/* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
17327 {
17328 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
6772dd07 17329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17330 },
17331/* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17332 {
17333 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
6772dd07 17334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17335 },
17336/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17337 {
17338 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17340 },
17341/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17342 {
17343 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17345 },
17346/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17347 {
17348 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17350 },
17351/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17352 {
17353 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17355 },
17356/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17357 {
17358 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17360 },
17361/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17362 {
17363 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17365 },
17366/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17367 {
17368 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17370 },
17371/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17372 {
17373 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17375 },
17376/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17377 {
17378 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 17379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17380 },
17381/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
17382 {
17383 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17385 },
17386/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
17387 {
17388 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17390 },
17391/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17392 {
17393 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17395 },
17396/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
17397 {
17398 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17400 },
17401/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
17402 {
17403 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17405 },
17406/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17407 {
17408 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17410 },
17411/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
17412 {
17413 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17415 },
17416/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
17417 {
17418 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17420 },
17421/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17422 {
17423 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
6772dd07 17424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17425 },
17426/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
17427 {
17428 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17430 },
17431/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
17432 {
17433 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17435 },
17436/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17437 {
17438 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
6772dd07 17439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17440 },
17441/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
17442 {
17443 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
6772dd07 17444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17445 },
17446/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
17447 {
17448 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
6772dd07 17449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17450 },
17451/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17452 {
17453 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
6772dd07 17454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17455 },
17456/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
17457 {
17458 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
6772dd07 17459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17460 },
17461/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
17462 {
17463 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
6772dd07 17464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17465 },
17466/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17467 {
17468 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
6772dd07 17469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17470 },
17471/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17472 {
17473 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
6772dd07 17474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17475 },
17476/* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
17477 {
17478 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
6772dd07 17479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17480 },
17481/* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
17482 {
17483 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
6772dd07 17484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17485 },
17486/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17487 {
17488 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
6772dd07 17489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17490 },
17491/* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
17492 {
17493 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
6772dd07 17494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17495 },
17496/* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
17497 {
17498 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
6772dd07 17499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17500 },
17501/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17502 {
17503 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
6772dd07 17504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17505 },
17506/* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
17507 {
17508 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
6772dd07 17509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17510 },
17511/* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
17512 {
17513 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
6772dd07 17514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17515 },
17516/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17517 {
17518 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17520 },
17521/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17522 {
17523 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17525 },
17526/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17527 {
17528 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17530 },
17531/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17532 {
17533 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17535 },
17536/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17537 {
17538 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17540 },
17541/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17542 {
17543 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17545 },
17546/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17547 {
17548 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17550 },
17551/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17552 {
17553 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17555 },
17556/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17557 {
17558 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17560 },
17561/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
17562 {
17563 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17565 },
17566/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
17567 {
17568 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17570 },
17571/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
17572 {
17573 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17575 },
17576/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
17577 {
17578 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17580 },
17581/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
17582 {
17583 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17585 },
17586/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
17587 {
17588 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17590 },
17591/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
17592 {
17593 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17595 },
17596/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
17597 {
17598 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17600 },
17601/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
17602 {
17603 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 17604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17605 },
17606/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
17607 {
17608 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17610 },
17611/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
17612 {
17613 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17615 },
17616/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
17617 {
17618 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17620 },
17621/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
17622 {
17623 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
6772dd07 17624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17625 },
17626/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
17627 {
17628 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
6772dd07 17629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17630 },
17631/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
17632 {
17633 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
6772dd07 17634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17635 },
17636/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
17637 {
17638 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 17639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17640 },
17641/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
17642 {
17643 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 17644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17645 },
17646/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
17647 {
17648 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 17649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17650 },
17651/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17652 {
17653 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17655 },
17656/* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
17657 {
17658 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17660 },
17661/* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
17662 {
17663 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17665 },
17666/* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
17667 {
17668 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17670 },
17671/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17672 {
17673 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17675 },
17676/* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
17677 {
17678 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17680 },
17681/* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
17682 {
17683 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17685 },
17686/* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
17687 {
17688 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
6772dd07 17689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17690 },
17691/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17692 {
17693 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
6772dd07 17694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17695 },
17696/* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17697 {
17698 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
6772dd07 17699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17700 },
17701/* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17702 {
17703 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
6772dd07 17704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17705 },
17706/* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17707 {
17708 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
6772dd07 17709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17710 },
17711/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17712 {
17713 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17715 },
17716/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17717 {
17718 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17720 },
17721/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17722 {
17723 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17725 },
17726/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17727 {
17728 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17730 },
17731/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17732 {
17733 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17735 },
17736/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17737 {
17738 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17740 },
17741/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17742 {
17743 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17745 },
17746/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17747 {
17748 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17750 },
17751/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17752 {
17753 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17755 },
17756/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17757 {
17758 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17760 },
17761/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17762 {
17763 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17765 },
17766/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17767 {
17768 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17770 },
17771/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17772 {
17773 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17775 },
17776/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17777 {
17778 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17780 },
17781/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17782 {
17783 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17785 },
17786/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17787 {
17788 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17790 },
17791/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17792 {
17793 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17795 },
17796/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17797 {
17798 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17800 },
17801/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17802 {
17803 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17805 },
17806/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17807 {
17808 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17810 },
17811/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17812 {
17813 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17815 },
17816/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17817 {
17818 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17820 },
17821/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17822 {
17823 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17825 },
17826/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17827 {
17828 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 17829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17830 },
17831/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17832 {
17833 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17835 },
17836/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17837 {
17838 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17840 },
17841/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17842 {
17843 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17845 },
17846/* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17847 {
17848 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17850 },
17851/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17852 {
17853 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 17854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17855 },
17856/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17857 {
17858 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 17859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17860 },
17861/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17862 {
17863 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 17864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17865 },
17866/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
17867 {
17868 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 17869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17870 },
17871/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17872 {
17873 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
6772dd07 17874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17875 },
17876/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17877 {
17878 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
6772dd07 17879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17880 },
17881/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17882 {
17883 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
6772dd07 17884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17885 },
17886/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
17887 {
17888 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
6772dd07 17889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17890 },
17891/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17892 {
17893 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
6772dd07 17894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17895 },
17896/* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
17897 {
17898 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
6772dd07 17899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17900 },
17901/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17902 {
17903 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
6772dd07 17904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17905 },
17906/* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
17907 {
17908 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
6772dd07 17909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17910 },
17911/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17912 {
17913 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
6772dd07 17914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17915 },
17916/* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17917 {
17918 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
6772dd07 17919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17920 },
17921/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17922 {
17923 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17925 },
17926/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17927 {
17928 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17930 },
17931/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17932 {
17933 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17935 },
17936/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17937 {
17938 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17940 },
17941/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17942 {
17943 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
6772dd07 17944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17945 },
17946/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17947 {
17948 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
6772dd07 17949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17950 },
17951/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17952 {
17953 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17955 },
17956/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17957 {
17958 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17960 },
17961/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17962 {
17963 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17965 },
17966/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17967 {
17968 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17970 },
17971/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17972 {
17973 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17975 },
17976/* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17977 {
17978 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
6772dd07 17979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17980 },
17981/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17982 {
17983 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17985 },
17986/* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17987 {
17988 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
6772dd07 17989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17990 },
17991/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17992 {
17993 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
6772dd07 17994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 17995 },
17996/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
17997 {
17998 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
6772dd07 17999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18000 },
18001/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
18002 {
18003 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
6772dd07 18004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18005 },
18006/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
18007 {
18008 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
6772dd07 18009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18010 },
18011/* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
18012 {
18013 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
6772dd07 18014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18015 },
18016/* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
18017 {
18018 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
6772dd07 18019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18020 },
18021/* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
18022 {
18023 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
6772dd07 18024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18025 },
18026/* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
18027 {
18028 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
6772dd07 18029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18030 },
18031/* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
18032 {
18033 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
6772dd07 18034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18035 },
18036/* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
18037 {
18038 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
6772dd07 18039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18040 },
18041/* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
18042 {
18043 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
6772dd07 18044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18045 },
18046/* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
18047 {
18048 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
6772dd07 18049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18050 },
18051/* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
18052 {
18053 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
6772dd07 18054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18055 },
18056/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18057 {
18058 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18060 },
18061/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18062 {
18063 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18065 },
18066/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
18067 {
18068 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18070 },
18071/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18072 {
18073 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18075 },
18076/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18077 {
18078 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18080 },
18081/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
18082 {
18083 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18085 },
18086/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18087 {
18088 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 18089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18090 },
18091/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18092 {
18093 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 18094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18095 },
18096/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
18097 {
18098 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 18099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18100 },
18101/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
18102 {
18103 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18105 },
18106/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
18107 {
18108 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18110 },
18111/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
18112 {
18113 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18115 },
18116/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
18117 {
18118 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18120 },
18121/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
18122 {
18123 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18125 },
18126/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
18127 {
18128 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18130 },
18131/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
18132 {
18133 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18135 },
18136/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
18137 {
18138 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18140 },
18141/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
18142 {
18143 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
6772dd07 18144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18145 },
18146/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
18147 {
18148 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18150 },
18151/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
18152 {
18153 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18155 },
18156/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
18157 {
18158 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 18159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18160 },
18161/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
18162 {
18163 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
6772dd07 18164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18165 },
18166/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
18167 {
18168 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
6772dd07 18169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18170 },
18171/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
18172 {
18173 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
6772dd07 18174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18175 },
18176/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
18177 {
18178 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
6772dd07 18179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18180 },
18181/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
18182 {
18183 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
6772dd07 18184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18185 },
18186/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
18187 {
18188 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
6772dd07 18189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18190 },
18191/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
18192 {
18193 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
6772dd07 18194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18195 },
18196/* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
18197 {
18198 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
6772dd07 18199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18200 },
18201/* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
18202 {
18203 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
6772dd07 18204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18205 },
18206/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
18207 {
18208 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24,
6772dd07 18209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18210 },
18211/* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
18212 {
18213 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24,
6772dd07 18214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18215 },
18216/* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
18217 {
18218 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24,
6772dd07 18219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18220 },
18221/* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18222 {
18223 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24,
6772dd07 18224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18225 },
18226/* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18227 {
18228 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
6772dd07 18229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18230 },
18231/* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18232 {
18233 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
6772dd07 18234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18235 },
18236/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18237 {
18238 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
6772dd07 18239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18240 },
18241/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18242 {
18243 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
6772dd07 18244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18245 },
18246/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18247 {
18248 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
6772dd07 18249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18250 },
18251/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18252 {
18253 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
6772dd07 18254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18255 },
18256/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18257 {
18258 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
6772dd07 18259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18260 },
18261/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18262 {
18263 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
6772dd07 18264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18265 },
18266/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18267 {
18268 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
6772dd07 18269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18270 },
18271/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18272 {
18273 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
6772dd07 18274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18275 },
18276/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18277 {
18278 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
6772dd07 18279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18280 },
18281/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18282 {
18283 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
6772dd07 18284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18285 },
18286/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18287 {
18288 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
6772dd07 18289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18290 },
18291/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18292 {
18293 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
6772dd07 18294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18295 },
18296/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18297 {
18298 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
6772dd07 18299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18300 },
18301/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18302 {
18303 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
6772dd07 18304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18305 },
18306/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18307 {
18308 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
6772dd07 18309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18310 },
18311/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18312 {
18313 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
6772dd07 18314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18315 },
18316/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18317 {
18318 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
6772dd07 18319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18320 },
18321/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18322 {
18323 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
6772dd07 18324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18325 },
18326/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
18327 {
18328 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
6772dd07 18329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18330 },
18331/* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
18332 {
18333 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
6772dd07 18334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18335 },
18336/* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
18337 {
18338 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32,
6772dd07 18339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18340 },
18341/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
18342 {
18343 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32,
6772dd07 18344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18345 },
18346/* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
18347 {
18348 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32,
6772dd07 18349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18350 },
18351/* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
18352 {
18353 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32,
6772dd07 18354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18355 },
18356/* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18357 {
18358 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32,
6772dd07 18359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18360 },
18361/* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18362 {
18363 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32,
6772dd07 18364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18365 },
18366/* or.w${G} ${Dsp-16-u16},[$Dst16An] */
18367 {
18368 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32,
6772dd07 18369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18370 },
18371/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18372 {
18373 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
6772dd07 18374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18375 },
18376/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18377 {
18378 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
6772dd07 18379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18380 },
18381/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18382 {
18383 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40,
6772dd07 18384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18385 },
18386/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18387 {
18388 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
6772dd07 18389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18390 },
18391/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18392 {
18393 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
6772dd07 18394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18395 },
18396/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18397 {
18398 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48,
6772dd07 18399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18400 },
18401/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18402 {
18403 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
6772dd07 18404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18405 },
18406/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18407 {
18408 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
6772dd07 18409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18410 },
18411/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18412 {
18413 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
6772dd07 18414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18415 },
18416/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18417 {
18418 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
6772dd07 18419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18420 },
18421/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18422 {
18423 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
6772dd07 18424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18425 },
18426/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18427 {
18428 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
6772dd07 18429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18430 },
18431/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18432 {
18433 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
6772dd07 18434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18435 },
18436/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18437 {
18438 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
6772dd07 18439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18440 },
18441/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18442 {
18443 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
6772dd07 18444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18445 },
18446/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18447 {
18448 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
6772dd07 18449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18450 },
18451/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18452 {
18453 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
6772dd07 18454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18455 },
18456/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
18457 {
18458 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48,
6772dd07 18459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18460 },
18461/* or.w${G} $Src16RnHI,$Dst16RnHI */
18462 {
18463 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
6772dd07 18464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18465 },
18466/* or.w${G} $Src16AnHI,$Dst16RnHI */
18467 {
18468 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
6772dd07 18469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18470 },
18471/* or.w${G} [$Src16An],$Dst16RnHI */
18472 {
18473 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16,
6772dd07 18474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18475 },
18476/* or.w${G} $Src16RnHI,$Dst16AnHI */
18477 {
18478 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16,
6772dd07 18479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18480 },
18481/* or.w${G} $Src16AnHI,$Dst16AnHI */
18482 {
18483 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16,
6772dd07 18484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18485 },
18486/* or.w${G} [$Src16An],$Dst16AnHI */
18487 {
18488 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16,
6772dd07 18489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18490 },
18491/* or.w${G} $Src16RnHI,[$Dst16An] */
18492 {
18493 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16,
6772dd07 18494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18495 },
18496/* or.w${G} $Src16AnHI,[$Dst16An] */
18497 {
18498 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16,
6772dd07 18499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18500 },
18501/* or.w${G} [$Src16An],[$Dst16An] */
18502 {
18503 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16,
6772dd07 18504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18505 },
18506/* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
18507 {
18508 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
6772dd07 18509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18510 },
18511/* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
18512 {
18513 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
6772dd07 18514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18515 },
18516/* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18517 {
18518 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24,
6772dd07 18519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18520 },
18521/* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
18522 {
18523 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
6772dd07 18524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18525 },
18526/* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
18527 {
18528 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
6772dd07 18529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18530 },
18531/* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18532 {
18533 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32,
6772dd07 18534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18535 },
18536/* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
18537 {
18538 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
6772dd07 18539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18540 },
18541/* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
18542 {
18543 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
6772dd07 18544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18545 },
18546/* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
18547 {
18548 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
6772dd07 18549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18550 },
18551/* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
18552 {
18553 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
6772dd07 18554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18555 },
18556/* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
18557 {
18558 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
6772dd07 18559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18560 },
18561/* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
18562 {
18563 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
6772dd07 18564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18565 },
18566/* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
18567 {
18568 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
6772dd07 18569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18570 },
18571/* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
18572 {
18573 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
6772dd07 18574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18575 },
18576/* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
18577 {
18578 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
6772dd07 18579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18580 },
18581/* or.w${G} $Src16RnHI,${Dsp-16-u16} */
18582 {
18583 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
6772dd07 18584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18585 },
18586/* or.w${G} $Src16AnHI,${Dsp-16-u16} */
18587 {
18588 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
6772dd07 18589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18590 },
18591/* or.w${G} [$Src16An],${Dsp-16-u16} */
18592 {
18593 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32,
6772dd07 18594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18595 },
18596/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
18597 {
18598 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
6772dd07 18599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18600 },
18601/* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
18602 {
18603 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
6772dd07 18604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18605 },
18606/* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
18607 {
18608 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
6772dd07 18609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18610 },
18611/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
18612 {
18613 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24,
6772dd07 18614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18615 },
18616/* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
18617 {
18618 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24,
6772dd07 18619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18620 },
18621/* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
18622 {
18623 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24,
6772dd07 18624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18625 },
18626/* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18627 {
18628 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24,
6772dd07 18629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18630 },
18631/* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18632 {
18633 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
6772dd07 18634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18635 },
18636/* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18637 {
18638 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
6772dd07 18639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18640 },
18641/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18642 {
18643 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
6772dd07 18644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18645 },
18646/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18647 {
18648 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
6772dd07 18649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18650 },
18651/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18652 {
18653 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
6772dd07 18654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18655 },
18656/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18657 {
18658 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
6772dd07 18659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18660 },
18661/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18662 {
18663 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
6772dd07 18664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18665 },
18666/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18667 {
18668 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
6772dd07 18669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18670 },
18671/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18672 {
18673 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
6772dd07 18674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18675 },
18676/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18677 {
18678 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
6772dd07 18679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18680 },
18681/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18682 {
18683 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
6772dd07 18684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18685 },
18686/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18687 {
18688 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
6772dd07 18689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18690 },
18691/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18692 {
18693 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
6772dd07 18694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18695 },
18696/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18697 {
18698 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
6772dd07 18699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18700 },
18701/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18702 {
18703 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
6772dd07 18704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18705 },
18706/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18707 {
18708 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
6772dd07 18709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18710 },
18711/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18712 {
18713 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
6772dd07 18714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18715 },
18716/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18717 {
18718 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
6772dd07 18719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18720 },
18721/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18722 {
18723 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
6772dd07 18724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18725 },
18726/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18727 {
18728 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
6772dd07 18729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18730 },
18731/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
18732 {
18733 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
6772dd07 18734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18735 },
18736/* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
18737 {
18738 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
6772dd07 18739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18740 },
18741/* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
18742 {
18743 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32,
6772dd07 18744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18745 },
18746/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
18747 {
18748 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32,
6772dd07 18749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18750 },
18751/* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
18752 {
18753 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32,
6772dd07 18754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18755 },
18756/* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
18757 {
18758 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32,
6772dd07 18759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18760 },
18761/* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18762 {
18763 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32,
6772dd07 18764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18765 },
18766/* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18767 {
18768 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32,
6772dd07 18769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18770 },
18771/* or.b${G} ${Dsp-16-u16},[$Dst16An] */
18772 {
18773 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32,
6772dd07 18774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18775 },
18776/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18777 {
18778 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
6772dd07 18779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18780 },
18781/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18782 {
18783 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
6772dd07 18784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18785 },
18786/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18787 {
18788 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40,
6772dd07 18789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18790 },
18791/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18792 {
18793 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
6772dd07 18794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18795 },
18796/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18797 {
18798 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
6772dd07 18799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18800 },
18801/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18802 {
18803 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48,
6772dd07 18804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18805 },
18806/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18807 {
18808 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
6772dd07 18809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18810 },
18811/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18812 {
18813 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
6772dd07 18814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18815 },
18816/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18817 {
18818 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
6772dd07 18819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18820 },
18821/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18822 {
18823 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
6772dd07 18824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18825 },
18826/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18827 {
18828 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
6772dd07 18829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18830 },
18831/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18832 {
18833 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
6772dd07 18834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18835 },
18836/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18837 {
18838 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
6772dd07 18839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18840 },
18841/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18842 {
18843 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
6772dd07 18844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18845 },
18846/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18847 {
18848 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
6772dd07 18849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18850 },
18851/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18852 {
18853 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
6772dd07 18854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18855 },
18856/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18857 {
18858 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
6772dd07 18859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18860 },
18861/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
18862 {
18863 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48,
6772dd07 18864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18865 },
18866/* or.b${G} $Src16RnQI,$Dst16RnQI */
18867 {
18868 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
6772dd07 18869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18870 },
18871/* or.b${G} $Src16AnQI,$Dst16RnQI */
18872 {
18873 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
6772dd07 18874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18875 },
18876/* or.b${G} [$Src16An],$Dst16RnQI */
18877 {
18878 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16,
6772dd07 18879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18880 },
18881/* or.b${G} $Src16RnQI,$Dst16AnQI */
18882 {
18883 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16,
6772dd07 18884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18885 },
18886/* or.b${G} $Src16AnQI,$Dst16AnQI */
18887 {
18888 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16,
6772dd07 18889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18890 },
18891/* or.b${G} [$Src16An],$Dst16AnQI */
18892 {
18893 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16,
6772dd07 18894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18895 },
18896/* or.b${G} $Src16RnQI,[$Dst16An] */
18897 {
18898 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16,
6772dd07 18899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18900 },
18901/* or.b${G} $Src16AnQI,[$Dst16An] */
18902 {
18903 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16,
6772dd07 18904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18905 },
18906/* or.b${G} [$Src16An],[$Dst16An] */
18907 {
18908 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16,
6772dd07 18909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18910 },
18911/* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
18912 {
18913 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
6772dd07 18914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18915 },
18916/* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
18917 {
18918 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
6772dd07 18919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18920 },
18921/* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18922 {
18923 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24,
6772dd07 18924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18925 },
18926/* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
18927 {
18928 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
6772dd07 18929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18930 },
18931/* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
18932 {
18933 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
6772dd07 18934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18935 },
18936/* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18937 {
18938 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32,
6772dd07 18939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18940 },
18941/* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
18942 {
18943 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
6772dd07 18944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18945 },
18946/* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
18947 {
18948 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
6772dd07 18949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18950 },
18951/* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
18952 {
18953 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
6772dd07 18954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18955 },
18956/* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
18957 {
18958 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
6772dd07 18959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18960 },
18961/* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
18962 {
18963 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
6772dd07 18964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18965 },
18966/* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
18967 {
18968 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
6772dd07 18969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18970 },
18971/* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
18972 {
18973 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
6772dd07 18974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18975 },
18976/* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
18977 {
18978 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
6772dd07 18979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18980 },
18981/* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
18982 {
18983 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
6772dd07 18984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18985 },
18986/* or.b${G} $Src16RnQI,${Dsp-16-u16} */
18987 {
18988 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
6772dd07 18989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18990 },
18991/* or.b${G} $Src16AnQI,${Dsp-16-u16} */
18992 {
18993 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
6772dd07 18994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 18995 },
18996/* or.b${G} [$Src16An],${Dsp-16-u16} */
18997 {
18998 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32,
6772dd07 18999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19000 },
19001/* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
19002 {
19003 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32,
6772dd07 19004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19005 },
19006/* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
19007 {
19008 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32,
6772dd07 19009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19010 },
19011/* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
19012 {
19013 M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40,
6772dd07 19014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19015 },
19016/* or.w${S} #${Imm-8-HI},r0 */
19017 {
19018 M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24,
6772dd07 19019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19020 },
19021/* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
19022 {
19023 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24,
6772dd07 19024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19025 },
19026/* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
19027 {
19028 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24,
6772dd07 19029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19030 },
19031/* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
19032 {
19033 M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32,
6772dd07 19034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19035 },
19036/* or.b${S} #${Imm-8-QI},r0l */
19037 {
19038 M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16,
6772dd07 19039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19040 },
19041/* or.b${S} #${Imm-8-QI},r0l */
19042 {
19043 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16,
6772dd07 19044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19045 },
19046/* or.b${S} #${Imm-8-QI},r0h */
19047 {
19048 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16,
6772dd07 19049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19050 },
19051/* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
19052 {
19053 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24,
6772dd07 19054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19055 },
19056/* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
19057 {
19058 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24,
6772dd07 19059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19060 },
19061/* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
19062 {
19063 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32,
6772dd07 19064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 19065 },
19066/* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
19067 {
19068 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
6772dd07 19069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19070 },
19071/* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
19072 {
19073 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32,
6772dd07 19074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19075 },
19076/* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
19077 {
19078 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
6772dd07 19079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19080 },
19081/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19082 {
19083 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40,
6772dd07 19084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19085 },
19086/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19087 {
19088 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 19089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19090 },
19091/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19092 {
19093 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40,
6772dd07 19094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19095 },
19096/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19097 {
19098 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48,
6772dd07 19099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19100 },
19101/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19102 {
19103 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 19104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19105 },
19106/* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
19107 {
19108 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48,
6772dd07 19109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19110 },
19111/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19112 {
19113 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48,
6772dd07 19114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19115 },
19116/* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19117 {
19118 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56,
6772dd07 19119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19120 },
19121/* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
19122 {
19123 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56,
6772dd07 19124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19125 },
19126/* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
19127 {
19128 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
6772dd07 19129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19130 },
19131/* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
19132 {
19133 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24,
6772dd07 19134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19135 },
19136/* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19137 {
19138 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
6772dd07 19139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19140 },
19141/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19142 {
19143 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32,
6772dd07 19144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19145 },
19146/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19147 {
19148 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 19149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19150 },
19151/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19152 {
19153 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32,
6772dd07 19154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19155 },
19156/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19157 {
19158 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40,
6772dd07 19159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19160 },
19161/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19162 {
19163 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 19164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19165 },
19166/* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19167 {
19168 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40,
6772dd07 19169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19170 },
19171/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19172 {
19173 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40,
6772dd07 19174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19175 },
19176/* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19177 {
19178 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48,
6772dd07 19179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19180 },
19181/* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
19182 {
19183 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48,
6772dd07 19184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19185 },
19186/* or.w${G} #${Imm-16-HI},$Dst16RnHI */
19187 {
19188 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32,
6772dd07 19189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19190 },
19191/* or.w${G} #${Imm-16-HI},$Dst16AnHI */
19192 {
19193 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32,
6772dd07 19194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19195 },
19196/* or.w${G} #${Imm-16-HI},[$Dst16An] */
19197 {
19198 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32,
6772dd07 19199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19200 },
19201/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
19202 {
19203 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40,
6772dd07 19204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19205 },
19206/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19207 {
19208 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40,
6772dd07 19209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19210 },
19211/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19212 {
19213 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40,
6772dd07 19214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19215 },
19216/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
19217 {
19218 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48,
6772dd07 19219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19220 },
19221/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19222 {
19223 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48,
6772dd07 19224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19225 },
19226/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19227 {
19228 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48,
6772dd07 19229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19230 },
19231/* or.b${G} #${Imm-16-QI},$Dst16RnQI */
19232 {
19233 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24,
6772dd07 19234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19235 },
19236/* or.b${G} #${Imm-16-QI},$Dst16AnQI */
19237 {
19238 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24,
6772dd07 19239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19240 },
19241/* or.b${G} #${Imm-16-QI},[$Dst16An] */
19242 {
19243 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24,
6772dd07 19244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19245 },
19246/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
19247 {
19248 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32,
6772dd07 19249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19250 },
19251/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19252 {
19253 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32,
6772dd07 19254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19255 },
19256/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19257 {
19258 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32,
6772dd07 19259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19260 },
19261/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
19262 {
19263 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40,
6772dd07 19264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19265 },
19266/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19267 {
19268 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40,
6772dd07 19269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19270 },
19271/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19272 {
19273 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
6772dd07 19274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19275 },
c6552317
DD		 19276/* not.b:s r0l */
19277 {
19278 M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI, "not16.b.s-dst16-3-S-R0l-direct-QI", "not.b:s", 8,
6772dd07 19279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
c6552317
DD		 19280 },
19281/* not.b:s r0h */
19282 {
19283 M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, "not16.b.s-dst16-3-S-R0h-direct-QI", "not.b:s", 8,
6772dd07 19284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
c6552317
DD		 19285 },
19286/* not.b:s ${Dsp-8-u8}[sb] */
19287 {
19288 M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-SB-relative-QI", "not.b:s", 16,
6772dd07 19289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
c6552317
DD		 19290 },
19291/* not.b:s ${Dsp-8-s8}[fb] */
19292 {
19293 M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-FB-relative-QI", "not.b:s", 16,
6772dd07 19294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
c6552317
DD		 19295 },
19296/* not.b:s ${Dsp-8-u16} */
19297 {
19298 M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI, "not16.b.s-dst16-3-S-8-16-absolute-QI", "not.b:s", 24,
6772dd07 19299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
c6552317
DD		 19300 },
19301/* not.w${G} $Dst32RnUnprefixedHI */
49f58d10
JB		 19302 {
19303 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
6772dd07 19304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19305 },
c6552317 19306/* not.w${G} $Dst32AnUnprefixedHI */
49f58d10
JB		 19307 {
19308 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
6772dd07 19309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19310 },
c6552317 19311/* not.w${G} [$Dst32AnUnprefixed] */
49f58d10
JB		 19312 {
19313 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
6772dd07 19314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19315 },
c6552317 19316/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 19317 {
19318 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
6772dd07 19319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19320 },
c6552317 19321/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 19322 {
19323 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
6772dd07 19324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19325 },
c6552317 19326/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 19327 {
19328 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
6772dd07 19329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19330 },
c6552317 19331/* not.w${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 19332 {
19333 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
6772dd07 19334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19335 },
c6552317 19336/* not.w${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 19337 {
19338 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
6772dd07 19339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19340 },
c6552317 19341/* not.w${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 19342 {
19343 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
6772dd07 19344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19345 },
c6552317 19346/* not.w${G} ${Dsp-16-s16}[fb] */
49f58d10
JB		 19347 {
19348 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
6772dd07 19349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19350 },
c6552317 19351/* not.w${G} ${Dsp-16-u16} */
49f58d10
JB		 19352 {
19353 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
6772dd07 19354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19355 },
c6552317 19356/* not.w${G} ${Dsp-16-u24} */
49f58d10
JB		 19357 {
19358 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
6772dd07 19359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19360 },
c6552317 19361/* not.b${G} $Dst32RnUnprefixedQI */
49f58d10
JB		 19362 {
19363 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
6772dd07 19364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19365 },
c6552317 19366/* not.b${G} $Dst32AnUnprefixedQI */
49f58d10
JB		 19367 {
19368 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
6772dd07 19369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19370 },
c6552317 19371/* not.b${G} [$Dst32AnUnprefixed] */
49f58d10
JB		 19372 {
19373 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
6772dd07 19374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19375 },
c6552317 19376/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 19377 {
19378 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
6772dd07 19379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19380 },
c6552317 19381/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 19382 {
19383 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
6772dd07 19384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19385 },
c6552317 19386/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 19387 {
19388 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
6772dd07 19389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19390 },
c6552317 19391/* not.b${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 19392 {
19393 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
6772dd07 19394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19395 },
c6552317 19396/* not.b${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 19397 {
19398 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
6772dd07 19399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19400 },
c6552317 19401/* not.b${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 19402 {
19403 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
6772dd07 19404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19405 },
c6552317 19406/* not.b${G} ${Dsp-16-s16}[fb] */
49f58d10
JB		 19407 {
19408 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
6772dd07 19409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19410 },
c6552317 19411/* not.b${G} ${Dsp-16-u16} */
49f58d10
JB		 19412 {
19413 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
6772dd07 19414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19415 },
c6552317 19416/* not.b${G} ${Dsp-16-u24} */
49f58d10
JB		 19417 {
19418 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
6772dd07 19419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19420 },
c6552317 19421/* not.w${G} $Dst16RnHI */
49f58d10
JB		 19422 {
19423 M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
6772dd07 19424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19425 },
c6552317 19426/* not.w${G} $Dst16AnHI */
49f58d10
JB		 19427 {
19428 M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
6772dd07 19429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19430 },
c6552317 19431/* not.w${G} [$Dst16An] */
49f58d10
JB		 19432 {
19433 M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
6772dd07 19434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19435 },
c6552317 19436/* not.w${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 19437 {
19438 M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
6772dd07 19439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19440 },
c6552317 19441/* not.w${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 19442 {
19443 M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
6772dd07 19444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19445 },
c6552317 19446/* not.w${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 19447 {
19448 M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
6772dd07 19449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19450 },
c6552317 19451/* not.w${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 19452 {
19453 M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
6772dd07 19454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19455 },
c6552317 19456/* not.w${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 19457 {
19458 M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
6772dd07 19459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19460 },
c6552317 19461/* not.w${G} ${Dsp-16-u16} */
49f58d10
JB		 19462 {
19463 M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
6772dd07 19464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19465 },
c6552317 19466/* not.b${G} $Dst16RnQI */
49f58d10
JB		 19467 {
19468 M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
6772dd07 19469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19470 },
c6552317 19471/* not.b${G} $Dst16AnQI */
49f58d10
JB		 19472 {
19473 M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
6772dd07 19474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19475 },
c6552317 19476/* not.b${G} [$Dst16An] */
49f58d10
JB		 19477 {
19478 M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
6772dd07 19479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19480 },
c6552317 19481/* not.b${G} ${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 19482 {
19483 M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
6772dd07 19484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19485 },
c6552317 19486/* not.b${G} ${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 19487 {
19488 M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
6772dd07 19489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19490 },
c6552317 19491/* not.b${G} ${Dsp-16-u8}[sb] */
49f58d10
JB		 19492 {
19493 M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
6772dd07 19494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19495 },
c6552317 19496/* not.b${G} ${Dsp-16-u16}[sb] */
49f58d10
JB		 19497 {
19498 M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
6772dd07 19499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19500 },
c6552317 19501/* not.b${G} ${Dsp-16-s8}[fb] */
49f58d10
JB		 19502 {
19503 M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
6772dd07 19504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 19505 },
c6552317 19506/* not.b${G} ${Dsp-16-u16} */
49f58d10
JB		 19507 {
19508 M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
6772dd07 19509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19510 },
19511/* neg.w $Dst32RnUnprefixedHI */
19512 {
19513 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16,
6772dd07 19514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19515 },
19516/* neg.w $Dst32AnUnprefixedHI */
19517 {
19518 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16,
6772dd07 19519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19520 },
19521/* neg.w [$Dst32AnUnprefixed] */
19522 {
19523 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16,
6772dd07 19524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19525 },
19526/* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19527 {
19528 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24,
6772dd07 19529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19530 },
19531/* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19532 {
19533 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32,
6772dd07 19534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19535 },
19536/* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19537 {
19538 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40,
6772dd07 19539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19540 },
19541/* neg.w ${Dsp-16-u8}[sb] */
19542 {
19543 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24,
6772dd07 19544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19545 },
19546/* neg.w ${Dsp-16-u16}[sb] */
19547 {
19548 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32,
6772dd07 19549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19550 },
19551/* neg.w ${Dsp-16-s8}[fb] */
19552 {
19553 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24,
6772dd07 19554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19555 },
19556/* neg.w ${Dsp-16-s16}[fb] */
19557 {
19558 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32,
6772dd07 19559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19560 },
19561/* neg.w ${Dsp-16-u16} */
19562 {
19563 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32,
6772dd07 19564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19565 },
19566/* neg.w ${Dsp-16-u24} */
19567 {
19568 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40,
6772dd07 19569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19570 },
19571/* neg.b $Dst32RnUnprefixedQI */
19572 {
19573 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16,
6772dd07 19574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19575 },
19576/* neg.b $Dst32AnUnprefixedQI */
19577 {
19578 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16,
6772dd07 19579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19580 },
19581/* neg.b [$Dst32AnUnprefixed] */
19582 {
19583 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16,
6772dd07 19584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19585 },
19586/* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19587 {
19588 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24,
6772dd07 19589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19590 },
19591/* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19592 {
19593 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32,
6772dd07 19594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19595 },
19596/* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19597 {
19598 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40,
6772dd07 19599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19600 },
19601/* neg.b ${Dsp-16-u8}[sb] */
19602 {
19603 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24,
6772dd07 19604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19605 },
19606/* neg.b ${Dsp-16-u16}[sb] */
19607 {
19608 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32,
6772dd07 19609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19610 },
19611/* neg.b ${Dsp-16-s8}[fb] */
19612 {
19613 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24,
6772dd07 19614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19615 },
19616/* neg.b ${Dsp-16-s16}[fb] */
19617 {
19618 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32,
6772dd07 19619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19620 },
19621/* neg.b ${Dsp-16-u16} */
19622 {
19623 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32,
6772dd07 19624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19625 },
19626/* neg.b ${Dsp-16-u24} */
19627 {
19628 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40,
6772dd07 19629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19630 },
19631/* neg.w $Dst16RnHI */
19632 {
19633 M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16,
6772dd07 19634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19635 },
19636/* neg.w $Dst16AnHI */
19637 {
19638 M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16,
6772dd07 19639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19640 },
19641/* neg.w [$Dst16An] */
19642 {
19643 M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16,
6772dd07 19644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19645 },
19646/* neg.w ${Dsp-16-u8}[$Dst16An] */
19647 {
19648 M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24,
6772dd07 19649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19650 },
19651/* neg.w ${Dsp-16-u16}[$Dst16An] */
19652 {
19653 M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32,
6772dd07 19654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19655 },
19656/* neg.w ${Dsp-16-u8}[sb] */
19657 {
19658 M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24,
6772dd07 19659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19660 },
19661/* neg.w ${Dsp-16-u16}[sb] */
19662 {
19663 M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32,
6772dd07 19664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19665 },
19666/* neg.w ${Dsp-16-s8}[fb] */
19667 {
19668 M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24,
6772dd07 19669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19670 },
19671/* neg.w ${Dsp-16-u16} */
19672 {
19673 M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32,
6772dd07 19674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19675 },
19676/* neg.b $Dst16RnQI */
19677 {
19678 M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16,
6772dd07 19679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19680 },
19681/* neg.b $Dst16AnQI */
19682 {
19683 M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16,
6772dd07 19684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19685 },
19686/* neg.b [$Dst16An] */
19687 {
19688 M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16,
6772dd07 19689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19690 },
19691/* neg.b ${Dsp-16-u8}[$Dst16An] */
19692 {
19693 M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24,
6772dd07 19694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19695 },
19696/* neg.b ${Dsp-16-u16}[$Dst16An] */
19697 {
19698 M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32,
6772dd07 19699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19700 },
19701/* neg.b ${Dsp-16-u8}[sb] */
19702 {
19703 M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24,
6772dd07 19704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19705 },
19706/* neg.b ${Dsp-16-u16}[sb] */
19707 {
19708 M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32,
6772dd07 19709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19710 },
19711/* neg.b ${Dsp-16-s8}[fb] */
19712 {
19713 M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24,
6772dd07 19714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19715 },
19716/* neg.b ${Dsp-16-u16} */
19717 {
19718 M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32,
6772dd07 19719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 19720 },
19721/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19722 {
19723 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
6772dd07 19724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19725 },
19726/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
19727 {
19728 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
6772dd07 19729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19730 },
19731/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
19732 {
19733 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
6772dd07 19734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19735 },
19736/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19737 {
19738 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
6772dd07 19739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19740 },
19741/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
19742 {
19743 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
6772dd07 19744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19745 },
19746/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
19747 {
19748 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
6772dd07 19749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19750 },
19751/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19752 {
19753 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
6772dd07 19754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19755 },
19756/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
19757 {
19758 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
6772dd07 19759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19760 },
19761/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
19762 {
19763 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
6772dd07 19764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19765 },
19766/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19767 {
19768 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19770 },
19771/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19772 {
19773 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19775 },
19776/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19777 {
19778 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19780 },
19781/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19782 {
19783 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19785 },
19786/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19787 {
19788 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19790 },
19791/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19792 {
19793 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19795 },
19796/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19797 {
19798 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 19799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19800 },
19801/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19802 {
19803 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 19804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19805 },
19806/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19807 {
19808 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 19809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19810 },
19811/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
19812 {
19813 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19815 },
19816/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
19817 {
19818 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19820 },
19821/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
19822 {
19823 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19825 },
19826/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
19827 {
19828 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19830 },
19831/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
19832 {
19833 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19835 },
19836/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
19837 {
19838 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19840 },
19841/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
19842 {
19843 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19845 },
19846/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
19847 {
19848 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19850 },
19851/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
19852 {
19853 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 19854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19855 },
19856/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
19857 {
19858 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19860 },
19861/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
19862 {
19863 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19865 },
19866/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
19867 {
19868 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19870 },
19871/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
19872 {
19873 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
6772dd07 19874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19875 },
19876/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
19877 {
19878 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
6772dd07 19879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19880 },
19881/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
19882 {
19883 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
6772dd07 19884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19885 },
19886/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
19887 {
19888 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 19889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19890 },
19891/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
19892 {
19893 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 19894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19895 },
19896/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
19897 {
19898 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 19899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19900 },
19901/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19902 {
19903 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19905 },
19906/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
19907 {
19908 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19910 },
19911/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
19912 {
19913 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19915 },
19916/* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
19917 {
19918 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19920 },
19921/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19922 {
19923 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19925 },
19926/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
19927 {
19928 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19930 },
19931/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
19932 {
19933 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19935 },
19936/* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
19937 {
19938 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 19939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19940 },
19941/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19942 {
19943 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
6772dd07 19944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19945 },
19946/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
19947 {
19948 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
6772dd07 19949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19950 },
19951/* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
19952 {
19953 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
6772dd07 19954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19955 },
19956/* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
19957 {
19958 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
6772dd07 19959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19960 },
19961/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19962 {
19963 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19965 },
19966/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19967 {
19968 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19970 },
19971/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19972 {
19973 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19975 },
19976/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
19977 {
19978 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 19979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19980 },
19981/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19982 {
19983 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 19984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19985 },
19986/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19987 {
19988 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 19989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19990 },
19991/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19992 {
19993 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 19994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 19995 },
19996/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
19997 {
19998 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 19999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20000 },
20001/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20002 {
20003 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20005 },
20006/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20007 {
20008 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20010 },
20011/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20012 {
20013 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20015 },
20016/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
20017 {
20018 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20020 },
20021/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
20022 {
20023 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20025 },
20026/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
20027 {
20028 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20030 },
20031/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20032 {
20033 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20035 },
20036/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20037 {
20038 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20040 },
20041/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20042 {
20043 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20045 },
20046/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20047 {
20048 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20050 },
20051/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20052 {
20053 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20055 },
20056/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20057 {
20058 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20060 },
20061/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20062 {
20063 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20065 },
20066/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20067 {
20068 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20070 },
20071/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20072 {
20073 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20075 },
20076/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20077 {
20078 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20080 },
20081/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20082 {
20083 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20085 },
20086/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20087 {
20088 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20090 },
20091/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20092 {
20093 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20095 },
20096/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20097 {
20098 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20100 },
20101/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20102 {
20103 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 20104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20105 },
20106/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20107 {
20108 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 20109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20110 },
20111/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20112 {
20113 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 20114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20115 },
20116/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
20117 {
20118 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 20119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20120 },
20121/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20122 {
20123 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
6772dd07 20124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20125 },
20126/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20127 {
20128 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
6772dd07 20129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20130 },
20131/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20132 {
20133 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
6772dd07 20134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20135 },
20136/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
20137 {
20138 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
6772dd07 20139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20140 },
20141/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20142 {
20143 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
6772dd07 20144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20145 },
20146/* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
20147 {
20148 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
6772dd07 20149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20150 },
20151/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20152 {
20153 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
6772dd07 20154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20155 },
20156/* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
20157 {
20158 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
6772dd07 20159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20160 },
20161/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20162 {
20163 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
6772dd07 20164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20165 },
20166/* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20167 {
20168 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
6772dd07 20169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20170 },
20171/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20172 {
20173 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20175 },
20176/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20177 {
20178 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20180 },
20181/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20182 {
20183 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20185 },
20186/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20187 {
20188 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20190 },
20191/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20192 {
20193 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
6772dd07 20194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20195 },
20196/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20197 {
20198 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
6772dd07 20199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20200 },
20201/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20202 {
20203 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20205 },
20206/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20207 {
20208 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20210 },
20211/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20212 {
20213 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20215 },
20216/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20217 {
20218 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20220 },
20221/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20222 {
20223 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20225 },
20226/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20227 {
20228 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 20229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20230 },
20231/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20232 {
20233 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20235 },
20236/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20237 {
20238 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 20239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20240 },
20241/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20242 {
20243 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
6772dd07 20244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20245 },
20246/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
20247 {
20248 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
6772dd07 20249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20250 },
20251/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20252 {
20253 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
6772dd07 20254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20255 },
20256/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
20257 {
20258 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
6772dd07 20259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20260 },
20261/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
20262 {
20263 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
6772dd07 20264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20265 },
20266/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
20267 {
20268 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
6772dd07 20269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20270 },
20271/* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20272 {
20273 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
6772dd07 20274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20275 },
20276/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
20277 {
20278 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
6772dd07 20279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20280 },
20281/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
20282 {
20283 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
6772dd07 20284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20285 },
20286/* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20287 {
20288 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
6772dd07 20289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20290 },
20291/* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
20292 {
20293 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
6772dd07 20294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20295 },
20296/* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
20297 {
20298 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
6772dd07 20299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20300 },
20301/* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20302 {
20303 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
6772dd07 20304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20305 },
20306/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20307 {
20308 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20310 },
20311/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20312 {
20313 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20315 },
20316/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
20317 {
20318 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20320 },
20321/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20322 {
20323 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20325 },
20326/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20327 {
20328 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20330 },
20331/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
20332 {
20333 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20335 },
20336/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20337 {
20338 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20340 },
20341/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20342 {
20343 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20345 },
20346/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
20347 {
20348 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 20349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20350 },
20351/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
20352 {
20353 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20355 },
20356/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
20357 {
20358 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20360 },
20361/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
20362 {
20363 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20365 },
20366/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
20367 {
20368 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20370 },
20371/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
20372 {
20373 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20375 },
20376/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
20377 {
20378 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20380 },
20381/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
20382 {
20383 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20385 },
20386/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
20387 {
20388 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20390 },
20391/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
20392 {
20393 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
6772dd07 20394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20395 },
20396/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
20397 {
20398 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20400 },
20401/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
20402 {
20403 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20405 },
20406/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
20407 {
20408 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
6772dd07 20409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20410 },
20411/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
20412 {
20413 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
6772dd07 20414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20415 },
20416/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
20417 {
20418 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
6772dd07 20419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20420 },
20421/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
20422 {
20423 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
6772dd07 20424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20425 },
20426/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
20427 {
20428 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
6772dd07 20429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20430 },
20431/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
20432 {
20433 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
6772dd07 20434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20435 },
20436/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
20437 {
20438 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
6772dd07 20439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20440 },
20441/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20442 {
20443 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 20444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20445 },
20446/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
20447 {
20448 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 20449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20450 },
20451/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
20452 {
20453 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 20454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20455 },
20456/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20457 {
20458 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 20459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20460 },
20461/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
20462 {
20463 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 20464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20465 },
20466/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
20467 {
20468 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 20469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20470 },
20471/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20472 {
20473 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
6772dd07 20474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20475 },
20476/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
20477 {
20478 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
6772dd07 20479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20480 },
20481/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
20482 {
20483 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
6772dd07 20484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20485 },
20486/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20487 {
20488 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20490 },
20491/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20492 {
20493 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20495 },
20496/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20497 {
20498 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20500 },
20501/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20502 {
20503 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20505 },
20506/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20507 {
20508 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20510 },
20511/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20512 {
20513 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20515 },
20516/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20517 {
20518 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20520 },
20521/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20522 {
20523 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20525 },
20526/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20527 {
20528 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20530 },
20531/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
20532 {
20533 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20535 },
20536/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
20537 {
20538 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20540 },
20541/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
20542 {
20543 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20545 },
20546/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
20547 {
20548 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20550 },
20551/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
20552 {
20553 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20555 },
20556/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
20557 {
20558 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20560 },
20561/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
20562 {
20563 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20565 },
20566/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
20567 {
20568 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20570 },
20571/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
20572 {
20573 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 20574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20575 },
20576/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
20577 {
20578 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20580 },
20581/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
20582 {
20583 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20585 },
20586/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
20587 {
20588 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20590 },
20591/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
20592 {
20593 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
6772dd07 20594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20595 },
20596/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
20597 {
20598 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
6772dd07 20599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20600 },
20601/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
20602 {
20603 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
6772dd07 20604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20605 },
20606/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
20607 {
20608 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 20609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20610 },
20611/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
20612 {
20613 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 20614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20615 },
20616/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
20617 {
20618 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 20619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20620 },
20621/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20622 {
20623 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20625 },
20626/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
20627 {
20628 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20630 },
20631/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
20632 {
20633 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20635 },
20636/* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
20637 {
20638 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20640 },
20641/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20642 {
20643 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20645 },
20646/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
20647 {
20648 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20650 },
20651/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
20652 {
20653 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20655 },
20656/* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
20657 {
20658 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
6772dd07 20659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20660 },
20661/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20662 {
20663 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
6772dd07 20664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20665 },
20666/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
20667 {
20668 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
6772dd07 20669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20670 },
20671/* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
20672 {
20673 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
6772dd07 20674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20675 },
20676/* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
20677 {
20678 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
6772dd07 20679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20680 },
20681/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20682 {
20683 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20685 },
20686/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20687 {
20688 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20690 },
20691/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20692 {
20693 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20695 },
20696/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
20697 {
20698 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20700 },
20701/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20702 {
20703 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20705 },
20706/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20707 {
20708 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20710 },
20711/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20712 {
20713 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20715 },
20716/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
20717 {
20718 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20720 },
20721/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20722 {
20723 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20725 },
20726/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20727 {
20728 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20730 },
20731/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20732 {
20733 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20735 },
20736/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
20737 {
20738 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20740 },
20741/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
20742 {
20743 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20745 },
20746/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
20747 {
20748 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20750 },
20751/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20752 {
20753 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20755 },
20756/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20757 {
20758 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20760 },
20761/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20762 {
20763 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20765 },
20766/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20767 {
20768 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20770 },
20771/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20772 {
20773 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20775 },
20776/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20777 {
20778 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20780 },
20781/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20782 {
20783 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20785 },
20786/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20787 {
20788 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20790 },
20791/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20792 {
20793 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20795 },
20796/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20797 {
20798 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 20799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20800 },
20801/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20802 {
20803 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20805 },
20806/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20807 {
20808 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20810 },
20811/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20812 {
20813 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20815 },
20816/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20817 {
20818 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20820 },
20821/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20822 {
20823 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 20824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20825 },
20826/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20827 {
20828 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 20829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20830 },
20831/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20832 {
20833 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 20834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20835 },
20836/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
20837 {
20838 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 20839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20840 },
20841/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20842 {
20843 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
6772dd07 20844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20845 },
20846/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20847 {
20848 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
6772dd07 20849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20850 },
20851/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20852 {
20853 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
6772dd07 20854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20855 },
20856/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
20857 {
20858 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
6772dd07 20859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20860 },
20861/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20862 {
20863 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
6772dd07 20864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20865 },
20866/* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
20867 {
20868 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
6772dd07 20869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20870 },
20871/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20872 {
20873 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
6772dd07 20874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20875 },
20876/* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
20877 {
20878 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
6772dd07 20879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20880 },
20881/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20882 {
20883 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
6772dd07 20884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20885 },
20886/* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20887 {
20888 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
6772dd07 20889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20890 },
20891/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20892 {
20893 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20895 },
20896/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20897 {
20898 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20900 },
20901/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20902 {
20903 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20905 },
20906/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20907 {
20908 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20910 },
20911/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20912 {
20913 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
6772dd07 20914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20915 },
20916/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20917 {
20918 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
6772dd07 20919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20920 },
20921/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20922 {
20923 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20925 },
20926/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20927 {
20928 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20930 },
20931/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20932 {
20933 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20935 },
20936/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20937 {
20938 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20940 },
20941/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20942 {
20943 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20945 },
20946/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20947 {
20948 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 20949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20950 },
20951/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20952 {
20953 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20955 },
20956/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20957 {
20958 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
6772dd07 20959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20960 },
20961/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20962 {
20963 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
6772dd07 20964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20965 },
20966/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
20967 {
20968 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
6772dd07 20969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20970 },
20971/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20972 {
20973 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
6772dd07 20974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20975 },
20976/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
20977 {
20978 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
6772dd07 20979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20980 },
20981/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
20982 {
20983 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
6772dd07 20984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20985 },
20986/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
20987 {
20988 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
6772dd07 20989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20990 },
20991/* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20992 {
20993 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
6772dd07 20994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 20995 },
20996/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
20997 {
20998 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
6772dd07 20999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21000 },
21001/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
21002 {
21003 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
6772dd07 21004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21005 },
21006/* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
21007 {
21008 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
6772dd07 21009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21010 },
21011/* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
21012 {
21013 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
6772dd07 21014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21015 },
21016/* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
21017 {
21018 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
6772dd07 21019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21020 },
21021/* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
21022 {
21023 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
6772dd07 21024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21025 },
21026/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
21027 {
21028 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21030 },
21031/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
21032 {
21033 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21035 },
21036/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
21037 {
21038 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21040 },
21041/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
21042 {
21043 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21045 },
21046/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
21047 {
21048 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21050 },
21051/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
21052 {
21053 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21055 },
21056/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21057 {
21058 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 21059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21060 },
21061/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21062 {
21063 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 21064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21065 },
21066/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
21067 {
21068 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 21069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21070 },
21071/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
21072 {
21073 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21075 },
21076/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
21077 {
21078 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21080 },
21081/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
21082 {
21083 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21085 },
21086/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
21087 {
21088 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21090 },
21091/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
21092 {
21093 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21095 },
21096/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
21097 {
21098 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21100 },
21101/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
21102 {
21103 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21105 },
21106/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
21107 {
21108 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21110 },
21111/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
21112 {
21113 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
6772dd07 21114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21115 },
21116/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
21117 {
21118 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21120 },
21121/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
21122 {
21123 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21125 },
21126/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
21127 {
21128 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 21129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21130 },
21131/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
21132 {
21133 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
6772dd07 21134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21135 },
21136/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
21137 {
21138 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
6772dd07 21139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21140 },
21141/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
21142 {
21143 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
6772dd07 21144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21145 },
21146/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
21147 {
21148 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
6772dd07 21149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21150 },
21151/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
21152 {
21153 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
6772dd07 21154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21155 },
21156/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
21157 {
21158 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
6772dd07 21159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21160 },
21161/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21162 {
21163 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
6772dd07 21164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21165 },
21166/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
21167 {
21168 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
6772dd07 21169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21170 },
21171/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
21172 {
21173 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
6772dd07 21174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21175 },
21176/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21177 {
21178 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
6772dd07 21179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21180 },
21181/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
21182 {
21183 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
6772dd07 21184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21185 },
21186/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
21187 {
21188 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
6772dd07 21189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21190 },
21191/* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21192 {
21193 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
6772dd07 21194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21195 },
21196/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21197 {
21198 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
6772dd07 21199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21200 },
21201/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21202 {
21203 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
6772dd07 21204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21205 },
21206/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21207 {
21208 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
6772dd07 21209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21210 },
21211/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21212 {
21213 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
6772dd07 21214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21215 },
21216/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21217 {
21218 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
6772dd07 21219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21220 },
21221/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21222 {
21223 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
6772dd07 21224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21225 },
21226/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21227 {
21228 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
6772dd07 21229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21230 },
21231/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21232 {
21233 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
6772dd07 21234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21235 },
21236/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21237 {
21238 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
6772dd07 21239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21240 },
21241/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21242 {
21243 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
6772dd07 21244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21245 },
21246/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21247 {
21248 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
6772dd07 21249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21250 },
21251/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21252 {
21253 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
6772dd07 21254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21255 },
21256/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21257 {
21258 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
6772dd07 21259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21260 },
21261/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21262 {
21263 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
6772dd07 21264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21265 },
21266/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21267 {
21268 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
6772dd07 21269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21270 },
21271/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21272 {
21273 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
6772dd07 21274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21275 },
21276/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21277 {
21278 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
6772dd07 21279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21280 },
21281/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21282 {
21283 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
6772dd07 21284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21285 },
21286/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21287 {
21288 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
6772dd07 21289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21290 },
21291/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21292 {
21293 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
6772dd07 21294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21295 },
21296/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
21297 {
21298 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
6772dd07 21299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21300 },
21301/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
21302 {
21303 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
6772dd07 21304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21305 },
21306/* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
21307 {
21308 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32,
6772dd07 21309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21310 },
21311/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
21312 {
21313 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
6772dd07 21314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21315 },
21316/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
21317 {
21318 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
6772dd07 21319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21320 },
21321/* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
21322 {
21323 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32,
6772dd07 21324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21325 },
21326/* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21327 {
21328 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
6772dd07 21329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21330 },
21331/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21332 {
21333 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
6772dd07 21334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21335 },
21336/* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
21337 {
21338 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32,
6772dd07 21339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21340 },
21341/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21342 {
21343 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
6772dd07 21344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21345 },
21346/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21347 {
21348 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
6772dd07 21349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21350 },
21351/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21352 {
21353 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
6772dd07 21354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21355 },
21356/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21357 {
21358 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
6772dd07 21359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21360 },
21361/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21362 {
21363 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
6772dd07 21364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21365 },
21366/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21367 {
21368 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
6772dd07 21369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21370 },
21371/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21372 {
21373 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
6772dd07 21374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21375 },
21376/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21377 {
21378 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
6772dd07 21379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21380 },
21381/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21382 {
21383 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
6772dd07 21384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21385 },
21386/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21387 {
21388 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
6772dd07 21389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21390 },
21391/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21392 {
21393 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
6772dd07 21394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21395 },
21396/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21397 {
21398 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
6772dd07 21399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21400 },
21401/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21402 {
21403 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
6772dd07 21404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21405 },
21406/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21407 {
21408 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
6772dd07 21409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21410 },
21411/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21412 {
21413 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
6772dd07 21414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21415 },
21416/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21417 {
21418 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
6772dd07 21419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21420 },
21421/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21422 {
21423 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
6772dd07 21424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21425 },
21426/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
21427 {
21428 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
6772dd07 21429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21430 },
21431/* mulu.w${G} $Src16RnHI,$Dst16RnHI */
21432 {
21433 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
6772dd07 21434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21435 },
21436/* mulu.w${G} $Src16AnHI,$Dst16RnHI */
21437 {
21438 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
6772dd07 21439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21440 },
21441/* mulu.w${G} [$Src16An],$Dst16RnHI */
21442 {
21443 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16,
6772dd07 21444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21445 },
21446/* mulu.w${G} $Src16RnHI,$Dst16AnHI */
21447 {
21448 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
6772dd07 21449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21450 },
21451/* mulu.w${G} $Src16AnHI,$Dst16AnHI */
21452 {
21453 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
6772dd07 21454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21455 },
21456/* mulu.w${G} [$Src16An],$Dst16AnHI */
21457 {
21458 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16,
6772dd07 21459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21460 },
21461/* mulu.w${G} $Src16RnHI,[$Dst16An] */
21462 {
21463 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
6772dd07 21464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21465 },
21466/* mulu.w${G} $Src16AnHI,[$Dst16An] */
21467 {
21468 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
6772dd07 21469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21470 },
21471/* mulu.w${G} [$Src16An],[$Dst16An] */
21472 {
21473 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16,
6772dd07 21474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21475 },
21476/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
21477 {
21478 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
6772dd07 21479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21480 },
21481/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
21482 {
21483 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
6772dd07 21484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21485 },
21486/* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21487 {
21488 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
6772dd07 21489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21490 },
21491/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
21492 {
21493 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
6772dd07 21494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21495 },
21496/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
21497 {
21498 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
6772dd07 21499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21500 },
21501/* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21502 {
21503 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
6772dd07 21504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21505 },
21506/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
21507 {
21508 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
6772dd07 21509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21510 },
21511/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
21512 {
21513 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
6772dd07 21514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21515 },
21516/* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
21517 {
21518 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
6772dd07 21519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21520 },
21521/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
21522 {
21523 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
6772dd07 21524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21525 },
21526/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
21527 {
21528 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
6772dd07 21529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21530 },
21531/* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
21532 {
21533 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
6772dd07 21534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21535 },
21536/* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
21537 {
21538 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
6772dd07 21539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21540 },
21541/* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
21542 {
21543 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
6772dd07 21544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21545 },
21546/* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
21547 {
21548 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
6772dd07 21549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21550 },
21551/* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
21552 {
21553 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
6772dd07 21554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21555 },
21556/* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
21557 {
21558 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
6772dd07 21559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21560 },
21561/* mulu.w${G} [$Src16An],${Dsp-16-u16} */
21562 {
21563 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
6772dd07 21564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21565 },
21566/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
21567 {
21568 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
6772dd07 21569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21570 },
21571/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
21572 {
21573 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
6772dd07 21574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21575 },
21576/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
21577 {
21578 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
6772dd07 21579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21580 },
21581/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
21582 {
21583 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
6772dd07 21584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21585 },
21586/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
21587 {
21588 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
6772dd07 21589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21590 },
21591/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
21592 {
21593 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
6772dd07 21594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21595 },
21596/* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21597 {
21598 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
6772dd07 21599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21600 },
21601/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21602 {
21603 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
6772dd07 21604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21605 },
21606/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21607 {
21608 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
6772dd07 21609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21610 },
21611/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21612 {
21613 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
6772dd07 21614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21615 },
21616/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21617 {
21618 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
6772dd07 21619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21620 },
21621/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21622 {
21623 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
6772dd07 21624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21625 },
21626/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21627 {
21628 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
6772dd07 21629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21630 },
21631/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21632 {
21633 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
6772dd07 21634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21635 },
21636/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21637 {
21638 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
6772dd07 21639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21640 },
21641/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21642 {
21643 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
6772dd07 21644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21645 },
21646/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21647 {
21648 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
6772dd07 21649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21650 },
21651/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21652 {
21653 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
6772dd07 21654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21655 },
21656/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21657 {
21658 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
6772dd07 21659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21660 },
21661/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21662 {
21663 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
6772dd07 21664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21665 },
21666/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21667 {
21668 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
6772dd07 21669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21670 },
21671/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21672 {
21673 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
6772dd07 21674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21675 },
21676/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21677 {
21678 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
6772dd07 21679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21680 },
21681/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21682 {
21683 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
6772dd07 21684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21685 },
21686/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21687 {
21688 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
6772dd07 21689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21690 },
21691/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21692 {
21693 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
6772dd07 21694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21695 },
21696/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21697 {
21698 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
6772dd07 21699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21700 },
21701/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
21702 {
21703 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
6772dd07 21704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21705 },
21706/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
21707 {
21708 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
6772dd07 21709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21710 },
21711/* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
21712 {
21713 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32,
6772dd07 21714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21715 },
21716/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
21717 {
21718 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
6772dd07 21719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21720 },
21721/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
21722 {
21723 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
6772dd07 21724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21725 },
21726/* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
21727 {
21728 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32,
6772dd07 21729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21730 },
21731/* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21732 {
21733 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
6772dd07 21734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21735 },
21736/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21737 {
21738 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
6772dd07 21739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21740 },
21741/* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
21742 {
21743 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32,
6772dd07 21744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21745 },
21746/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21747 {
21748 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
6772dd07 21749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21750 },
21751/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21752 {
21753 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
6772dd07 21754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21755 },
21756/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21757 {
21758 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
6772dd07 21759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21760 },
21761/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21762 {
21763 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
6772dd07 21764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21765 },
21766/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21767 {
21768 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
6772dd07 21769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21770 },
21771/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21772 {
21773 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
6772dd07 21774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21775 },
21776/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21777 {
21778 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
6772dd07 21779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21780 },
21781/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21782 {
21783 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
6772dd07 21784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21785 },
21786/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21787 {
21788 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
6772dd07 21789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21790 },
21791/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21792 {
21793 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
6772dd07 21794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21795 },
21796/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21797 {
21798 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
6772dd07 21799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21800 },
21801/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21802 {
21803 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
6772dd07 21804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21805 },
21806/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21807 {
21808 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
6772dd07 21809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21810 },
21811/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21812 {
21813 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
6772dd07 21814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21815 },
21816/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21817 {
21818 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
6772dd07 21819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21820 },
21821/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21822 {
21823 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
6772dd07 21824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21825 },
21826/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21827 {
21828 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
6772dd07 21829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21830 },
21831/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
21832 {
21833 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
6772dd07 21834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21835 },
21836/* mulu.b${G} $Src16RnQI,$Dst16RnQI */
21837 {
21838 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
6772dd07 21839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21840 },
21841/* mulu.b${G} $Src16AnQI,$Dst16RnQI */
21842 {
21843 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
6772dd07 21844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21845 },
21846/* mulu.b${G} [$Src16An],$Dst16RnQI */
21847 {
21848 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16,
6772dd07 21849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21850 },
21851/* mulu.b${G} $Src16RnQI,$Dst16AnQI */
21852 {
21853 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
6772dd07 21854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21855 },
21856/* mulu.b${G} $Src16AnQI,$Dst16AnQI */
21857 {
21858 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
6772dd07 21859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21860 },
21861/* mulu.b${G} [$Src16An],$Dst16AnQI */
21862 {
21863 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16,
6772dd07 21864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21865 },
21866/* mulu.b${G} $Src16RnQI,[$Dst16An] */
21867 {
21868 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
6772dd07 21869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21870 },
21871/* mulu.b${G} $Src16AnQI,[$Dst16An] */
21872 {
21873 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
6772dd07 21874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21875 },
21876/* mulu.b${G} [$Src16An],[$Dst16An] */
21877 {
21878 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16,
6772dd07 21879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21880 },
21881/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
21882 {
21883 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
6772dd07 21884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21885 },
21886/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
21887 {
21888 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
6772dd07 21889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21890 },
21891/* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21892 {
21893 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
6772dd07 21894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21895 },
21896/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
21897 {
21898 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
6772dd07 21899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21900 },
21901/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
21902 {
21903 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
6772dd07 21904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21905 },
21906/* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21907 {
21908 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
6772dd07 21909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21910 },
21911/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
21912 {
21913 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
6772dd07 21914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21915 },
21916/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
21917 {
21918 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
6772dd07 21919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21920 },
21921/* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
21922 {
21923 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
6772dd07 21924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21925 },
21926/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
21927 {
21928 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
6772dd07 21929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21930 },
21931/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
21932 {
21933 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
6772dd07 21934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21935 },
21936/* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
21937 {
21938 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
6772dd07 21939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21940 },
21941/* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
21942 {
21943 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
6772dd07 21944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21945 },
21946/* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
21947 {
21948 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
6772dd07 21949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21950 },
21951/* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
21952 {
21953 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
6772dd07 21954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21955 },
21956/* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
21957 {
21958 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
6772dd07 21959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21960 },
21961/* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
21962 {
21963 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
6772dd07 21964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21965 },
21966/* mulu.b${G} [$Src16An],${Dsp-16-u16} */
21967 {
21968 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
6772dd07 21969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 21970 },
21971/* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
21972 {
21973 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 21974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 21975 },
21976/* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
21977 {
21978 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
6772dd07 21979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 21980 },
21981/* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
21982 {
21983 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
6772dd07 21984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 21985 },
21986/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
21987 {
21988 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 21989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 21990 },
21991/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
21992 {
21993 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 21994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 21995 },
21996/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
21997 {
21998 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
6772dd07 21999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22000 },
22001/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
22002 {
22003 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 22004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22005 },
22006/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22007 {
22008 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 22009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22010 },
22011/* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
22012 {
22013 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
6772dd07 22014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22015 },
22016/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
22017 {
22018 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48,
6772dd07 22019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22020 },
22021/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
22022 {
22023 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56,
6772dd07 22024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22025 },
22026/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
22027 {
22028 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56,
6772dd07 22029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22030 },
22031/* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
22032 {
22033 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 22034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22035 },
22036/* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
22037 {
22038 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
6772dd07 22039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22040 },
22041/* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
22042 {
22043 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
6772dd07 22044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22045 },
22046/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
22047 {
22048 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 22049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22050 },
22051/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22052 {
22053 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 22054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22055 },
22056/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22057 {
22058 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
6772dd07 22059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22060 },
22061/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
22062 {
22063 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 22064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22065 },
22066/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22067 {
22068 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 22069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22070 },
22071/* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
22072 {
22073 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
6772dd07 22074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22075 },
22076/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22077 {
22078 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40,
6772dd07 22079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22080 },
22081/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
22082 {
22083 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48,
6772dd07 22084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22085 },
22086/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
22087 {
22088 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48,
6772dd07 22089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22090 },
22091/* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
22092 {
22093 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32,
6772dd07 22094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22095 },
22096/* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
22097 {
22098 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32,
6772dd07 22099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22100 },
22101/* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
22102 {
22103 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32,
6772dd07 22104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22105 },
22106/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22107 {
22108 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40,
6772dd07 22109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22110 },
22111/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22112 {
22113 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40,
6772dd07 22114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22115 },
22116/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22117 {
22118 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40,
6772dd07 22119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22120 },
22121/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22122 {
22123 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48,
6772dd07 22124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22125 },
22126/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22127 {
22128 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48,
6772dd07 22129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22130 },
22131/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
22132 {
22133 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48,
6772dd07 22134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22135 },
22136/* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
22137 {
22138 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24,
6772dd07 22139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22140 },
22141/* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
22142 {
22143 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24,
6772dd07 22144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22145 },
22146/* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
22147 {
22148 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24,
6772dd07 22149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22150 },
22151/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
22152 {
22153 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32,
6772dd07 22154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22155 },
22156/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22157 {
22158 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32,
6772dd07 22159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22160 },
22161/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22162 {
22163 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32,
6772dd07 22164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22165 },
22166/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
22167 {
22168 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40,
6772dd07 22169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22170 },
22171/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22172 {
22173 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40,
6772dd07 22174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22175 },
22176/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22177 {
22178 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40,
6772dd07 22179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 22180 },
22181/* mulex $R3 */
22182 {
22183 M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16,
6772dd07 22184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22185 },
22186/* mulex $Dst32AnUnprefixedHI */
22187 {
22188 M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16,
6772dd07 22189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22190 },
22191/* mulex [$Dst32AnUnprefixed] */
22192 {
22193 M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16,
6772dd07 22194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22195 },
22196/* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
22197 {
22198 M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24,
6772dd07 22199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22200 },
22201/* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
22202 {
22203 M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32,
6772dd07 22204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22205 },
22206/* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
22207 {
22208 M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40,
6772dd07 22209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22210 },
22211/* mulex ${Dsp-16-u8}[sb] */
22212 {
22213 M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24,
6772dd07 22214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22215 },
22216/* mulex ${Dsp-16-u16}[sb] */
22217 {
22218 M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32,
6772dd07 22219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22220 },
22221/* mulex ${Dsp-16-s8}[fb] */
22222 {
22223 M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24,
6772dd07 22224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22225 },
22226/* mulex ${Dsp-16-s16}[fb] */
22227 {
22228 M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32,
6772dd07 22229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22230 },
22231/* mulex ${Dsp-16-u16} */
22232 {
22233 M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32,
6772dd07 22234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22235 },
22236/* mulex ${Dsp-16-u24} */
22237 {
22238 M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40,
6772dd07 22239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 22240 },
22241/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22242 {
22243 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
6772dd07 22244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22245 },
22246/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
22247 {
22248 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
6772dd07 22249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22250 },
22251/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
22252 {
22253 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
6772dd07 22254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22255 },
22256/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22257 {
22258 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
6772dd07 22259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22260 },
22261/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
22262 {
22263 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
6772dd07 22264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22265 },
22266/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
22267 {
22268 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
6772dd07 22269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22270 },
22271/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22272 {
22273 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
6772dd07 22274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22275 },
22276/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22277 {
22278 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
6772dd07 22279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22280 },
22281/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22282 {
22283 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
6772dd07 22284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22285 },
22286/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22287 {
22288 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22290 },
22291/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22292 {
22293 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22295 },
22296/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22297 {
22298 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22300 },
22301/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22302 {
22303 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22305 },
22306/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22307 {
22308 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22310 },
22311/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22312 {
22313 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22315 },
22316/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22317 {
22318 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22320 },
22321/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22322 {
22323 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22325 },
22326/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22327 {
22328 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22330 },
22331/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
22332 {
22333 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22335 },
22336/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22337 {
22338 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22340 },
22341/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22342 {
22343 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22345 },
22346/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
22347 {
22348 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22350 },
22351/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22352 {
22353 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22355 },
22356/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22357 {
22358 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22360 },
22361/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
22362 {
22363 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22365 },
22366/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22367 {
22368 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22370 },
22371/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22372 {
22373 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22375 },
22376/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
22377 {
22378 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22380 },
22381/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
22382 {
22383 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22385 },
22386/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
22387 {
22388 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22390 },
22391/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
22392 {
22393 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
6772dd07 22394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22395 },
22396/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22397 {
22398 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
6772dd07 22399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22400 },
22401/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22402 {
22403 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
6772dd07 22404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22405 },
22406/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
22407 {
22408 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 22409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22410 },
22411/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
22412 {
22413 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 22414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22415 },
22416/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
22417 {
22418 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 22419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22420 },
22421/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22422 {
22423 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22425 },
22426/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
22427 {
22428 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22430 },
22431/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
22432 {
22433 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22435 },
22436/* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
22437 {
22438 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22440 },
22441/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22442 {
22443 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22445 },
22446/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
22447 {
22448 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22450 },
22451/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
22452 {
22453 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22455 },
22456/* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
22457 {
22458 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 22459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22460 },
22461/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22462 {
22463 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
6772dd07 22464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22465 },
22466/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
22467 {
22468 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
6772dd07 22469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22470 },
22471/* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
22472 {
22473 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
6772dd07 22474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22475 },
22476/* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
22477 {
22478 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
6772dd07 22479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22480 },
22481/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22482 {
22483 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22485 },
22486/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22487 {
22488 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22490 },
22491/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22492 {
22493 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22495 },
22496/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
22497 {
22498 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22500 },
22501/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22502 {
22503 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22505 },
22506/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22507 {
22508 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22510 },
22511/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22512 {
22513 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22515 },
22516/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
22517 {
22518 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22520 },
22521/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22522 {
22523 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22525 },
22526/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22527 {
22528 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22530 },
22531/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22532 {
22533 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22535 },
22536/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
22537 {
22538 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22540 },
22541/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
22542 {
22543 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22545 },
22546/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22547 {
22548 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22550 },
22551/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
22552 {
22553 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22555 },
22556/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22557 {
22558 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22560 },
22561/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
22562 {
22563 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22565 },
22566/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22567 {
22568 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22570 },
22571/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
22572 {
22573 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22575 },
22576/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22577 {
22578 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22580 },
22581/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
22582 {
22583 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22585 },
22586/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22587 {
22588 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22590 },
22591/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
22592 {
22593 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22595 },
22596/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22597 {
22598 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22600 },
22601/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
22602 {
22603 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22605 },
22606/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
22607 {
22608 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22610 },
22611/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
22612 {
22613 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22615 },
22616/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
22617 {
22618 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22620 },
22621/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
22622 {
22623 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 22624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22625 },
22626/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22627 {
22628 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 22629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22630 },
22631/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
22632 {
22633 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 22634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22635 },
22636/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
22637 {
22638 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 22639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22640 },
22641/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
22642 {
22643 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
6772dd07 22644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22645 },
22646/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
22647 {
22648 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
6772dd07 22649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22650 },
22651/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
22652 {
22653 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
6772dd07 22654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22655 },
22656/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
22657 {
22658 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
6772dd07 22659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22660 },
22661/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22662 {
22663 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
6772dd07 22664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22665 },
22666/* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
22667 {
22668 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
6772dd07 22669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22670 },
22671/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22672 {
22673 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
6772dd07 22674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22675 },
22676/* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
22677 {
22678 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
6772dd07 22679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22680 },
22681/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22682 {
22683 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
6772dd07 22684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22685 },
22686/* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
22687 {
22688 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
6772dd07 22689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22690 },
22691/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
22692 {
22693 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22695 },
22696/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
22697 {
22698 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22700 },
22701/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
22702 {
22703 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22705 },
22706/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
22707 {
22708 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22710 },
22711/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
22712 {
22713 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
6772dd07 22714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22715 },
22716/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
22717 {
22718 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
6772dd07 22719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22720 },
22721/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
22722 {
22723 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22725 },
22726/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
22727 {
22728 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22730 },
22731/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
22732 {
22733 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22735 },
22736/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
22737 {
22738 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22740 },
22741/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
22742 {
22743 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22745 },
22746/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
22747 {
22748 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 22749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22750 },
22751/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
22752 {
22753 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22755 },
22756/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
22757 {
22758 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 22759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22760 },
22761/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
22762 {
22763 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
6772dd07 22764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22765 },
22766/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
22767 {
22768 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
6772dd07 22769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22770 },
22771/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
22772 {
22773 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
6772dd07 22774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22775 },
22776/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
22777 {
22778 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
6772dd07 22779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22780 },
22781/* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
22782 {
22783 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
6772dd07 22784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22785 },
22786/* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
22787 {
22788 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
6772dd07 22789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22790 },
22791/* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22792 {
22793 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
6772dd07 22794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22795 },
22796/* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
22797 {
22798 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
6772dd07 22799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22800 },
22801/* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
22802 {
22803 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
6772dd07 22804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22805 },
22806/* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22807 {
22808 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
6772dd07 22809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22810 },
22811/* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
22812 {
22813 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
6772dd07 22814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22815 },
22816/* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
22817 {
22818 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
6772dd07 22819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22820 },
22821/* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22822 {
22823 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
6772dd07 22824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22825 },
22826/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22827 {
22828 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22830 },
22831/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22832 {
22833 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22835 },
22836/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
22837 {
22838 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22840 },
22841/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22842 {
22843 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22845 },
22846/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22847 {
22848 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22850 },
22851/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
22852 {
22853 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22855 },
22856/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22857 {
22858 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22860 },
22861/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22862 {
22863 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22865 },
22866/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
22867 {
22868 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 22869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22870 },
22871/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
22872 {
22873 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22875 },
22876/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
22877 {
22878 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22880 },
22881/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
22882 {
22883 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22885 },
22886/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
22887 {
22888 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22890 },
22891/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
22892 {
22893 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22895 },
22896/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
22897 {
22898 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22900 },
22901/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
22902 {
22903 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22905 },
22906/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
22907 {
22908 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22910 },
22911/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
22912 {
22913 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
6772dd07 22914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22915 },
22916/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
22917 {
22918 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22920 },
22921/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
22922 {
22923 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22925 },
22926/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
22927 {
22928 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
6772dd07 22929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22930 },
22931/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
22932 {
22933 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
6772dd07 22934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22935 },
22936/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
22937 {
22938 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
6772dd07 22939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22940 },
22941/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
22942 {
22943 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
6772dd07 22944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22945 },
22946/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
22947 {
22948 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
6772dd07 22949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22950 },
22951/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
22952 {
22953 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
6772dd07 22954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22955 },
22956/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
22957 {
22958 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
6772dd07 22959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22960 },
22961/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
22962 {
22963 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 22964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22965 },
22966/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
22967 {
22968 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 22969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22970 },
22971/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
22972 {
22973 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 22974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22975 },
22976/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
22977 {
22978 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 22979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22980 },
22981/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
22982 {
22983 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 22984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22985 },
22986/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
22987 {
22988 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 22989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22990 },
22991/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22992 {
22993 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
6772dd07 22994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 22995 },
22996/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22997 {
22998 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
6772dd07 22999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23000 },
23001/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
23002 {
23003 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
6772dd07 23004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23005 },
23006/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
23007 {
23008 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23010 },
23011/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
23012 {
23013 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23015 },
23016/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
23017 {
23018 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23020 },
23021/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
23022 {
23023 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23025 },
23026/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
23027 {
23028 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23030 },
23031/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
23032 {
23033 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23035 },
23036/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23037 {
23038 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23040 },
23041/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23042 {
23043 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23045 },
23046/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23047 {
23048 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23050 },
23051/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
23052 {
23053 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23055 },
23056/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23057 {
23058 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23060 },
23061/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23062 {
23063 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23065 },
23066/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
23067 {
23068 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23070 },
23071/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23072 {
23073 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23075 },
23076/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23077 {
23078 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23080 },
23081/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
23082 {
23083 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23085 },
23086/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23087 {
23088 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23090 },
23091/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23092 {
23093 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23095 },
23096/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
23097 {
23098 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23100 },
23101/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
23102 {
23103 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23105 },
23106/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
23107 {
23108 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23110 },
23111/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
23112 {
23113 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
6772dd07 23114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23115 },
23116/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23117 {
23118 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
6772dd07 23119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23120 },
23121/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23122 {
23123 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
6772dd07 23124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23125 },
23126/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
23127 {
23128 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 23129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23130 },
23131/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
23132 {
23133 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 23134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23135 },
23136/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
23137 {
23138 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 23139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23140 },
23141/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23142 {
23143 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23145 },
23146/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
23147 {
23148 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23150 },
23151/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
23152 {
23153 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23155 },
23156/* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
23157 {
23158 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23160 },
23161/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23162 {
23163 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23165 },
23166/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
23167 {
23168 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23170 },
23171/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
23172 {
23173 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23175 },
23176/* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
23177 {
23178 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
6772dd07 23179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23180 },
23181/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23182 {
23183 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
6772dd07 23184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23185 },
23186/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
23187 {
23188 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
6772dd07 23189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23190 },
23191/* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
23192 {
23193 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
6772dd07 23194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23195 },
23196/* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
23197 {
23198 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
6772dd07 23199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23200 },
23201/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23202 {
23203 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23205 },
23206/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23207 {
23208 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23210 },
23211/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23212 {
23213 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23215 },
23216/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
23217 {
23218 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23220 },
23221/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23222 {
23223 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23225 },
23226/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23227 {
23228 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23230 },
23231/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23232 {
23233 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23235 },
23236/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
23237 {
23238 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23240 },
23241/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23242 {
23243 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23245 },
23246/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23247 {
23248 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23250 },
23251/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23252 {
23253 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23255 },
23256/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
23257 {
23258 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23260 },
23261/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
23262 {
23263 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23265 },
23266/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23267 {
23268 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23270 },
23271/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
23272 {
23273 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23275 },
23276/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23277 {
23278 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23280 },
23281/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
23282 {
23283 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23285 },
23286/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23287 {
23288 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23290 },
23291/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
23292 {
23293 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23295 },
23296/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23297 {
23298 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23300 },
23301/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
23302 {
23303 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23305 },
23306/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23307 {
23308 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23310 },
23311/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
23312 {
23313 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23315 },
23316/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23317 {
23318 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23320 },
23321/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
23322 {
23323 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23325 },
23326/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
23327 {
23328 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23330 },
23331/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
23332 {
23333 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23335 },
23336/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
23337 {
23338 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23340 },
23341/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
23342 {
23343 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 23344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23345 },
23346/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23347 {
23348 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 23349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23350 },
23351/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
23352 {
23353 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 23354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23355 },
23356/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
23357 {
23358 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 23359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23360 },
23361/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
23362 {
23363 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
6772dd07 23364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23365 },
23366/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
23367 {
23368 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
6772dd07 23369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23370 },
23371/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
23372 {
23373 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
6772dd07 23374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23375 },
23376/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
23377 {
23378 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
6772dd07 23379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23380 },
23381/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23382 {
23383 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
6772dd07 23384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23385 },
23386/* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
23387 {
23388 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
6772dd07 23389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23390 },
23391/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23392 {
23393 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
6772dd07 23394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23395 },
23396/* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
23397 {
23398 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
6772dd07 23399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23400 },
23401/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23402 {
23403 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
6772dd07 23404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23405 },
23406/* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
23407 {
23408 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
6772dd07 23409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23410 },
23411/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
23412 {
23413 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23415 },
23416/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
23417 {
23418 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23420 },
23421/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
23422 {
23423 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23425 },
23426/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
23427 {
23428 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23430 },
23431/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
23432 {
23433 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
6772dd07 23434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23435 },
23436/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
23437 {
23438 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
6772dd07 23439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23440 },
23441/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
23442 {
23443 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23445 },
23446/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
23447 {
23448 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23450 },
23451/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
23452 {
23453 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23455 },
23456/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
23457 {
23458 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23460 },
23461/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
23462 {
23463 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23465 },
23466/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
23467 {
23468 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 23469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23470 },
23471/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
23472 {
23473 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23475 },
23476/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
23477 {
23478 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
6772dd07 23479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23480 },
23481/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
23482 {
23483 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
6772dd07 23484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23485 },
23486/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
23487 {
23488 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
6772dd07 23489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23490 },
23491/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
23492 {
23493 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
6772dd07 23494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23495 },
23496/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
23497 {
23498 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
6772dd07 23499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23500 },
23501/* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
23502 {
23503 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
6772dd07 23504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23505 },
23506/* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
23507 {
23508 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
6772dd07 23509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23510 },
23511/* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23512 {
23513 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
6772dd07 23514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23515 },
23516/* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
23517 {
23518 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
6772dd07 23519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23520 },
23521/* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
23522 {
23523 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
6772dd07 23524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23525 },
23526/* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23527 {
23528 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
6772dd07 23529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23530 },
23531/* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
23532 {
23533 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
6772dd07 23534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23535 },
23536/* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
23537 {
23538 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
6772dd07 23539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23540 },
23541/* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23542 {
23543 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
6772dd07 23544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23545 },
23546/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23547 {
23548 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23550 },
23551/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23552 {
23553 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23555 },
23556/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
23557 {
23558 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23560 },
23561/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23562 {
23563 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23565 },
23566/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23567 {
23568 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23570 },
23571/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
23572 {
23573 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23575 },
23576/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23577 {
23578 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23580 },
23581/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23582 {
23583 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23585 },
23586/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
23587 {
23588 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 23589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23590 },
23591/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
23592 {
23593 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23595 },
23596/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
23597 {
23598 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23600 },
23601/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
23602 {
23603 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23605 },
23606/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
23607 {
23608 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23610 },
23611/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
23612 {
23613 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23615 },
23616/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
23617 {
23618 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23620 },
23621/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
23622 {
23623 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23625 },
23626/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
23627 {
23628 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23630 },
23631/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
23632 {
23633 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
6772dd07 23634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23635 },
23636/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
23637 {
23638 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23640 },
23641/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
23642 {
23643 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23645 },
23646/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
23647 {
23648 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 23649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23650 },
23651/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
23652 {
23653 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
6772dd07 23654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23655 },
23656/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
23657 {
23658 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
6772dd07 23659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23660 },
23661/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
23662 {
23663 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
6772dd07 23664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23665 },
23666/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
23667 {
23668 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
6772dd07 23669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23670 },
23671/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
23672 {
23673 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
6772dd07 23674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23675 },
23676/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
23677 {
23678 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
6772dd07 23679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23680 },
23681/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
23682 {
23683 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
6772dd07 23684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23685 },
23686/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
23687 {
23688 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
6772dd07 23689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23690 },
23691/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
23692 {
23693 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
6772dd07 23694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23695 },
23696/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
23697 {
23698 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24,
6772dd07 23699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23700 },
23701/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
23702 {
23703 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
6772dd07 23704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23705 },
23706/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
23707 {
23708 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
6772dd07 23709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23710 },
23711/* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
23712 {
23713 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
6772dd07 23714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23715 },
23716/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
23717 {
23718 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
6772dd07 23719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23720 },
23721/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
23722 {
23723 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
6772dd07 23724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23725 },
23726/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
23727 {
23728 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
6772dd07 23729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23730 },
23731/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
23732 {
23733 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
6772dd07 23734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23735 },
23736/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
23737 {
23738 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
6772dd07 23739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23740 },
23741/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
23742 {
23743 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
6772dd07 23744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23745 },
23746/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
23747 {
23748 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
6772dd07 23749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23750 },
23751/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
23752 {
23753 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
6772dd07 23754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23755 },
23756/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
23757 {
23758 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
6772dd07 23759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23760 },
23761/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23762 {
23763 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
6772dd07 23764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23765 },
23766/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23767 {
23768 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
6772dd07 23769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23770 },
23771/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
23772 {
23773 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
6772dd07 23774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23775 },
23776/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23777 {
23778 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
6772dd07 23779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23780 },
23781/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23782 {
23783 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
6772dd07 23784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23785 },
23786/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
23787 {
23788 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
6772dd07 23789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23790 },
23791/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23792 {
23793 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
6772dd07 23794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23795 },
23796/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23797 {
23798 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
6772dd07 23799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23800 },
23801/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
23802 {
23803 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
6772dd07 23804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23805 },
23806/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23807 {
23808 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
6772dd07 23809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23810 },
23811/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23812 {
23813 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
6772dd07 23814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23815 },
23816/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
23817 {
23818 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
6772dd07 23819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23820 },
23821/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
23822 {
23823 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
6772dd07 23824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23825 },
23826/* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
23827 {
23828 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32,
6772dd07 23829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23830 },
23831/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
23832 {
23833 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32,
6772dd07 23834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23835 },
23836/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
23837 {
23838 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32,
6772dd07 23839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23840 },
23841/* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
23842 {
23843 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32,
6772dd07 23844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23845 },
23846/* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
23847 {
23848 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
6772dd07 23849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23850 },
23851/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
23852 {
23853 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
6772dd07 23854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23855 },
23856/* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
23857 {
23858 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32,
6772dd07 23859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23860 },
23861/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
23862 {
23863 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
6772dd07 23864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23865 },
23866/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
23867 {
23868 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
6772dd07 23869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23870 },
23871/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
23872 {
23873 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
6772dd07 23874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23875 },
23876/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
23877 {
23878 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
6772dd07 23879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23880 },
23881/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
23882 {
23883 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
6772dd07 23884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23885 },
23886/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
23887 {
23888 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
6772dd07 23889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23890 },
23891/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
23892 {
23893 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
6772dd07 23894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23895 },
23896/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23897 {
23898 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
6772dd07 23899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23900 },
23901/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23902 {
23903 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
6772dd07 23904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23905 },
23906/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
23907 {
23908 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
6772dd07 23909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23910 },
23911/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23912 {
23913 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
6772dd07 23914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23915 },
23916/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23917 {
23918 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
6772dd07 23919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23920 },
23921/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
23922 {
23923 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
6772dd07 23924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23925 },
23926/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23927 {
23928 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
6772dd07 23929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23930 },
23931/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23932 {
23933 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
6772dd07 23934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23935 },
23936/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
23937 {
23938 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
6772dd07 23939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23940 },
23941/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23942 {
23943 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
6772dd07 23944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23945 },
23946/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
23947 {
23948 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48,
6772dd07 23949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23950 },
23951/* mul.w${G} $Src16RnHI,$Dst16RnHI */
23952 {
23953 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
6772dd07 23954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23955 },
23956/* mul.w${G} $Src16AnHI,$Dst16RnHI */
23957 {
23958 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
6772dd07 23959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23960 },
23961/* mul.w${G} [$Src16An],$Dst16RnHI */
23962 {
23963 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16,
6772dd07 23964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23965 },
23966/* mul.w${G} $Src16RnHI,$Dst16AnHI */
23967 {
23968 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16,
6772dd07 23969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23970 },
23971/* mul.w${G} $Src16AnHI,$Dst16AnHI */
23972 {
23973 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16,
6772dd07 23974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23975 },
23976/* mul.w${G} [$Src16An],$Dst16AnHI */
23977 {
23978 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16,
6772dd07 23979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23980 },
23981/* mul.w${G} $Src16RnHI,[$Dst16An] */
23982 {
23983 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
6772dd07 23984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23985 },
23986/* mul.w${G} $Src16AnHI,[$Dst16An] */
23987 {
23988 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
6772dd07 23989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23990 },
23991/* mul.w${G} [$Src16An],[$Dst16An] */
23992 {
23993 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16,
6772dd07 23994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 23995 },
23996/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
23997 {
23998 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
6772dd07 23999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24000 },
24001/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
24002 {
24003 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
6772dd07 24004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24005 },
24006/* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
24007 {
24008 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
6772dd07 24009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24010 },
24011/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
24012 {
24013 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
6772dd07 24014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24015 },
24016/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
24017 {
24018 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
6772dd07 24019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24020 },
24021/* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
24022 {
24023 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
6772dd07 24024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24025 },
24026/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
24027 {
24028 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
6772dd07 24029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24030 },
24031/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
24032 {
24033 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
6772dd07 24034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24035 },
24036/* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
24037 {
24038 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
6772dd07 24039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24040 },
24041/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
24042 {
24043 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
6772dd07 24044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24045 },
24046/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
24047 {
24048 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
6772dd07 24049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24050 },
24051/* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
24052 {
24053 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
6772dd07 24054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24055 },
24056/* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
24057 {
24058 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
6772dd07 24059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24060 },
24061/* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
24062 {
24063 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
6772dd07 24064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24065 },
24066/* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
24067 {
24068 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
6772dd07 24069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24070 },
24071/* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
24072 {
24073 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
6772dd07 24074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24075 },
24076/* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
24077 {
24078 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
6772dd07 24079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24080 },
24081/* mul.w${G} [$Src16An],${Dsp-16-u16} */
24082 {
24083 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32,
6772dd07 24084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24085 },
24086/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
24087 {
24088 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
6772dd07 24089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24090 },
24091/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
24092 {
24093 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
6772dd07 24094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24095 },
24096/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
24097 {
24098 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
6772dd07 24099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24100 },
24101/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
24102 {
24103 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24,
6772dd07 24104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24105 },
24106/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
24107 {
24108 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
6772dd07 24109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24110 },
24111/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
24112 {
24113 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
6772dd07 24114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24115 },
24116/* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
24117 {
24118 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
6772dd07 24119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24120 },
24121/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
24122 {
24123 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
6772dd07 24124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24125 },
24126/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
24127 {
24128 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
6772dd07 24129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24130 },
24131/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
24132 {
24133 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
6772dd07 24134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24135 },
24136/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
24137 {
24138 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
6772dd07 24139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24140 },
24141/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
24142 {
24143 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
6772dd07 24144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24145 },
24146/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
24147 {
24148 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
6772dd07 24149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24150 },
24151/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
24152 {
24153 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
6772dd07 24154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24155 },
24156/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
24157 {
24158 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
6772dd07 24159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24160 },
24161/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
24162 {
24163 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
6772dd07 24164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24165 },
24166/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24167 {
24168 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
6772dd07 24169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24170 },
24171/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24172 {
24173 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
6772dd07 24174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24175 },
24176/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
24177 {
24178 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
6772dd07 24179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24180 },
24181/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24182 {
24183 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
6772dd07 24184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24185 },
24186/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24187 {
24188 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
6772dd07 24189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24190 },
24191/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
24192 {
24193 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
6772dd07 24194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24195 },
24196/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24197 {
24198 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
6772dd07 24199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24200 },
24201/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24202 {
24203 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
6772dd07 24204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24205 },
24206/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
24207 {
24208 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
6772dd07 24209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24210 },
24211/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24212 {
24213 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
6772dd07 24214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24215 },
24216/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24217 {
24218 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
6772dd07 24219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24220 },
24221/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
24222 {
24223 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
6772dd07 24224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24225 },
24226/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
24227 {
24228 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
6772dd07 24229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24230 },
24231/* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
24232 {
24233 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32,
6772dd07 24234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24235 },
24236/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
24237 {
24238 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32,
6772dd07 24239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24240 },
24241/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
24242 {
24243 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32,
6772dd07 24244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24245 },
24246/* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
24247 {
24248 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32,
6772dd07 24249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24250 },
24251/* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
24252 {
24253 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
6772dd07 24254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24255 },
24256/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
24257 {
24258 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
6772dd07 24259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24260 },
24261/* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
24262 {
24263 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32,
6772dd07 24264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24265 },
24266/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
24267 {
24268 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
6772dd07 24269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24270 },
24271/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
24272 {
24273 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
6772dd07 24274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24275 },
24276/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
24277 {
24278 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
6772dd07 24279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24280 },
24281/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
24282 {
24283 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
6772dd07 24284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24285 },
24286/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
24287 {
24288 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
6772dd07 24289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24290 },
24291/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
24292 {
24293 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
6772dd07 24294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24295 },
24296/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
24297 {
24298 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
6772dd07 24299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24300 },
24301/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
24302 {
24303 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
6772dd07 24304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24305 },
24306/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
24307 {
24308 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
6772dd07 24309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24310 },
24311/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
24312 {
24313 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
6772dd07 24314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24315 },
24316/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
24317 {
24318 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
6772dd07 24319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24320 },
24321/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
24322 {
24323 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
6772dd07 24324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24325 },
24326/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
24327 {
24328 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
6772dd07 24329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24330 },
24331/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
24332 {
24333 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
6772dd07 24334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24335 },
24336/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
24337 {
24338 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
6772dd07 24339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24340 },
24341/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
24342 {
24343 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
6772dd07 24344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24345 },
24346/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
24347 {
24348 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
6772dd07 24349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24350 },
24351/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
24352 {
24353 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48,
6772dd07 24354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24355 },
24356/* mul.b${G} $Src16RnQI,$Dst16RnQI */
24357 {
24358 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
6772dd07 24359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24360 },
24361/* mul.b${G} $Src16AnQI,$Dst16RnQI */
24362 {
24363 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
6772dd07 24364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24365 },
24366/* mul.b${G} [$Src16An],$Dst16RnQI */
24367 {
24368 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16,
6772dd07 24369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24370 },
24371/* mul.b${G} $Src16RnQI,$Dst16AnQI */
24372 {
24373 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16,
6772dd07 24374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24375 },
24376/* mul.b${G} $Src16AnQI,$Dst16AnQI */
24377 {
24378 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16,
6772dd07 24379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24380 },
24381/* mul.b${G} [$Src16An],$Dst16AnQI */
24382 {
24383 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16,
6772dd07 24384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24385 },
24386/* mul.b${G} $Src16RnQI,[$Dst16An] */
24387 {
24388 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
6772dd07 24389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24390 },
24391/* mul.b${G} $Src16AnQI,[$Dst16An] */
24392 {
24393 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
6772dd07 24394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24395 },
24396/* mul.b${G} [$Src16An],[$Dst16An] */
24397 {
24398 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16,
6772dd07 24399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24400 },
24401/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
24402 {
24403 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
6772dd07 24404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24405 },
24406/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
24407 {
24408 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
6772dd07 24409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24410 },
24411/* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
24412 {
24413 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
6772dd07 24414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24415 },
24416/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
24417 {
24418 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
6772dd07 24419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24420 },
24421/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
24422 {
24423 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
6772dd07 24424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24425 },
24426/* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
24427 {
24428 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
6772dd07 24429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24430 },
24431/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
24432 {
24433 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
6772dd07 24434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24435 },
24436/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
24437 {
24438 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
6772dd07 24439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24440 },
24441/* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
24442 {
24443 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
6772dd07 24444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24445 },
24446/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
24447 {
24448 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
6772dd07 24449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24450 },
24451/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
24452 {
24453 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
6772dd07 24454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24455 },
24456/* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
24457 {
24458 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
6772dd07 24459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24460 },
24461/* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
24462 {
24463 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
6772dd07 24464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24465 },
24466/* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
24467 {
24468 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
6772dd07 24469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24470 },
24471/* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
24472 {
24473 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
6772dd07 24474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24475 },
24476/* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
24477 {
24478 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
6772dd07 24479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24480 },
24481/* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
24482 {
24483 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
6772dd07 24484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24485 },
24486/* mul.b${G} [$Src16An],${Dsp-16-u16} */
24487 {
24488 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32,
6772dd07 24489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 24490 },
24491/* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
24492 {
24493 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 24494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24495 },
24496/* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
24497 {
24498 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
6772dd07 24499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24500 },
24501/* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
24502 {
24503 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
6772dd07 24504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24505 },
24506/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24507 {
24508 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 24509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24510 },
24511/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24512 {
24513 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 24514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24515 },
24516/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24517 {
24518 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40,
6772dd07 24519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24520 },
24521/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24522 {
24523 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 24524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24525 },
24526/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24527 {
24528 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 24529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24530 },
24531/* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
24532 {
24533 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48,
6772dd07 24534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24535 },
24536/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24537 {
24538 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48,
6772dd07 24539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24540 },
24541/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24542 {
24543 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56,
6772dd07 24544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24545 },
24546/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
24547 {
24548 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56,
6772dd07 24549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24550 },
24551/* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
24552 {
24553 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 24554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24555 },
24556/* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
24557 {
24558 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
6772dd07 24559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24560 },
24561/* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24562 {
24563 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
6772dd07 24564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24565 },
24566/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24567 {
24568 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 24569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24570 },
24571/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24572 {
24573 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 24574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24575 },
24576/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24577 {
24578 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32,
6772dd07 24579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24580 },
24581/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24582 {
24583 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 24584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24585 },
24586/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24587 {
24588 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 24589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24590 },
24591/* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24592 {
24593 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40,
6772dd07 24594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24595 },
24596/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24597 {
24598 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40,
6772dd07 24599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24600 },
24601/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24602 {
24603 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48,
6772dd07 24604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24605 },
24606/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
24607 {
24608 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48,
6772dd07 24609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24610 },
24611/* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
24612 {
24613 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32,
6772dd07 24614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24615 },
24616/* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
24617 {
24618 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32,
6772dd07 24619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24620 },
24621/* mul.w${G} #${Imm-16-HI},[$Dst16An] */
24622 {
24623 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32,
6772dd07 24624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24625 },
24626/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
24627 {
24628 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40,
6772dd07 24629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24630 },
24631/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24632 {
24633 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40,
6772dd07 24634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24635 },
24636/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24637 {
24638 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40,
6772dd07 24639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24640 },
24641/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
24642 {
24643 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48,
6772dd07 24644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24645 },
24646/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24647 {
24648 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48,
6772dd07 24649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24650 },
24651/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24652 {
24653 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48,
6772dd07 24654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24655 },
24656/* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
24657 {
24658 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24,
6772dd07 24659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24660 },
24661/* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
24662 {
24663 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24,
6772dd07 24664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24665 },
24666/* mul.b${G} #${Imm-16-QI},[$Dst16An] */
24667 {
24668 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24,
6772dd07 24669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24670 },
24671/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
24672 {
24673 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32,
6772dd07 24674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24675 },
24676/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24677 {
24678 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32,
6772dd07 24679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24680 },
24681/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24682 {
24683 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32,
6772dd07 24684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24685 },
24686/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
24687 {
24688 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40,
6772dd07 24689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24690 },
24691/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24692 {
24693 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40,
6772dd07 24694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24695 },
24696/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24697 {
24698 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40,
6772dd07 24699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24700 },
24701/* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
24702 {
24703 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24,
6772dd07 24704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24705 },
24706/* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
24707 {
24708 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24,
6772dd07 24709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24710 },
24711/* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24712 {
24713 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24,
6772dd07 24714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24715 },
24716/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24717 {
24718 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32,
6772dd07 24719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24720 },
24721/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24722 {
24723 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32,
6772dd07 24724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24725 },
24726/* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24727 {
24728 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32,
6772dd07 24729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24730 },
24731/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24732 {
24733 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40,
6772dd07 24734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24735 },
24736/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24737 {
24738 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40,
6772dd07 24739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24740 },
24741/* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24742 {
24743 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40,
6772dd07 24744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24745 },
24746/* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
24747 {
24748 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40,
6772dd07 24749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24750 },
24751/* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24752 {
24753 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48,
6772dd07 24754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24755 },
24756/* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
24757 {
24758 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48,
6772dd07 24759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 24760 },
24761/* movhh $Dst32RnPrefixedQI,r0l */
24762 {
24763 M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
6772dd07 24764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24765 },
24766/* movhh $Dst32AnPrefixedQI,r0l */
24767 {
24768 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24,
6772dd07 24769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24770 },
24771/* movhh [$Dst32AnPrefixed],r0l */
24772 {
24773 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24,
6772dd07 24774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24775 },
24776/* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24777 {
24778 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
6772dd07 24779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24780 },
24781/* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24782 {
24783 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
6772dd07 24784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24785 },
24786/* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24787 {
24788 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
6772dd07 24789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24790 },
24791/* movhh ${Dsp-24-u8}[sb],r0l */
24792 {
24793 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
6772dd07 24794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24795 },
24796/* movhh ${Dsp-24-u16}[sb],r0l */
24797 {
24798 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
6772dd07 24799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24800 },
24801/* movhh ${Dsp-24-s8}[fb],r0l */
24802 {
24803 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
6772dd07 24804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24805 },
24806/* movhh ${Dsp-24-s16}[fb],r0l */
24807 {
24808 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
6772dd07 24809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24810 },
24811/* movhh ${Dsp-24-u16},r0l */
24812 {
24813 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
6772dd07 24814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24815 },
24816/* movhh ${Dsp-24-u24},r0l */
24817 {
24818 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
6772dd07 24819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24820 },
24821/* movhl $Dst32RnPrefixedQI,r0l */
24822 {
24823 M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
6772dd07 24824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24825 },
24826/* movhl $Dst32AnPrefixedQI,r0l */
24827 {
24828 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24,
6772dd07 24829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24830 },
24831/* movhl [$Dst32AnPrefixed],r0l */
24832 {
24833 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24,
6772dd07 24834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24835 },
24836/* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24837 {
24838 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
6772dd07 24839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24840 },
24841/* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24842 {
24843 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
6772dd07 24844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24845 },
24846/* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24847 {
24848 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
6772dd07 24849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24850 },
24851/* movhl ${Dsp-24-u8}[sb],r0l */
24852 {
24853 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
6772dd07 24854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24855 },
24856/* movhl ${Dsp-24-u16}[sb],r0l */
24857 {
24858 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
6772dd07 24859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24860 },
24861/* movhl ${Dsp-24-s8}[fb],r0l */
24862 {
24863 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
6772dd07 24864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24865 },
24866/* movhl ${Dsp-24-s16}[fb],r0l */
24867 {
24868 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
6772dd07 24869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24870 },
24871/* movhl ${Dsp-24-u16},r0l */
24872 {
24873 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
6772dd07 24874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24875 },
24876/* movhl ${Dsp-24-u24},r0l */
24877 {
24878 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
6772dd07 24879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24880 },
24881/* movlh $Dst32RnPrefixedQI,r0l */
24882 {
24883 M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
6772dd07 24884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24885 },
24886/* movlh $Dst32AnPrefixedQI,r0l */
24887 {
24888 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24,
6772dd07 24889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24890 },
24891/* movlh [$Dst32AnPrefixed],r0l */
24892 {
24893 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24,
6772dd07 24894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24895 },
24896/* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24897 {
24898 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
6772dd07 24899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24900 },
24901/* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24902 {
24903 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
6772dd07 24904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24905 },
24906/* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24907 {
24908 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
6772dd07 24909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24910 },
24911/* movlh ${Dsp-24-u8}[sb],r0l */
24912 {
24913 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
6772dd07 24914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24915 },
24916/* movlh ${Dsp-24-u16}[sb],r0l */
24917 {
24918 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
6772dd07 24919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24920 },
24921/* movlh ${Dsp-24-s8}[fb],r0l */
24922 {
24923 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
6772dd07 24924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24925 },
24926/* movlh ${Dsp-24-s16}[fb],r0l */
24927 {
24928 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
6772dd07 24929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24930 },
24931/* movlh ${Dsp-24-u16},r0l */
24932 {
24933 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
6772dd07 24934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24935 },
24936/* movlh ${Dsp-24-u24},r0l */
24937 {
24938 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
6772dd07 24939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24940 },
24941/* movll $Dst32RnPrefixedQI,r0l */
24942 {
24943 M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24,
6772dd07 24944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24945 },
24946/* movll $Dst32AnPrefixedQI,r0l */
24947 {
24948 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24,
6772dd07 24949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24950 },
24951/* movll [$Dst32AnPrefixed],r0l */
24952 {
24953 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24,
6772dd07 24954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24955 },
24956/* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24957 {
24958 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
6772dd07 24959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24960 },
24961/* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24962 {
24963 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
6772dd07 24964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24965 },
24966/* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24967 {
24968 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
6772dd07 24969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24970 },
24971/* movll ${Dsp-24-u8}[sb],r0l */
24972 {
24973 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
6772dd07 24974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24975 },
24976/* movll ${Dsp-24-u16}[sb],r0l */
24977 {
24978 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
6772dd07 24979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24980 },
24981/* movll ${Dsp-24-s8}[fb],r0l */
24982 {
24983 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
6772dd07 24984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24985 },
24986/* movll ${Dsp-24-s16}[fb],r0l */
24987 {
24988 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
6772dd07 24989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24990 },
24991/* movll ${Dsp-24-u16},r0l */
24992 {
24993 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
6772dd07 24994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 24995 },
24996/* movll ${Dsp-24-u24},r0l */
24997 {
24998 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
6772dd07 24999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25000 },
25001/* movhh r0l,$Dst32RnPrefixedQI */
25002 {
25003 M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
6772dd07 25004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25005 },
25006/* movhh r0l,$Dst32AnPrefixedQI */
25007 {
25008 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24,
6772dd07 25009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25010 },
25011/* movhh r0l,[$Dst32AnPrefixed] */
25012 {
25013 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24,
6772dd07 25014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25015 },
25016/* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25017 {
25018 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
6772dd07 25019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25020 },
25021/* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25022 {
25023 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
6772dd07 25024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25025 },
25026/* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25027 {
25028 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
6772dd07 25029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25030 },
25031/* movhh r0l,${Dsp-24-u8}[sb] */
25032 {
25033 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
6772dd07 25034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25035 },
25036/* movhh r0l,${Dsp-24-u16}[sb] */
25037 {
25038 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
6772dd07 25039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25040 },
25041/* movhh r0l,${Dsp-24-s8}[fb] */
25042 {
25043 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
6772dd07 25044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25045 },
25046/* movhh r0l,${Dsp-24-s16}[fb] */
25047 {
25048 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
6772dd07 25049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25050 },
25051/* movhh r0l,${Dsp-24-u16} */
25052 {
25053 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
6772dd07 25054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25055 },
25056/* movhh r0l,${Dsp-24-u24} */
25057 {
25058 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
6772dd07 25059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25060 },
25061/* movhl r0l,$Dst32RnPrefixedQI */
25062 {
25063 M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
6772dd07 25064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25065 },
25066/* movhl r0l,$Dst32AnPrefixedQI */
25067 {
25068 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24,
6772dd07 25069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25070 },
25071/* movhl r0l,[$Dst32AnPrefixed] */
25072 {
25073 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24,
6772dd07 25074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25075 },
25076/* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25077 {
25078 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
6772dd07 25079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25080 },
25081/* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25082 {
25083 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
6772dd07 25084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25085 },
25086/* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25087 {
25088 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
6772dd07 25089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25090 },
25091/* movhl r0l,${Dsp-24-u8}[sb] */
25092 {
25093 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
6772dd07 25094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25095 },
25096/* movhl r0l,${Dsp-24-u16}[sb] */
25097 {
25098 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
6772dd07 25099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25100 },
25101/* movhl r0l,${Dsp-24-s8}[fb] */
25102 {
25103 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
6772dd07 25104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25105 },
25106/* movhl r0l,${Dsp-24-s16}[fb] */
25107 {
25108 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
6772dd07 25109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25110 },
25111/* movhl r0l,${Dsp-24-u16} */
25112 {
25113 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
6772dd07 25114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25115 },
25116/* movhl r0l,${Dsp-24-u24} */
25117 {
25118 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
6772dd07 25119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25120 },
25121/* movlh r0l,$Dst32RnPrefixedQI */
25122 {
25123 M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
6772dd07 25124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25125 },
25126/* movlh r0l,$Dst32AnPrefixedQI */
25127 {
25128 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24,
6772dd07 25129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25130 },
25131/* movlh r0l,[$Dst32AnPrefixed] */
25132 {
25133 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24,
6772dd07 25134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25135 },
25136/* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25137 {
25138 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
6772dd07 25139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25140 },
25141/* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25142 {
25143 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
6772dd07 25144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25145 },
25146/* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25147 {
25148 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
6772dd07 25149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25150 },
25151/* movlh r0l,${Dsp-24-u8}[sb] */
25152 {
25153 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
6772dd07 25154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25155 },
25156/* movlh r0l,${Dsp-24-u16}[sb] */
25157 {
25158 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
6772dd07 25159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25160 },
25161/* movlh r0l,${Dsp-24-s8}[fb] */
25162 {
25163 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
6772dd07 25164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25165 },
25166/* movlh r0l,${Dsp-24-s16}[fb] */
25167 {
25168 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
6772dd07 25169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25170 },
25171/* movlh r0l,${Dsp-24-u16} */
25172 {
25173 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
6772dd07 25174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25175 },
25176/* movlh r0l,${Dsp-24-u24} */
25177 {
25178 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
6772dd07 25179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25180 },
25181/* movll r0l,$Dst32RnPrefixedQI */
25182 {
25183 M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24,
6772dd07 25184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25185 },
25186/* movll r0l,$Dst32AnPrefixedQI */
25187 {
25188 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24,
6772dd07 25189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25190 },
25191/* movll r0l,[$Dst32AnPrefixed] */
25192 {
25193 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24,
6772dd07 25194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25195 },
25196/* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25197 {
25198 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
6772dd07 25199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25200 },
25201/* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25202 {
25203 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
6772dd07 25204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25205 },
25206/* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25207 {
25208 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
6772dd07 25209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25210 },
25211/* movll r0l,${Dsp-24-u8}[sb] */
25212 {
25213 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
6772dd07 25214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25215 },
25216/* movll r0l,${Dsp-24-u16}[sb] */
25217 {
25218 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
6772dd07 25219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25220 },
25221/* movll r0l,${Dsp-24-s8}[fb] */
25222 {
25223 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
6772dd07 25224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25225 },
25226/* movll r0l,${Dsp-24-s16}[fb] */
25227 {
25228 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
6772dd07 25229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25230 },
25231/* movll r0l,${Dsp-24-u16} */
25232 {
25233 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
6772dd07 25234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25235 },
25236/* movll r0l,${Dsp-24-u24} */
25237 {
25238 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
6772dd07 25239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25240 },
25241/* movhh $Dst16RnQI,r0l */
25242 {
25243 M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16,
6772dd07 25244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25245 },
25246/* movhh $Dst16AnQI,r0l */
25247 {
25248 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16,
6772dd07 25249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25250 },
25251/* movhh [$Dst16An],r0l */
25252 {
25253 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16,
6772dd07 25254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25255 },
25256/* movhh ${Dsp-16-u8}[$Dst16An],r0l */
25257 {
25258 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24,
6772dd07 25259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25260 },
25261/* movhh ${Dsp-16-u16}[$Dst16An],r0l */
25262 {
25263 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32,
6772dd07 25264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25265 },
25266/* movhh ${Dsp-16-u8}[sb],r0l */
25267 {
25268 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24,
6772dd07 25269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25270 },
25271/* movhh ${Dsp-16-u16}[sb],r0l */
25272 {
25273 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32,
6772dd07 25274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25275 },
25276/* movhh ${Dsp-16-s8}[fb],r0l */
25277 {
25278 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24,
6772dd07 25279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25280 },
25281/* movhh ${Dsp-16-u16},r0l */
25282 {
25283 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32,
6772dd07 25284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25285 },
25286/* movhl $Dst16RnQI,r0l */
25287 {
25288 M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16,
6772dd07 25289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25290 },
25291/* movhl $Dst16AnQI,r0l */
25292 {
25293 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16,
6772dd07 25294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25295 },
25296/* movhl [$Dst16An],r0l */
25297 {
25298 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16,
6772dd07 25299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25300 },
25301/* movhl ${Dsp-16-u8}[$Dst16An],r0l */
25302 {
25303 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24,
6772dd07 25304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25305 },
25306/* movhl ${Dsp-16-u16}[$Dst16An],r0l */
25307 {
25308 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32,
6772dd07 25309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25310 },
25311/* movhl ${Dsp-16-u8}[sb],r0l */
25312 {
25313 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24,
6772dd07 25314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25315 },
25316/* movhl ${Dsp-16-u16}[sb],r0l */
25317 {
25318 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32,
6772dd07 25319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25320 },
25321/* movhl ${Dsp-16-s8}[fb],r0l */
25322 {
25323 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24,
6772dd07 25324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25325 },
25326/* movhl ${Dsp-16-u16},r0l */
25327 {
25328 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32,
6772dd07 25329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25330 },
25331/* movlh $Dst16RnQI,r0l */
25332 {
25333 M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16,
6772dd07 25334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25335 },
25336/* movlh $Dst16AnQI,r0l */
25337 {
25338 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16,
6772dd07 25339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25340 },
25341/* movlh [$Dst16An],r0l */
25342 {
25343 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16,
6772dd07 25344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25345 },
25346/* movlh ${Dsp-16-u8}[$Dst16An],r0l */
25347 {
25348 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24,
6772dd07 25349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25350 },
25351/* movlh ${Dsp-16-u16}[$Dst16An],r0l */
25352 {
25353 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32,
6772dd07 25354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25355 },
25356/* movlh ${Dsp-16-u8}[sb],r0l */
25357 {
25358 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24,
6772dd07 25359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25360 },
25361/* movlh ${Dsp-16-u16}[sb],r0l */
25362 {
25363 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32,
6772dd07 25364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25365 },
25366/* movlh ${Dsp-16-s8}[fb],r0l */
25367 {
25368 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24,
6772dd07 25369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25370 },
25371/* movlh ${Dsp-16-u16},r0l */
25372 {
25373 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32,
6772dd07 25374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25375 },
25376/* movll $Dst16RnQI,r0l */
25377 {
25378 M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16,
6772dd07 25379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25380 },
25381/* movll $Dst16AnQI,r0l */
25382 {
25383 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16,
6772dd07 25384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25385 },
25386/* movll [$Dst16An],r0l */
25387 {
25388 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16,
6772dd07 25389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25390 },
25391/* movll ${Dsp-16-u8}[$Dst16An],r0l */
25392 {
25393 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24,
6772dd07 25394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25395 },
25396/* movll ${Dsp-16-u16}[$Dst16An],r0l */
25397 {
25398 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32,
6772dd07 25399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25400 },
25401/* movll ${Dsp-16-u8}[sb],r0l */
25402 {
25403 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24,
6772dd07 25404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25405 },
25406/* movll ${Dsp-16-u16}[sb],r0l */
25407 {
25408 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32,
6772dd07 25409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25410 },
25411/* movll ${Dsp-16-s8}[fb],r0l */
25412 {
25413 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24,
6772dd07 25414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25415 },
25416/* movll ${Dsp-16-u16},r0l */
25417 {
25418 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32,
6772dd07 25419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25420 },
25421/* movhh r0l,$Dst16RnQI */
25422 {
25423 M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16,
6772dd07 25424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25425 },
25426/* movhh r0l,$Dst16AnQI */
25427 {
25428 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16,
6772dd07 25429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25430 },
25431/* movhh r0l,[$Dst16An] */
25432 {
25433 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16,
6772dd07 25434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25435 },
25436/* movhh r0l,${Dsp-16-u8}[$Dst16An] */
25437 {
25438 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24,
6772dd07 25439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25440 },
25441/* movhh r0l,${Dsp-16-u16}[$Dst16An] */
25442 {
25443 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32,
6772dd07 25444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25445 },
25446/* movhh r0l,${Dsp-16-u8}[sb] */
25447 {
25448 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24,
6772dd07 25449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25450 },
25451/* movhh r0l,${Dsp-16-u16}[sb] */
25452 {
25453 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32,
6772dd07 25454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25455 },
25456/* movhh r0l,${Dsp-16-s8}[fb] */
25457 {
25458 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24,
6772dd07 25459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25460 },
25461/* movhh r0l,${Dsp-16-u16} */
25462 {
25463 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32,
6772dd07 25464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25465 },
25466/* movhl r0l,$Dst16RnQI */
25467 {
25468 M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16,
6772dd07 25469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25470 },
25471/* movhl r0l,$Dst16AnQI */
25472 {
25473 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16,
6772dd07 25474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25475 },
25476/* movhl r0l,[$Dst16An] */
25477 {
25478 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16,
6772dd07 25479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25480 },
25481/* movhl r0l,${Dsp-16-u8}[$Dst16An] */
25482 {
25483 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24,
6772dd07 25484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25485 },
25486/* movhl r0l,${Dsp-16-u16}[$Dst16An] */
25487 {
25488 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32,
6772dd07 25489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25490 },
25491/* movhl r0l,${Dsp-16-u8}[sb] */
25492 {
25493 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24,
6772dd07 25494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25495 },
25496/* movhl r0l,${Dsp-16-u16}[sb] */
25497 {
25498 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32,
6772dd07 25499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25500 },
25501/* movhl r0l,${Dsp-16-s8}[fb] */
25502 {
25503 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24,
6772dd07 25504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25505 },
25506/* movhl r0l,${Dsp-16-u16} */
25507 {
25508 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32,
6772dd07 25509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25510 },
25511/* movlh r0l,$Dst16RnQI */
25512 {
25513 M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16,
6772dd07 25514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25515 },
25516/* movlh r0l,$Dst16AnQI */
25517 {
25518 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16,
6772dd07 25519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25520 },
25521/* movlh r0l,[$Dst16An] */
25522 {
25523 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16,
6772dd07 25524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25525 },
25526/* movlh r0l,${Dsp-16-u8}[$Dst16An] */
25527 {
25528 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24,
6772dd07 25529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25530 },
25531/* movlh r0l,${Dsp-16-u16}[$Dst16An] */
25532 {
25533 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32,
6772dd07 25534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25535 },
25536/* movlh r0l,${Dsp-16-u8}[sb] */
25537 {
25538 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24,
6772dd07 25539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25540 },
25541/* movlh r0l,${Dsp-16-u16}[sb] */
25542 {
25543 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32,
6772dd07 25544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25545 },
25546/* movlh r0l,${Dsp-16-s8}[fb] */
25547 {
25548 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24,
6772dd07 25549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25550 },
25551/* movlh r0l,${Dsp-16-u16} */
25552 {
25553 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32,
6772dd07 25554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25555 },
25556/* movll r0l,$Dst16RnQI */
25557 {
25558 M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16,
6772dd07 25559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25560 },
25561/* movll r0l,$Dst16AnQI */
25562 {
25563 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16,
6772dd07 25564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25565 },
25566/* movll r0l,[$Dst16An] */
25567 {
25568 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16,
6772dd07 25569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25570 },
25571/* movll r0l,${Dsp-16-u8}[$Dst16An] */
25572 {
25573 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24,
6772dd07 25574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25575 },
25576/* movll r0l,${Dsp-16-u16}[$Dst16An] */
25577 {
25578 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32,
6772dd07 25579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25580 },
25581/* movll r0l,${Dsp-16-u8}[sb] */
25582 {
25583 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24,
6772dd07 25584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25585 },
25586/* movll r0l,${Dsp-16-u16}[sb] */
25587 {
25588 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32,
6772dd07 25589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25590 },
25591/* movll r0l,${Dsp-16-s8}[fb] */
25592 {
25593 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24,
6772dd07 25594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25595 },
25596/* movll r0l,${Dsp-16-u16} */
25597 {
25598 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32,
6772dd07 25599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25600 },
25601/* mova [$Dst32AnUnprefixed],a1 */
25602 {
25603 M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
6772dd07 25604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25605 },
25606/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
25607 {
25608 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25610 },
25611/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
25612 {
25613 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25615 },
25616/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
25617 {
25618 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25620 },
25621/* mova ${Dsp-16-u8}[sb],a1 */
25622 {
25623 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25625 },
25626/* mova ${Dsp-16-u16}[sb],a1 */
25627 {
25628 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25630 },
25631/* mova ${Dsp-16-s8}[fb],a1 */
25632 {
25633 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25635 },
25636/* mova ${Dsp-16-s16}[fb],a1 */
25637 {
25638 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25640 },
25641/* mova ${Dsp-16-u16},a1 */
25642 {
25643 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25645 },
25646/* mova ${Dsp-16-u24},a1 */
25647 {
25648 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25650 },
25651/* mova [$Dst32AnUnprefixed],a0 */
25652 {
25653 M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
6772dd07 25654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25655 },
25656/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
25657 {
25658 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25660 },
25661/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
25662 {
25663 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25665 },
25666/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
25667 {
25668 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25670 },
25671/* mova ${Dsp-16-u8}[sb],a0 */
25672 {
25673 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25675 },
25676/* mova ${Dsp-16-u16}[sb],a0 */
25677 {
25678 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25680 },
25681/* mova ${Dsp-16-s8}[fb],a0 */
25682 {
25683 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25685 },
25686/* mova ${Dsp-16-s16}[fb],a0 */
25687 {
25688 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25690 },
25691/* mova ${Dsp-16-u16},a0 */
25692 {
25693 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25695 },
25696/* mova ${Dsp-16-u24},a0 */
25697 {
25698 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25700 },
25701/* mova [$Dst32AnUnprefixed],r3r1 */
25702 {
25703 M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
6772dd07 25704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25705 },
25706/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
25707 {
25708 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25710 },
25711/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
25712 {
25713 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25715 },
25716/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
25717 {
25718 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25720 },
25721/* mova ${Dsp-16-u8}[sb],r3r1 */
25722 {
25723 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25725 },
25726/* mova ${Dsp-16-u16}[sb],r3r1 */
25727 {
25728 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25730 },
25731/* mova ${Dsp-16-s8}[fb],r3r1 */
25732 {
25733 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25735 },
25736/* mova ${Dsp-16-s16}[fb],r3r1 */
25737 {
25738 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25740 },
25741/* mova ${Dsp-16-u16},r3r1 */
25742 {
25743 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25745 },
25746/* mova ${Dsp-16-u24},r3r1 */
25747 {
25748 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25750 },
25751/* mova [$Dst32AnUnprefixed],r2r0 */
25752 {
25753 M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
6772dd07 25754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25755 },
25756/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
25757 {
25758 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25760 },
25761/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
25762 {
25763 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25765 },
25766/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
25767 {
25768 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25770 },
25771/* mova ${Dsp-16-u8}[sb],r2r0 */
25772 {
25773 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25775 },
25776/* mova ${Dsp-16-u16}[sb],r2r0 */
25777 {
25778 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25780 },
25781/* mova ${Dsp-16-s8}[fb],r2r0 */
25782 {
25783 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
6772dd07 25784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25785 },
25786/* mova ${Dsp-16-s16}[fb],r2r0 */
25787 {
25788 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25790 },
25791/* mova ${Dsp-16-u16},r2r0 */
25792 {
25793 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
6772dd07 25794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25795 },
25796/* mova ${Dsp-16-u24},r2r0 */
25797 {
25798 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
6772dd07 25799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25800 },
25801/* mova [$Dst16An],a1 */
25802 {
25803 M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16,
6772dd07 25804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25805 },
25806/* mova ${Dsp-16-u8}[$Dst16An],a1 */
25807 {
25808 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
6772dd07 25809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25810 },
25811/* mova ${Dsp-16-u16}[$Dst16An],a1 */
25812 {
25813 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
6772dd07 25814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25815 },
25816/* mova ${Dsp-16-u8}[sb],a1 */
25817 {
25818 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
6772dd07 25819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25820 },
25821/* mova ${Dsp-16-u16}[sb],a1 */
25822 {
25823 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
6772dd07 25824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25825 },
25826/* mova ${Dsp-16-s8}[fb],a1 */
25827 {
25828 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
6772dd07 25829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25830 },
25831/* mova ${Dsp-16-u16},a1 */
25832 {
25833 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32,
6772dd07 25834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25835 },
25836/* mova [$Dst16An],a0 */
25837 {
25838 M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16,
6772dd07 25839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25840 },
25841/* mova ${Dsp-16-u8}[$Dst16An],a0 */
25842 {
25843 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
6772dd07 25844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25845 },
25846/* mova ${Dsp-16-u16}[$Dst16An],a0 */
25847 {
25848 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
6772dd07 25849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25850 },
25851/* mova ${Dsp-16-u8}[sb],a0 */
25852 {
25853 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
6772dd07 25854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25855 },
25856/* mova ${Dsp-16-u16}[sb],a0 */
25857 {
25858 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
6772dd07 25859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25860 },
25861/* mova ${Dsp-16-s8}[fb],a0 */
25862 {
25863 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
6772dd07 25864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25865 },
25866/* mova ${Dsp-16-u16},a0 */
25867 {
25868 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32,
6772dd07 25869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25870 },
25871/* mova [$Dst16An],r3 */
25872 {
25873 M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16,
6772dd07 25874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25875 },
25876/* mova ${Dsp-16-u8}[$Dst16An],r3 */
25877 {
25878 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24,
6772dd07 25879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25880 },
25881/* mova ${Dsp-16-u16}[$Dst16An],r3 */
25882 {
25883 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32,
6772dd07 25884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25885 },
25886/* mova ${Dsp-16-u8}[sb],r3 */
25887 {
25888 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
6772dd07 25889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25890 },
25891/* mova ${Dsp-16-u16}[sb],r3 */
25892 {
25893 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
6772dd07 25894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25895 },
25896/* mova ${Dsp-16-s8}[fb],r3 */
25897 {
25898 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
6772dd07 25899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25900 },
25901/* mova ${Dsp-16-u16},r3 */
25902 {
25903 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32,
6772dd07 25904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25905 },
25906/* mova [$Dst16An],r2 */
25907 {
25908 M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16,
6772dd07 25909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25910 },
25911/* mova ${Dsp-16-u8}[$Dst16An],r2 */
25912 {
25913 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24,
6772dd07 25914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25915 },
25916/* mova ${Dsp-16-u16}[$Dst16An],r2 */
25917 {
25918 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32,
6772dd07 25919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25920 },
25921/* mova ${Dsp-16-u8}[sb],r2 */
25922 {
25923 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
6772dd07 25924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25925 },
25926/* mova ${Dsp-16-u16}[sb],r2 */
25927 {
25928 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
6772dd07 25929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25930 },
25931/* mova ${Dsp-16-s8}[fb],r2 */
25932 {
25933 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
6772dd07 25934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25935 },
25936/* mova ${Dsp-16-u16},r2 */
25937 {
25938 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32,
6772dd07 25939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25940 },
25941/* mova [$Dst16An],r1 */
25942 {
25943 M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16,
6772dd07 25944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25945 },
25946/* mova ${Dsp-16-u8}[$Dst16An],r1 */
25947 {
25948 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
6772dd07 25949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25950 },
25951/* mova ${Dsp-16-u16}[$Dst16An],r1 */
25952 {
25953 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
6772dd07 25954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25955 },
25956/* mova ${Dsp-16-u8}[sb],r1 */
25957 {
25958 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
6772dd07 25959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25960 },
25961/* mova ${Dsp-16-u16}[sb],r1 */
25962 {
25963 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
6772dd07 25964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25965 },
25966/* mova ${Dsp-16-s8}[fb],r1 */
25967 {
25968 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
6772dd07 25969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25970 },
25971/* mova ${Dsp-16-u16},r1 */
25972 {
25973 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32,
6772dd07 25974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25975 },
25976/* mova [$Dst16An],r0 */
25977 {
25978 M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16,
6772dd07 25979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25980 },
25981/* mova ${Dsp-16-u8}[$Dst16An],r0 */
25982 {
25983 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
6772dd07 25984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25985 },
25986/* mova ${Dsp-16-u16}[$Dst16An],r0 */
25987 {
25988 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
6772dd07 25989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25990 },
25991/* mova ${Dsp-16-u8}[sb],r0 */
25992 {
25993 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
6772dd07 25994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 25995 },
25996/* mova ${Dsp-16-u16}[sb],r0 */
25997 {
25998 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
6772dd07 25999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26000 },
26001/* mova ${Dsp-16-s8}[fb],r0 */
26002 {
26003 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
6772dd07 26004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26005 },
26006/* mova ${Dsp-16-u16},r0 */
26007 {
26008 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32,
6772dd07 26009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26010 },
f75eb1c0 26011/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
49f58d10
JB		 26012 {
26013 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 26014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26015 },
f75eb1c0 26016/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26017 {
26018 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 26019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26020 },
f75eb1c0 26021/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26022 {
26023 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 26024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26025 },
f75eb1c0 26026/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
49f58d10
JB		 26027 {
26028 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 26029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26030 },
f75eb1c0 26031/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 26032 {
26033 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 26034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26035 },
f75eb1c0 26036/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
49f58d10
JB		 26037 {
26038 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 26039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26040 },
f75eb1c0 26041/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 26042 {
26043 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 26044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26045 },
f75eb1c0 26046/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
49f58d10
JB		 26047 {
26048 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 26049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26050 },
f75eb1c0 26051/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
49f58d10
JB		 26052 {
26053 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 26054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26055 },
f75eb1c0 26056/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26057 {
26058 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 26059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26060 },
f75eb1c0 26061/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26062 {
26063 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 26064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26065 },
f75eb1c0 26066/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
49f58d10
JB		 26067 {
26068 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
6772dd07 26069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26070 },
f75eb1c0 26071/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
49f58d10
JB		 26072 {
26073 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 26074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26075 },
f75eb1c0 26076/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26077 {
26078 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 26079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26080 },
f75eb1c0 26081/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26082 {
26083 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 26084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26085 },
f75eb1c0 26086/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
49f58d10
JB		 26087 {
26088 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 26089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26090 },
f75eb1c0 26091/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 26092 {
26093 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 26094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26095 },
f75eb1c0 26096/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
49f58d10
JB		 26097 {
26098 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 26099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26100 },
f75eb1c0 26101/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 26102 {
26103 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 26104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26105 },
f75eb1c0 26106/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
49f58d10
JB		 26107 {
26108 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 26109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26110 },
f75eb1c0 26111/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
49f58d10
JB		 26112 {
26113 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 26114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26115 },
f75eb1c0 26116/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26117 {
26118 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 26119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26120 },
f75eb1c0 26121/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26122 {
26123 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 26124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26125 },
f75eb1c0 26126/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
49f58d10
JB		 26127 {
26128 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
6772dd07 26129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26130 },
f75eb1c0 26131/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
49f58d10
JB		 26132 {
26133 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
6772dd07 26134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26135 },
f75eb1c0 26136/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26137 {
26138 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
6772dd07 26139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26140 },
f75eb1c0 26141/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26142 {
26143 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
6772dd07 26144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26145 },
f75eb1c0 26146/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
49f58d10
JB		 26147 {
26148 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
6772dd07 26149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26150 },
f75eb1c0 26151/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 26152 {
26153 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
6772dd07 26154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26155 },
f75eb1c0 26156/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 26157 {
26158 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
6772dd07 26159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26160 },
f75eb1c0 26161/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26162 {
26163 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24,
6772dd07 26164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26165 },
f75eb1c0 26166/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26167 {
26168 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24,
6772dd07 26169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26170 },
f75eb1c0 26171/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
49f58d10
JB		 26172 {
26173 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24,
6772dd07 26174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26175 },
f75eb1c0 26176/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
49f58d10
JB		 26177 {
26178 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
6772dd07 26179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26180 },
f75eb1c0 26181/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26182 {
26183 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
6772dd07 26184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26185 },
f75eb1c0 26186/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
49f58d10
JB		 26187 {
26188 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
6772dd07 26189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26190 },
f75eb1c0 26191/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
49f58d10
JB		 26192 {
26193 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
6772dd07 26194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26195 },
f75eb1c0 26196/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
49f58d10
JB		 26197 {
26198 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
6772dd07 26199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26200 },
f75eb1c0 26201/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
49f58d10
JB		 26202 {
26203 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
6772dd07 26204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26205 },
f75eb1c0 26206/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26207 {
26208 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24,
6772dd07 26209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26210 },
f75eb1c0 26211/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
49f58d10
JB		 26212 {
26213 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24,
6772dd07 26214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26215 },
f75eb1c0 26216/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
49f58d10
JB		 26217 {
26218 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24,
6772dd07 26219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26220 },
f75eb1c0 26221/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 26222 {
26223 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 26224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26225 },
f75eb1c0 26226/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 26227 {
26228 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 26229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26230 },
f75eb1c0 26231/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 26232 {
26233 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 26234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26235 },
f75eb1c0 26236/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 26237 {
26238 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 26239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26240 },
f75eb1c0 26241/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 26242 {
26243 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 26244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26245 },
f75eb1c0 26246/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
49f58d10
JB		 26247 {
26248 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 26249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26250 },
f75eb1c0 26251/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 26252 {
26253 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 26254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26255 },
f75eb1c0 26256/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 26257 {
26258 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 26259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26260 },
f75eb1c0 26261/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
49f58d10
JB		 26262 {
26263 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 26264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26265 },
f75eb1c0 26266/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
49f58d10
JB		 26267 {
26268 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 26269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26270 },
f75eb1c0 26271/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
49f58d10
JB		 26272 {
26273 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 26274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26275 },
f75eb1c0 26276/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
49f58d10
JB		 26277 {
26278 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
6772dd07 26279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26280 },
f75eb1c0 26281/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49f58d10
JB		 26282 {
26283 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 26284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26285 },
f75eb1c0 26286/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 26287 {
26288 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 26289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26290 },
f75eb1c0 26291/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 26292 {
26293 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 26294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26295 },
f75eb1c0 26296/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49f58d10
JB		 26297 {
26298 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 26299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26300 },
f75eb1c0 26301/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 26302 {
26303 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 26304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26305 },
f75eb1c0 26306/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
49f58d10
JB		 26307 {
26308 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 26309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26310 },
f75eb1c0 26311/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 26312 {
26313 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 26314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26315 },
f75eb1c0 26316/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10
JB		 26317 {
26318 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 26319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26320 },
f75eb1c0 26321/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
49f58d10
JB		 26322 {
26323 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 26324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26325 },
f75eb1c0 26326/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
49f58d10
JB		 26327 {
26328 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 26329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26330 },
f75eb1c0 26331/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
49f58d10
JB		 26332 {
26333 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 26334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26335 },
f75eb1c0 26336/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
49f58d10
JB		 26337 {
26338 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
6772dd07 26339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26340 },
f75eb1c0 26341/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 26342 {
26343 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
6772dd07 26344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26345 },
f75eb1c0 26346/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 26347 {
26348 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
6772dd07 26349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26350 },
f75eb1c0 26351/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 26352 {
26353 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
6772dd07 26354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26355 },
f75eb1c0 26356/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 26357 {
26358 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
6772dd07 26359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26360 },
f75eb1c0 26361/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 26362 {
26363 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
6772dd07 26364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26365 },
f75eb1c0 26366/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 26367 {
26368 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
6772dd07 26369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26370 },
f75eb1c0 26371/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
49f58d10
JB		 26372 {
26373 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24,
6772dd07 26374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26375 },
f75eb1c0 26376/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
49f58d10
JB		 26377 {
26378 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24,
6772dd07 26379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26380 },
f75eb1c0 26381/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
49f58d10
JB		 26382 {
26383 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24,
6772dd07 26384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26385 },
f75eb1c0 26386/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
49f58d10
JB		 26387 {
26388 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
6772dd07 26389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26390 },
f75eb1c0 26391/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
49f58d10
JB		 26392 {
26393 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
6772dd07 26394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26395 },
f75eb1c0 26396/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
49f58d10
JB		 26397 {
26398 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
6772dd07 26399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26400 },
f75eb1c0 26401/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
49f58d10
JB		 26402 {
26403 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
6772dd07 26404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26405 },
f75eb1c0 26406/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
49f58d10
JB		 26407 {
26408 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
6772dd07 26409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26410 },
f75eb1c0 26411/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
49f58d10
JB		 26412 {
26413 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
6772dd07 26414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26415 },
f75eb1c0 26416/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
49f58d10
JB		 26417 {
26418 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24,
6772dd07 26419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26420 },
f75eb1c0 26421/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
49f58d10
JB		 26422 {
26423 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24,
6772dd07 26424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26425 },
f75eb1c0 26426/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
49f58d10
JB		 26427 {
26428 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24,
6772dd07 26429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26430 },
26431/* mov.l${S} ${Dsp-8-u8}[sb],a1 */
26432 {
26433 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
6772dd07 26434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26435 },
26436/* mov.l${S} ${Dsp-8-s8}[fb],a1 */
26437 {
26438 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
6772dd07 26439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26440 },
26441/* mov.l${S} ${Dsp-8-u8}[sb],a0 */
26442 {
26443 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
6772dd07 26444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26445 },
26446/* mov.l${S} ${Dsp-8-s8}[fb],a0 */
26447 {
26448 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
6772dd07 26449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26450 },
26451/* mov.l${S} ${Dsp-8-u16},a1 */
26452 {
26453 M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24,
6772dd07 26454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26455 },
26456/* mov.l${S} ${Dsp-8-u16},a0 */
26457 {
26458 M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24,
6772dd07 26459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26460 },
26461/* mov.w${S} r0,${Dsp-8-u8}[sb] */
26462 {
26463 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
6772dd07 26464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26465 },
26466/* mov.w${S} r0,${Dsp-8-s8}[fb] */
26467 {
26468 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
6772dd07 26469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26470 },
26471/* mov.b${S} r0l,${Dsp-8-u8}[sb] */
26472 {
26473 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
6772dd07 26474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26475 },
26476/* mov.b${S} r0l,${Dsp-8-s8}[fb] */
26477 {
26478 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
6772dd07 26479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26480 },
26481/* mov.w${S} r0,${Dsp-8-u16} */
26482 {
26483 M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
6772dd07 26484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26485 },
26486/* mov.b${S} r0l,${Dsp-8-u16} */
26487 {
26488 M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
6772dd07 26489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26490 },
26491/* mov.w${S} ${Dsp-8-u8}[sb],r1 */
26492 {
26493 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
6772dd07 26494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26495 },
26496/* mov.w${S} ${Dsp-8-s8}[fb],r1 */
26497 {
26498 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
6772dd07 26499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26500 },
26501/* mov.b${S} ${Dsp-8-u8}[sb],r1l */
26502 {
26503 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
6772dd07 26504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26505 },
26506/* mov.b${S} ${Dsp-8-s8}[fb],r1l */
26507 {
26508 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
6772dd07 26509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26510 },
26511/* mov.w${S} ${Dsp-8-u16},r1 */
26512 {
26513 M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24,
6772dd07 26514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26515 },
26516/* mov.b${S} ${Dsp-8-u16},r1l */
26517 {
26518 M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24,
6772dd07 26519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 26520 },
f75eb1c0 26521/* mov.w${S} r0,r1 */
49f58d10 26522 {
f75eb1c0 26523 M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1-dst32-2-S-R0-direct-HI", "mov.w", 8,
6772dd07 26524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26525 },
26526/* mov.b${S} r0l,r1l */
26527 {
26528 M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8,
6772dd07 26529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26530 },
26531/* mov.w${S} ${Dsp-8-u8}[sb],r0 */
26532 {
26533 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
6772dd07 26534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26535 },
26536/* mov.w${S} ${Dsp-8-s8}[fb],r0 */
26537 {
26538 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
6772dd07 26539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26540 },
26541/* mov.b${S} ${Dsp-8-u8}[sb],r0l */
26542 {
26543 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
6772dd07 26544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26545 },
26546/* mov.b${S} ${Dsp-8-s8}[fb],r0l */
26547 {
26548 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
6772dd07 26549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26550 },
26551/* mov.w${S} ${Dsp-8-u16},r0 */
26552 {
26553 M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24,
6772dd07 26554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26555 },
26556/* mov.b${S} ${Dsp-8-u16},r0l */
26557 {
26558 M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24,
6772dd07 26559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26560 },
26561/* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
26562 {
26563 M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8,
6772dd07 26564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26565 },
26566/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
26567 {
26568 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16,
6772dd07 26569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26570 },
26571/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
26572 {
26573 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16,
6772dd07 26574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26575 },
26576/* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
26577 {
26578 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24,
6772dd07 26579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26580 },
26581/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
26582 {
26583 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
6772dd07 26584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26585 },
26586/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
26587 {
26588 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
6772dd07 26589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26590 },
26591/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
26592 {
26593 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24,
6772dd07 26594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 26595 },
26596/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26597 {
26598 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
6772dd07 26599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26600 },
26601/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
26602 {
26603 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
6772dd07 26604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26605 },
26606/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
26607 {
26608 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
6772dd07 26609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26610 },
26611/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26612 {
26613 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
6772dd07 26614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26615 },
26616/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
26617 {
26618 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
6772dd07 26619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26620 },
26621/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
26622 {
26623 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
6772dd07 26624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26625 },
26626/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26627 {
26628 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
6772dd07 26629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26630 },
26631/* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
26632 {
26633 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
6772dd07 26634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26635 },
26636/* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
26637 {
26638 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
6772dd07 26639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26640 },
26641/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26642 {
26643 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26645 },
26646/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26647 {
26648 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26650 },
26651/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26652 {
26653 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26655 },
26656/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26657 {
26658 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26660 },
26661/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26662 {
26663 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26665 },
26666/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26667 {
26668 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26670 },
26671/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26672 {
26673 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26675 },
26676/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26677 {
26678 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26680 },
26681/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26682 {
26683 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26685 },
26686/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
26687 {
26688 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26690 },
26691/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26692 {
26693 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26695 },
26696/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26697 {
26698 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26700 },
26701/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
26702 {
26703 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26705 },
26706/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26707 {
26708 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26710 },
26711/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26712 {
26713 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26715 },
26716/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
26717 {
26718 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26720 },
26721/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26722 {
26723 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26725 },
26726/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26727 {
26728 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 26729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26730 },
26731/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
26732 {
26733 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26735 },
26736/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
26737 {
26738 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26740 },
26741/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
26742 {
26743 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26745 },
26746/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
26747 {
26748 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
6772dd07 26749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26750 },
26751/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26752 {
26753 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
6772dd07 26754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26755 },
26756/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26757 {
26758 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
6772dd07 26759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26760 },
26761/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
26762 {
26763 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
6772dd07 26764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26765 },
26766/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
26767 {
26768 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
6772dd07 26769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26770 },
26771/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
26772 {
26773 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
6772dd07 26774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26775 },
26776/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26777 {
26778 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26780 },
26781/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
26782 {
26783 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26785 },
26786/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
26787 {
26788 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26790 },
26791/* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
26792 {
26793 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26795 },
26796/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26797 {
26798 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26800 },
26801/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
26802 {
26803 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26805 },
26806/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
26807 {
26808 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26810 },
26811/* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
26812 {
26813 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
6772dd07 26814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26815 },
26816/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26817 {
26818 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
6772dd07 26819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26820 },
26821/* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
26822 {
26823 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
6772dd07 26824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26825 },
26826/* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
26827 {
26828 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
6772dd07 26829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26830 },
26831/* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
26832 {
26833 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
6772dd07 26834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26835 },
26836/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26837 {
26838 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26840 },
26841/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26842 {
26843 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26845 },
26846/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26847 {
26848 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26850 },
26851/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
26852 {
26853 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26855 },
26856/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26857 {
26858 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26860 },
26861/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26862 {
26863 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26865 },
26866/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26867 {
26868 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26870 },
26871/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
26872 {
26873 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26875 },
26876/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26877 {
26878 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 26879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26880 },
26881/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26882 {
26883 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 26884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26885 },
26886/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26887 {
26888 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 26889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26890 },
26891/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
26892 {
26893 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 26894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26895 },
26896/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
26897 {
26898 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26900 },
26901/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26902 {
26903 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26905 },
26906/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
26907 {
26908 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26910 },
26911/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26912 {
26913 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26915 },
26916/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
26917 {
26918 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26920 },
26921/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26922 {
26923 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26925 },
26926/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
26927 {
26928 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26930 },
26931/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26932 {
26933 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26935 },
26936/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
26937 {
26938 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26940 },
26941/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26942 {
26943 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26945 },
26946/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
26947 {
26948 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26950 },
26951/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26952 {
26953 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 26954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26955 },
26956/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
26957 {
26958 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26960 },
26961/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
26962 {
26963 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26965 },
26966/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
26967 {
26968 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26970 },
26971/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
26972 {
26973 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 26974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26975 },
26976/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
26977 {
26978 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
6772dd07 26979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26980 },
26981/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26982 {
26983 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
6772dd07 26984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26985 },
26986/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
26987 {
26988 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
6772dd07 26989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26990 },
26991/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
26992 {
26993 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
6772dd07 26994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 26995 },
26996/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
26997 {
26998 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
6772dd07 26999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27000 },
27001/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
27002 {
27003 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
6772dd07 27004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27005 },
27006/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
27007 {
27008 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
6772dd07 27009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27010 },
27011/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
27012 {
27013 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
6772dd07 27014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27015 },
27016/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
27017 {
27018 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
6772dd07 27019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27020 },
27021/* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
27022 {
27023 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
6772dd07 27024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27025 },
27026/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
27027 {
27028 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
6772dd07 27029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27030 },
27031/* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
27032 {
27033 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
6772dd07 27034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27035 },
27036/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27037 {
27038 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
6772dd07 27039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27040 },
27041/* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27042 {
27043 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
6772dd07 27044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27045 },
27046/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27047 {
27048 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 27049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27050 },
27051/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27052 {
27053 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 27054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27055 },
27056/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27057 {
27058 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 27059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27060 },
27061/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27062 {
27063 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 27064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27065 },
27066/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27067 {
27068 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
6772dd07 27069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27070 },
27071/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27072 {
27073 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
6772dd07 27074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27075 },
27076/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27077 {
27078 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 27079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27080 },
27081/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27082 {
27083 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 27084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27085 },
27086/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27087 {
27088 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 27089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27090 },
27091/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27092 {
27093 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 27094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27095 },
27096/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27097 {
27098 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 27099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27100 },
27101/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27102 {
27103 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
6772dd07 27104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27105 },
27106/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27107 {
27108 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 27109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27110 },
27111/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27112 {
27113 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 27114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27115 },
27116/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27117 {
27118 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
6772dd07 27119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27120 },
27121/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
27122 {
27123 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
6772dd07 27124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27125 },
27126/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27127 {
27128 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
6772dd07 27129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27130 },
27131/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
27132 {
27133 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
6772dd07 27134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27135 },
27136/* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
27137 {
27138 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
6772dd07 27139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27140 },
27141/* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
27142 {
27143 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
6772dd07 27144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27145 },
27146/* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
27147 {
27148 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
6772dd07 27149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27150 },
27151/* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
27152 {
27153 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
6772dd07 27154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27155 },
27156/* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
27157 {
27158 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
6772dd07 27159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27160 },
27161/* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
27162 {
27163 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
6772dd07 27164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27165 },
27166/* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
27167 {
27168 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
6772dd07 27169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27170 },
27171/* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
27172 {
27173 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
6772dd07 27174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27175 },
27176/* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27177 {
27178 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
6772dd07 27179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27180 },
27181/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27182 {
27183 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27185 },
27186/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27187 {
27188 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27190 },
27191/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27192 {
27193 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27195 },
27196/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27197 {
27198 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27200 },
27201/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27202 {
27203 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27205 },
27206/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27207 {
27208 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27210 },
27211/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27212 {
27213 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 27214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27215 },
27216/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27217 {
27218 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 27219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27220 },
27221/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27222 {
27223 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
6772dd07 27224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27225 },
27226/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
27227 {
27228 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27230 },
27231/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
27232 {
27233 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27235 },
27236/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27237 {
27238 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27240 },
27241/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
27242 {
27243 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27245 },
27246/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
27247 {
27248 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27250 },
27251/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27252 {
27253 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27255 },
27256/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
27257 {
27258 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27260 },
27261/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
27262 {
27263 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27265 },
27266/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27267 {
27268 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
6772dd07 27269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27270 },
27271/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
27272 {
27273 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27275 },
27276/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
27277 {
27278 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27280 },
27281/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27282 {
27283 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
6772dd07 27284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27285 },
27286/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
27287 {
27288 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
6772dd07 27289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27290 },
27291/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
27292 {
27293 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
6772dd07 27294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27295 },
27296/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
27297 {
27298 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
6772dd07 27299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27300 },
27301/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
27302 {
27303 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
6772dd07 27304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27305 },
27306/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
27307 {
27308 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
6772dd07 27309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27310 },
27311/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
27312 {
27313 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
6772dd07 27314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27315 },
27316/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
27317 {
27318 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
6772dd07 27319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 27320 },
27321/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
27322 {
27323 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
6772dd07 27324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 27325 },
27326/* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
27327 {
27328 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24,
6772dd07 27329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 27330 },
27331/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27332 {
27333 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 27334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27335 },
27336/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
27337 {
27338 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 27339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27340 },
27341/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
27342 {
27343 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 27344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27345 },
27346/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27347 {
27348 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 27349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27350 },
27351/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
27352 {
27353 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 27354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27355 },
27356/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
27357 {
27358 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
6772dd07 27359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27360 },
27361/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27362 {
27363 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
6772dd07 27364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27365 },
27366/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
27367 {
27368 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
6772dd07 27369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27370 },
27371/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
27372 {
27373 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
6772dd07 27374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27375 },
27376/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27377 {
27378 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27380 },
27381/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27382 {
27383 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27385 },
27386/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27387 {
27388 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27390 },
27391/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27392 {
27393 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27395 },
27396/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27397 {
27398 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27400 },
27401/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27402 {
27403 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27405 },
27406/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27407 {
27408 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27410 },
27411/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27412 {
27413 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27415 },
27416/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27417 {
27418 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27420 },
27421/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
27422 {
27423 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27425 },
27426/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
27427 {
27428 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27430 },
27431/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
27432 {
27433 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27435 },
27436/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
27437 {
27438 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27440 },
27441/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
27442 {
27443 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27445 },
27446/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
27447 {
27448 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27450 },
27451/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
27452 {
27453 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27455 },
27456/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
27457 {
27458 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27460 },
27461/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
27462 {
27463 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27465 },
27466/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
27467 {
27468 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27470 },
27471/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
27472 {
27473 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27475 },
27476/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
27477 {
27478 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27480 },
27481/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
27482 {
27483 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 27484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27485 },
27486/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
27487 {
27488 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 27489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27490 },
27491/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
27492 {
27493 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 27494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27495 },
27496/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
27497 {
27498 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 27499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27500 },
27501/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
27502 {
27503 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 27504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27505 },
27506/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
27507 {
27508 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 27509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27510 },
27511/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27512 {
27513 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27515 },
27516/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
27517 {
27518 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27520 },
27521/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
27522 {
27523 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27525 },
27526/* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
27527 {
27528 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27530 },
27531/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27532 {
27533 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27535 },
27536/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
27537 {
27538 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27540 },
27541/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
27542 {
27543 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27545 },
27546/* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
27547 {
27548 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 27549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27550 },
27551/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27552 {
27553 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
6772dd07 27554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27555 },
27556/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
27557 {
27558 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
6772dd07 27559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27560 },
27561/* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
27562 {
27563 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
6772dd07 27564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27565 },
27566/* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
27567 {
27568 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
6772dd07 27569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27570 },
27571/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27572 {
27573 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27575 },
27576/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27577 {
27578 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27580 },
27581/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27582 {
27583 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27585 },
27586/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
27587 {
27588 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27590 },
27591/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27592 {
27593 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27595 },
27596/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27597 {
27598 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27600 },
27601/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27602 {
27603 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27605 },
27606/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
27607 {
27608 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27610 },
27611/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27612 {
27613 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27615 },
27616/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27617 {
27618 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27620 },
27621/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27622 {
27623 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27625 },
27626/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
27627 {
27628 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27630 },
27631/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
27632 {
27633 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27635 },
27636/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27637 {
27638 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27640 },
27641/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
27642 {
27643 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27645 },
27646/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27647 {
27648 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27650 },
27651/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
27652 {
27653 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27655 },
27656/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27657 {
27658 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27660 },
27661/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
27662 {
27663 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27665 },
27666/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27667 {
27668 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27670 },
27671/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
27672 {
27673 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27675 },
27676/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27677 {
27678 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27680 },
27681/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
27682 {
27683 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27685 },
27686/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27687 {
27688 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27690 },
27691/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
27692 {
27693 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27695 },
27696/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
27697 {
27698 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27700 },
27701/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
27702 {
27703 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27705 },
27706/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
27707 {
27708 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27710 },
27711/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
27712 {
27713 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 27714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27715 },
27716/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27717 {
27718 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 27719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27720 },
27721/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
27722 {
27723 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 27724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27725 },
27726/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
27727 {
27728 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 27729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27730 },
27731/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
27732 {
27733 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
6772dd07 27734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27735 },
27736/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
27737 {
27738 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
6772dd07 27739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27740 },
27741/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
27742 {
27743 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
6772dd07 27744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27745 },
27746/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
27747 {
27748 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
6772dd07 27749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27750 },
27751/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27752 {
27753 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
6772dd07 27754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27755 },
27756/* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
27757 {
27758 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
6772dd07 27759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27760 },
27761/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27762 {
27763 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
6772dd07 27764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27765 },
27766/* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
27767 {
27768 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
6772dd07 27769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27770 },
27771/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27772 {
27773 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
6772dd07 27774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27775 },
27776/* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27777 {
27778 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
6772dd07 27779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27780 },
27781/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27782 {
27783 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27785 },
27786/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27787 {
27788 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27790 },
27791/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27792 {
27793 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27795 },
27796/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27797 {
27798 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27800 },
27801/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27802 {
27803 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
6772dd07 27804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27805 },
27806/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27807 {
27808 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
6772dd07 27809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27810 },
27811/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27812 {
27813 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27815 },
27816/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27817 {
27818 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27820 },
27821/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27822 {
27823 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27825 },
27826/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27827 {
27828 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27830 },
27831/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27832 {
27833 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27835 },
27836/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27837 {
27838 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 27839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27840 },
27841/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27842 {
27843 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27845 },
27846/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27847 {
27848 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 27849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27850 },
27851/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27852 {
27853 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
6772dd07 27854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27855 },
27856/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
27857 {
27858 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
6772dd07 27859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27860 },
27861/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27862 {
27863 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
6772dd07 27864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27865 },
27866/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
27867 {
27868 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
6772dd07 27869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27870 },
27871/* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
27872 {
27873 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 27874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27875 },
27876/* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
27877 {
27878 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 27879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27880 },
27881/* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27882 {
27883 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 27884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27885 },
27886/* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
27887 {
27888 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 27889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27890 },
27891/* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
27892 {
27893 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 27894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27895 },
27896/* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27897 {
27898 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 27899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27900 },
27901/* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
27902 {
27903 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
6772dd07 27904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27905 },
27906/* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
27907 {
27908 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
6772dd07 27909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27910 },
27911/* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27912 {
27913 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
6772dd07 27914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27915 },
27916/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27917 {
27918 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27920 },
27921/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27922 {
27923 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27925 },
27926/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27927 {
27928 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27930 },
27931/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27932 {
27933 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27935 },
27936/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27937 {
27938 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27940 },
27941/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27942 {
27943 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27945 },
27946/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27947 {
27948 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27950 },
27951/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27952 {
27953 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27955 },
27956/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27957 {
27958 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 27959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27960 },
27961/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
27962 {
27963 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27965 },
27966/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
27967 {
27968 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27970 },
27971/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27972 {
27973 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27975 },
27976/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
27977 {
27978 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27980 },
27981/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
27982 {
27983 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27985 },
27986/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27987 {
27988 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 27989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27990 },
27991/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
27992 {
27993 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 27995 },
27996/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
27997 {
27998 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 27999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28000 },
28001/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
28002 {
28003 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 28004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28005 },
28006/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
28007 {
28008 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 28009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28010 },
28011/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
28012 {
28013 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 28014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28015 },
28016/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28017 {
28018 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 28019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28020 },
28021/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
28022 {
28023 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
6772dd07 28024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28025 },
28026/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
28027 {
28028 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
6772dd07 28029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28030 },
28031/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28032 {
28033 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
6772dd07 28034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28035 },
28036/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
28037 {
28038 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 28039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28040 },
28041/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
28042 {
28043 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 28044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28045 },
28046/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28047 {
28048 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 28049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28050 },
28051/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28052 {
28053 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 28054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28055 },
28056/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
28057 {
28058 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 28059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28060 },
28061/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
28062 {
28063 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 28064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28065 },
28066/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28067 {
28068 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 28069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28070 },
28071/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
28072 {
28073 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 28074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28075 },
28076/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
28077 {
28078 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 28079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28080 },
28081/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28082 {
28083 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
6772dd07 28084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28085 },
28086/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28087 {
28088 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
6772dd07 28089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28090 },
28091/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28092 {
28093 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
6772dd07 28094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28095 },
28096/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28097 {
28098 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28100 },
28101/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28102 {
28103 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28105 },
28106/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28107 {
28108 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28110 },
28111/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28112 {
28113 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28115 },
28116/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28117 {
28118 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28120 },
28121/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28122 {
28123 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28125 },
28126/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28127 {
28128 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28130 },
28131/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28132 {
28133 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28135 },
28136/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28137 {
28138 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28140 },
28141/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28142 {
28143 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28145 },
28146/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28147 {
28148 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28150 },
28151/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28152 {
28153 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28155 },
28156/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28157 {
28158 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28160 },
28161/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28162 {
28163 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28165 },
28166/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28167 {
28168 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28170 },
28171/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28172 {
28173 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28175 },
28176/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28177 {
28178 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28180 },
28181/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28182 {
28183 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28185 },
28186/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28187 {
28188 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28190 },
28191/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28192 {
28193 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28195 },
28196/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28197 {
28198 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28200 },
28201/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28202 {
28203 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 28204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28205 },
28206/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28207 {
28208 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 28209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28210 },
28211/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28212 {
28213 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 28214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28215 },
28216/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28217 {
28218 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 28219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28220 },
28221/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28222 {
28223 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 28224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28225 },
28226/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28227 {
28228 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 28229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28230 },
28231/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28232 {
28233 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28235 },
28236/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
28237 {
28238 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28240 },
28241/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
28242 {
28243 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28245 },
28246/* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
28247 {
28248 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28250 },
28251/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28252 {
28253 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28255 },
28256/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
28257 {
28258 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28260 },
28261/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
28262 {
28263 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28265 },
28266/* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
28267 {
28268 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
6772dd07 28269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28270 },
28271/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28272 {
28273 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
6772dd07 28274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28275 },
28276/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28277 {
28278 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
6772dd07 28279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28280 },
28281/* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28282 {
28283 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
6772dd07 28284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28285 },
28286/* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28287 {
28288 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
6772dd07 28289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28290 },
28291/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28292 {
28293 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28295 },
28296/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28297 {
28298 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28300 },
28301/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28302 {
28303 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28305 },
28306/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28307 {
28308 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28310 },
28311/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28312 {
28313 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28315 },
28316/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28317 {
28318 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28320 },
28321/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28322 {
28323 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28325 },
28326/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28327 {
28328 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28330 },
28331/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28332 {
28333 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28335 },
28336/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28337 {
28338 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28340 },
28341/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28342 {
28343 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28345 },
28346/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28347 {
28348 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28350 },
28351/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28352 {
28353 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28355 },
28356/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28357 {
28358 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28360 },
28361/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28362 {
28363 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28365 },
28366/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28367 {
28368 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28370 },
28371/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28372 {
28373 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28375 },
28376/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28377 {
28378 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28380 },
28381/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28382 {
28383 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28385 },
28386/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28387 {
28388 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28390 },
28391/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28392 {
28393 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28395 },
28396/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28397 {
28398 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28400 },
28401/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28402 {
28403 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28405 },
28406/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28407 {
28408 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28410 },
28411/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28412 {
28413 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28415 },
28416/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28417 {
28418 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28420 },
28421/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28422 {
28423 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28425 },
28426/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28427 {
28428 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28430 },
28431/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28432 {
28433 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 28434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28435 },
28436/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28437 {
28438 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 28439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28440 },
28441/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28442 {
28443 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 28444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28445 },
28446/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
28447 {
28448 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 28449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28450 },
28451/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28452 {
28453 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
6772dd07 28454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28455 },
28456/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28457 {
28458 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
6772dd07 28459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28460 },
28461/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28462 {
28463 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
6772dd07 28464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28465 },
28466/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
28467 {
28468 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
6772dd07 28469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28470 },
28471/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28472 {
28473 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
6772dd07 28474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28475 },
28476/* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
28477 {
28478 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
6772dd07 28479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28480 },
28481/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28482 {
28483 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
6772dd07 28484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28485 },
28486/* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
28487 {
28488 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
6772dd07 28489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28490 },
28491/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28492 {
28493 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
6772dd07 28494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28495 },
28496/* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28497 {
28498 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
6772dd07 28499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28500 },
28501/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28502 {
28503 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28505 },
28506/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28507 {
28508 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28510 },
28511/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28512 {
28513 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28515 },
28516/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28517 {
28518 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28520 },
28521/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28522 {
28523 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
6772dd07 28524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28525 },
28526/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28527 {
28528 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
6772dd07 28529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28530 },
28531/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28532 {
28533 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28535 },
28536/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28537 {
28538 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28540 },
28541/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28542 {
28543 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28545 },
28546/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28547 {
28548 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28550 },
28551/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28552 {
28553 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28555 },
28556/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28557 {
28558 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 28559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28560 },
28561/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28562 {
28563 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28565 },
28566/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28567 {
28568 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
6772dd07 28569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28570 },
28571/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28572 {
28573 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
6772dd07 28574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28575 },
28576/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
28577 {
28578 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
6772dd07 28579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28580 },
28581/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28582 {
28583 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
6772dd07 28584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28585 },
28586/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
28587 {
28588 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
6772dd07 28589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28590 },
28591/* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
28592 {
28593 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 28594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28595 },
28596/* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
28597 {
28598 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 28599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28600 },
28601/* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28602 {
28603 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 28604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28605 },
28606/* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
28607 {
28608 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 28609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28610 },
28611/* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
28612 {
28613 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 28614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28615 },
28616/* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28617 {
28618 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 28619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28620 },
28621/* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
28622 {
28623 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
6772dd07 28624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28625 },
28626/* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
28627 {
28628 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
6772dd07 28629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28630 },
28631/* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28632 {
28633 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
6772dd07 28634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28635 },
28636/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28637 {
28638 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28640 },
28641/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28642 {
28643 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28645 },
28646/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
28647 {
28648 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28650 },
28651/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28652 {
28653 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28655 },
28656/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28657 {
28658 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28660 },
28661/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
28662 {
28663 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28665 },
28666/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28667 {
28668 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28670 },
28671/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28672 {
28673 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28675 },
28676/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
28677 {
28678 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 28679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28680 },
28681/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
28682 {
28683 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28685 },
28686/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
28687 {
28688 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28690 },
28691/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
28692 {
28693 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28695 },
28696/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
28697 {
28698 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28700 },
28701/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
28702 {
28703 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28705 },
28706/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
28707 {
28708 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28710 },
28711/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
28712 {
28713 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28715 },
28716/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
28717 {
28718 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28720 },
28721/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
28722 {
28723 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 28724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28725 },
28726/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
28727 {
28728 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28730 },
28731/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
28732 {
28733 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28735 },
28736/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28737 {
28738 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 28739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28740 },
28741/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
28742 {
28743 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
6772dd07 28744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28745 },
28746/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
28747 {
28748 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
6772dd07 28749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28750 },
28751/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28752 {
28753 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
6772dd07 28754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28755 },
28756/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
28757 {
28758 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 28759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28760 },
28761/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
28762 {
28763 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 28764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28765 },
28766/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28767 {
28768 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 28769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28770 },
28771/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
28772 {
28773 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
6772dd07 28774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28775 },
28776/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
28777 {
28778 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
6772dd07 28779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28780 },
28781/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
28782 {
28783 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
6772dd07 28784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28785 },
28786/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
28787 {
28788 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24,
6772dd07 28789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28790 },
28791/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
28792 {
28793 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
6772dd07 28794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28795 },
28796/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
28797 {
28798 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
6772dd07 28799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28800 },
28801/* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
28802 {
28803 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
6772dd07 28804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28805 },
28806/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
28807 {
28808 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
6772dd07 28809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28810 },
28811/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
28812 {
28813 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
6772dd07 28814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28815 },
28816/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
28817 {
28818 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
6772dd07 28819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28820 },
28821/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
28822 {
28823 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
6772dd07 28824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28825 },
28826/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
28827 {
28828 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
6772dd07 28829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28830 },
28831/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
28832 {
28833 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
6772dd07 28834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28835 },
28836/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
28837 {
28838 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
6772dd07 28839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28840 },
28841/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
28842 {
28843 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
6772dd07 28844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28845 },
28846/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
28847 {
28848 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
6772dd07 28849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28850 },
28851/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28852 {
28853 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
6772dd07 28854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28855 },
28856/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28857 {
28858 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
6772dd07 28859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28860 },
28861/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
28862 {
28863 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
6772dd07 28864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28865 },
28866/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28867 {
28868 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
6772dd07 28869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28870 },
28871/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28872 {
28873 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
6772dd07 28874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28875 },
28876/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
28877 {
28878 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
6772dd07 28879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28880 },
28881/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28882 {
28883 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
6772dd07 28884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28885 },
28886/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28887 {
28888 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
6772dd07 28889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28890 },
28891/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
28892 {
28893 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
6772dd07 28894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28895 },
28896/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28897 {
28898 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
6772dd07 28899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28900 },
28901/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28902 {
28903 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
6772dd07 28904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28905 },
28906/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
28907 {
28908 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
6772dd07 28909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28910 },
28911/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
28912 {
28913 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
6772dd07 28914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28915 },
28916/* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
28917 {
28918 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32,
6772dd07 28919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28920 },
28921/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
28922 {
28923 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32,
6772dd07 28924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28925 },
28926/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
28927 {
28928 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32,
6772dd07 28929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28930 },
28931/* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
28932 {
28933 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32,
6772dd07 28934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28935 },
28936/* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
28937 {
28938 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
6772dd07 28939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28940 },
28941/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
28942 {
28943 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
6772dd07 28944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28945 },
28946/* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
28947 {
28948 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32,
6772dd07 28949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28950 },
28951/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
28952 {
28953 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
6772dd07 28954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28955 },
28956/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
28957 {
28958 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
6772dd07 28959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28960 },
28961/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
28962 {
28963 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
6772dd07 28964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28965 },
28966/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
28967 {
28968 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
6772dd07 28969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28970 },
28971/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
28972 {
28973 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
6772dd07 28974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28975 },
28976/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
28977 {
28978 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
6772dd07 28979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28980 },
28981/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
28982 {
28983 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
6772dd07 28984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28985 },
28986/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28987 {
28988 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
6772dd07 28989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28990 },
28991/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28992 {
28993 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
6772dd07 28994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 28995 },
28996/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
28997 {
28998 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
6772dd07 28999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29000 },
29001/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29002 {
29003 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
6772dd07 29004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29005 },
29006/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29007 {
29008 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
6772dd07 29009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29010 },
29011/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
29012 {
29013 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
6772dd07 29014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29015 },
29016/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29017 {
29018 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
6772dd07 29019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29020 },
29021/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29022 {
29023 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
6772dd07 29024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29025 },
29026/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
29027 {
29028 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
6772dd07 29029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29030 },
29031/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29032 {
29033 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
6772dd07 29034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29035 },
29036/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
29037 {
29038 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48,
6772dd07 29039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29040 },
29041/* mov.w${G} $Src16RnHI,$Dst16RnHI */
29042 {
29043 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
6772dd07 29044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29045 },
29046/* mov.w${G} $Src16AnHI,$Dst16RnHI */
29047 {
29048 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
6772dd07 29049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29050 },
29051/* mov.w${G} [$Src16An],$Dst16RnHI */
29052 {
29053 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16,
6772dd07 29054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29055 },
29056/* mov.w${G} $Src16RnHI,$Dst16AnHI */
29057 {
29058 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16,
6772dd07 29059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29060 },
29061/* mov.w${G} $Src16AnHI,$Dst16AnHI */
29062 {
29063 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16,
6772dd07 29064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29065 },
29066/* mov.w${G} [$Src16An],$Dst16AnHI */
29067 {
29068 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16,
6772dd07 29069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29070 },
29071/* mov.w${G} $Src16RnHI,[$Dst16An] */
29072 {
29073 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
6772dd07 29074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29075 },
29076/* mov.w${G} $Src16AnHI,[$Dst16An] */
29077 {
29078 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
6772dd07 29079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29080 },
29081/* mov.w${G} [$Src16An],[$Dst16An] */
29082 {
29083 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16,
6772dd07 29084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29085 },
29086/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
29087 {
29088 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
6772dd07 29089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29090 },
29091/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
29092 {
29093 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
6772dd07 29094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29095 },
29096/* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29097 {
29098 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
6772dd07 29099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29100 },
29101/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
29102 {
29103 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
6772dd07 29104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29105 },
29106/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
29107 {
29108 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
6772dd07 29109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29110 },
29111/* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29112 {
29113 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
6772dd07 29114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29115 },
29116/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
29117 {
29118 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
6772dd07 29119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29120 },
29121/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
29122 {
29123 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
6772dd07 29124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29125 },
29126/* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
29127 {
29128 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
6772dd07 29129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29130 },
29131/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
29132 {
29133 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
6772dd07 29134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29135 },
29136/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
29137 {
29138 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
6772dd07 29139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29140 },
29141/* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
29142 {
29143 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
6772dd07 29144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29145 },
29146/* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
29147 {
29148 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
6772dd07 29149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29150 },
29151/* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
29152 {
29153 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
6772dd07 29154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29155 },
29156/* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
29157 {
29158 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
6772dd07 29159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29160 },
29161/* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
29162 {
29163 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
6772dd07 29164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29165 },
29166/* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
29167 {
29168 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
6772dd07 29169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29170 },
29171/* mov.w${G} [$Src16An],${Dsp-16-u16} */
29172 {
29173 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32,
6772dd07 29174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29175 },
29176/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
29177 {
29178 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
6772dd07 29179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29180 },
29181/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
29182 {
29183 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
6772dd07 29184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29185 },
29186/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
29187 {
29188 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
6772dd07 29189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29190 },
29191/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
29192 {
29193 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24,
6772dd07 29194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29195 },
29196/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
29197 {
29198 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
6772dd07 29199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29200 },
29201/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
29202 {
29203 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
6772dd07 29204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29205 },
29206/* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
29207 {
29208 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
6772dd07 29209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29210 },
29211/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
29212 {
29213 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
6772dd07 29214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29215 },
29216/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
29217 {
29218 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
6772dd07 29219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29220 },
29221/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
29222 {
29223 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
6772dd07 29224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29225 },
29226/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
29227 {
29228 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
6772dd07 29229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29230 },
29231/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
29232 {
29233 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
6772dd07 29234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29235 },
29236/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
29237 {
29238 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
6772dd07 29239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29240 },
29241/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
29242 {
29243 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
6772dd07 29244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29245 },
29246/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
29247 {
29248 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
6772dd07 29249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29250 },
29251/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
29252 {
29253 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
6772dd07 29254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29255 },
29256/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29257 {
29258 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
6772dd07 29259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29260 },
29261/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29262 {
29263 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
6772dd07 29264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29265 },
29266/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
29267 {
29268 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
6772dd07 29269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29270 },
29271/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29272 {
29273 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
6772dd07 29274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29275 },
29276/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29277 {
29278 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
6772dd07 29279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29280 },
29281/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
29282 {
29283 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
6772dd07 29284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29285 },
29286/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29287 {
29288 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
6772dd07 29289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29290 },
29291/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29292 {
29293 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
6772dd07 29294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29295 },
29296/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
29297 {
29298 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
6772dd07 29299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29300 },
29301/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29302 {
29303 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
6772dd07 29304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29305 },
29306/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29307 {
29308 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
6772dd07 29309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29310 },
29311/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
29312 {
29313 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
6772dd07 29314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29315 },
29316/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
29317 {
29318 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
6772dd07 29319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29320 },
29321/* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
29322 {
29323 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32,
6772dd07 29324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29325 },
29326/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
29327 {
29328 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32,
6772dd07 29329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29330 },
29331/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
29332 {
29333 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32,
6772dd07 29334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29335 },
29336/* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
29337 {
29338 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32,
6772dd07 29339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29340 },
29341/* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
29342 {
29343 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
6772dd07 29344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29345 },
29346/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
29347 {
29348 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
6772dd07 29349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29350 },
29351/* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
29352 {
29353 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32,
6772dd07 29354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29355 },
29356/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
29357 {
29358 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
6772dd07 29359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29360 },
29361/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
29362 {
29363 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
6772dd07 29364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29365 },
29366/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
29367 {
29368 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
6772dd07 29369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29370 },
29371/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
29372 {
29373 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
6772dd07 29374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29375 },
29376/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
29377 {
29378 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
6772dd07 29379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29380 },
29381/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
29382 {
29383 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
6772dd07 29384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29385 },
29386/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
29387 {
29388 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
6772dd07 29389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29390 },
29391/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29392 {
29393 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
6772dd07 29394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29395 },
29396/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29397 {
29398 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
6772dd07 29399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29400 },
29401/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
29402 {
29403 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
6772dd07 29404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29405 },
29406/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29407 {
29408 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
6772dd07 29409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29410 },
29411/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29412 {
29413 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
6772dd07 29414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29415 },
29416/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
29417 {
29418 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
6772dd07 29419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29420 },
29421/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29422 {
29423 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
6772dd07 29424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29425 },
29426/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29427 {
29428 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
6772dd07 29429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29430 },
29431/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
29432 {
29433 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
6772dd07 29434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29435 },
29436/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29437 {
29438 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
6772dd07 29439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29440 },
29441/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29442 {
29443 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48,
6772dd07 29444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29445 },
29446/* mov.b${G} $Src16RnQI,$Dst16RnQI */
29447 {
29448 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
6772dd07 29449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29450 },
29451/* mov.b${G} $Src16AnQI,$Dst16RnQI */
29452 {
29453 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
6772dd07 29454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29455 },
29456/* mov.b${G} [$Src16An],$Dst16RnQI */
29457 {
29458 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16,
6772dd07 29459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29460 },
29461/* mov.b${G} $Src16RnQI,$Dst16AnQI */
29462 {
29463 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16,
6772dd07 29464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29465 },
29466/* mov.b${G} $Src16AnQI,$Dst16AnQI */
29467 {
29468 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16,
6772dd07 29469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29470 },
29471/* mov.b${G} [$Src16An],$Dst16AnQI */
29472 {
29473 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16,
6772dd07 29474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29475 },
29476/* mov.b${G} $Src16RnQI,[$Dst16An] */
29477 {
29478 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
6772dd07 29479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29480 },
29481/* mov.b${G} $Src16AnQI,[$Dst16An] */
29482 {
29483 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
6772dd07 29484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29485 },
29486/* mov.b${G} [$Src16An],[$Dst16An] */
29487 {
29488 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16,
6772dd07 29489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29490 },
29491/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
29492 {
29493 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
6772dd07 29494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29495 },
29496/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
29497 {
29498 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
6772dd07 29499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29500 },
29501/* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29502 {
29503 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
6772dd07 29504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29505 },
29506/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
29507 {
29508 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
6772dd07 29509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29510 },
29511/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
29512 {
29513 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
6772dd07 29514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29515 },
29516/* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29517 {
29518 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
6772dd07 29519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29520 },
29521/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
29522 {
29523 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
6772dd07 29524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29525 },
29526/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
29527 {
29528 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
6772dd07 29529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29530 },
29531/* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
29532 {
29533 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
6772dd07 29534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29535 },
29536/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
29537 {
29538 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
6772dd07 29539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29540 },
29541/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
29542 {
29543 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
6772dd07 29544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29545 },
29546/* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
29547 {
29548 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
6772dd07 29549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29550 },
29551/* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
29552 {
29553 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
6772dd07 29554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29555 },
29556/* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
29557 {
29558 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
6772dd07 29559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29560 },
29561/* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
29562 {
29563 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
6772dd07 29564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29565 },
29566/* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
29567 {
29568 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
6772dd07 29569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29570 },
29571/* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
29572 {
29573 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
6772dd07 29574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29575 },
29576/* mov.b${G} [$Src16An],${Dsp-16-u16} */
29577 {
29578 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32,
6772dd07 29579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 29580 },
29581/* mov.w${Z} #0,${Dsp-8-u8}[sb] */
29582 {
29583 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
6772dd07 29584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29585 },
29586/* mov.w${Z} #0,${Dsp-8-s8}[fb] */
29587 {
29588 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
6772dd07 29589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29590 },
29591/* mov.w${Z} #0,${Dsp-8-u16} */
29592 {
29593 M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
6772dd07 29594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29595 },
29596/* mov.w${Z} #0,r0 */
29597 {
29598 M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8,
6772dd07 29599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29600 },
29601/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29602 {
29603 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
6772dd07 29604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29605 },
29606/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29607 {
29608 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
6772dd07 29609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29610 },
29611/* mov.b${Z} #0,${Dsp-8-u16} */
29612 {
29613 M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
6772dd07 29614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29615 },
29616/* mov.b${Z} #0,r0l */
29617 {
29618 M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8,
6772dd07 29619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29620 },
29621/* mov.b${Z} #0,r0l */
29622 {
29623 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8,
6772dd07 29624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29625 },
29626/* mov.b${Z} #0,r0h */
29627 {
29628 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8,
6772dd07 29629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29630 },
29631/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29632 {
29633 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16,
6772dd07 29634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29635 },
29636/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29637 {
29638 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16,
6772dd07 29639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 29640 },
29641/* mov.b${Z} #0,${Dsp-8-u16} */
29642 {
29643 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
6772dd07 29644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 29645 },
49f58d10
JB		 29646/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
29647 {
29648 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 29649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29650 },
29651/* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
29652 {
29653 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
6772dd07 29654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29655 },
29656/* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29657 {
29658 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
6772dd07 29659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29660 },
29661/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29662 {
29663 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 29664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29665 },
29666/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29667 {
29668 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 29669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29670 },
29671/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29672 {
29673 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 29674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29675 },
29676/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29677 {
29678 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 29679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29680 },
29681/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29682 {
29683 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 29684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29685 },
29686/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29687 {
29688 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
6772dd07 29689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29690 },
29691/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29692 {
29693 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
6772dd07 29694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29695 },
29696/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
29697 {
29698 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
6772dd07 29699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29700 },
29701/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
29702 {
29703 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
6772dd07 29704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29705 },
29706/* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
29707 {
29708 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 29709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29710 },
29711/* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
29712 {
29713 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
6772dd07 29714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29715 },
29716/* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29717 {
29718 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
6772dd07 29719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29720 },
29721/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29722 {
29723 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 29724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29725 },
29726/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29727 {
29728 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 29729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29730 },
29731/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29732 {
29733 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 29734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29735 },
29736/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29737 {
29738 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 29739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29740 },
29741/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29742 {
29743 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 29744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29745 },
29746/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29747 {
29748 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
6772dd07 29749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29750 },
29751/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29752 {
29753 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 29754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29755 },
29756/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
29757 {
29758 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
6772dd07 29759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29760 },
29761/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
29762 {
29763 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 29764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 29765 },
db313fa6 29766/* mov.w${Q} #${Imm-8-s4},$Dst16RnHI */
49f58d10 29767 {
db313fa6 29768 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "mov16.w-imm4-Q-16-dst16-Rn-direct-HI", "mov.w", 16,
6772dd07 29769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 29770 },
db313fa6 29771/* mov.w${Q} #${Imm-8-s4},$Dst16AnHI */
49f58d10 29772 {
db313fa6 29773 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "mov16.w-imm4-Q-16-dst16-An-direct-HI", "mov.w", 16,
6772dd07 29774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29775 },
29776/* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
29777 {
db313fa6 29778 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "mov16.w-imm4-Q-16-dst16-An-indirect-HI", "mov.w", 16,
6772dd07 29779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29780 },
29781/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29782 {
db313fa6 29783 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "mov.w", 24,
6772dd07 29784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29785 },
29786/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29787 {
db313fa6 29788 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "mov.w", 32,
6772dd07 29789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29790 },
29791/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29792 {
db313fa6 29793 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "mov.w", 24,
6772dd07 29794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29795 },
29796/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29797 {
db313fa6 29798 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "mov.w", 32,
6772dd07 29799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29800 },
29801/* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29802 {
db313fa6 29803 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "mov.w", 24,
6772dd07 29804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29805 },
29806/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
29807 {
db313fa6 29808 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-HI", "mov.w", 32,
6772dd07 29809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29810 },
29811/* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
29812 {
29813 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16,
6772dd07 29814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29815 },
29816/* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
29817 {
29818 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16,
6772dd07 29819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29820 },
29821/* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
29822 {
29823 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16,
6772dd07 29824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29825 },
29826/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29827 {
29828 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24,
6772dd07 29829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29830 },
29831/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29832 {
29833 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32,
6772dd07 29834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29835 },
29836/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29837 {
29838 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24,
6772dd07 29839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29840 },
29841/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29842 {
29843 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32,
6772dd07 29844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29845 },
29846/* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29847 {
29848 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24,
6772dd07 29849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29850 },
29851/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
29852 {
29853 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
6772dd07 29854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 29855 },
e729279b
NC		 29856/* mov.b${S} #${Imm-8-QI},r0l */
29857 {
29858 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
6772dd07 29859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29860 },
29861/* mov.b${S} #${Imm-8-QI},r0h */
29862 {
29863 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
6772dd07 29864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29865 },
29866/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
29867 {
29868 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
6772dd07 29869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29870 },
29871/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
29872 {
29873 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
6772dd07 29874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29875 },
29876/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
29877 {
29878 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
6772dd07 29879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29880 },
29881/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
29882 {
29883 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
6772dd07 29884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29885 },
29886/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
29887 {
29888 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
6772dd07 29889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29890 },
29891/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
29892 {
29893 M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
6772dd07 29894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29895 },
29896/* mov.w${S} #${Imm-8-HI},r0 */
29897 {
29898 M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
6772dd07 29899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29900 },
29901/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
29902 {
29903 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
6772dd07 29904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29905 },
29906/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
29907 {
29908 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
6772dd07 29909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29910 },
29911/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
29912 {
29913 M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
6772dd07 29914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b
NC		 29915 },
29916/* mov.b${S} #${Imm-8-QI},r0l */
29917 {
29918 M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
6772dd07 29919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
e729279b 29920 },
49f58d10
JB		 29921/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
29922 {
29923 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
6772dd07 29924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29925 },
29926/* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
29927 {
29928 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48,
6772dd07 29929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29930 },
29931/* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
29932 {
29933 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48,
6772dd07 29934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29935 },
29936/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29937 {
29938 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 29939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29940 },
29941/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
29942 {
29943 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 29944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29945 },
29946/* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
29947 {
29948 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56,
6772dd07 29949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29950 },
29951/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29952 {
29953 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64,
6772dd07 29954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29955 },
29956/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
29957 {
29958 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64,
6772dd07 29959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29960 },
29961/* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
29962 {
29963 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64,
6772dd07 29964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29965 },
29966/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
29967 {
29968 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64,
6772dd07 29969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29970 },
29971/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29972 {
29973 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72,
6772dd07 29974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29975 },
29976/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
29977 {
29978 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72,
6772dd07 29979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29980 },
29981/* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
29982 {
29983 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 29984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29985 },
29986/* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
29987 {
29988 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
6772dd07 29989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29990 },
29991/* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
29992 {
29993 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
6772dd07 29994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 29995 },
29996/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29997 {
29998 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 29999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30000 },
30001/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30002 {
30003 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 30004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30005 },
30006/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30007 {
30008 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40,
6772dd07 30009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30010 },
30011/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30012 {
30013 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 30014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30015 },
30016/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30017 {
30018 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 30019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30020 },
30021/* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
30022 {
30023 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48,
6772dd07 30024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30025 },
30026/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30027 {
30028 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48,
6772dd07 30029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30030 },
30031/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30032 {
30033 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56,
6772dd07 30034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30035 },
30036/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
30037 {
30038 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56,
6772dd07 30039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30040 },
30041/* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
30042 {
30043 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 30044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30045 },
30046/* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
30047 {
30048 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
6772dd07 30049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30050 },
30051/* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
30052 {
30053 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
6772dd07 30054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30055 },
30056/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
30057 {
30058 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 30059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30060 },
30061/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30062 {
30063 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 30064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30065 },
30066/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30067 {
30068 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
6772dd07 30069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30070 },
30071/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30072 {
30073 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 30074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30075 },
30076/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30077 {
30078 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 30079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30080 },
30081/* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
30082 {
30083 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
6772dd07 30084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30085 },
30086/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30087 {
30088 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
6772dd07 30089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30090 },
30091/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30092 {
30093 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
6772dd07 30094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30095 },
30096/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
30097 {
30098 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
6772dd07 30099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30100 },
30101/* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
30102 {
30103 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32,
6772dd07 30104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30105 },
30106/* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
30107 {
30108 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32,
6772dd07 30109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30110 },
30111/* mov.w${G} #${Imm-16-HI},[$Dst16An] */
30112 {
30113 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32,
6772dd07 30114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30115 },
30116/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
30117 {
30118 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40,
6772dd07 30119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30120 },
30121/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30122 {
30123 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40,
6772dd07 30124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30125 },
30126/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30127 {
30128 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40,
6772dd07 30129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30130 },
30131/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
30132 {
30133 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48,
6772dd07 30134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30135 },
30136/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30137 {
30138 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48,
6772dd07 30139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30140 },
30141/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30142 {
30143 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48,
6772dd07 30144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30145 },
30146/* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
30147 {
30148 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24,
6772dd07 30149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30150 },
30151/* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
30152 {
30153 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24,
6772dd07 30154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30155 },
30156/* mov.b${G} #${Imm-16-QI},[$Dst16An] */
30157 {
30158 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24,
6772dd07 30159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30160 },
30161/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
30162 {
30163 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
6772dd07 30164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30165 },
30166/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30167 {
30168 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
6772dd07 30169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30170 },
30171/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30172 {
30173 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
6772dd07 30174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30175 },
30176/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
30177 {
30178 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
6772dd07 30179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30180 },
30181/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30182 {
30183 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
6772dd07 30184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30185 },
30186/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30187 {
30188 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
6772dd07 30189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 30190 },
30191/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30192 {
30193 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
6772dd07 30194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30195 },
30196/* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
30197 {
30198 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
6772dd07 30199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30200 },
30201/* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
30202 {
30203 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
6772dd07 30204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30205 },
30206/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30207 {
30208 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
6772dd07 30209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30210 },
30211/* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
30212 {
30213 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
6772dd07 30214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30215 },
30216/* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
30217 {
30218 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
6772dd07 30219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30220 },
30221/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30222 {
30223 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
6772dd07 30224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30225 },
30226/* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30227 {
30228 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
6772dd07 30229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30230 },
30231/* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30232 {
30233 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
6772dd07 30234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30235 },
30236/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30237 {
30238 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
6772dd07 30239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30240 },
30241/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30242 {
30243 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
6772dd07 30244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30245 },
30246/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30247 {
30248 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
6772dd07 30249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30250 },
30251/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30252 {
30253 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30255 },
30256/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30257 {
30258 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30260 },
30261/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30262 {
30263 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30265 },
30266/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30267 {
30268 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30270 },
30271/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30272 {
30273 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30275 },
30276/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30277 {
30278 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30280 },
30281/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30282 {
30283 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30285 },
30286/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30287 {
30288 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30290 },
30291/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30292 {
30293 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30295 },
30296/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30297 {
30298 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30300 },
30301/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30302 {
30303 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30305 },
30306/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30307 {
30308 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30310 },
30311/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
30312 {
30313 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30315 },
30316/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
30317 {
30318 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30320 },
30321/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
30322 {
30323 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30325 },
30326/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
30327 {
30328 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30330 },
30331/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
30332 {
30333 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30335 },
30336/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
30337 {
30338 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30340 },
30341/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
30342 {
30343 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
6772dd07 30344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30345 },
30346/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
30347 {
30348 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
6772dd07 30349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30350 },
30351/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
30352 {
30353 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
6772dd07 30354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30355 },
30356/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
30357 {
30358 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
6772dd07 30359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30360 },
30361/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
30362 {
30363 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
6772dd07 30364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30365 },
30366/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
30367 {
30368 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
6772dd07 30369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30370 },
30371/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30372 {
30373 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
6772dd07 30374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30375 },
30376/* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
30377 {
30378 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
6772dd07 30379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30380 },
30381/* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
30382 {
30383 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
6772dd07 30384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30385 },
30386/* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
30387 {
30388 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
6772dd07 30389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30390 },
30391/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30392 {
30393 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
6772dd07 30394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30395 },
30396/* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
30397 {
30398 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
6772dd07 30399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30400 },
30401/* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
30402 {
30403 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
6772dd07 30404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30405 },
30406/* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
30407 {
30408 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
6772dd07 30409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30410 },
30411/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30412 {
30413 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
6772dd07 30414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30415 },
30416/* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
30417 {
30418 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
6772dd07 30419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30420 },
30421/* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
30422 {
30423 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
6772dd07 30424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30425 },
30426/* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
30427 {
30428 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
6772dd07 30429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30430 },
30431/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
30432 {
30433 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30435 },
30436/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30437 {
30438 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30440 },
30441/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30442 {
30443 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30445 },
30446/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
30447 {
30448 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30450 },
30451/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
30452 {
30453 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30455 },
30456/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30457 {
30458 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30460 },
30461/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30462 {
30463 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30465 },
30466/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
30467 {
30468 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30470 },
30471/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
30472 {
30473 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
6772dd07 30474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30475 },
30476/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30477 {
30478 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
6772dd07 30479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30480 },
30481/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30482 {
30483 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
6772dd07 30484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30485 },
30486/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
30487 {
30488 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
6772dd07 30489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30490 },
30491/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
30492 {
30493 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30495 },
30496/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
30497 {
30498 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30500 },
30501/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
30502 {
30503 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30505 },
30506/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
30507 {
30508 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30510 },
30511/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
30512 {
30513 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30515 },
30516/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
30517 {
30518 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30520 },
30521/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
30522 {
30523 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30525 },
30526/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
30527 {
30528 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30530 },
30531/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
30532 {
30533 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30535 },
30536/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
30537 {
30538 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30540 },
30541/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
30542 {
30543 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30545 },
30546/* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
30547 {
30548 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 30549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30550 },
30551/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
30552 {
30553 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30555 },
30556/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
30557 {
30558 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30560 },
30561/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
30562 {
30563 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30565 },
30566/* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
30567 {
30568 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30570 },
30571/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
30572 {
30573 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
6772dd07 30574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30575 },
30576/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
30577 {
30578 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
6772dd07 30579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30580 },
30581/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
30582 {
30583 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
6772dd07 30584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30585 },
30586/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
30587 {
30588 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
6772dd07 30589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30590 },
30591/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
30592 {
30593 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
6772dd07 30594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30595 },
30596/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
30597 {
30598 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
6772dd07 30599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30600 },
30601/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
30602 {
30603 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
6772dd07 30604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30605 },
30606/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
30607 {
30608 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
6772dd07 30609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30610 },
30611/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30612 {
30613 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
6772dd07 30614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30615 },
30616/* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
30617 {
30618 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
6772dd07 30619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30620 },
30621/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30622 {
30623 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
6772dd07 30624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30625 },
30626/* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
30627 {
30628 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
6772dd07 30629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30630 },
30631/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30632 {
30633 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
6772dd07 30634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30635 },
30636/* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
30637 {
30638 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
6772dd07 30639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30640 },
30641/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
30642 {
30643 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30645 },
30646/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
30647 {
30648 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 30649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30650 },
30651/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
30652 {
30653 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
6772dd07 30654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30655 },
30656/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
30657 {
30658 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
6772dd07 30659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30660 },
30661/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
30662 {
30663 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
6772dd07 30664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30665 },
30666/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
30667 {
30668 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
6772dd07 30669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30670 },
30671/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
30672 {
30673 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30675 },
30676/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
30677 {
30678 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30680 },
30681/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
30682 {
30683 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
6772dd07 30684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30685 },
30686/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
30687 {
30688 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
6772dd07 30689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30690 },
30691/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
30692 {
30693 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30695 },
30696/* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
30697 {
30698 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
6772dd07 30699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30700 },
30701/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
30702 {
30703 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
6772dd07 30704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30705 },
30706/* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
30707 {
30708 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
6772dd07 30709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30710 },
30711/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
30712 {
30713 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
6772dd07 30714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30715 },
30716/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
30717 {
30718 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
6772dd07 30719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30720 },
30721/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
30722 {
30723 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
6772dd07 30724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30725 },
30726/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
30727 {
30728 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
6772dd07 30729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30730 },
30731/* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
30732 {
30733 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
6772dd07 30734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30735 },
30736/* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
30737 {
30738 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
6772dd07 30739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30740 },
30741/* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
30742 {
30743 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
6772dd07 30744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30745 },
30746/* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
30747 {
30748 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
6772dd07 30749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30750 },
30751/* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
30752 {
30753 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
6772dd07 30754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30755 },
30756/* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
30757 {
30758 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
6772dd07 30759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30760 },
30761/* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
30762 {
30763 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
6772dd07 30764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30765 },
30766/* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
30767 {
30768 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
6772dd07 30769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30770 },
30771/* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
30772 {
30773 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
6772dd07 30774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30775 },
30776/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30777 {
30778 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
6772dd07 30779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30780 },
30781/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30782 {
30783 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
6772dd07 30784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30785 },
30786/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
30787 {
30788 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
6772dd07 30789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30790 },
30791/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30792 {
30793 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
6772dd07 30794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30795 },
30796/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30797 {
30798 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
6772dd07 30799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30800 },
30801/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
30802 {
30803 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
6772dd07 30804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30805 },
30806/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30807 {
30808 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30810 },
30811/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30812 {
30813 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30815 },
30816/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
30817 {
30818 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 30819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30820 },
30821/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
30822 {
30823 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
6772dd07 30824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30825 },
30826/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
30827 {
30828 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
6772dd07 30829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30830 },
30831/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
30832 {
30833 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
6772dd07 30834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30835 },
30836/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
30837 {
30838 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30840 },
30841/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
30842 {
30843 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30845 },
30846/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
30847 {
30848 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30850 },
30851/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
30852 {
30853 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
6772dd07 30854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30855 },
30856/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
30857 {
30858 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
6772dd07 30859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30860 },
30861/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
30862 {
30863 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
6772dd07 30864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30865 },
30866/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
30867 {
30868 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30870 },
30871/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
30872 {
30873 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30875 },
30876/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
30877 {
30878 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
6772dd07 30879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30880 },
30881/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
30882 {
30883 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
6772dd07 30884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30885 },
30886/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
30887 {
30888 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
6772dd07 30889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30890 },
30891/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
30892 {
30893 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
6772dd07 30894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30895 },
30896/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
30897 {
30898 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
6772dd07 30899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30900 },
30901/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
30902 {
30903 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
6772dd07 30904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30905 },
30906/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
30907 {
30908 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
6772dd07 30909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30910 },
30911/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
30912 {
30913 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
6772dd07 30914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30915 },
30916/* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
30917 {
30918 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
6772dd07 30919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30920 },
30921/* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
30922 {
30923 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
6772dd07 30924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30925 },
30926/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
30927 {
30928 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
6772dd07 30929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30930 },
30931/* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
30932 {
30933 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
6772dd07 30934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30935 },
30936/* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
30937 {
30938 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
6772dd07 30939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30940 },
30941/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30942 {
30943 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
6772dd07 30944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30945 },
30946/* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30947 {
30948 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
6772dd07 30949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30950 },
30951/* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30952 {
30953 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
6772dd07 30954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30955 },
30956/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30957 {
30958 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
6772dd07 30959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30960 },
30961/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30962 {
30963 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
6772dd07 30964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30965 },
30966/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30967 {
30968 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
6772dd07 30969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30970 },
30971/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30972 {
30973 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 30974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30975 },
30976/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30977 {
30978 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 30979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30980 },
30981/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30982 {
30983 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 30984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30985 },
30986/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30987 {
30988 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 30989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30990 },
30991/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30992 {
30993 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 30994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 30995 },
30996/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30997 {
30998 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 30999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31000 },
31001/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
31002 {
31003 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31005 },
31006/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
31007 {
31008 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31010 },
31011/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
31012 {
31013 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31015 },
31016/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
31017 {
31018 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31020 },
31021/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
31022 {
31023 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31025 },
31026/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
31027 {
31028 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31030 },
31031/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31032 {
31033 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31035 },
31036/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31037 {
31038 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31040 },
31041/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31042 {
31043 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31045 },
31046/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31047 {
31048 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31050 },
31051/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31052 {
31053 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31055 },
31056/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31057 {
31058 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31060 },
31061/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31062 {
31063 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
6772dd07 31064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31065 },
31066/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31067 {
31068 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
6772dd07 31069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31070 },
31071/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31072 {
31073 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
6772dd07 31074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31075 },
31076/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31077 {
31078 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31080 },
31081/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31082 {
31083 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31085 },
31086/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31087 {
31088 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31090 },
31091/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31092 {
31093 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
6772dd07 31094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31095 },
31096/* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
31097 {
31098 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
6772dd07 31099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31100 },
31101/* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
31102 {
31103 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
6772dd07 31104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31105 },
31106/* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
31107 {
31108 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
6772dd07 31109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31110 },
31111/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31112 {
31113 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
6772dd07 31114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31115 },
31116/* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
31117 {
31118 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
6772dd07 31119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31120 },
31121/* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
31122 {
31123 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
6772dd07 31124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31125 },
31126/* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
31127 {
31128 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
6772dd07 31129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31130 },
31131/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31132 {
31133 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
6772dd07 31134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31135 },
31136/* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31137 {
31138 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
6772dd07 31139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31140 },
31141/* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31142 {
31143 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
6772dd07 31144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31145 },
31146/* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31147 {
31148 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
6772dd07 31149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31150 },
31151/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31152 {
31153 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31155 },
31156/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31157 {
31158 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31160 },
31161/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31162 {
31163 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31165 },
31166/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31167 {
31168 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31170 },
31171/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31172 {
31173 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 31174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31175 },
31176/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31177 {
31178 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 31179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31180 },
31181/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31182 {
31183 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 31184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31185 },
31186/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31187 {
31188 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 31189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31190 },
31191/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
31192 {
31193 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
6772dd07 31194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31195 },
31196/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31197 {
31198 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
6772dd07 31199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31200 },
31201/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31202 {
31203 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
6772dd07 31204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31205 },
31206/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
31207 {
31208 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
6772dd07 31209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31210 },
31211/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
31212 {
31213 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31215 },
31216/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
31217 {
31218 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31220 },
31221/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
31222 {
31223 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31225 },
31226/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
31227 {
31228 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31230 },
31231/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
31232 {
31233 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31235 },
31236/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
31237 {
31238 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31240 },
31241/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
31242 {
31243 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31245 },
31246/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
31247 {
31248 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31250 },
31251/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
31252 {
31253 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31255 },
31256/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
31257 {
31258 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31260 },
31261/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
31262 {
31263 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31265 },
31266/* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
31267 {
31268 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31270 },
31271/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
31272 {
31273 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31275 },
31276/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
31277 {
31278 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31280 },
31281/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
31282 {
31283 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31285 },
31286/* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
31287 {
31288 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31290 },
31291/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
31292 {
31293 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31295 },
31296/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
31297 {
31298 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31300 },
31301/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
31302 {
31303 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31305 },
31306/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
31307 {
31308 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31310 },
31311/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
31312 {
31313 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
6772dd07 31314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31315 },
31316/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
31317 {
31318 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
6772dd07 31319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31320 },
31321/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
31322 {
31323 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
6772dd07 31324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31325 },
31326/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
31327 {
31328 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
6772dd07 31329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31330 },
31331/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31332 {
31333 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
6772dd07 31334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31335 },
31336/* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
31337 {
31338 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
6772dd07 31339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31340 },
31341/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31342 {
31343 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
6772dd07 31344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31345 },
31346/* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
31347 {
31348 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
6772dd07 31349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31350 },
31351/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31352 {
31353 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
6772dd07 31354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31355 },
31356/* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
31357 {
31358 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
6772dd07 31359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31360 },
31361/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
31362 {
31363 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 31364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31365 },
31366/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
31367 {
31368 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 31369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31370 },
31371/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
31372 {
31373 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
6772dd07 31374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31375 },
31376/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
31377 {
31378 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
6772dd07 31379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31380 },
31381/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
31382 {
31383 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
6772dd07 31384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31385 },
31386/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
31387 {
31388 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
6772dd07 31389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31390 },
31391/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
31392 {
31393 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31395 },
31396/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
31397 {
31398 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31400 },
31401/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
31402 {
31403 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
6772dd07 31404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31405 },
31406/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
31407 {
31408 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
6772dd07 31409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31410 },
31411/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
31412 {
31413 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31415 },
31416/* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
31417 {
31418 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
6772dd07 31419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31420 },
31421/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
31422 {
31423 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
6772dd07 31424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31425 },
31426/* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
31427 {
31428 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
6772dd07 31429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31430 },
31431/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
31432 {
31433 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
6772dd07 31434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31435 },
31436/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
31437 {
31438 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
6772dd07 31439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31440 },
31441/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
31442 {
31443 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
6772dd07 31444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31445 },
31446/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
31447 {
31448 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
6772dd07 31449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31450 },
31451/* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
31452 {
31453 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
6772dd07 31454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31455 },
31456/* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
31457 {
31458 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
6772dd07 31459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31460 },
31461/* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
31462 {
31463 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
6772dd07 31464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31465 },
31466/* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
31467 {
31468 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
6772dd07 31469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31470 },
31471/* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
31472 {
31473 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
6772dd07 31474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31475 },
31476/* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
31477 {
31478 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
6772dd07 31479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31480 },
31481/* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
31482 {
31483 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
6772dd07 31484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31485 },
31486/* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
31487 {
31488 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
6772dd07 31489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31490 },
31491/* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
31492 {
31493 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
6772dd07 31494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31495 },
31496/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31497 {
31498 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
6772dd07 31499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31500 },
31501/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31502 {
31503 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
6772dd07 31504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31505 },
31506/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
31507 {
31508 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
6772dd07 31509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31510 },
31511/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31512 {
31513 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
6772dd07 31514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31515 },
31516/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31517 {
31518 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
6772dd07 31519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31520 },
31521/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
31522 {
31523 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
6772dd07 31524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31525 },
31526/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31527 {
31528 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31530 },
31531/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31532 {
31533 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31535 },
31536/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
31537 {
31538 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31540 },
31541/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
31542 {
31543 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
6772dd07 31544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31545 },
31546/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
31547 {
31548 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
6772dd07 31549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31550 },
31551/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
31552 {
31553 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
6772dd07 31554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31555 },
31556/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
31557 {
31558 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31560 },
31561/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
31562 {
31563 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31565 },
31566/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
31567 {
31568 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31570 },
31571/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
31572 {
31573 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
6772dd07 31574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31575 },
31576/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
31577 {
31578 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
6772dd07 31579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31580 },
31581/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
31582 {
31583 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
6772dd07 31584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31585 },
31586/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
31587 {
31588 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31590 },
31591/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
31592 {
31593 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31595 },
31596/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
31597 {
31598 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31600 },
31601/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
31602 {
31603 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
6772dd07 31604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31605 },
31606/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
31607 {
31608 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
6772dd07 31609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31610 },
31611/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
31612 {
31613 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
6772dd07 31614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31615 },
31616/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
31617 {
31618 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
6772dd07 31619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31620 },
31621/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
31622 {
31623 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
6772dd07 31624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31625 },
31626/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
31627 {
31628 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
6772dd07 31629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31630 },
31631/* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
31632 {
31633 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
6772dd07 31634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31635 },
31636/* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
31637 {
31638 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40,
6772dd07 31639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31640 },
31641/* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
31642 {
31643 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40,
6772dd07 31644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31645 },
31646/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31647 {
31648 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48,
6772dd07 31649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31650 },
31651/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
31652 {
31653 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48,
6772dd07 31654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31655 },
31656/* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
31657 {
31658 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48,
6772dd07 31659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31660 },
31661/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31662 {
31663 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56,
6772dd07 31664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31665 },
31666/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
31667 {
31668 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56,
6772dd07 31669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31670 },
31671/* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
31672 {
31673 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56,
6772dd07 31674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31675 },
31676/* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
31677 {
31678 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56,
6772dd07 31679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31680 },
31681/* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31682 {
31683 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64,
6772dd07 31684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31685 },
31686/* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
31687 {
31688 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64,
6772dd07 31689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31690 },
31691/* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
31692 {
31693 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
6772dd07 31694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31695 },
31696/* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
31697 {
31698 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32,
6772dd07 31699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31700 },
31701/* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
31702 {
31703 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32,
6772dd07 31704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31705 },
31706/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31707 {
31708 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40,
6772dd07 31709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31710 },
31711/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
31712 {
31713 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31715 },
31716/* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
31717 {
31718 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40,
6772dd07 31719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31720 },
31721/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31722 {
31723 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48,
6772dd07 31724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31725 },
31726/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
31727 {
31728 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31730 },
31731/* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
31732 {
31733 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48,
6772dd07 31734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31735 },
31736/* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
31737 {
31738 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48,
6772dd07 31739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31740 },
31741/* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31742 {
31743 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56,
6772dd07 31744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31745 },
31746/* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
31747 {
31748 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56,
6772dd07 31749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 31750 },
31751/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31752 {
31753 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
6772dd07 31754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31755 },
31756/* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
31757 {
31758 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
6772dd07 31759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31760 },
31761/* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
31762 {
31763 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
6772dd07 31764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31765 },
31766/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31767 {
31768 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
6772dd07 31769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31770 },
31771/* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
31772 {
31773 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
6772dd07 31774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31775 },
31776/* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
31777 {
31778 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
6772dd07 31779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31780 },
31781/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31782 {
31783 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
6772dd07 31784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31785 },
31786/* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
31787 {
31788 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
6772dd07 31789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31790 },
31791/* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
31792 {
31793 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
6772dd07 31794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31795 },
31796/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
31797 {
31798 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
6772dd07 31799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31800 },
31801/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31802 {
31803 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
6772dd07 31804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31805 },
31806/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31807 {
31808 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
6772dd07 31809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31810 },
31811/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
31812 {
31813 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 31814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31815 },
31816/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31817 {
31818 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 31819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31820 },
31821/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31822 {
31823 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 31824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31825 },
31826/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
31827 {
31828 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 31829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31830 },
31831/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31832 {
31833 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 31834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31835 },
31836/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31837 {
31838 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 31839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31840 },
31841/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
31842 {
31843 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
6772dd07 31844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31845 },
31846/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
31847 {
31848 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
6772dd07 31849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31850 },
31851/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
31852 {
31853 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
6772dd07 31854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31855 },
31856/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
31857 {
31858 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 31859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31860 },
31861/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
31862 {
31863 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 31864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31865 },
31866/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
31867 {
31868 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 31869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31870 },
31871/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31872 {
31873 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
6772dd07 31874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31875 },
31876/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31877 {
31878 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
6772dd07 31879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31880 },
31881/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31882 {
31883 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
6772dd07 31884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31885 },
31886/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31887 {
31888 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 31889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31890 },
31891/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31892 {
31893 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 31894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31895 },
31896/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31897 {
31898 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 31899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31900 },
31901/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31902 {
31903 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
6772dd07 31904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31905 },
31906/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31907 {
31908 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
6772dd07 31909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31910 },
31911/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31912 {
31913 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
6772dd07 31914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31915 },
31916/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31917 {
31918 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
6772dd07 31919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31920 },
31921/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31922 {
31923 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
6772dd07 31924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31925 },
31926/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31927 {
31928 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
6772dd07 31929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31930 },
31931/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31932 {
31933 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
6772dd07 31934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31935 },
31936/* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
31937 {
31938 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
6772dd07 31939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31940 },
31941/* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
31942 {
31943 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
6772dd07 31944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31945 },
31946/* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
31947 {
31948 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
6772dd07 31949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31950 },
31951/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31952 {
31953 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
6772dd07 31954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31955 },
31956/* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
31957 {
31958 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
6772dd07 31959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31960 },
31961/* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
31962 {
31963 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
6772dd07 31964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31965 },
31966/* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
31967 {
31968 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
6772dd07 31969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31970 },
31971/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31972 {
31973 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
6772dd07 31974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31975 },
31976/* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31977 {
31978 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
6772dd07 31979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31980 },
31981/* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31982 {
31983 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
6772dd07 31984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31985 },
31986/* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31987 {
31988 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
6772dd07 31989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31990 },
31991/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31992 {
31993 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 31994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 31995 },
31996/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31997 {
31998 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 31999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32000 },
32001/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32002 {
32003 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 32004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32005 },
32006/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
32007 {
32008 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 32009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32010 },
32011/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
32012 {
32013 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 32014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32015 },
32016/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32017 {
32018 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 32019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32020 },
32021/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32022 {
32023 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 32024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32025 },
32026/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
32027 {
32028 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 32029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32030 },
32031/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32032 {
32033 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
6772dd07 32034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32035 },
32036/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32037 {
32038 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
6772dd07 32039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32040 },
32041/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32042 {
32043 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
6772dd07 32044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32045 },
32046/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32047 {
32048 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
6772dd07 32049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32050 },
32051/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32052 {
32053 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32055 },
32056/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32057 {
32058 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32060 },
32061/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32062 {
32063 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32065 },
32066/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32067 {
32068 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32070 },
32071/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32072 {
32073 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32075 },
32076/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32077 {
32078 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32080 },
32081/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32082 {
32083 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32085 },
32086/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32087 {
32088 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32090 },
32091/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32092 {
32093 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32095 },
32096/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32097 {
32098 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32100 },
32101/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32102 {
32103 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32105 },
32106/* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32107 {
32108 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 32109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32110 },
32111/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32112 {
32113 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32115 },
32116/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32117 {
32118 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32120 },
32121/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32122 {
32123 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32125 },
32126/* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32127 {
32128 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32130 },
32131/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32132 {
32133 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
6772dd07 32134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32135 },
32136/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32137 {
32138 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
6772dd07 32139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32140 },
32141/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32142 {
32143 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
6772dd07 32144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32145 },
32146/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
32147 {
32148 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
6772dd07 32149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32150 },
32151/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32152 {
32153 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
6772dd07 32154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32155 },
32156/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32157 {
32158 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
6772dd07 32159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32160 },
32161/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32162 {
32163 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
6772dd07 32164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32165 },
32166/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
32167 {
32168 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
6772dd07 32169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32170 },
32171/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
32172 {
32173 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
6772dd07 32174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32175 },
32176/* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
32177 {
32178 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
6772dd07 32179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32180 },
32181/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
32182 {
32183 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
6772dd07 32184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32185 },
32186/* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
32187 {
32188 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
6772dd07 32189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32190 },
32191/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32192 {
32193 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
6772dd07 32194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32195 },
32196/* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32197 {
32198 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
6772dd07 32199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32200 },
32201/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32202 {
32203 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 32204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32205 },
32206/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32207 {
32208 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 32209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32210 },
32211/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32212 {
32213 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
6772dd07 32214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32215 },
32216/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32217 {
32218 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
6772dd07 32219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32220 },
32221/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32222 {
32223 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
6772dd07 32224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32225 },
32226/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32227 {
32228 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
6772dd07 32229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32230 },
32231/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32232 {
32233 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32235 },
32236/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32237 {
32238 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32240 },
32241/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32242 {
32243 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
6772dd07 32244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32245 },
32246/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32247 {
32248 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
6772dd07 32249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32250 },
32251/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32252 {
32253 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32255 },
32256/* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32257 {
32258 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
6772dd07 32259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32260 },
32261/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32262 {
32263 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
6772dd07 32264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32265 },
32266/* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32267 {
32268 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
6772dd07 32269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32270 },
32271/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32272 {
32273 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
6772dd07 32274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32275 },
32276/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
32277 {
32278 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
6772dd07 32279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32280 },
32281/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32282 {
32283 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
6772dd07 32284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32285 },
32286/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
32287 {
32288 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
6772dd07 32289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32290 },
32291/* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
32292 {
32293 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
6772dd07 32294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32295 },
32296/* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
32297 {
32298 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
6772dd07 32299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32300 },
32301/* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
32302 {
32303 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
6772dd07 32304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32305 },
32306/* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
32307 {
32308 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
6772dd07 32309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32310 },
32311/* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
32312 {
32313 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
6772dd07 32314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32315 },
32316/* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
32317 {
32318 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
6772dd07 32319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32320 },
32321/* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
32322 {
32323 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
6772dd07 32324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32325 },
32326/* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
32327 {
32328 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
6772dd07 32329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32330 },
32331/* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
32332 {
32333 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
6772dd07 32334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32335 },
32336/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32337 {
32338 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
6772dd07 32339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32340 },
32341/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32342 {
32343 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
6772dd07 32344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32345 },
32346/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
32347 {
32348 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
6772dd07 32349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32350 },
32351/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32352 {
32353 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
6772dd07 32354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32355 },
32356/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32357 {
32358 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
6772dd07 32359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32360 },
32361/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
32362 {
32363 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
6772dd07 32364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32365 },
32366/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32367 {
32368 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 32369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32370 },
32371/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32372 {
32373 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 32374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32375 },
32376/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
32377 {
32378 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 32379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32380 },
32381/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
32382 {
32383 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
6772dd07 32384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32385 },
32386/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
32387 {
32388 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
6772dd07 32389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32390 },
32391/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
32392 {
32393 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
6772dd07 32394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32395 },
32396/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
32397 {
32398 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
6772dd07 32399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32400 },
32401/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
32402 {
32403 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
6772dd07 32404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32405 },
32406/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
32407 {
32408 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
6772dd07 32409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32410 },
32411/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
32412 {
32413 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
6772dd07 32414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32415 },
32416/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
32417 {
32418 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
6772dd07 32419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32420 },
32421/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
32422 {
32423 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
6772dd07 32424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32425 },
32426/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
32427 {
32428 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
6772dd07 32429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32430 },
32431/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
32432 {
32433 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
6772dd07 32434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32435 },
32436/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
32437 {
32438 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
6772dd07 32439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32440 },
32441/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
32442 {
32443 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
6772dd07 32444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32445 },
32446/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
32447 {
32448 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
6772dd07 32449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32450 },
32451/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
32452 {
32453 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
6772dd07 32454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32455 },
32456/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
32457 {
32458 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
6772dd07 32459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32460 },
32461/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
32462 {
32463 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
6772dd07 32464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32465 },
32466/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
32467 {
32468 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
6772dd07 32469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32470 },
32471/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32472 {
32473 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
6772dd07 32474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32475 },
32476/* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
32477 {
32478 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
6772dd07 32479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32480 },
32481/* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
32482 {
32483 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
6772dd07 32484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32485 },
32486/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32487 {
32488 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
6772dd07 32489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32490 },
32491/* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
32492 {
32493 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
6772dd07 32494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32495 },
32496/* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
32497 {
32498 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
6772dd07 32499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32500 },
32501/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32502 {
32503 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
6772dd07 32504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32505 },
32506/* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
32507 {
32508 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
6772dd07 32509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32510 },
32511/* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
32512 {
32513 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
6772dd07 32514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32515 },
32516/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
32517 {
32518 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
6772dd07 32519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32520 },
32521/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32522 {
32523 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
6772dd07 32524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32525 },
32526/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32527 {
32528 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
6772dd07 32529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32530 },
32531/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
32532 {
32533 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 32534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32535 },
32536/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32537 {
32538 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 32539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32540 },
32541/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32542 {
32543 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 32544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32545 },
32546/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
32547 {
32548 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32550 },
32551/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32552 {
32553 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32555 },
32556/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32557 {
32558 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32560 },
32561/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
32562 {
32563 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
6772dd07 32564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32565 },
32566/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
32567 {
32568 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
6772dd07 32569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32570 },
32571/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
32572 {
32573 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
6772dd07 32574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32575 },
32576/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
32577 {
32578 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32580 },
32581/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
32582 {
32583 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32585 },
32586/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
32587 {
32588 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32590 },
32591/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
32592 {
32593 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
6772dd07 32594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32595 },
32596/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
32597 {
32598 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
6772dd07 32599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32600 },
32601/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
32602 {
32603 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
6772dd07 32604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32605 },
32606/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
32607 {
32608 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32610 },
32611/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
32612 {
32613 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32615 },
32616/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
32617 {
32618 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32620 },
32621/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
32622 {
32623 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
6772dd07 32624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32625 },
32626/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
32627 {
32628 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
6772dd07 32629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32630 },
32631/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
32632 {
32633 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
6772dd07 32634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32635 },
32636/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
32637 {
32638 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
6772dd07 32639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32640 },
32641/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
32642 {
32643 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
6772dd07 32644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32645 },
32646/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
32647 {
32648 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
6772dd07 32649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32650 },
32651/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32652 {
32653 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
6772dd07 32654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32655 },
32656/* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
32657 {
32658 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
6772dd07 32659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32660 },
32661/* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
32662 {
32663 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
6772dd07 32664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32665 },
32666/* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
32667 {
32668 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
6772dd07 32669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32670 },
32671/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32672 {
32673 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
6772dd07 32674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32675 },
32676/* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
32677 {
32678 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
6772dd07 32679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32680 },
32681/* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
32682 {
32683 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
6772dd07 32684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32685 },
32686/* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
32687 {
32688 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
6772dd07 32689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32690 },
32691/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32692 {
32693 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
6772dd07 32694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32695 },
32696/* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
32697 {
32698 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
6772dd07 32699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32700 },
32701/* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
32702 {
32703 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
6772dd07 32704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32705 },
32706/* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
32707 {
32708 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
6772dd07 32709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32710 },
32711/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
32712 {
32713 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 32714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32715 },
32716/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32717 {
32718 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 32719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32720 },
32721/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32722 {
32723 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 32724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32725 },
32726/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
32727 {
32728 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 32729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32730 },
32731/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
32732 {
32733 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32735 },
32736/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32737 {
32738 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32740 },
32741/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32742 {
32743 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32745 },
32746/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
32747 {
32748 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32750 },
32751/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32752 {
32753 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
6772dd07 32754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32755 },
32756/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32757 {
32758 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
6772dd07 32759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32760 },
32761/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32762 {
32763 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
6772dd07 32764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32765 },
32766/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32767 {
32768 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
6772dd07 32769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32770 },
32771/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32772 {
32773 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32775 },
32776/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32777 {
32778 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32780 },
32781/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32782 {
32783 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32785 },
32786/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32787 {
32788 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32790 },
32791/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32792 {
32793 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32795 },
32796/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32797 {
32798 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32800 },
32801/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32802 {
32803 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32805 },
32806/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32807 {
32808 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32810 },
32811/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32812 {
32813 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32815 },
32816/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32817 {
32818 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32820 },
32821/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32822 {
32823 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32825 },
32826/* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32827 {
32828 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 32829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32830 },
32831/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32832 {
32833 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32835 },
32836/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32837 {
32838 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32840 },
32841/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32842 {
32843 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32845 },
32846/* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32847 {
32848 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32850 },
32851/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32852 {
32853 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
6772dd07 32854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32855 },
32856/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32857 {
32858 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
6772dd07 32859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32860 },
32861/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32862 {
32863 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
6772dd07 32864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32865 },
32866/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
32867 {
32868 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
6772dd07 32869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32870 },
32871/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32872 {
32873 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
6772dd07 32874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32875 },
32876/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32877 {
32878 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
6772dd07 32879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32880 },
32881/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32882 {
32883 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
6772dd07 32884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32885 },
32886/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
32887 {
32888 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
6772dd07 32889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32890 },
32891/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32892 {
32893 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
6772dd07 32894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32895 },
32896/* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
32897 {
32898 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
6772dd07 32899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32900 },
32901/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32902 {
32903 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
6772dd07 32904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32905 },
32906/* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
32907 {
32908 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
6772dd07 32909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32910 },
32911/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32912 {
32913 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
6772dd07 32914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32915 },
32916/* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32917 {
32918 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
6772dd07 32919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32920 },
32921/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32922 {
32923 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32925 },
32926/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32927 {
32928 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 32929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32930 },
32931/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32932 {
32933 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
6772dd07 32934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32935 },
32936/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32937 {
32938 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
6772dd07 32939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32940 },
32941/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32942 {
32943 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
6772dd07 32944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32945 },
32946/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32947 {
32948 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
6772dd07 32949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32950 },
32951/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32952 {
32953 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32955 },
32956/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32957 {
32958 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32960 },
32961/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32962 {
32963 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
6772dd07 32964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32965 },
32966/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32967 {
32968 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
6772dd07 32969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32970 },
32971/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32972 {
32973 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32975 },
32976/* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32977 {
32978 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
6772dd07 32979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32980 },
32981/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32982 {
32983 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
6772dd07 32984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32985 },
32986/* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32987 {
32988 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
6772dd07 32989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32990 },
32991/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32992 {
32993 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
6772dd07 32994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 32995 },
32996/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
32997 {
32998 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
6772dd07 32999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33000 },
33001/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
33002 {
33003 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
6772dd07 33004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33005 },
33006/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
33007 {
33008 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
6772dd07 33009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33010 },
33011/* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
33012 {
33013 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
6772dd07 33014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33015 },
33016/* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
33017 {
33018 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
6772dd07 33019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33020 },
33021/* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
33022 {
33023 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
6772dd07 33024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33025 },
33026/* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
33027 {
33028 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
6772dd07 33029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33030 },
33031/* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
33032 {
33033 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
6772dd07 33034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33035 },
33036/* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
33037 {
33038 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
6772dd07 33039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33040 },
33041/* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
33042 {
33043 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
6772dd07 33044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33045 },
33046/* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
33047 {
33048 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
6772dd07 33049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33050 },
33051/* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
33052 {
33053 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
6772dd07 33054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33055 },
33056/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33057 {
33058 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
6772dd07 33059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33060 },
33061/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33062 {
33063 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
6772dd07 33064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33065 },
33066/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
33067 {
33068 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
6772dd07 33069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33070 },
33071/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33072 {
33073 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
6772dd07 33074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33075 },
33076/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33077 {
33078 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
6772dd07 33079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33080 },
33081/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
33082 {
33083 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
6772dd07 33084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33085 },
33086/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33087 {
33088 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 33089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33090 },
33091/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33092 {
33093 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 33094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33095 },
33096/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
33097 {
33098 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 33099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33100 },
33101/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
33102 {
33103 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
6772dd07 33104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33105 },
33106/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
33107 {
33108 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
6772dd07 33109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33110 },
33111/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
33112 {
33113 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
6772dd07 33114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33115 },
33116/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
33117 {
33118 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33120 },
33121/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
33122 {
33123 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33125 },
33126/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
33127 {
33128 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33130 },
33131/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
33132 {
33133 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
6772dd07 33134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33135 },
33136/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
33137 {
33138 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
6772dd07 33139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33140 },
33141/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
33142 {
33143 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
6772dd07 33144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33145 },
33146/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
33147 {
33148 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33150 },
33151/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
33152 {
33153 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33155 },
33156/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
33157 {
33158 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33160 },
33161/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
33162 {
33163 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
6772dd07 33164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33165 },
33166/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
33167 {
33168 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
6772dd07 33169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33170 },
33171/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
33172 {
33173 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
6772dd07 33174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33175 },
33176/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
33177 {
33178 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
6772dd07 33179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33180 },
33181/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
33182 {
33183 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
6772dd07 33184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33185 },
33186/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
33187 {
33188 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
6772dd07 33189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 33190 },
33191/* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
33192 {
33193 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
6772dd07 33194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33195 },
33196/* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
33197 {
33198 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40,
6772dd07 33199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33200 },
33201/* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
33202 {
33203 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40,
6772dd07 33204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33205 },
33206/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33207 {
33208 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48,
6772dd07 33209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33210 },
33211/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
33212 {
33213 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48,
6772dd07 33214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33215 },
33216/* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
33217 {
33218 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48,
6772dd07 33219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33220 },
33221/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33222 {
33223 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56,
6772dd07 33224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33225 },
33226/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
33227 {
33228 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56,
6772dd07 33229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33230 },
33231/* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
33232 {
33233 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56,
6772dd07 33234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33235 },
33236/* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
33237 {
33238 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56,
6772dd07 33239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33240 },
33241/* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33242 {
33243 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64,
6772dd07 33244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33245 },
33246/* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
33247 {
33248 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64,
6772dd07 33249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33250 },
33251/* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
33252 {
33253 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
6772dd07 33254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33255 },
33256/* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
33257 {
33258 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32,
6772dd07 33259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33260 },
33261/* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
33262 {
33263 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32,
6772dd07 33264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33265 },
33266/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33267 {
33268 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40,
6772dd07 33269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33270 },
33271/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
33272 {
33273 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33275 },
33276/* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
33277 {
33278 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40,
6772dd07 33279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33280 },
33281/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33282 {
33283 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48,
6772dd07 33284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33285 },
33286/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
33287 {
33288 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48,
6772dd07 33289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33290 },
33291/* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
33292 {
33293 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48,
6772dd07 33294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33295 },
33296/* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
33297 {
33298 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48,
6772dd07 33299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33300 },
33301/* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33302 {
33303 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56,
6772dd07 33304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 33305 },
33306/* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
33307 {
33308 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
6772dd07 33309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 33310 },
a1a280bb 33311/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
49f58d10 33312 {
a1a280bb 33313 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32,
6772dd07 33314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33315 },
a1a280bb 33316/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
49f58d10 33317 {
a1a280bb 33318 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32,
6772dd07 33319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33320 },
a1a280bb
DD		 33321/* ste.w ${Dsp-16-u16},[a1a0] */
33322 {
33323 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32,
6772dd07 33324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33325 },
33326/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
49f58d10 33327 {
a1a280bb 33328 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56,
6772dd07 33329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33330 },
33331/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33332 {
33333 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56,
6772dd07 33334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33335 },
33336/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33337 {
33338 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56,
6772dd07 33339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33340 },
33341/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33342 {
a1a280bb 33343 M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56,
6772dd07 33344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33345 },
33346/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33347 {
a1a280bb 33348 M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56,
6772dd07 33349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33350 },
33351/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
33352 {
a1a280bb 33353 M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56,
6772dd07 33354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33355 },
33356/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
33357 {
33358 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24,
6772dd07 33359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33360 },
33361/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
33362 {
33363 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24,
6772dd07 33364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33365 },
33366/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
33367 {
33368 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24,
6772dd07 33369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33370 },
33371/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33372 {
33373 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48,
6772dd07 33374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33375 },
33376/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33377 {
33378 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48,
6772dd07 33379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33380 },
33381/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33382 {
33383 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48,
6772dd07 33384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33385 },
33386/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33387 {
33388 M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48,
6772dd07 33389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33390 },
33391/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33392 {
33393 M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48,
6772dd07 33394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33395 },
33396/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33397 {
33398 M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48,
6772dd07 33399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33400 },
33401/* ste.w $Dst16RnHI,[a1a0] */
33402 {
33403 M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16,
6772dd07 33404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33405 },
33406/* ste.w $Dst16AnHI,[a1a0] */
33407 {
33408 M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16,
6772dd07 33409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33410 },
33411/* ste.w [$Dst16An],[a1a0] */
33412 {
33413 M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16,
6772dd07 33414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33415 },
33416/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
33417 {
33418 M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40,
6772dd07 33419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33420 },
33421/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
33422 {
33423 M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40,
6772dd07 33424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33425 },
33426/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
33427 {
33428 M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40,
6772dd07 33429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33430 },
33431/* ste.w $Dst16RnHI,${Dsp-16-u20} */
33432 {
a1a280bb 33433 M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40,
6772dd07 33434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33435 },
33436/* ste.w $Dst16AnHI,${Dsp-16-u20} */
33437 {
a1a280bb 33438 M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40,
6772dd07 33439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33440 },
33441/* ste.w [$Dst16An],${Dsp-16-u20} */
33442 {
a1a280bb 33443 M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40,
6772dd07 33444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33445 },
a1a280bb 33446/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
49f58d10 33447 {
a1a280bb 33448 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32,
6772dd07 33449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33450 },
a1a280bb 33451/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
49f58d10 33452 {
a1a280bb 33453 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32,
6772dd07 33454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33455 },
a1a280bb 33456/* ste.b ${Dsp-16-u16},[a1a0] */
49f58d10 33457 {
a1a280bb 33458 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32,
6772dd07 33459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33460 },
33461/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
33462 {
33463 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56,
6772dd07 33464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33465 },
33466/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33467 {
33468 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56,
6772dd07 33469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33470 },
33471/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33472 {
33473 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56,
6772dd07 33474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33475 },
33476/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33477 {
a1a280bb 33478 M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56,
6772dd07 33479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33480 },
33481/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33482 {
a1a280bb 33483 M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56,
6772dd07 33484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33485 },
33486/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
33487 {
a1a280bb 33488 M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56,
6772dd07 33489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33490 },
33491/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
33492 {
33493 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24,
6772dd07 33494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33495 },
33496/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
33497 {
33498 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24,
6772dd07 33499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33500 },
33501/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
33502 {
33503 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24,
6772dd07 33504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33505 },
33506/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33507 {
33508 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48,
6772dd07 33509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33510 },
33511/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33512 {
33513 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48,
6772dd07 33514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33515 },
33516/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33517 {
33518 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48,
6772dd07 33519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33520 },
33521/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33522 {
33523 M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48,
6772dd07 33524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33525 },
33526/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33527 {
33528 M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48,
6772dd07 33529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33530 },
33531/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33532 {
33533 M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48,
6772dd07 33534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33535 },
33536/* ste.b $Dst16RnQI,[a1a0] */
33537 {
33538 M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16,
6772dd07 33539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33540 },
33541/* ste.b $Dst16AnQI,[a1a0] */
33542 {
33543 M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16,
6772dd07 33544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33545 },
33546/* ste.b [$Dst16An],[a1a0] */
33547 {
33548 M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16,
6772dd07 33549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33550 },
33551/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
33552 {
33553 M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40,
6772dd07 33554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33555 },
33556/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
33557 {
33558 M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40,
6772dd07 33559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33560 },
33561/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
33562 {
33563 M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40,
6772dd07 33564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33565 },
33566/* ste.b $Dst16RnQI,${Dsp-16-u20} */
33567 {
a1a280bb 33568 M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40,
6772dd07 33569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33570 },
33571/* ste.b $Dst16AnQI,${Dsp-16-u20} */
33572 {
a1a280bb 33573 M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40,
6772dd07 33574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33575 },
33576/* ste.b [$Dst16An],${Dsp-16-u20} */
33577 {
a1a280bb 33578 M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40,
6772dd07 33579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33580 },
a1a280bb 33581/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
49f58d10 33582 {
a1a280bb 33583 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32,
6772dd07 33584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33585 },
a1a280bb 33586/* lde.w [a1a0],${Dsp-16-u16}[sb] */
49f58d10 33587 {
a1a280bb 33588 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32,
6772dd07 33589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33590 },
a1a280bb
DD		 33591/* lde.w [a1a0],${Dsp-16-u16} */
33592 {
33593 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32,
6772dd07 33594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33595 },
33596/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
33597 {
33598 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56,
6772dd07 33599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33600 },
33601/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33602 {
33603 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56,
6772dd07 33604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33605 },
33606/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
49f58d10 33607 {
a1a280bb 33608 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56,
6772dd07 33609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33610 },
33611/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33612 {
a1a280bb 33613 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56,
6772dd07 33614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33615 },
33616/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33617 {
a1a280bb 33618 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56,
6772dd07 33619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33620 },
33621/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
33622 {
a1a280bb 33623 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56,
6772dd07 33624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33625 },
33626/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
33627 {
33628 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24,
6772dd07 33629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33630 },
33631/* lde.w [a1a0],${Dsp-16-u8}[sb] */
33632 {
33633 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24,
6772dd07 33634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33635 },
33636/* lde.w [a1a0],${Dsp-16-s8}[fb] */
33637 {
33638 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24,
6772dd07 33639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33640 },
33641/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33642 {
33643 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48,
6772dd07 33644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33645 },
33646/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33647 {
33648 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48,
6772dd07 33649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33650 },
33651/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33652 {
33653 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48,
6772dd07 33654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33655 },
33656/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33657 {
33658 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48,
6772dd07 33659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33660 },
33661/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33662 {
33663 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48,
6772dd07 33664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33665 },
33666/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33667 {
33668 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48,
6772dd07 33669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33670 },
33671/* lde.w [a1a0],$Dst16RnHI */
33672 {
33673 M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16,
6772dd07 33674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33675 },
33676/* lde.w [a1a0],$Dst16AnHI */
33677 {
33678 M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16,
6772dd07 33679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33680 },
33681/* lde.w [a1a0],[$Dst16An] */
33682 {
33683 M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16,
6772dd07 33684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33685 },
33686/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
33687 {
33688 M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40,
6772dd07 33689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33690 },
33691/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
33692 {
33693 M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40,
6772dd07 33694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33695 },
33696/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
33697 {
33698 M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40,
6772dd07 33699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33700 },
33701/* lde.w ${Dsp-16-u20},$Dst16RnHI */
33702 {
a1a280bb 33703 M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40,
6772dd07 33704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33705 },
33706/* lde.w ${Dsp-16-u20},$Dst16AnHI */
33707 {
a1a280bb 33708 M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40,
6772dd07 33709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33710 },
33711/* lde.w ${Dsp-16-u20},[$Dst16An] */
33712 {
a1a280bb 33713 M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40,
6772dd07 33714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33715 },
a1a280bb 33716/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
49f58d10 33717 {
a1a280bb 33718 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32,
6772dd07 33719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33720 },
a1a280bb 33721/* lde.b [a1a0],${Dsp-16-u16}[sb] */
49f58d10 33722 {
a1a280bb 33723 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32,
6772dd07 33724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 33725 },
a1a280bb
DD		 33726/* lde.b [a1a0],${Dsp-16-u16} */
33727 {
33728 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32,
6772dd07 33729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33730 },
33731/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
49f58d10 33732 {
a1a280bb 33733 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56,
6772dd07 33734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33735 },
33736/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33737 {
33738 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56,
6772dd07 33739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33740 },
33741/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
33742 {
33743 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56,
6772dd07 33744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33745 },
33746/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33747 {
a1a280bb 33748 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56,
6772dd07 33749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33750 },
33751/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33752 {
a1a280bb 33753 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56,
6772dd07 33754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33755 },
33756/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
33757 {
a1a280bb 33758 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56,
6772dd07 33759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33760 },
33761/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
33762 {
33763 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24,
6772dd07 33764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33765 },
33766/* lde.b [a1a0],${Dsp-16-u8}[sb] */
33767 {
33768 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24,
6772dd07 33769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33770 },
33771/* lde.b [a1a0],${Dsp-16-s8}[fb] */
33772 {
33773 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24,
6772dd07 33774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33775 },
33776/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33777 {
33778 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48,
6772dd07 33779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33780 },
33781/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33782 {
33783 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48,
6772dd07 33784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33785 },
33786/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33787 {
33788 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48,
6772dd07 33789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33790 },
33791/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33792 {
33793 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48,
6772dd07 33794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33795 },
33796/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33797 {
33798 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48,
6772dd07 33799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33800 },
33801/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33802 {
33803 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48,
6772dd07 33804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33805 },
33806/* lde.b [a1a0],$Dst16RnQI */
33807 {
33808 M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16,
6772dd07 33809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33810 },
33811/* lde.b [a1a0],$Dst16AnQI */
33812 {
33813 M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16,
6772dd07 33814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33815 },
33816/* lde.b [a1a0],[$Dst16An] */
33817 {
33818 M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16,
6772dd07 33819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33820 },
33821/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
33822 {
33823 M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40,
6772dd07 33824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33825 },
33826/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
33827 {
33828 M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40,
6772dd07 33829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
a1a280bb
DD		 33830 },
33831/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
33832 {
33833 M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40,
6772dd07 33834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33835 },
33836/* lde.b ${Dsp-16-u20},$Dst16RnQI */
33837 {
a1a280bb 33838 M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40,
6772dd07 33839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33840 },
33841/* lde.b ${Dsp-16-u20},$Dst16AnQI */
33842 {
a1a280bb 33843 M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40,
6772dd07 33844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33845 },
33846/* lde.b ${Dsp-16-u20},[$Dst16An] */
33847 {
a1a280bb 33848 M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40,
6772dd07 33849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33850 },
33851/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
33852 {
33853 M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24,
6772dd07 33854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33855 },
33856/* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
33857 {
33858 M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24,
6772dd07 33859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33860 },
33861/* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
33862 {
33863 M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24,
6772dd07 33864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33865 },
33866/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33867 {
33868 M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32,
6772dd07 33869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33870 },
33871/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33872 {
33873 M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40,
6772dd07 33874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33875 },
33876/* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33877 {
33878 M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48,
6772dd07 33879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33880 },
33881/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
33882 {
33883 M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32,
6772dd07 33884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33885 },
33886/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
33887 {
33888 M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40,
6772dd07 33889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33890 },
33891/* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
33892 {
33893 M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32,
6772dd07 33894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33895 },
33896/* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
33897 {
33898 M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40,
6772dd07 33899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33900 },
33901/* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
33902 {
33903 M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40,
6772dd07 33904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33905 },
33906/* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
33907 {
33908 M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48,
6772dd07 33909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33910 },
33911/* stc ${cr2-32},$Dst32RnUnprefixedSI */
33912 {
33913 M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16,
6772dd07 33914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33915 },
33916/* stc ${cr2-32},$Dst32AnUnprefixedSI */
33917 {
33918 M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16,
6772dd07 33919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33920 },
33921/* stc ${cr2-32},[$Dst32AnUnprefixed] */
33922 {
33923 M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16,
6772dd07 33924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33925 },
33926/* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
33927 {
33928 M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24,
6772dd07 33929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33930 },
33931/* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
33932 {
33933 M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32,
6772dd07 33934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33935 },
33936/* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
33937 {
33938 M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40,
6772dd07 33939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33940 },
33941/* stc ${cr2-32},${Dsp-16-u8}[sb] */
33942 {
33943 M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24,
6772dd07 33944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33945 },
33946/* stc ${cr2-32},${Dsp-16-u16}[sb] */
33947 {
33948 M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32,
6772dd07 33949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33950 },
33951/* stc ${cr2-32},${Dsp-16-s8}[fb] */
33952 {
33953 M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24,
6772dd07 33954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33955 },
33956/* stc ${cr2-32},${Dsp-16-s16}[fb] */
33957 {
33958 M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32,
6772dd07 33959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33960 },
33961/* stc ${cr2-32},${Dsp-16-u16} */
33962 {
33963 M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32,
6772dd07 33964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33965 },
33966/* stc ${cr2-32},${Dsp-16-u24} */
33967 {
33968 M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40,
6772dd07 33969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33970 },
33971/* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
33972 {
33973 M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24,
6772dd07 33974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33975 },
33976/* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
33977 {
33978 M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24,
6772dd07 33979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33980 },
33981/* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
33982 {
33983 M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24,
6772dd07 33984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33985 },
33986/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33987 {
33988 M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32,
6772dd07 33989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33990 },
33991/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33992 {
33993 M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40,
6772dd07 33994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 33995 },
33996/* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33997 {
33998 M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48,
6772dd07 33999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34000 },
34001/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
34002 {
34003 M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32,
6772dd07 34004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34005 },
34006/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
34007 {
34008 M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40,
6772dd07 34009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34010 },
34011/* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
34012 {
34013 M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32,
6772dd07 34014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34015 },
34016/* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
34017 {
34018 M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40,
6772dd07 34019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34020 },
34021/* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
34022 {
34023 M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40,
6772dd07 34024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34025 },
34026/* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
34027 {
34028 M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48,
6772dd07 34029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34030 },
34031/* stc pc,$Dst16RnHI */
34032 {
34033 M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16,
6772dd07 34034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34035 },
34036/* stc pc,$Dst16AnHI */
34037 {
34038 M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16,
6772dd07 34039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34040 },
34041/* stc pc,[$Dst16An] */
34042 {
34043 M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16,
6772dd07 34044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34045 },
34046/* stc pc,${Dsp-16-u8}[$Dst16An] */
34047 {
34048 M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24,
6772dd07 34049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34050 },
34051/* stc pc,${Dsp-16-u16}[$Dst16An] */
34052 {
34053 M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32,
6772dd07 34054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34055 },
34056/* stc pc,${Dsp-16-u8}[sb] */
34057 {
34058 M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24,
6772dd07 34059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34060 },
34061/* stc pc,${Dsp-16-u16}[sb] */
34062 {
34063 M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32,
6772dd07 34064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34065 },
34066/* stc pc,${Dsp-16-s8}[fb] */
34067 {
34068 M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24,
6772dd07 34069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34070 },
34071/* stc pc,${Dsp-16-u16} */
34072 {
34073 M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32,
6772dd07 34074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34075 },
34076/* stc ${cr16},$Dst16RnHI */
34077 {
34078 M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16,
6772dd07 34079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34080 },
34081/* stc ${cr16},$Dst16AnHI */
34082 {
34083 M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16,
6772dd07 34084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34085 },
34086/* stc ${cr16},[$Dst16An] */
34087 {
34088 M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16,
6772dd07 34089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34090 },
34091/* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
34092 {
34093 M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24,
6772dd07 34094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34095 },
34096/* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
34097 {
34098 M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32,
6772dd07 34099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34100 },
34101/* stc ${cr16},${Dsp-16-u8}[sb] */
34102 {
34103 M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24,
6772dd07 34104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34105 },
34106/* stc ${cr16},${Dsp-16-u16}[sb] */
34107 {
34108 M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32,
6772dd07 34109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34110 },
34111/* stc ${cr16},${Dsp-16-s8}[fb] */
34112 {
34113 M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24,
6772dd07 34114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34115 },
34116/* stc ${cr16},${Dsp-16-u16} */
34117 {
34118 M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32,
6772dd07 34119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34120 },
34121/* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
34122 {
34123 M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24,
6772dd07 34124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34125 },
34126/* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
34127 {
34128 M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24,
6772dd07 34129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34130 },
34131/* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
34132 {
34133 M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24,
6772dd07 34134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34135 },
34136/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34137 {
34138 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32,
6772dd07 34139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34140 },
34141/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34142 {
34143 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40,
6772dd07 34144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34145 },
34146/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34147 {
34148 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48,
6772dd07 34149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34150 },
34151/* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
34152 {
34153 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32,
6772dd07 34154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34155 },
34156/* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
34157 {
34158 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40,
6772dd07 34159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34160 },
34161/* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
34162 {
34163 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32,
6772dd07 34164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34165 },
34166/* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
34167 {
34168 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40,
6772dd07 34169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34170 },
34171/* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
34172 {
34173 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40,
6772dd07 34174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34175 },
34176/* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
34177 {
34178 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48,
6772dd07 34179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34180 },
34181/* ldc $Dst32RnUnprefixedSI,${cr2-32} */
34182 {
34183 M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16,
6772dd07 34184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34185 },
34186/* ldc $Dst32AnUnprefixedSI,${cr2-32} */
34187 {
34188 M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16,
6772dd07 34189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34190 },
34191/* ldc [$Dst32AnUnprefixed],${cr2-32} */
34192 {
34193 M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16,
6772dd07 34194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34195 },
34196/* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
34197 {
34198 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24,
6772dd07 34199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34200 },
34201/* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
34202 {
34203 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32,
6772dd07 34204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34205 },
34206/* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
34207 {
34208 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40,
6772dd07 34209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34210 },
34211/* ldc ${Dsp-16-u8}[sb],${cr2-32} */
34212 {
34213 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24,
6772dd07 34214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34215 },
34216/* ldc ${Dsp-16-u16}[sb],${cr2-32} */
34217 {
34218 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32,
6772dd07 34219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34220 },
34221/* ldc ${Dsp-16-s8}[fb],${cr2-32} */
34222 {
34223 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24,
6772dd07 34224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34225 },
34226/* ldc ${Dsp-16-s16}[fb],${cr2-32} */
34227 {
34228 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32,
6772dd07 34229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34230 },
34231/* ldc ${Dsp-16-u16},${cr2-32} */
34232 {
34233 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32,
6772dd07 34234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34235 },
34236/* ldc ${Dsp-16-u24},${cr2-32} */
34237 {
34238 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40,
6772dd07 34239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34240 },
34241/* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
34242 {
34243 M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24,
6772dd07 34244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34245 },
34246/* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
34247 {
34248 M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24,
6772dd07 34249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34250 },
34251/* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
34252 {
34253 M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24,
6772dd07 34254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34255 },
34256/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34257 {
34258 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32,
6772dd07 34259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34260 },
34261/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34262 {
34263 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40,
6772dd07 34264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34265 },
34266/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34267 {
34268 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48,
6772dd07 34269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34270 },
34271/* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
34272 {
34273 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32,
6772dd07 34274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34275 },
34276/* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
34277 {
34278 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40,
6772dd07 34279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34280 },
34281/* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
34282 {
34283 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32,
6772dd07 34284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34285 },
34286/* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
34287 {
34288 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40,
6772dd07 34289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34290 },
34291/* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
34292 {
34293 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40,
6772dd07 34294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34295 },
34296/* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
34297 {
34298 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48,
6772dd07 34299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34300 },
34301/* ldc $Dst16RnHI,${cr16} */
34302 {
34303 M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16,
6772dd07 34304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34305 },
34306/* ldc $Dst16AnHI,${cr16} */
34307 {
34308 M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16,
6772dd07 34309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34310 },
34311/* ldc [$Dst16An],${cr16} */
34312 {
34313 M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16,
6772dd07 34314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34315 },
34316/* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
34317 {
34318 M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24,
6772dd07 34319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34320 },
34321/* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
34322 {
34323 M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32,
6772dd07 34324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34325 },
34326/* ldc ${Dsp-16-u8}[sb],${cr16} */
34327 {
34328 M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24,
6772dd07 34329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34330 },
34331/* ldc ${Dsp-16-u16}[sb],${cr16} */
34332 {
34333 M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32,
6772dd07 34334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34335 },
34336/* ldc ${Dsp-16-s8}[fb],${cr16} */
34337 {
34338 M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24,
6772dd07 34339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34340 },
34341/* ldc ${Dsp-16-u16},${cr16} */
34342 {
34343 M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
6772dd07 34344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 34345 },
34346/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34347 {
34348 M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40,
6772dd07 34349 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34350 },
34351/* jsri.w ${Dsp-16-u24} */
34352 {
34353 M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
6772dd07 34354 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34355 },
eda87aba
DD		 34356/* jsri.a $Dst32RnUnprefixedSI */
34357 {
34358 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
6772dd07 34359 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
eda87aba
DD		 34360 },
34361/* jsri.a $Dst32AnUnprefixedSI */
34362 {
34363 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
6772dd07 34364 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
eda87aba
DD		 34365 },
34366/* jsri.a [$Dst32AnUnprefixed] */
34367 {
34368 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
6772dd07 34369 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
eda87aba
DD		 34370 },
34371/* jsri.a $Dst16RnSI */
34372 {
34373 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
6772dd07 34374 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
eda87aba
DD		 34375 },
34376/* jsri.a $Dst16AnSI */
34377 {
34378 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
6772dd07 34379 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
eda87aba
DD		 34380 },
34381/* jsri.a [$Dst16An] */
34382 {
34383 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
6772dd07 34384 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
eda87aba 34385 },
49f58d10
JB		 34386/* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34387 {
34388 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
6772dd07 34389 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34390 },
34391/* jsri.a ${Dsp-16-u16}[sb] */
34392 {
34393 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
6772dd07 34394 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34395 },
34396/* jsri.a ${Dsp-16-s16}[fb] */
34397 {
34398 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
6772dd07 34399 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34400 },
34401/* jsri.a ${Dsp-16-u16} */
34402 {
34403 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
6772dd07 34404 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34405 },
34406/* jsri.a ${Dsp-16-u16}[$Dst16An] */
34407 {
34408 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32,
6772dd07 34409 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34410 },
34411/* jsri.a ${Dsp-16-u16}[sb] */
34412 {
34413 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
6772dd07 34414 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34415 },
34416/* jsri.a ${Dsp-16-u16} */
34417 {
34418 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
6772dd07 34419 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34420 },
34421/* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34422 {
34423 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24,
6772dd07 34424 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34425 },
34426/* jsri.a ${Dsp-16-u8}[sb] */
34427 {
34428 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24,
6772dd07 34429 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34430 },
34431/* jsri.a ${Dsp-16-s8}[fb] */
34432 {
34433 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24,
6772dd07 34434 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34435 },
34436/* jsri.a ${Dsp-16-u8}[$Dst16An] */
34437 {
34438 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24,
6772dd07 34439 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34440 },
34441/* jsri.a ${Dsp-16-u8}[sb] */
34442 {
34443 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24,
6772dd07 34444 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34445 },
34446/* jsri.a ${Dsp-16-s8}[fb] */
34447 {
34448 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
6772dd07 34449 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34450 },
eda87aba 34451/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
49f58d10 34452 {
eda87aba 34453 M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
6772dd07 34454 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34455 },
eda87aba 34456/* jsri.w ${Dsp-16-u24} */
49f58d10 34457 {
eda87aba 34458 M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
6772dd07 34459 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34460 },
eda87aba 34461/* jsri.w $Dst32RnUnprefixedHI */
49f58d10 34462 {
eda87aba 34463 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
6772dd07 34464 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34465 },
eda87aba 34466/* jsri.w $Dst32AnUnprefixedHI */
49f58d10 34467 {
eda87aba 34468 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
6772dd07 34469 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34470 },
eda87aba 34471/* jsri.w [$Dst32AnUnprefixed] */
49f58d10 34472 {
eda87aba 34473 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
6772dd07 34474 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34475 },
eda87aba 34476/* jsri.w $Dst16RnHI */
49f58d10 34477 {
eda87aba 34478 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
6772dd07 34479 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34480 },
eda87aba 34481/* jsri.w $Dst16AnHI */
49f58d10 34482 {
eda87aba 34483 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
6772dd07 34484 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34485 },
eda87aba 34486/* jsri.w [$Dst16An] */
49f58d10 34487 {
eda87aba 34488 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
6772dd07 34489 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34490 },
34491/* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34492 {
34493 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32,
6772dd07 34494 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34495 },
34496/* jsri.w ${Dsp-16-u16}[sb] */
34497 {
34498 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
6772dd07 34499 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34500 },
34501/* jsri.w ${Dsp-16-s16}[fb] */
34502 {
34503 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
6772dd07 34504 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34505 },
34506/* jsri.w ${Dsp-16-u16} */
34507 {
34508 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
6772dd07 34509 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34510 },
34511/* jsri.w ${Dsp-16-u16}[$Dst16An] */
34512 {
34513 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32,
6772dd07 34514 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34515 },
34516/* jsri.w ${Dsp-16-u16}[sb] */
34517 {
34518 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
6772dd07 34519 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34520 },
34521/* jsri.w ${Dsp-16-u16} */
34522 {
34523 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
6772dd07 34524 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34525 },
34526/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34527 {
34528 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
6772dd07 34529 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34530 },
34531/* jsri.w ${Dsp-16-u8}[sb] */
34532 {
34533 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
6772dd07 34534 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34535 },
34536/* jsri.w ${Dsp-16-s8}[fb] */
34537 {
34538 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
6772dd07 34539 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34540 },
34541/* jsri.w ${Dsp-16-u8}[$Dst16An] */
34542 {
34543 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
6772dd07 34544 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34545 },
34546/* jsri.w ${Dsp-16-u8}[sb] */
34547 {
34548 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
6772dd07 34549 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34550 },
34551/* jsri.w ${Dsp-16-s8}[fb] */
34552 {
34553 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
6772dd07 34554 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 34555 },
49f58d10
JB		 34556/* jmpi.a $Dst32RnUnprefixedSI */
34557 {
34558 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
6772dd07 34559 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34560 },
34561/* jmpi.a $Dst32AnUnprefixedSI */
34562 {
34563 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16,
6772dd07 34564 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34565 },
34566/* jmpi.a [$Dst32AnUnprefixed] */
34567 {
34568 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16,
6772dd07 34569 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34570 },
34571/* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34572 {
34573 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24,
6772dd07 34574 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34575 },
34576/* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34577 {
34578 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32,
6772dd07 34579 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34580 },
34581/* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34582 {
34583 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40,
6772dd07 34584 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34585 },
34586/* jmpi.a ${Dsp-16-u8}[sb] */
34587 {
34588 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24,
6772dd07 34589 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34590 },
34591/* jmpi.a ${Dsp-16-u16}[sb] */
34592 {
34593 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32,
6772dd07 34594 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34595 },
34596/* jmpi.a ${Dsp-16-s8}[fb] */
34597 {
34598 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24,
6772dd07 34599 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34600 },
34601/* jmpi.a ${Dsp-16-s16}[fb] */
34602 {
34603 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32,
6772dd07 34604 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34605 },
34606/* jmpi.a ${Dsp-16-u16} */
34607 {
34608 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32,
6772dd07 34609 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34610 },
34611/* jmpi.a ${Dsp-16-u24} */
34612 {
34613 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40,
6772dd07 34614 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34615 },
34616/* jmpi.a $Dst16RnSI */
34617 {
34618 M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16,
6772dd07 34619 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34620 },
34621/* jmpi.a $Dst16AnSI */
34622 {
34623 M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16,
6772dd07 34624 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34625 },
34626/* jmpi.a [$Dst16An] */
34627 {
34628 M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16,
6772dd07 34629 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34630 },
34631/* jmpi.a ${Dsp-16-u8}[$Dst16An] */
34632 {
34633 M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24,
6772dd07 34634 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34635 },
34636/* jmpi.a ${Dsp-16-u16}[$Dst16An] */
34637 {
34638 M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32,
6772dd07 34639 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34640 },
34641/* jmpi.a ${Dsp-16-u8}[sb] */
34642 {
34643 M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24,
6772dd07 34644 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34645 },
34646/* jmpi.a ${Dsp-16-u16}[sb] */
34647 {
34648 M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32,
6772dd07 34649 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34650 },
34651/* jmpi.a ${Dsp-16-s8}[fb] */
34652 {
34653 M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24,
6772dd07 34654 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34655 },
34656/* jmpi.a ${Dsp-16-u16} */
34657 {
34658 M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32,
6772dd07 34659 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34660 },
34661/* jmpi.w $Dst32RnUnprefixedHI */
34662 {
34663 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16,
6772dd07 34664 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34665 },
34666/* jmpi.w $Dst32AnUnprefixedHI */
34667 {
34668 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16,
6772dd07 34669 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34670 },
34671/* jmpi.w [$Dst32AnUnprefixed] */
34672 {
34673 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16,
6772dd07 34674 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34675 },
34676/* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34677 {
34678 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24,
6772dd07 34679 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34680 },
34681/* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34682 {
34683 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32,
6772dd07 34684 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34685 },
34686/* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34687 {
34688 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40,
6772dd07 34689 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34690 },
34691/* jmpi.w ${Dsp-16-u8}[sb] */
34692 {
34693 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24,
6772dd07 34694 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34695 },
34696/* jmpi.w ${Dsp-16-u16}[sb] */
34697 {
34698 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32,
6772dd07 34699 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34700 },
34701/* jmpi.w ${Dsp-16-s8}[fb] */
34702 {
34703 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24,
6772dd07 34704 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34705 },
34706/* jmpi.w ${Dsp-16-s16}[fb] */
34707 {
34708 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32,
6772dd07 34709 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34710 },
34711/* jmpi.w ${Dsp-16-u16} */
34712 {
34713 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32,
6772dd07 34714 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34715 },
34716/* jmpi.w ${Dsp-16-u24} */
34717 {
34718 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40,
6772dd07 34719 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34720 },
34721/* jmpi.w $Dst16RnHI */
34722 {
34723 M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16,
6772dd07 34724 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34725 },
34726/* jmpi.w $Dst16AnHI */
34727 {
34728 M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16,
6772dd07 34729 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34730 },
34731/* jmpi.w [$Dst16An] */
34732 {
34733 M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16,
6772dd07 34734 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34735 },
34736/* jmpi.w ${Dsp-16-u8}[$Dst16An] */
34737 {
34738 M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24,
6772dd07 34739 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34740 },
34741/* jmpi.w ${Dsp-16-u16}[$Dst16An] */
34742 {
34743 M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32,
6772dd07 34744 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34745 },
34746/* jmpi.w ${Dsp-16-u8}[sb] */
34747 {
34748 M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24,
6772dd07 34749 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34750 },
34751/* jmpi.w ${Dsp-16-u16}[sb] */
34752 {
34753 M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32,
6772dd07 34754 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34755 },
34756/* jmpi.w ${Dsp-16-s8}[fb] */
34757 {
34758 M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24,
6772dd07 34759 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34760 },
34761/* jmpi.w ${Dsp-16-u16} */
34762 {
34763 M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32,
6772dd07 34764 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34765 },
34766/* indexws.w $Dst32RnUnprefixedHI */
34767 {
34768 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16,
6772dd07 34769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34770 },
34771/* indexws.w $Dst32AnUnprefixedHI */
34772 {
34773 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16,
6772dd07 34774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34775 },
34776/* indexws.w [$Dst32AnUnprefixed] */
34777 {
34778 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16,
6772dd07 34779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34780 },
34781/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34782 {
34783 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24,
6772dd07 34784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34785 },
34786/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34787 {
34788 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32,
6772dd07 34789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34790 },
34791/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34792 {
34793 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40,
6772dd07 34794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34795 },
34796/* indexws.w ${Dsp-16-u8}[sb] */
34797 {
34798 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24,
6772dd07 34799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34800 },
34801/* indexws.w ${Dsp-16-u16}[sb] */
34802 {
34803 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32,
6772dd07 34804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34805 },
34806/* indexws.w ${Dsp-16-s8}[fb] */
34807 {
34808 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24,
6772dd07 34809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34810 },
34811/* indexws.w ${Dsp-16-s16}[fb] */
34812 {
34813 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32,
6772dd07 34814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34815 },
34816/* indexws.w ${Dsp-16-u16} */
34817 {
34818 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32,
6772dd07 34819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34820 },
34821/* indexws.w ${Dsp-16-u24} */
34822 {
34823 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40,
6772dd07 34824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34825 },
34826/* indexws.b $Dst32RnUnprefixedQI */
34827 {
34828 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16,
6772dd07 34829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34830 },
34831/* indexws.b $Dst32AnUnprefixedQI */
34832 {
34833 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16,
6772dd07 34834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34835 },
34836/* indexws.b [$Dst32AnUnprefixed] */
34837 {
34838 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16,
6772dd07 34839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34840 },
34841/* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34842 {
34843 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24,
6772dd07 34844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34845 },
34846/* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34847 {
34848 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32,
6772dd07 34849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34850 },
34851/* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34852 {
34853 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40,
6772dd07 34854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34855 },
34856/* indexws.b ${Dsp-16-u8}[sb] */
34857 {
34858 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24,
6772dd07 34859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34860 },
34861/* indexws.b ${Dsp-16-u16}[sb] */
34862 {
34863 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32,
6772dd07 34864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34865 },
34866/* indexws.b ${Dsp-16-s8}[fb] */
34867 {
34868 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24,
6772dd07 34869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34870 },
34871/* indexws.b ${Dsp-16-s16}[fb] */
34872 {
34873 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32,
6772dd07 34874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34875 },
34876/* indexws.b ${Dsp-16-u16} */
34877 {
34878 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32,
6772dd07 34879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34880 },
34881/* indexws.b ${Dsp-16-u24} */
34882 {
34883 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40,
6772dd07 34884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34885 },
34886/* indexwd.w $Dst32RnUnprefixedHI */
34887 {
34888 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16,
6772dd07 34889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34890 },
34891/* indexwd.w $Dst32AnUnprefixedHI */
34892 {
34893 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16,
6772dd07 34894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34895 },
34896/* indexwd.w [$Dst32AnUnprefixed] */
34897 {
34898 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16,
6772dd07 34899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34900 },
34901/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34902 {
34903 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24,
6772dd07 34904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34905 },
34906/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34907 {
34908 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32,
6772dd07 34909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34910 },
34911/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34912 {
34913 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40,
6772dd07 34914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34915 },
34916/* indexwd.w ${Dsp-16-u8}[sb] */
34917 {
34918 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24,
6772dd07 34919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34920 },
34921/* indexwd.w ${Dsp-16-u16}[sb] */
34922 {
34923 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32,
6772dd07 34924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34925 },
34926/* indexwd.w ${Dsp-16-s8}[fb] */
34927 {
34928 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24,
6772dd07 34929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34930 },
34931/* indexwd.w ${Dsp-16-s16}[fb] */
34932 {
34933 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32,
6772dd07 34934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34935 },
34936/* indexwd.w ${Dsp-16-u16} */
34937 {
34938 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32,
6772dd07 34939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34940 },
34941/* indexwd.w ${Dsp-16-u24} */
34942 {
34943 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40,
6772dd07 34944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34945 },
34946/* indexwd.b $Dst32RnUnprefixedQI */
34947 {
34948 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16,
6772dd07 34949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34950 },
34951/* indexwd.b $Dst32AnUnprefixedQI */
34952 {
34953 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16,
6772dd07 34954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34955 },
34956/* indexwd.b [$Dst32AnUnprefixed] */
34957 {
34958 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16,
6772dd07 34959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34960 },
34961/* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34962 {
34963 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24,
6772dd07 34964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34965 },
34966/* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34967 {
34968 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32,
6772dd07 34969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34970 },
34971/* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34972 {
34973 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40,
6772dd07 34974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34975 },
34976/* indexwd.b ${Dsp-16-u8}[sb] */
34977 {
34978 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24,
6772dd07 34979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34980 },
34981/* indexwd.b ${Dsp-16-u16}[sb] */
34982 {
34983 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32,
6772dd07 34984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34985 },
34986/* indexwd.b ${Dsp-16-s8}[fb] */
34987 {
34988 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24,
6772dd07 34989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34990 },
34991/* indexwd.b ${Dsp-16-s16}[fb] */
34992 {
34993 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32,
6772dd07 34994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 34995 },
34996/* indexwd.b ${Dsp-16-u16} */
34997 {
34998 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32,
6772dd07 34999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35000 },
35001/* indexwd.b ${Dsp-16-u24} */
35002 {
35003 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40,
6772dd07 35004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35005 },
35006/* indexw.w $Dst32RnUnprefixedHI */
35007 {
35008 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16,
6772dd07 35009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35010 },
35011/* indexw.w $Dst32AnUnprefixedHI */
35012 {
35013 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16,
6772dd07 35014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35015 },
35016/* indexw.w [$Dst32AnUnprefixed] */
35017 {
35018 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16,
6772dd07 35019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35020 },
35021/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35022 {
35023 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24,
6772dd07 35024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35025 },
35026/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35027 {
35028 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32,
6772dd07 35029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35030 },
35031/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35032 {
35033 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40,
6772dd07 35034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35035 },
35036/* indexw.w ${Dsp-16-u8}[sb] */
35037 {
35038 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24,
6772dd07 35039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35040 },
35041/* indexw.w ${Dsp-16-u16}[sb] */
35042 {
35043 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32,
6772dd07 35044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35045 },
35046/* indexw.w ${Dsp-16-s8}[fb] */
35047 {
35048 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24,
6772dd07 35049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35050 },
35051/* indexw.w ${Dsp-16-s16}[fb] */
35052 {
35053 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32,
6772dd07 35054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35055 },
35056/* indexw.w ${Dsp-16-u16} */
35057 {
35058 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32,
6772dd07 35059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35060 },
35061/* indexw.w ${Dsp-16-u24} */
35062 {
35063 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40,
6772dd07 35064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35065 },
35066/* indexw.b $Dst32RnUnprefixedQI */
35067 {
35068 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16,
6772dd07 35069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35070 },
35071/* indexw.b $Dst32AnUnprefixedQI */
35072 {
35073 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16,
6772dd07 35074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35075 },
35076/* indexw.b [$Dst32AnUnprefixed] */
35077 {
35078 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16,
6772dd07 35079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35080 },
35081/* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35082 {
35083 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24,
6772dd07 35084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35085 },
35086/* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35087 {
35088 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32,
6772dd07 35089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35090 },
35091/* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35092 {
35093 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40,
6772dd07 35094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35095 },
35096/* indexw.b ${Dsp-16-u8}[sb] */
35097 {
35098 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24,
6772dd07 35099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35100 },
35101/* indexw.b ${Dsp-16-u16}[sb] */
35102 {
35103 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32,
6772dd07 35104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35105 },
35106/* indexw.b ${Dsp-16-s8}[fb] */
35107 {
35108 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24,
6772dd07 35109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35110 },
35111/* indexw.b ${Dsp-16-s16}[fb] */
35112 {
35113 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32,
6772dd07 35114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35115 },
35116/* indexw.b ${Dsp-16-u16} */
35117 {
35118 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32,
6772dd07 35119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35120 },
35121/* indexw.b ${Dsp-16-u24} */
35122 {
35123 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40,
6772dd07 35124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35125 },
35126/* indexls.w $Dst32RnUnprefixedHI */
35127 {
35128 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16,
6772dd07 35129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35130 },
35131/* indexls.w $Dst32AnUnprefixedHI */
35132 {
35133 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16,
6772dd07 35134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35135 },
35136/* indexls.w [$Dst32AnUnprefixed] */
35137 {
35138 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16,
6772dd07 35139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35140 },
35141/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35142 {
35143 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24,
6772dd07 35144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35145 },
35146/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35147 {
35148 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32,
6772dd07 35149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35150 },
35151/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35152 {
35153 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40,
6772dd07 35154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35155 },
35156/* indexls.w ${Dsp-16-u8}[sb] */
35157 {
35158 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24,
6772dd07 35159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35160 },
35161/* indexls.w ${Dsp-16-u16}[sb] */
35162 {
35163 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32,
6772dd07 35164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35165 },
35166/* indexls.w ${Dsp-16-s8}[fb] */
35167 {
35168 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24,
6772dd07 35169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35170 },
35171/* indexls.w ${Dsp-16-s16}[fb] */
35172 {
35173 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32,
6772dd07 35174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35175 },
35176/* indexls.w ${Dsp-16-u16} */
35177 {
35178 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32,
6772dd07 35179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35180 },
35181/* indexls.w ${Dsp-16-u24} */
35182 {
35183 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40,
6772dd07 35184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35185 },
35186/* indexls.b $Dst32RnUnprefixedQI */
35187 {
35188 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16,
6772dd07 35189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35190 },
35191/* indexls.b $Dst32AnUnprefixedQI */
35192 {
35193 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16,
6772dd07 35194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35195 },
35196/* indexls.b [$Dst32AnUnprefixed] */
35197 {
35198 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16,
6772dd07 35199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35200 },
35201/* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35202 {
35203 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24,
6772dd07 35204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35205 },
35206/* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35207 {
35208 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32,
6772dd07 35209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35210 },
35211/* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35212 {
35213 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40,
6772dd07 35214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35215 },
35216/* indexls.b ${Dsp-16-u8}[sb] */
35217 {
35218 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24,
6772dd07 35219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35220 },
35221/* indexls.b ${Dsp-16-u16}[sb] */
35222 {
35223 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32,
6772dd07 35224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35225 },
35226/* indexls.b ${Dsp-16-s8}[fb] */
35227 {
35228 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24,
6772dd07 35229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35230 },
35231/* indexls.b ${Dsp-16-s16}[fb] */
35232 {
35233 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32,
6772dd07 35234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35235 },
35236/* indexls.b ${Dsp-16-u16} */
35237 {
35238 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32,
6772dd07 35239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35240 },
35241/* indexls.b ${Dsp-16-u24} */
35242 {
35243 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40,
6772dd07 35244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35245 },
35246/* indexld.w $Dst32RnUnprefixedHI */
35247 {
35248 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16,
6772dd07 35249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35250 },
35251/* indexld.w $Dst32AnUnprefixedHI */
35252 {
35253 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16,
6772dd07 35254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35255 },
35256/* indexld.w [$Dst32AnUnprefixed] */
35257 {
35258 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16,
6772dd07 35259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35260 },
35261/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35262 {
35263 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24,
6772dd07 35264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35265 },
35266/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35267 {
35268 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32,
6772dd07 35269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35270 },
35271/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35272 {
35273 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40,
6772dd07 35274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35275 },
35276/* indexld.w ${Dsp-16-u8}[sb] */
35277 {
35278 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24,
6772dd07 35279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35280 },
35281/* indexld.w ${Dsp-16-u16}[sb] */
35282 {
35283 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32,
6772dd07 35284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35285 },
35286/* indexld.w ${Dsp-16-s8}[fb] */
35287 {
35288 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24,
6772dd07 35289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35290 },
35291/* indexld.w ${Dsp-16-s16}[fb] */
35292 {
35293 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32,
6772dd07 35294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35295 },
35296/* indexld.w ${Dsp-16-u16} */
35297 {
35298 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32,
6772dd07 35299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35300 },
35301/* indexld.w ${Dsp-16-u24} */
35302 {
35303 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40,
6772dd07 35304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35305 },
35306/* indexld.b $Dst32RnUnprefixedQI */
35307 {
35308 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16,
6772dd07 35309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35310 },
35311/* indexld.b $Dst32AnUnprefixedQI */
35312 {
35313 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16,
6772dd07 35314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35315 },
35316/* indexld.b [$Dst32AnUnprefixed] */
35317 {
35318 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16,
6772dd07 35319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35320 },
35321/* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35322 {
35323 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24,
6772dd07 35324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35325 },
35326/* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35327 {
35328 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32,
6772dd07 35329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35330 },
35331/* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35332 {
35333 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40,
6772dd07 35334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35335 },
35336/* indexld.b ${Dsp-16-u8}[sb] */
35337 {
35338 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24,
6772dd07 35339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35340 },
35341/* indexld.b ${Dsp-16-u16}[sb] */
35342 {
35343 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32,
6772dd07 35344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35345 },
35346/* indexld.b ${Dsp-16-s8}[fb] */
35347 {
35348 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24,
6772dd07 35349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35350 },
35351/* indexld.b ${Dsp-16-s16}[fb] */
35352 {
35353 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32,
6772dd07 35354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35355 },
35356/* indexld.b ${Dsp-16-u16} */
35357 {
35358 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32,
6772dd07 35359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35360 },
35361/* indexld.b ${Dsp-16-u24} */
35362 {
35363 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40,
6772dd07 35364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35365 },
35366/* indexl.w $Dst32RnUnprefixedHI */
35367 {
35368 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16,
6772dd07 35369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35370 },
35371/* indexl.w $Dst32AnUnprefixedHI */
35372 {
35373 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16,
6772dd07 35374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35375 },
35376/* indexl.w [$Dst32AnUnprefixed] */
35377 {
35378 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16,
6772dd07 35379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35380 },
35381/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35382 {
35383 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24,
6772dd07 35384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35385 },
35386/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35387 {
35388 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32,
6772dd07 35389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35390 },
35391/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35392 {
35393 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40,
6772dd07 35394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35395 },
35396/* indexl.w ${Dsp-16-u8}[sb] */
35397 {
35398 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24,
6772dd07 35399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35400 },
35401/* indexl.w ${Dsp-16-u16}[sb] */
35402 {
35403 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32,
6772dd07 35404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35405 },
35406/* indexl.w ${Dsp-16-s8}[fb] */
35407 {
35408 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24,
6772dd07 35409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35410 },
35411/* indexl.w ${Dsp-16-s16}[fb] */
35412 {
35413 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32,
6772dd07 35414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35415 },
35416/* indexl.w ${Dsp-16-u16} */
35417 {
35418 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32,
6772dd07 35419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35420 },
35421/* indexl.w ${Dsp-16-u24} */
35422 {
35423 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40,
6772dd07 35424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35425 },
35426/* indexl.b $Dst32RnUnprefixedQI */
35427 {
35428 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16,
6772dd07 35429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35430 },
35431/* indexl.b $Dst32AnUnprefixedQI */
35432 {
35433 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16,
6772dd07 35434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35435 },
35436/* indexl.b [$Dst32AnUnprefixed] */
35437 {
35438 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16,
6772dd07 35439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35440 },
35441/* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35442 {
35443 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24,
6772dd07 35444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35445 },
35446/* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35447 {
35448 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32,
6772dd07 35449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35450 },
35451/* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35452 {
35453 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40,
6772dd07 35454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35455 },
35456/* indexl.b ${Dsp-16-u8}[sb] */
35457 {
35458 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24,
6772dd07 35459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35460 },
35461/* indexl.b ${Dsp-16-u16}[sb] */
35462 {
35463 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32,
6772dd07 35464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35465 },
35466/* indexl.b ${Dsp-16-s8}[fb] */
35467 {
35468 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24,
6772dd07 35469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35470 },
35471/* indexl.b ${Dsp-16-s16}[fb] */
35472 {
35473 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32,
6772dd07 35474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35475 },
35476/* indexl.b ${Dsp-16-u16} */
35477 {
35478 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32,
6772dd07 35479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35480 },
35481/* indexl.b ${Dsp-16-u24} */
35482 {
35483 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40,
6772dd07 35484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35485 },
35486/* indexbs.w $Dst32RnUnprefixedHI */
35487 {
35488 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16,
6772dd07 35489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35490 },
35491/* indexbs.w $Dst32AnUnprefixedHI */
35492 {
35493 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16,
6772dd07 35494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35495 },
35496/* indexbs.w [$Dst32AnUnprefixed] */
35497 {
35498 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16,
6772dd07 35499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35500 },
35501/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35502 {
35503 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24,
6772dd07 35504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35505 },
35506/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35507 {
35508 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32,
6772dd07 35509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35510 },
35511/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35512 {
35513 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40,
6772dd07 35514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35515 },
35516/* indexbs.w ${Dsp-16-u8}[sb] */
35517 {
35518 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24,
6772dd07 35519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35520 },
35521/* indexbs.w ${Dsp-16-u16}[sb] */
35522 {
35523 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32,
6772dd07 35524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35525 },
35526/* indexbs.w ${Dsp-16-s8}[fb] */
35527 {
35528 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24,
6772dd07 35529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35530 },
35531/* indexbs.w ${Dsp-16-s16}[fb] */
35532 {
35533 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32,
6772dd07 35534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35535 },
35536/* indexbs.w ${Dsp-16-u16} */
35537 {
35538 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32,
6772dd07 35539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35540 },
35541/* indexbs.w ${Dsp-16-u24} */
35542 {
35543 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40,
6772dd07 35544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35545 },
35546/* indexbs.b $Dst32RnUnprefixedQI */
35547 {
35548 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16,
6772dd07 35549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35550 },
35551/* indexbs.b $Dst32AnUnprefixedQI */
35552 {
35553 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16,
6772dd07 35554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35555 },
35556/* indexbs.b [$Dst32AnUnprefixed] */
35557 {
35558 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16,
6772dd07 35559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35560 },
35561/* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35562 {
35563 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24,
6772dd07 35564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35565 },
35566/* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35567 {
35568 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32,
6772dd07 35569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35570 },
35571/* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35572 {
35573 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40,
6772dd07 35574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35575 },
35576/* indexbs.b ${Dsp-16-u8}[sb] */
35577 {
35578 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24,
6772dd07 35579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35580 },
35581/* indexbs.b ${Dsp-16-u16}[sb] */
35582 {
35583 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32,
6772dd07 35584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35585 },
35586/* indexbs.b ${Dsp-16-s8}[fb] */
35587 {
35588 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24,
6772dd07 35589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35590 },
35591/* indexbs.b ${Dsp-16-s16}[fb] */
35592 {
35593 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32,
6772dd07 35594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35595 },
35596/* indexbs.b ${Dsp-16-u16} */
35597 {
35598 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32,
6772dd07 35599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35600 },
35601/* indexbs.b ${Dsp-16-u24} */
35602 {
35603 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40,
6772dd07 35604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35605 },
35606/* indexbd.w $Dst32RnUnprefixedHI */
35607 {
35608 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16,
6772dd07 35609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35610 },
35611/* indexbd.w $Dst32AnUnprefixedHI */
35612 {
35613 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16,
6772dd07 35614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35615 },
35616/* indexbd.w [$Dst32AnUnprefixed] */
35617 {
35618 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16,
6772dd07 35619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35620 },
35621/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35622 {
35623 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24,
6772dd07 35624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35625 },
35626/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35627 {
35628 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32,
6772dd07 35629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35630 },
35631/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35632 {
35633 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40,
6772dd07 35634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35635 },
35636/* indexbd.w ${Dsp-16-u8}[sb] */
35637 {
35638 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24,
6772dd07 35639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35640 },
35641/* indexbd.w ${Dsp-16-u16}[sb] */
35642 {
35643 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32,
6772dd07 35644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35645 },
35646/* indexbd.w ${Dsp-16-s8}[fb] */
35647 {
35648 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24,
6772dd07 35649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35650 },
35651/* indexbd.w ${Dsp-16-s16}[fb] */
35652 {
35653 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32,
6772dd07 35654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35655 },
35656/* indexbd.w ${Dsp-16-u16} */
35657 {
35658 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32,
6772dd07 35659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35660 },
35661/* indexbd.w ${Dsp-16-u24} */
35662 {
35663 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40,
6772dd07 35664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35665 },
35666/* indexbd.b $Dst32RnUnprefixedQI */
35667 {
35668 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16,
6772dd07 35669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35670 },
35671/* indexbd.b $Dst32AnUnprefixedQI */
35672 {
35673 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16,
6772dd07 35674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35675 },
35676/* indexbd.b [$Dst32AnUnprefixed] */
35677 {
35678 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16,
6772dd07 35679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35680 },
35681/* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35682 {
35683 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24,
6772dd07 35684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35685 },
35686/* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35687 {
35688 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32,
6772dd07 35689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35690 },
35691/* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35692 {
35693 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40,
6772dd07 35694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35695 },
35696/* indexbd.b ${Dsp-16-u8}[sb] */
35697 {
35698 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24,
6772dd07 35699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35700 },
35701/* indexbd.b ${Dsp-16-u16}[sb] */
35702 {
35703 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32,
6772dd07 35704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35705 },
35706/* indexbd.b ${Dsp-16-s8}[fb] */
35707 {
35708 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24,
6772dd07 35709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35710 },
35711/* indexbd.b ${Dsp-16-s16}[fb] */
35712 {
35713 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32,
6772dd07 35714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35715 },
35716/* indexbd.b ${Dsp-16-u16} */
35717 {
35718 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32,
6772dd07 35719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35720 },
35721/* indexbd.b ${Dsp-16-u24} */
35722 {
35723 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40,
6772dd07 35724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35725 },
35726/* indexb.w $Dst32RnUnprefixedHI */
35727 {
35728 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16,
6772dd07 35729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35730 },
35731/* indexb.w $Dst32AnUnprefixedHI */
35732 {
35733 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16,
6772dd07 35734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35735 },
35736/* indexb.w [$Dst32AnUnprefixed] */
35737 {
35738 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16,
6772dd07 35739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35740 },
35741/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35742 {
35743 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24,
6772dd07 35744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35745 },
35746/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35747 {
35748 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32,
6772dd07 35749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35750 },
35751/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35752 {
35753 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40,
6772dd07 35754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35755 },
35756/* indexb.w ${Dsp-16-u8}[sb] */
35757 {
35758 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24,
6772dd07 35759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35760 },
35761/* indexb.w ${Dsp-16-u16}[sb] */
35762 {
35763 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32,
6772dd07 35764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35765 },
35766/* indexb.w ${Dsp-16-s8}[fb] */
35767 {
35768 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24,
6772dd07 35769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35770 },
35771/* indexb.w ${Dsp-16-s16}[fb] */
35772 {
35773 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32,
6772dd07 35774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35775 },
35776/* indexb.w ${Dsp-16-u16} */
35777 {
35778 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32,
6772dd07 35779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35780 },
35781/* indexb.w ${Dsp-16-u24} */
35782 {
35783 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40,
6772dd07 35784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35785 },
35786/* indexb.b $Dst32RnUnprefixedQI */
35787 {
35788 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16,
6772dd07 35789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35790 },
35791/* indexb.b $Dst32AnUnprefixedQI */
35792 {
35793 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16,
6772dd07 35794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35795 },
35796/* indexb.b [$Dst32AnUnprefixed] */
35797 {
35798 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16,
6772dd07 35799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35800 },
35801/* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35802 {
35803 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24,
6772dd07 35804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35805 },
35806/* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35807 {
35808 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32,
6772dd07 35809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35810 },
35811/* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35812 {
35813 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40,
6772dd07 35814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35815 },
35816/* indexb.b ${Dsp-16-u8}[sb] */
35817 {
35818 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24,
6772dd07 35819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35820 },
35821/* indexb.b ${Dsp-16-u16}[sb] */
35822 {
35823 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32,
6772dd07 35824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35825 },
35826/* indexb.b ${Dsp-16-s8}[fb] */
35827 {
35828 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24,
6772dd07 35829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35830 },
35831/* indexb.b ${Dsp-16-s16}[fb] */
35832 {
35833 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32,
6772dd07 35834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35835 },
35836/* indexb.b ${Dsp-16-u16} */
35837 {
35838 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32,
6772dd07 35839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35840 },
35841/* indexb.b ${Dsp-16-u24} */
35842 {
35843 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40,
6772dd07 35844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35845 },
35846/* inc.w $Dst32RnUnprefixedHI */
35847 {
35848 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16,
6772dd07 35849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35850 },
35851/* inc.w $Dst32AnUnprefixedHI */
35852 {
35853 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16,
6772dd07 35854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35855 },
35856/* inc.w [$Dst32AnUnprefixed] */
35857 {
35858 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16,
6772dd07 35859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35860 },
35861/* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35862 {
35863 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24,
6772dd07 35864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35865 },
35866/* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35867 {
35868 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32,
6772dd07 35869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35870 },
35871/* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35872 {
35873 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40,
6772dd07 35874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35875 },
35876/* inc.w ${Dsp-16-u8}[sb] */
35877 {
35878 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24,
6772dd07 35879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35880 },
35881/* inc.w ${Dsp-16-u16}[sb] */
35882 {
35883 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32,
6772dd07 35884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35885 },
35886/* inc.w ${Dsp-16-s8}[fb] */
35887 {
35888 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24,
6772dd07 35889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35890 },
35891/* inc.w ${Dsp-16-s16}[fb] */
35892 {
35893 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32,
6772dd07 35894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35895 },
35896/* inc.w ${Dsp-16-u16} */
35897 {
35898 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32,
6772dd07 35899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35900 },
35901/* inc.w ${Dsp-16-u24} */
35902 {
35903 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40,
6772dd07 35904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35905 },
35906/* inc.b $Dst32RnUnprefixedQI */
35907 {
35908 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16,
6772dd07 35909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35910 },
35911/* inc.b $Dst32AnUnprefixedQI */
35912 {
35913 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16,
6772dd07 35914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35915 },
35916/* inc.b [$Dst32AnUnprefixed] */
35917 {
35918 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16,
6772dd07 35919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35920 },
35921/* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35922 {
35923 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24,
6772dd07 35924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35925 },
35926/* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35927 {
35928 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32,
6772dd07 35929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35930 },
35931/* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35932 {
35933 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40,
6772dd07 35934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35935 },
35936/* inc.b ${Dsp-16-u8}[sb] */
35937 {
35938 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24,
6772dd07 35939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35940 },
35941/* inc.b ${Dsp-16-u16}[sb] */
35942 {
35943 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32,
6772dd07 35944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35945 },
35946/* inc.b ${Dsp-16-s8}[fb] */
35947 {
35948 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24,
6772dd07 35949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35950 },
35951/* inc.b ${Dsp-16-s16}[fb] */
35952 {
35953 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32,
6772dd07 35954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35955 },
35956/* inc.b ${Dsp-16-u16} */
35957 {
35958 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32,
6772dd07 35959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35960 },
35961/* inc.b ${Dsp-16-u24} */
35962 {
35963 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40,
6772dd07 35964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 35965 },
35966/* inc.b r0l */
35967 {
35968 M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8,
6772dd07 35969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 35970 },
35971/* inc.b r0h */
35972 {
35973 M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8,
6772dd07 35974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 35975 },
35976/* inc.b ${Dsp-8-u8}[sb] */
35977 {
35978 M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16,
6772dd07 35979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 35980 },
35981/* inc.b ${Dsp-8-s8}[fb] */
35982 {
35983 M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16,
6772dd07 35984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 35985 },
35986/* inc.b ${Dsp-8-u16} */
35987 {
35988 M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24,
6772dd07 35989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 35990 },
35991/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
35992 {
35993 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
6772dd07 35994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 35995 },
35996/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
35997 {
35998 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
6772dd07 35999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36000 },
36001/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
36002 {
36003 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
6772dd07 36004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36005 },
36006/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36007 {
36008 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
6772dd07 36009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36010 },
36011/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
36012 {
36013 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
6772dd07 36014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36015 },
36016/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
36017 {
36018 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
6772dd07 36019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36020 },
36021/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36022 {
36023 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
6772dd07 36024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36025 },
36026/* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36027 {
36028 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
6772dd07 36029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36030 },
36031/* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36032 {
36033 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
6772dd07 36034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36035 },
36036/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36037 {
36038 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36040 },
36041/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36042 {
36043 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36045 },
36046/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36047 {
36048 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36050 },
36051/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36052 {
36053 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36055 },
36056/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36057 {
36058 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36060 },
36061/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36062 {
36063 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36065 },
36066/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36067 {
36068 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36070 },
36071/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36072 {
36073 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36075 },
36076/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36077 {
36078 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36080 },
36081/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36082 {
36083 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36085 },
36086/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36087 {
36088 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36090 },
36091/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36092 {
36093 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36095 },
36096/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36097 {
36098 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36100 },
36101/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36102 {
36103 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36105 },
36106/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36107 {
36108 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36110 },
36111/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36112 {
36113 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36115 },
36116/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36117 {
36118 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36120 },
36121/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36122 {
36123 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36125 },
36126/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36127 {
36128 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36130 },
36131/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36132 {
36133 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36135 },
36136/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36137 {
36138 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36140 },
36141/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36142 {
36143 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
6772dd07 36144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36145 },
36146/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36147 {
36148 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
6772dd07 36149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36150 },
36151/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36152 {
36153 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
6772dd07 36154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36155 },
36156/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36157 {
36158 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
6772dd07 36159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36160 },
36161/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36162 {
36163 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
6772dd07 36164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36165 },
36166/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36167 {
36168 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
6772dd07 36169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36170 },
36171/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36172 {
36173 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36175 },
36176/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
36177 {
36178 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36180 },
36181/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
36182 {
36183 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36185 },
36186/* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
36187 {
36188 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36190 },
36191/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36192 {
36193 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36195 },
36196/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
36197 {
36198 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36200 },
36201/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
36202 {
36203 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36205 },
36206/* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
36207 {
36208 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
6772dd07 36209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36210 },
36211/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36212 {
36213 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
6772dd07 36214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36215 },
36216/* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
36217 {
36218 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
6772dd07 36219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36220 },
36221/* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
36222 {
36223 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
6772dd07 36224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36225 },
36226/* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
36227 {
36228 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
6772dd07 36229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36230 },
36231/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36232 {
36233 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36235 },
36236/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36237 {
36238 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36240 },
36241/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36242 {
36243 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36245 },
36246/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
36247 {
36248 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36250 },
36251/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36252 {
36253 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36255 },
36256/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36257 {
36258 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36260 },
36261/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36262 {
36263 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36265 },
36266/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
36267 {
36268 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36270 },
36271/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36272 {
36273 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36275 },
36276/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36277 {
36278 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36280 },
36281/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36282 {
36283 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36285 },
36286/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
36287 {
36288 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36290 },
36291/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
36292 {
36293 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36295 },
36296/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
36297 {
36298 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36300 },
36301/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
36302 {
36303 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36305 },
36306/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
36307 {
36308 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36310 },
36311/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
36312 {
36313 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36315 },
36316/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
36317 {
36318 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36320 },
36321/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
36322 {
36323 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36325 },
36326/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
36327 {
36328 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36330 },
36331/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
36332 {
36333 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36335 },
36336/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
36337 {
36338 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36340 },
36341/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
36342 {
36343 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36345 },
36346/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
36347 {
36348 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36350 },
36351/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
36352 {
36353 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36355 },
36356/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
36357 {
36358 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36360 },
36361/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
36362 {
36363 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36365 },
36366/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
36367 {
36368 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36370 },
36371/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
36372 {
36373 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
6772dd07 36374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36375 },
36376/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
36377 {
36378 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
6772dd07 36379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36380 },
36381/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
36382 {
36383 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
6772dd07 36384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36385 },
36386/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
36387 {
36388 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
6772dd07 36389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36390 },
36391/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
36392 {
36393 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
6772dd07 36394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36395 },
36396/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
36397 {
36398 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
6772dd07 36399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36400 },
36401/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
36402 {
36403 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
6772dd07 36404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36405 },
36406/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
36407 {
36408 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
6772dd07 36409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36410 },
36411/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36412 {
36413 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
6772dd07 36414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36415 },
36416/* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
36417 {
36418 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
6772dd07 36419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36420 },
36421/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36422 {
36423 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
6772dd07 36424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36425 },
36426/* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
36427 {
36428 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
6772dd07 36429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36430 },
36431/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36432 {
36433 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
6772dd07 36434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36435 },
36436/* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
36437 {
36438 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
6772dd07 36439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36440 },
36441/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
36442 {
36443 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36445 },
36446/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
36447 {
36448 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36450 },
36451/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
36452 {
36453 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36455 },
36456/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
36457 {
36458 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36460 },
36461/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
36462 {
36463 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
6772dd07 36464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36465 },
36466/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
36467 {
36468 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
6772dd07 36469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36470 },
36471/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
36472 {
36473 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36475 },
36476/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
36477 {
36478 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36480 },
36481/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
36482 {
36483 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36485 },
36486/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
36487 {
36488 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36490 },
36491/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
36492 {
36493 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36495 },
36496/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
36497 {
36498 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
6772dd07 36499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36500 },
36501/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
36502 {
36503 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36505 },
36506/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
36507 {
36508 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36510 },
36511/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
36512 {
36513 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
6772dd07 36514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36515 },
36516/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
36517 {
36518 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
6772dd07 36519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36520 },
36521/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
36522 {
36523 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
6772dd07 36524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36525 },
36526/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
36527 {
36528 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
6772dd07 36529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36530 },
36531/* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
36532 {
36533 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
6772dd07 36534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36535 },
36536/* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
36537 {
36538 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
6772dd07 36539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36540 },
36541/* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36542 {
36543 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
6772dd07 36544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36545 },
36546/* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
36547 {
36548 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
6772dd07 36549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36550 },
36551/* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
36552 {
36553 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
6772dd07 36554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36555 },
36556/* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36557 {
36558 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
6772dd07 36559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36560 },
36561/* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
36562 {
36563 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
6772dd07 36564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36565 },
36566/* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
36567 {
36568 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
6772dd07 36569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36570 },
36571/* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36572 {
36573 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
6772dd07 36574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36575 },
36576/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36577 {
36578 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36580 },
36581/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36582 {
36583 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36585 },
36586/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
36587 {
36588 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36590 },
36591/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36592 {
36593 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36595 },
36596/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36597 {
36598 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36600 },
36601/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
36602 {
36603 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36605 },
36606/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36607 {
36608 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36610 },
36611/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36612 {
36613 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36615 },
36616/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
36617 {
36618 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
6772dd07 36619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36620 },
36621/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
36622 {
36623 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36625 },
36626/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
36627 {
36628 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36630 },
36631/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
36632 {
36633 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36635 },
36636/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
36637 {
36638 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36640 },
36641/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
36642 {
36643 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36645 },
36646/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
36647 {
36648 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36650 },
36651/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
36652 {
36653 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36655 },
36656/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
36657 {
36658 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36660 },
36661/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
36662 {
36663 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
6772dd07 36664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36665 },
36666/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
36667 {
36668 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36670 },
36671/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
36672 {
36673 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36675 },
36676/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
36677 {
36678 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
6772dd07 36679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36680 },
36681/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
36682 {
36683 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
6772dd07 36684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36685 },
36686/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
36687 {
36688 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
6772dd07 36689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36690 },
36691/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
36692 {
36693 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
6772dd07 36694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36695 },
36696/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
36697 {
36698 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
6772dd07 36699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36700 },
36701/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
36702 {
36703 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
6772dd07 36704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36705 },
36706/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
36707 {
36708 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
6772dd07 36709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36710 },
36711/* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
36712 {
36713 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32,
6772dd07 36714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36715 },
36716/* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
36717 {
36718 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32,
6772dd07 36719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36720 },
36721/* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
36722 {
36723 M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40,
6772dd07 36724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36725 },
36726/* sub.w${S} #${Imm-8-HI},r0 */
36727 {
36728 M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24,
6772dd07 36729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36730 },
36731/* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
36732 {
36733 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24,
6772dd07 36734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36735 },
36736/* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
36737 {
36738 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24,
6772dd07 36739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36740 },
36741/* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
36742 {
36743 M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32,
6772dd07 36744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36745 },
36746/* sub.b${S} #${Imm-8-QI},r0l */
36747 {
36748 M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16,
6772dd07 36749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36750 },
36751/* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
36752 {
36753 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48,
6772dd07 36754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36755 },
36756/* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
36757 {
36758 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48,
6772dd07 36759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36760 },
36761/* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
36762 {
36763 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48,
6772dd07 36764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36765 },
36766/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
36767 {
36768 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36770 },
36771/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
36772 {
36773 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36775 },
36776/* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
36777 {
36778 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56,
6772dd07 36779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36780 },
36781/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
36782 {
36783 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64,
6772dd07 36784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36785 },
36786/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
36787 {
36788 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64,
6772dd07 36789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36790 },
36791/* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
36792 {
36793 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64,
6772dd07 36794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36795 },
36796/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
36797 {
36798 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64,
6772dd07 36799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36800 },
36801/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
36802 {
36803 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72,
6772dd07 36804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36805 },
36806/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
36807 {
36808 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72,
6772dd07 36809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 36810 },
36811/* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36812 {
36813 M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8,
6772dd07 36814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36815 },
36816/* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36817 {
36818 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16,
6772dd07 36819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36820 },
36821/* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36822 {
36823 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16,
6772dd07 36824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36825 },
36826/* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36827 {
36828 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24,
6772dd07 36829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 36830 },
36831/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36832 {
36833 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
6772dd07 36834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36835 },
36836/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
36837 {
36838 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
6772dd07 36839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36840 },
36841/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
36842 {
36843 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
6772dd07 36844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36845 },
36846/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36847 {
36848 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
6772dd07 36849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36850 },
36851/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
36852 {
36853 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
6772dd07 36854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36855 },
36856/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
36857 {
36858 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
6772dd07 36859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36860 },
36861/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36862 {
36863 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
6772dd07 36864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36865 },
36866/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36867 {
36868 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
6772dd07 36869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36870 },
36871/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36872 {
36873 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
6772dd07 36874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36875 },
36876/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36877 {
36878 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36880 },
36881/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36882 {
36883 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36885 },
36886/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36887 {
36888 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36890 },
36891/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36892 {
36893 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36895 },
36896/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36897 {
36898 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36900 },
36901/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36902 {
36903 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36905 },
36906/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36907 {
36908 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 36909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36910 },
36911/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36912 {
36913 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 36914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36915 },
36916/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36917 {
36918 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 36919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36920 },
36921/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36922 {
36923 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36925 },
36926/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36927 {
36928 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36930 },
36931/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36932 {
36933 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36935 },
36936/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36937 {
36938 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36940 },
36941/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36942 {
36943 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36945 },
36946/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36947 {
36948 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36950 },
36951/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36952 {
36953 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36955 },
36956/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36957 {
36958 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36960 },
36961/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36962 {
36963 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 36964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36965 },
36966/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36967 {
36968 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36970 },
36971/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36972 {
36973 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36975 },
36976/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36977 {
36978 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 36979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36980 },
36981/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36982 {
36983 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
6772dd07 36984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36985 },
36986/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36987 {
36988 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
6772dd07 36989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36990 },
36991/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36992 {
36993 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
6772dd07 36994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 36995 },
36996/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36997 {
36998 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 36999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37000 },
37001/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37002 {
37003 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 37004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37005 },
37006/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37007 {
37008 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 37009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37010 },
37011/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37012 {
37013 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37015 },
37016/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
37017 {
37018 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37020 },
37021/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
37022 {
37023 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37025 },
37026/* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
37027 {
37028 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37030 },
37031/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37032 {
37033 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37035 },
37036/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
37037 {
37038 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37040 },
37041/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
37042 {
37043 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37045 },
37046/* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
37047 {
37048 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 37049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37050 },
37051/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37052 {
37053 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
6772dd07 37054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37055 },
37056/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37057 {
37058 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
6772dd07 37059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37060 },
37061/* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37062 {
37063 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
6772dd07 37064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37065 },
37066/* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37067 {
37068 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
6772dd07 37069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37070 },
37071/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37072 {
37073 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37075 },
37076/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37077 {
37078 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37080 },
37081/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37082 {
37083 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37085 },
37086/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37087 {
37088 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37090 },
37091/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37092 {
37093 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37095 },
37096/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37097 {
37098 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37100 },
37101/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37102 {
37103 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37105 },
37106/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37107 {
37108 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37110 },
37111/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37112 {
37113 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37115 },
37116/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37117 {
37118 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37120 },
37121/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37122 {
37123 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37125 },
37126/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37127 {
37128 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37130 },
37131/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37132 {
37133 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37135 },
37136/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37137 {
37138 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37140 },
37141/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37142 {
37143 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37145 },
37146/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37147 {
37148 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37150 },
37151/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37152 {
37153 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37155 },
37156/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37157 {
37158 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37160 },
37161/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37162 {
37163 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37165 },
37166/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37167 {
37168 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37170 },
37171/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37172 {
37173 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37175 },
37176/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37177 {
37178 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37180 },
37181/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37182 {
37183 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37185 },
37186/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37187 {
37188 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37190 },
37191/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37192 {
37193 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37195 },
37196/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37197 {
37198 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37200 },
37201/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37202 {
37203 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37205 },
37206/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37207 {
37208 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37210 },
37211/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37212 {
37213 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 37214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37215 },
37216/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37217 {
37218 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 37219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37220 },
37221/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37222 {
37223 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 37224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37225 },
37226/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
37227 {
37228 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 37229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37230 },
37231/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37232 {
37233 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
6772dd07 37234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37235 },
37236/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37237 {
37238 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
6772dd07 37239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37240 },
37241/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37242 {
37243 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
6772dd07 37244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37245 },
37246/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
37247 {
37248 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
6772dd07 37249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37250 },
37251/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37252 {
37253 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
6772dd07 37254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37255 },
37256/* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
37257 {
37258 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
6772dd07 37259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37260 },
37261/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37262 {
37263 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
6772dd07 37264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37265 },
37266/* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
37267 {
37268 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
6772dd07 37269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37270 },
37271/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37272 {
37273 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
6772dd07 37274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37275 },
37276/* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37277 {
37278 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
6772dd07 37279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37280 },
37281/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37282 {
37283 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37285 },
37286/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37287 {
37288 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37290 },
37291/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37292 {
37293 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37295 },
37296/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37297 {
37298 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37300 },
37301/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37302 {
37303 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
6772dd07 37304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37305 },
37306/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37307 {
37308 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
6772dd07 37309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37310 },
37311/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37312 {
37313 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37315 },
37316/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37317 {
37318 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37320 },
37321/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37322 {
37323 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37325 },
37326/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37327 {
37328 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37330 },
37331/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37332 {
37333 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37335 },
37336/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37337 {
37338 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 37339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37340 },
37341/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37342 {
37343 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37345 },
37346/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37347 {
37348 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 37349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37350 },
37351/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37352 {
37353 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
6772dd07 37354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37355 },
37356/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
37357 {
37358 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
6772dd07 37359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37360 },
37361/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37362 {
37363 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
6772dd07 37364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37365 },
37366/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
37367 {
37368 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
6772dd07 37369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37370 },
37371/* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
37372 {
37373 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
6772dd07 37374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37375 },
37376/* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
37377 {
37378 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
6772dd07 37379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37380 },
37381/* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37382 {
37383 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
6772dd07 37384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37385 },
37386/* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
37387 {
37388 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
6772dd07 37389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37390 },
37391/* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
37392 {
37393 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
6772dd07 37394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37395 },
37396/* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37397 {
37398 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
6772dd07 37399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37400 },
37401/* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
37402 {
37403 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
6772dd07 37404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37405 },
37406/* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
37407 {
37408 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
6772dd07 37409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37410 },
37411/* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37412 {
37413 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
6772dd07 37414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37415 },
37416/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37417 {
37418 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37420 },
37421/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37422 {
37423 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37425 },
37426/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37427 {
37428 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37430 },
37431/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37432 {
37433 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37435 },
37436/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37437 {
37438 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37440 },
37441/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37442 {
37443 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37445 },
37446/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37447 {
37448 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37450 },
37451/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37452 {
37453 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37455 },
37456/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37457 {
37458 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 37459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37460 },
37461/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
37462 {
37463 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37465 },
37466/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
37467 {
37468 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37470 },
37471/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37472 {
37473 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37475 },
37476/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
37477 {
37478 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37480 },
37481/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
37482 {
37483 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37485 },
37486/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37487 {
37488 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37490 },
37491/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
37492 {
37493 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37495 },
37496/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
37497 {
37498 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37500 },
37501/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37502 {
37503 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
6772dd07 37504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37505 },
37506/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
37507 {
37508 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37510 },
37511/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
37512 {
37513 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37515 },
37516/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37517 {
37518 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
6772dd07 37519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37520 },
37521/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
37522 {
37523 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
6772dd07 37524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37525 },
37526/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
37527 {
37528 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
6772dd07 37529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37530 },
37531/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37532 {
37533 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
6772dd07 37534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37535 },
37536/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
37537 {
37538 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
6772dd07 37539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37540 },
37541/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
37542 {
37543 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
6772dd07 37544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37545 },
37546/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37547 {
37548 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
6772dd07 37549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37550 },
37551/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37552 {
37553 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 37554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37555 },
37556/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
37557 {
37558 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 37559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37560 },
37561/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
37562 {
37563 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 37564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37565 },
37566/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37567 {
37568 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 37569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37570 },
37571/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
37572 {
37573 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 37574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37575 },
37576/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
37577 {
37578 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 37579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37580 },
37581/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37582 {
37583 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
6772dd07 37584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37585 },
37586/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37587 {
37588 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
6772dd07 37589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37590 },
37591/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37592 {
37593 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
6772dd07 37594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37595 },
37596/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37597 {
37598 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37600 },
37601/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37602 {
37603 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37605 },
37606/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37607 {
37608 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37610 },
37611/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37612 {
37613 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37615 },
37616/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37617 {
37618 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37620 },
37621/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37622 {
37623 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37625 },
37626/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37627 {
37628 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37630 },
37631/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37632 {
37633 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37635 },
37636/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37637 {
37638 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37640 },
37641/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37642 {
37643 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37645 },
37646/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37647 {
37648 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37650 },
37651/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37652 {
37653 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37655 },
37656/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37657 {
37658 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37660 },
37661/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37662 {
37663 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37665 },
37666/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37667 {
37668 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37670 },
37671/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37672 {
37673 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37675 },
37676/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37677 {
37678 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37680 },
37681/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37682 {
37683 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 37684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37685 },
37686/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37687 {
37688 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37690 },
37691/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37692 {
37693 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37695 },
37696/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37697 {
37698 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37700 },
37701/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37702 {
37703 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
6772dd07 37704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37705 },
37706/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37707 {
37708 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
6772dd07 37709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37710 },
37711/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37712 {
37713 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
6772dd07 37714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37715 },
37716/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37717 {
37718 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 37719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37720 },
37721/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37722 {
37723 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 37724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37725 },
37726/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37727 {
37728 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 37729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37730 },
37731/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37732 {
37733 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37735 },
37736/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
37737 {
37738 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37740 },
37741/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
37742 {
37743 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37745 },
37746/* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
37747 {
37748 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37750 },
37751/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37752 {
37753 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37755 },
37756/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
37757 {
37758 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37760 },
37761/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
37762 {
37763 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37765 },
37766/* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
37767 {
37768 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
6772dd07 37769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37770 },
37771/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37772 {
37773 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
6772dd07 37774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37775 },
37776/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37777 {
37778 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
6772dd07 37779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37780 },
37781/* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37782 {
37783 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
6772dd07 37784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37785 },
37786/* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37787 {
37788 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
6772dd07 37789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37790 },
37791/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37792 {
37793 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37795 },
37796/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37797 {
37798 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37800 },
37801/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37802 {
37803 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37805 },
37806/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37807 {
37808 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37810 },
37811/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37812 {
37813 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37815 },
37816/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37817 {
37818 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37820 },
37821/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37822 {
37823 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37825 },
37826/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37827 {
37828 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37830 },
37831/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37832 {
37833 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 37834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37835 },
37836/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37837 {
37838 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 37839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37840 },
37841/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37842 {
37843 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 37844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37845 },
37846/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37847 {
37848 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 37849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37850 },
37851/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37852 {
37853 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37855 },
37856/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37857 {
37858 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37860 },
37861/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37862 {
37863 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37865 },
37866/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37867 {
37868 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37870 },
37871/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37872 {
37873 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37875 },
37876/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37877 {
37878 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37880 },
37881/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37882 {
37883 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37885 },
37886/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37887 {
37888 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37890 },
37891/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37892 {
37893 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37895 },
37896/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37897 {
37898 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37900 },
37901/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37902 {
37903 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37905 },
37906/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37907 {
37908 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 37909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37910 },
37911/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37912 {
37913 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37915 },
37916/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37917 {
37918 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37920 },
37921/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37922 {
37923 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37925 },
37926/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37927 {
37928 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 37929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37930 },
37931/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37932 {
37933 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 37934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37935 },
37936/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37937 {
37938 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 37939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37940 },
37941/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37942 {
37943 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 37944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37945 },
37946/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
37947 {
37948 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 37949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37950 },
37951/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37952 {
37953 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
6772dd07 37954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37955 },
37956/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37957 {
37958 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
6772dd07 37959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37960 },
37961/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37962 {
37963 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
6772dd07 37964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37965 },
37966/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
37967 {
37968 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
6772dd07 37969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37970 },
37971/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37972 {
37973 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
6772dd07 37974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37975 },
37976/* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
37977 {
37978 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
6772dd07 37979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37980 },
37981/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37982 {
37983 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
6772dd07 37984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37985 },
37986/* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
37987 {
37988 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
6772dd07 37989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37990 },
37991/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37992 {
37993 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
6772dd07 37994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 37995 },
37996/* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37997 {
37998 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
6772dd07 37999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38000 },
38001/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
38002 {
38003 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 38004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38005 },
38006/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
38007 {
38008 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 38009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38010 },
38011/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
38012 {
38013 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 38014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38015 },
38016/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
38017 {
38018 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 38019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38020 },
38021/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
38022 {
38023 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
6772dd07 38024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38025 },
38026/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
38027 {
38028 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
6772dd07 38029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38030 },
38031/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
38032 {
38033 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 38034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38035 },
38036/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
38037 {
38038 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 38039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38040 },
38041/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
38042 {
38043 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 38044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38045 },
38046/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
38047 {
38048 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 38049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38050 },
38051/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
38052 {
38053 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 38054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38055 },
38056/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
38057 {
38058 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 38059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38060 },
38061/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
38062 {
38063 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 38064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38065 },
38066/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
38067 {
38068 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
6772dd07 38069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38070 },
38071/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
38072 {
38073 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
6772dd07 38074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38075 },
38076/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
38077 {
38078 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
6772dd07 38079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38080 },
38081/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
38082 {
38083 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
6772dd07 38084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38085 },
38086/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
38087 {
38088 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
6772dd07 38089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38090 },
38091/* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
38092 {
38093 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
6772dd07 38094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38095 },
38096/* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
38097 {
38098 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
6772dd07 38099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38100 },
38101/* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38102 {
38103 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
6772dd07 38104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38105 },
38106/* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
38107 {
38108 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
6772dd07 38109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38110 },
38111/* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
38112 {
38113 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
6772dd07 38114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38115 },
38116/* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38117 {
38118 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
6772dd07 38119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38120 },
38121/* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
38122 {
38123 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
6772dd07 38124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38125 },
38126/* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
38127 {
38128 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
6772dd07 38129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38130 },
38131/* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38132 {
38133 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
6772dd07 38134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38135 },
38136/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38137 {
38138 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38140 },
38141/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38142 {
38143 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38145 },
38146/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
38147 {
38148 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38150 },
38151/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38152 {
38153 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38155 },
38156/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38157 {
38158 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38160 },
38161/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
38162 {
38163 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38165 },
38166/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38167 {
38168 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 38169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38170 },
38171/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38172 {
38173 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 38174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38175 },
38176/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38177 {
38178 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 38179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38180 },
38181/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
38182 {
38183 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38185 },
38186/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
38187 {
38188 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38190 },
38191/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38192 {
38193 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38195 },
38196/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
38197 {
38198 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38200 },
38201/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
38202 {
38203 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38205 },
38206/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38207 {
38208 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38210 },
38211/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
38212 {
38213 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38215 },
38216/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
38217 {
38218 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38220 },
38221/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38222 {
38223 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
6772dd07 38224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38225 },
38226/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
38227 {
38228 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38230 },
38231/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
38232 {
38233 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38235 },
38236/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38237 {
38238 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 38239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38240 },
38241/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
38242 {
38243 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
6772dd07 38244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38245 },
38246/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
38247 {
38248 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
6772dd07 38249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38250 },
38251/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38252 {
38253 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
6772dd07 38254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38255 },
38256/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
38257 {
38258 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
6772dd07 38259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38260 },
38261/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
38262 {
38263 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
6772dd07 38264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38265 },
38266/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38267 {
38268 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
6772dd07 38269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38270 },
38271/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
38272 {
38273 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
6772dd07 38274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38275 },
38276/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
38277 {
38278 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
6772dd07 38279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38280 },
38281/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
38282 {
38283 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
6772dd07 38284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38285 },
38286/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
38287 {
38288 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24,
6772dd07 38289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38290 },
38291/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
38292 {
38293 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
6772dd07 38294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38295 },
38296/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
38297 {
38298 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
6772dd07 38299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38300 },
38301/* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38302 {
38303 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
6772dd07 38304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38305 },
38306/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38307 {
38308 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
6772dd07 38309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38310 },
38311/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38312 {
38313 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
6772dd07 38314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38315 },
38316/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38317 {
38318 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
6772dd07 38319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38320 },
38321/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38322 {
38323 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
6772dd07 38324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38325 },
38326/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38327 {
38328 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
6772dd07 38329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38330 },
38331/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38332 {
38333 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
6772dd07 38334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38335 },
38336/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38337 {
38338 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
6772dd07 38339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38340 },
38341/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38342 {
38343 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
6772dd07 38344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38345 },
38346/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38347 {
38348 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
6772dd07 38349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38350 },
38351/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38352 {
38353 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
6772dd07 38354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38355 },
38356/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38357 {
38358 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
6772dd07 38359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38360 },
38361/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38362 {
38363 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
6772dd07 38364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38365 },
38366/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38367 {
38368 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
6772dd07 38369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38370 },
38371/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38372 {
38373 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
6772dd07 38374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38375 },
38376/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38377 {
38378 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
6772dd07 38379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38380 },
38381/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38382 {
38383 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
6772dd07 38384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38385 },
38386/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38387 {
38388 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
6772dd07 38389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38390 },
38391/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38392 {
38393 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
6772dd07 38394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38395 },
38396/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38397 {
38398 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
6772dd07 38399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38400 },
38401/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38402 {
38403 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
6772dd07 38404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38405 },
38406/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
38407 {
38408 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
6772dd07 38409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38410 },
38411/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
38412 {
38413 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
6772dd07 38414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38415 },
38416/* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
38417 {
38418 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32,
6772dd07 38419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38420 },
38421/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
38422 {
38423 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32,
6772dd07 38424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38425 },
38426/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
38427 {
38428 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32,
6772dd07 38429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38430 },
38431/* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
38432 {
38433 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32,
6772dd07 38434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38435 },
38436/* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38437 {
38438 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
6772dd07 38439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38440 },
38441/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38442 {
38443 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
6772dd07 38444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38445 },
38446/* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
38447 {
38448 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32,
6772dd07 38449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38450 },
38451/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38452 {
38453 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
6772dd07 38454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38455 },
38456/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38457 {
38458 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
6772dd07 38459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38460 },
38461/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38462 {
38463 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
6772dd07 38464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38465 },
38466/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38467 {
38468 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
6772dd07 38469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38470 },
38471/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38472 {
38473 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
6772dd07 38474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38475 },
38476/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38477 {
38478 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
6772dd07 38479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38480 },
38481/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38482 {
38483 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
6772dd07 38484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38485 },
38486/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38487 {
38488 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
6772dd07 38489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38490 },
38491/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38492 {
38493 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
6772dd07 38494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38495 },
38496/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38497 {
38498 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
6772dd07 38499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38500 },
38501/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38502 {
38503 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
6772dd07 38504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38505 },
38506/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38507 {
38508 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
6772dd07 38509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38510 },
38511/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38512 {
38513 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
6772dd07 38514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38515 },
38516/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38517 {
38518 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
6772dd07 38519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38520 },
38521/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38522 {
38523 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
6772dd07 38524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38525 },
38526/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38527 {
38528 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
6772dd07 38529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38530 },
38531/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38532 {
38533 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
6772dd07 38534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38535 },
38536/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
38537 {
38538 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48,
6772dd07 38539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38540 },
38541/* sub.w${G} $Src16RnHI,$Dst16RnHI */
38542 {
38543 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
6772dd07 38544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38545 },
38546/* sub.w${G} $Src16AnHI,$Dst16RnHI */
38547 {
38548 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
6772dd07 38549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38550 },
38551/* sub.w${G} [$Src16An],$Dst16RnHI */
38552 {
38553 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16,
6772dd07 38554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38555 },
38556/* sub.w${G} $Src16RnHI,$Dst16AnHI */
38557 {
38558 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16,
6772dd07 38559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38560 },
38561/* sub.w${G} $Src16AnHI,$Dst16AnHI */
38562 {
38563 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16,
6772dd07 38564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38565 },
38566/* sub.w${G} [$Src16An],$Dst16AnHI */
38567 {
38568 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16,
6772dd07 38569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38570 },
38571/* sub.w${G} $Src16RnHI,[$Dst16An] */
38572 {
38573 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
6772dd07 38574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38575 },
38576/* sub.w${G} $Src16AnHI,[$Dst16An] */
38577 {
38578 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
6772dd07 38579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38580 },
38581/* sub.w${G} [$Src16An],[$Dst16An] */
38582 {
38583 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16,
6772dd07 38584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38585 },
38586/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
38587 {
38588 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
6772dd07 38589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38590 },
38591/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
38592 {
38593 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
6772dd07 38594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38595 },
38596/* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38597 {
38598 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
6772dd07 38599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38600 },
38601/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
38602 {
38603 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
6772dd07 38604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38605 },
38606/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
38607 {
38608 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
6772dd07 38609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38610 },
38611/* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38612 {
38613 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
6772dd07 38614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38615 },
38616/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
38617 {
38618 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
6772dd07 38619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38620 },
38621/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
38622 {
38623 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
6772dd07 38624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38625 },
38626/* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
38627 {
38628 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
6772dd07 38629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38630 },
38631/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
38632 {
38633 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
6772dd07 38634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38635 },
38636/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
38637 {
38638 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
6772dd07 38639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38640 },
38641/* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
38642 {
38643 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
6772dd07 38644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38645 },
38646/* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
38647 {
38648 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
6772dd07 38649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38650 },
38651/* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
38652 {
38653 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
6772dd07 38654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38655 },
38656/* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
38657 {
38658 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
6772dd07 38659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38660 },
38661/* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
38662 {
38663 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
6772dd07 38664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38665 },
38666/* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
38667 {
38668 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
6772dd07 38669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38670 },
38671/* sub.w${G} [$Src16An],${Dsp-16-u16} */
38672 {
38673 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32,
6772dd07 38674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38675 },
38676/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
38677 {
38678 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
6772dd07 38679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38680 },
38681/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
38682 {
38683 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
6772dd07 38684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38685 },
38686/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
38687 {
38688 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
6772dd07 38689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38690 },
38691/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
38692 {
38693 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24,
6772dd07 38694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38695 },
38696/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
38697 {
38698 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
6772dd07 38699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38700 },
38701/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
38702 {
38703 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
6772dd07 38704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38705 },
38706/* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38707 {
38708 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
6772dd07 38709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38710 },
38711/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38712 {
38713 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
6772dd07 38714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38715 },
38716/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38717 {
38718 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
6772dd07 38719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38720 },
38721/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38722 {
38723 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
6772dd07 38724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38725 },
38726/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38727 {
38728 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
6772dd07 38729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38730 },
38731/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38732 {
38733 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
6772dd07 38734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38735 },
38736/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38737 {
38738 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
6772dd07 38739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38740 },
38741/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38742 {
38743 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
6772dd07 38744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38745 },
38746/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38747 {
38748 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
6772dd07 38749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38750 },
38751/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38752 {
38753 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
6772dd07 38754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38755 },
38756/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38757 {
38758 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
6772dd07 38759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38760 },
38761/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38762 {
38763 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
6772dd07 38764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38765 },
38766/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38767 {
38768 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
6772dd07 38769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38770 },
38771/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38772 {
38773 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
6772dd07 38774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38775 },
38776/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38777 {
38778 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
6772dd07 38779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38780 },
38781/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38782 {
38783 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
6772dd07 38784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38785 },
38786/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38787 {
38788 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
6772dd07 38789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38790 },
38791/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38792 {
38793 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
6772dd07 38794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38795 },
38796/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38797 {
38798 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
6772dd07 38799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38800 },
38801/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38802 {
38803 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
6772dd07 38804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38805 },
38806/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38807 {
38808 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
6772dd07 38809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38810 },
38811/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
38812 {
38813 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
6772dd07 38814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38815 },
38816/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
38817 {
38818 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
6772dd07 38819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38820 },
38821/* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
38822 {
38823 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32,
6772dd07 38824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38825 },
38826/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
38827 {
38828 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32,
6772dd07 38829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38830 },
38831/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
38832 {
38833 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32,
6772dd07 38834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38835 },
38836/* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
38837 {
38838 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32,
6772dd07 38839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38840 },
38841/* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38842 {
38843 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
6772dd07 38844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38845 },
38846/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38847 {
38848 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
6772dd07 38849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38850 },
38851/* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
38852 {
38853 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32,
6772dd07 38854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38855 },
38856/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38857 {
38858 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
6772dd07 38859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38860 },
38861/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38862 {
38863 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
6772dd07 38864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38865 },
38866/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38867 {
38868 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
6772dd07 38869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38870 },
38871/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38872 {
38873 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
6772dd07 38874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38875 },
38876/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38877 {
38878 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
6772dd07 38879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38880 },
38881/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38882 {
38883 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
6772dd07 38884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38885 },
38886/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38887 {
38888 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
6772dd07 38889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38890 },
38891/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38892 {
38893 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
6772dd07 38894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38895 },
38896/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38897 {
38898 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
6772dd07 38899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38900 },
38901/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38902 {
38903 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
6772dd07 38904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38905 },
38906/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38907 {
38908 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
6772dd07 38909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38910 },
38911/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38912 {
38913 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
6772dd07 38914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38915 },
38916/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38917 {
38918 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
6772dd07 38919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38920 },
38921/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38922 {
38923 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
6772dd07 38924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38925 },
38926/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38927 {
38928 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
6772dd07 38929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38930 },
38931/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38932 {
38933 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
6772dd07 38934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38935 },
38936/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38937 {
38938 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
6772dd07 38939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38940 },
38941/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38942 {
38943 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48,
6772dd07 38944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38945 },
38946/* sub.b${G} $Src16RnQI,$Dst16RnQI */
38947 {
38948 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
6772dd07 38949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38950 },
38951/* sub.b${G} $Src16AnQI,$Dst16RnQI */
38952 {
38953 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
6772dd07 38954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38955 },
38956/* sub.b${G} [$Src16An],$Dst16RnQI */
38957 {
38958 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16,
6772dd07 38959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38960 },
38961/* sub.b${G} $Src16RnQI,$Dst16AnQI */
38962 {
38963 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16,
6772dd07 38964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38965 },
38966/* sub.b${G} $Src16AnQI,$Dst16AnQI */
38967 {
38968 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16,
6772dd07 38969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38970 },
38971/* sub.b${G} [$Src16An],$Dst16AnQI */
38972 {
38973 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16,
6772dd07 38974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38975 },
38976/* sub.b${G} $Src16RnQI,[$Dst16An] */
38977 {
38978 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
6772dd07 38979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38980 },
38981/* sub.b${G} $Src16AnQI,[$Dst16An] */
38982 {
38983 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
6772dd07 38984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38985 },
38986/* sub.b${G} [$Src16An],[$Dst16An] */
38987 {
38988 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16,
6772dd07 38989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38990 },
38991/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
38992 {
38993 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
6772dd07 38994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 38995 },
38996/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
38997 {
38998 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
6772dd07 38999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39000 },
39001/* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
39002 {
39003 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
6772dd07 39004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39005 },
39006/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
39007 {
39008 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
6772dd07 39009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39010 },
39011/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
39012 {
39013 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
6772dd07 39014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39015 },
39016/* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
39017 {
39018 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
6772dd07 39019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39020 },
39021/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
39022 {
39023 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
6772dd07 39024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39025 },
39026/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
39027 {
39028 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
6772dd07 39029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39030 },
39031/* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
39032 {
39033 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
6772dd07 39034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39035 },
39036/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
39037 {
39038 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
6772dd07 39039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39040 },
39041/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
39042 {
39043 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
6772dd07 39044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39045 },
39046/* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
39047 {
39048 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
6772dd07 39049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39050 },
39051/* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
39052 {
39053 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
6772dd07 39054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39055 },
39056/* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
39057 {
39058 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
6772dd07 39059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39060 },
39061/* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
39062 {
39063 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
6772dd07 39064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39065 },
39066/* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
39067 {
39068 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
6772dd07 39069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39070 },
39071/* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
39072 {
39073 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
6772dd07 39074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39075 },
39076/* sub.b${G} [$Src16An],${Dsp-16-u16} */
39077 {
39078 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32,
6772dd07 39079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39080 },
39081/* sub.b${S} #${Imm-8-QI},r0l */
39082 {
39083 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16,
6772dd07 39084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 39085 },
39086/* sub.b${S} #${Imm-8-QI},r0h */
39087 {
39088 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16,
6772dd07 39089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 39090 },
39091/* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
39092 {
39093 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24,
6772dd07 39094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 39095 },
39096/* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
39097 {
39098 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24,
6772dd07 39099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 39100 },
39101/* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
39102 {
39103 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32,
6772dd07 39104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 39105 },
39106/* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
39107 {
39108 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 39109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39110 },
39111/* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
39112 {
39113 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
6772dd07 39114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39115 },
39116/* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
39117 {
39118 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
6772dd07 39119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39120 },
39121/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39122 {
39123 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 39124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39125 },
39126/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39127 {
39128 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 39129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39130 },
39131/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39132 {
39133 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40,
6772dd07 39134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39135 },
39136/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39137 {
39138 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 39139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39140 },
39141/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39142 {
39143 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 39144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39145 },
39146/* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
39147 {
39148 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48,
6772dd07 39149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39150 },
39151/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39152 {
39153 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48,
6772dd07 39154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39155 },
39156/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39157 {
39158 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56,
6772dd07 39159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39160 },
39161/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
39162 {
39163 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56,
6772dd07 39164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39165 },
39166/* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
39167 {
39168 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 39169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39170 },
39171/* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
39172 {
39173 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
6772dd07 39174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39175 },
39176/* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
39177 {
39178 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
6772dd07 39179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39180 },
39181/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39182 {
39183 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 39184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39185 },
39186/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39187 {
39188 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 39189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39190 },
39191/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39192 {
39193 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32,
6772dd07 39194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39195 },
39196/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39197 {
39198 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 39199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39200 },
39201/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39202 {
39203 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 39204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39205 },
39206/* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
39207 {
39208 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40,
6772dd07 39209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39210 },
39211/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39212 {
39213 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40,
6772dd07 39214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39215 },
39216/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39217 {
39218 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48,
6772dd07 39219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39220 },
39221/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
39222 {
39223 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48,
6772dd07 39224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39225 },
39226/* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
39227 {
39228 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32,
6772dd07 39229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39230 },
39231/* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
39232 {
39233 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32,
6772dd07 39234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39235 },
39236/* sub.w${G} #${Imm-16-HI},[$Dst16An] */
39237 {
39238 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32,
6772dd07 39239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39240 },
39241/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
39242 {
39243 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40,
6772dd07 39244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39245 },
39246/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39247 {
39248 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40,
6772dd07 39249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39250 },
39251/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39252 {
39253 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40,
6772dd07 39254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39255 },
39256/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
39257 {
39258 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48,
6772dd07 39259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39260 },
39261/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39262 {
39263 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48,
6772dd07 39264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39265 },
39266/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39267 {
39268 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48,
6772dd07 39269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39270 },
39271/* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
39272 {
39273 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24,
6772dd07 39274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39275 },
39276/* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
39277 {
39278 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24,
6772dd07 39279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39280 },
39281/* sub.b${G} #${Imm-16-QI},[$Dst16An] */
39282 {
39283 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24,
6772dd07 39284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39285 },
39286/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
39287 {
39288 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32,
6772dd07 39289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39290 },
39291/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39292 {
39293 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32,
6772dd07 39294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39295 },
39296/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39297 {
39298 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32,
6772dd07 39299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39300 },
39301/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
39302 {
39303 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40,
6772dd07 39304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39305 },
39306/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39307 {
39308 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40,
6772dd07 39309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39310 },
39311/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39312 {
39313 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40,
6772dd07 39314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 39315 },
39316/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39317 {
39318 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
6772dd07 39319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39320 },
39321/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
39322 {
39323 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
6772dd07 39324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39325 },
39326/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
39327 {
39328 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
6772dd07 39329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39330 },
39331/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39332 {
39333 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
6772dd07 39334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39335 },
39336/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
39337 {
39338 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
6772dd07 39339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39340 },
39341/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
39342 {
39343 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
6772dd07 39344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39345 },
39346/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39347 {
39348 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
6772dd07 39349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39350 },
39351/* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
39352 {
39353 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
6772dd07 39354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39355 },
39356/* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
39357 {
39358 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
6772dd07 39359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39360 },
39361/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
39362 {
39363 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39365 },
39366/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39367 {
39368 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39370 },
39371/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39372 {
39373 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39375 },
39376/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
39377 {
39378 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39380 },
39381/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39382 {
39383 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39385 },
39386/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39387 {
39388 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39390 },
39391/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
39392 {
39393 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39395 },
39396/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39397 {
39398 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39400 },
39401/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39402 {
39403 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39405 },
39406/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
39407 {
39408 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39410 },
39411/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
39412 {
39413 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39415 },
39416/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
39417 {
39418 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39420 },
39421/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
39422 {
39423 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39425 },
39426/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
39427 {
39428 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39430 },
39431/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
39432 {
39433 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39435 },
39436/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
39437 {
39438 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39440 },
39441/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
39442 {
39443 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39445 },
39446/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
39447 {
39448 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39450 },
39451/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
39452 {
39453 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39455 },
39456/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
39457 {
39458 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39460 },
39461/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
39462 {
39463 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39465 },
39466/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
39467 {
39468 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
6772dd07 39469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39470 },
39471/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
39472 {
39473 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
6772dd07 39474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39475 },
39476/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
39477 {
39478 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
6772dd07 39479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39480 },
39481/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
39482 {
39483 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 39484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39485 },
39486/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
39487 {
39488 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 39489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39490 },
39491/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
39492 {
39493 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 39494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39495 },
39496/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39497 {
39498 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39500 },
39501/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
39502 {
39503 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39505 },
39506/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
39507 {
39508 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39510 },
39511/* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
39512 {
39513 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39515 },
39516/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39517 {
39518 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39520 },
39521/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
39522 {
39523 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39525 },
39526/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
39527 {
39528 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39530 },
39531/* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
39532 {
39533 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 39534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39535 },
39536/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39537 {
39538 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
6772dd07 39539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39540 },
39541/* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
39542 {
39543 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
6772dd07 39544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39545 },
39546/* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
39547 {
39548 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
6772dd07 39549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39550 },
39551/* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
39552 {
39553 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
6772dd07 39554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39555 },
39556/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
39557 {
39558 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39560 },
39561/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39562 {
39563 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39565 },
39566/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39567 {
39568 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39570 },
39571/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
39572 {
39573 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39575 },
39576/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
39577 {
39578 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39580 },
39581/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39582 {
39583 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39585 },
39586/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39587 {
39588 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39590 },
39591/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
39592 {
39593 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39595 },
39596/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
39597 {
39598 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39600 },
39601/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39602 {
39603 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39605 },
39606/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39607 {
39608 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39610 },
39611/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
39612 {
39613 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39615 },
39616/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
39617 {
39618 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39620 },
39621/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
39622 {
39623 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39625 },
39626/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
39627 {
39628 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39630 },
39631/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
39632 {
39633 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39635 },
39636/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
39637 {
39638 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39640 },
39641/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
39642 {
39643 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39645 },
39646/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
39647 {
39648 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39650 },
39651/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
39652 {
39653 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39655 },
39656/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
39657 {
39658 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39660 },
39661/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
39662 {
39663 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39665 },
39666/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
39667 {
39668 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39670 },
39671/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
39672 {
39673 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39675 },
39676/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
39677 {
39678 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39680 },
39681/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
39682 {
39683 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39685 },
39686/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
39687 {
39688 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39690 },
39691/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
39692 {
39693 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39695 },
39696/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
39697 {
39698 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 39699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39700 },
39701/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
39702 {
39703 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 39704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39705 },
39706/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
39707 {
39708 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 39709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39710 },
39711/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
39712 {
39713 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 39714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39715 },
39716/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
39717 {
39718 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
6772dd07 39719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39720 },
39721/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
39722 {
39723 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
6772dd07 39724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39725 },
39726/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
39727 {
39728 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
6772dd07 39729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39730 },
39731/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
39732 {
39733 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
6772dd07 39734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39735 },
39736/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39737 {
39738 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
6772dd07 39739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39740 },
39741/* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
39742 {
39743 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
6772dd07 39744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39745 },
39746/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39747 {
39748 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
6772dd07 39749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39750 },
39751/* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
39752 {
39753 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
6772dd07 39754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39755 },
39756/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39757 {
39758 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
6772dd07 39759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39760 },
39761/* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
39762 {
39763 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
6772dd07 39764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39765 },
39766/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
39767 {
39768 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39770 },
39771/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
39772 {
39773 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39775 },
39776/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
39777 {
39778 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39780 },
39781/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
39782 {
39783 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39785 },
39786/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
39787 {
39788 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
6772dd07 39789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39790 },
39791/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
39792 {
39793 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
6772dd07 39794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39795 },
39796/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
39797 {
39798 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39800 },
39801/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
39802 {
39803 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39805 },
39806/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
39807 {
39808 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39810 },
39811/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
39812 {
39813 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39815 },
39816/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
39817 {
39818 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39820 },
39821/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
39822 {
39823 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 39824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39825 },
39826/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
39827 {
39828 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39830 },
39831/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
39832 {
39833 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 39834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39835 },
39836/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
39837 {
39838 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
6772dd07 39839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39840 },
39841/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
39842 {
39843 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
6772dd07 39844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39845 },
39846/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
39847 {
39848 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
6772dd07 39849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39850 },
39851/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
39852 {
39853 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
6772dd07 39854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39855 },
39856/* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
39857 {
39858 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
6772dd07 39859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39860 },
39861/* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
39862 {
39863 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
6772dd07 39864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39865 },
39866/* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
39867 {
39868 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
6772dd07 39869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39870 },
39871/* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
39872 {
39873 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
6772dd07 39874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39875 },
39876/* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
39877 {
39878 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
6772dd07 39879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39880 },
39881/* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
39882 {
39883 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
6772dd07 39884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39885 },
39886/* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
39887 {
39888 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
6772dd07 39889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39890 },
39891/* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
39892 {
39893 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
6772dd07 39894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39895 },
39896/* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
39897 {
39898 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
6772dd07 39899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39900 },
39901/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39902 {
39903 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39905 },
39906/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39907 {
39908 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39910 },
39911/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
39912 {
39913 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39915 },
39916/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39917 {
39918 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39920 },
39921/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39922 {
39923 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39925 },
39926/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
39927 {
39928 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39930 },
39931/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39932 {
39933 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39935 },
39936/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39937 {
39938 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39940 },
39941/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
39942 {
39943 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 39944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39945 },
39946/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
39947 {
39948 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39950 },
39951/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
39952 {
39953 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39955 },
39956/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
39957 {
39958 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39960 },
39961/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
39962 {
39963 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39965 },
39966/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
39967 {
39968 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39970 },
39971/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
39972 {
39973 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39975 },
39976/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
39977 {
39978 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39980 },
39981/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
39982 {
39983 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39985 },
39986/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
39987 {
39988 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
6772dd07 39989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39990 },
39991/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
39992 {
39993 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 39995 },
39996/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
39997 {
39998 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 39999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40000 },
40001/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
40002 {
40003 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
6772dd07 40004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40005 },
40006/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
40007 {
40008 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
6772dd07 40009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40010 },
40011/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
40012 {
40013 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
6772dd07 40014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40015 },
40016/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
40017 {
40018 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
6772dd07 40019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40020 },
40021/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
40022 {
40023 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
6772dd07 40024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40025 },
40026/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
40027 {
40028 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
6772dd07 40029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40030 },
40031/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40032 {
40033 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
6772dd07 40034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40035 },
40036/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40037 {
40038 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40040 },
40041/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
40042 {
40043 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40045 },
40046/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
40047 {
40048 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40050 },
40051/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40052 {
40053 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40055 },
40056/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
40057 {
40058 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40060 },
40061/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
40062 {
40063 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40065 },
40066/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40067 {
40068 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
6772dd07 40069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40070 },
40071/* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40072 {
40073 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
6772dd07 40074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40075 },
40076/* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40077 {
40078 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
6772dd07 40079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40080 },
40081/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40082 {
40083 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40085 },
40086/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40087 {
40088 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40090 },
40091/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40092 {
40093 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40095 },
40096/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40097 {
40098 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40100 },
40101/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40102 {
40103 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40105 },
40106/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40107 {
40108 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40110 },
40111/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40112 {
40113 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40115 },
40116/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40117 {
40118 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40120 },
40121/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40122 {
40123 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40125 },
40126/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40127 {
40128 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40130 },
40131/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40132 {
40133 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40135 },
40136/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40137 {
40138 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40140 },
40141/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40142 {
40143 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40145 },
40146/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40147 {
40148 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40150 },
40151/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40152 {
40153 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40155 },
40156/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40157 {
40158 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40160 },
40161/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40162 {
40163 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40165 },
40166/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40167 {
40168 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40170 },
40171/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40172 {
40173 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40175 },
40176/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40177 {
40178 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40180 },
40181/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40182 {
40183 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40185 },
40186/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40187 {
40188 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
6772dd07 40189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40190 },
40191/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
40192 {
40193 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
6772dd07 40194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40195 },
40196/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
40197 {
40198 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
6772dd07 40199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40200 },
40201/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
40202 {
40203 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40205 },
40206/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
40207 {
40208 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40210 },
40211/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
40212 {
40213 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40215 },
40216/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40217 {
40218 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40220 },
40221/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
40222 {
40223 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40225 },
40226/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
40227 {
40228 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40230 },
40231/* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
40232 {
40233 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40235 },
40236/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40237 {
40238 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40240 },
40241/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
40242 {
40243 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40245 },
40246/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
40247 {
40248 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40250 },
40251/* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
40252 {
40253 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
6772dd07 40254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40255 },
40256/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40257 {
40258 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
6772dd07 40259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40260 },
40261/* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
40262 {
40263 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
6772dd07 40264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40265 },
40266/* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
40267 {
40268 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
6772dd07 40269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40270 },
40271/* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
40272 {
40273 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
6772dd07 40274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40275 },
40276/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
40277 {
40278 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40280 },
40281/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40282 {
40283 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40285 },
40286/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40287 {
40288 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40290 },
40291/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
40292 {
40293 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40295 },
40296/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
40297 {
40298 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40300 },
40301/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40302 {
40303 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40305 },
40306/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40307 {
40308 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40310 },
40311/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
40312 {
40313 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40315 },
40316/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
40317 {
40318 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40320 },
40321/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40322 {
40323 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40325 },
40326/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40327 {
40328 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40330 },
40331/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
40332 {
40333 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40335 },
40336/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
40337 {
40338 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40340 },
40341/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
40342 {
40343 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40345 },
40346/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
40347 {
40348 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40350 },
40351/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
40352 {
40353 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40355 },
40356/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
40357 {
40358 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40360 },
40361/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
40362 {
40363 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40365 },
40366/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
40367 {
40368 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40370 },
40371/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
40372 {
40373 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40375 },
40376/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
40377 {
40378 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40380 },
40381/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
40382 {
40383 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40385 },
40386/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
40387 {
40388 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40390 },
40391/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
40392 {
40393 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40395 },
40396/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
40397 {
40398 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40400 },
40401/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
40402 {
40403 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40405 },
40406/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
40407 {
40408 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40410 },
40411/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
40412 {
40413 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40415 },
40416/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
40417 {
40418 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40420 },
40421/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
40422 {
40423 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40425 },
40426/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
40427 {
40428 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40430 },
40431/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
40432 {
40433 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40435 },
40436/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
40437 {
40438 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
6772dd07 40439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40440 },
40441/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
40442 {
40443 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
6772dd07 40444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40445 },
40446/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
40447 {
40448 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
6772dd07 40449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40450 },
40451/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
40452 {
40453 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
6772dd07 40454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40455 },
40456/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40457 {
40458 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
6772dd07 40459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40460 },
40461/* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
40462 {
40463 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
6772dd07 40464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40465 },
40466/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40467 {
40468 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
6772dd07 40469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40470 },
40471/* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
40472 {
40473 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
6772dd07 40474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40475 },
40476/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40477 {
40478 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
6772dd07 40479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40480 },
40481/* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
40482 {
40483 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
6772dd07 40484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40485 },
40486/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
40487 {
40488 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40490 },
40491/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
40492 {
40493 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40495 },
40496/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
40497 {
40498 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40500 },
40501/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
40502 {
40503 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40505 },
40506/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
40507 {
40508 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
6772dd07 40509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40510 },
40511/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
40512 {
40513 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
6772dd07 40514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40515 },
40516/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
40517 {
40518 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40520 },
40521/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
40522 {
40523 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40525 },
40526/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
40527 {
40528 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40530 },
40531/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
40532 {
40533 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40535 },
40536/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
40537 {
40538 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40540 },
40541/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
40542 {
40543 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40545 },
40546/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
40547 {
40548 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40550 },
40551/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
40552 {
40553 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
6772dd07 40554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40555 },
40556/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
40557 {
40558 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
6772dd07 40559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40560 },
40561/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
40562 {
40563 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
6772dd07 40564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40565 },
40566/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
40567 {
40568 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
6772dd07 40569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40570 },
40571/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
40572 {
40573 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
6772dd07 40574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40575 },
40576/* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
40577 {
40578 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
6772dd07 40579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40580 },
40581/* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
40582 {
40583 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
6772dd07 40584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40585 },
40586/* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
40587 {
40588 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
6772dd07 40589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40590 },
40591/* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
40592 {
40593 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
6772dd07 40594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40595 },
40596/* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
40597 {
40598 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
6772dd07 40599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40600 },
40601/* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
40602 {
40603 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
6772dd07 40604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40605 },
40606/* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
40607 {
40608 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
6772dd07 40609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40610 },
40611/* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
40612 {
40613 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
6772dd07 40614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40615 },
40616/* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
40617 {
40618 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
6772dd07 40619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40620 },
40621/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40622 {
40623 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40625 },
40626/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40627 {
40628 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40630 },
40631/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
40632 {
40633 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40635 },
40636/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40637 {
40638 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40640 },
40641/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40642 {
40643 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40645 },
40646/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
40647 {
40648 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40650 },
40651/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40652 {
40653 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40655 },
40656/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40657 {
40658 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40660 },
40661/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
40662 {
40663 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40665 },
40666/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
40667 {
40668 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40670 },
40671/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
40672 {
40673 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40675 },
40676/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
40677 {
40678 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40680 },
40681/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
40682 {
40683 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40685 },
40686/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
40687 {
40688 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40690 },
40691/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
40692 {
40693 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40695 },
40696/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
40697 {
40698 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40700 },
40701/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
40702 {
40703 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40705 },
40706/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
40707 {
40708 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
6772dd07 40709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40710 },
40711/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
40712 {
40713 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40715 },
40716/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
40717 {
40718 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40720 },
40721/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
40722 {
40723 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40725 },
40726/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
40727 {
40728 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
6772dd07 40729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40730 },
40731/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
40732 {
40733 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
6772dd07 40734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40735 },
40736/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
40737 {
40738 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
6772dd07 40739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40740 },
40741/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
40742 {
40743 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
6772dd07 40744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40745 },
40746/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
40747 {
40748 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
6772dd07 40749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40750 },
40751/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40752 {
40753 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
6772dd07 40754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40755 },
40756/* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
40757 {
40758 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 40759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40760 },
40761/* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
40762 {
40763 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
6772dd07 40764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40765 },
40766/* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
40767 {
40768 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
6772dd07 40769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40770 },
40771/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40772 {
40773 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 40774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40775 },
40776/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
40777 {
40778 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 40779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40780 },
40781/* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
40782 {
40783 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48,
6772dd07 40784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40785 },
40786/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40787 {
40788 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 40789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40790 },
40791/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
40792 {
40793 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 40794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40795 },
40796/* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
40797 {
40798 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56,
6772dd07 40799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40800 },
40801/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
40802 {
40803 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56,
6772dd07 40804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40805 },
40806/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40807 {
40808 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64,
6772dd07 40809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40810 },
40811/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
40812 {
40813 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64,
6772dd07 40814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40815 },
40816/* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
40817 {
40818 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40820 },
40821/* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
40822 {
40823 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
6772dd07 40824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40825 },
40826/* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
40827 {
40828 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
6772dd07 40829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40830 },
40831/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40832 {
40833 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40835 },
40836/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
40837 {
40838 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40840 },
40841/* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
40842 {
40843 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40,
6772dd07 40844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40845 },
40846/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40847 {
40848 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40850 },
40851/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
40852 {
40853 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40855 },
40856/* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
40857 {
40858 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48,
6772dd07 40859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40860 },
40861/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
40862 {
40863 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48,
6772dd07 40864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40865 },
40866/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40867 {
40868 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56,
6772dd07 40869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40870 },
40871/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
40872 {
40873 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56,
6772dd07 40874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 40875 },
40876/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40877 {
40878 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
6772dd07 40879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40880 },
40881/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
40882 {
40883 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
6772dd07 40884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40885 },
40886/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
40887 {
40888 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
6772dd07 40889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40890 },
40891/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40892 {
40893 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
6772dd07 40894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40895 },
40896/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
40897 {
40898 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
6772dd07 40899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40900 },
40901/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
40902 {
40903 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
6772dd07 40904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40905 },
40906/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40907 {
40908 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
6772dd07 40909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40910 },
40911/* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40912 {
40913 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
6772dd07 40914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40915 },
40916/* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40917 {
40918 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
6772dd07 40919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40920 },
40921/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40922 {
40923 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 40924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40925 },
40926/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40927 {
40928 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 40929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40930 },
40931/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40932 {
40933 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 40934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40935 },
40936/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40937 {
40938 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 40939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40940 },
40941/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40942 {
40943 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 40944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40945 },
40946/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40947 {
40948 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 40949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40950 },
40951/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40952 {
40953 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 40954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40955 },
40956/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40957 {
40958 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 40959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40960 },
40961/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40962 {
40963 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 40964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40965 },
40966/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40967 {
40968 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 40969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40970 },
40971/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40972 {
40973 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 40974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40975 },
40976/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40977 {
40978 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 40979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40980 },
40981/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40982 {
40983 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 40984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40985 },
40986/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40987 {
40988 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 40989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40990 },
40991/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40992 {
40993 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 40994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 40995 },
40996/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40997 {
40998 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 40999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41000 },
41001/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41002 {
41003 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41005 },
41006/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41007 {
41008 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41010 },
41011/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41012 {
41013 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41015 },
41016/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41017 {
41018 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41020 },
41021/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41022 {
41023 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41025 },
41026/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41027 {
41028 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
6772dd07 41029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41030 },
41031/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41032 {
41033 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
6772dd07 41034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41035 },
41036/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41037 {
41038 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
6772dd07 41039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41040 },
41041/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41042 {
41043 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 41044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41045 },
41046/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41047 {
41048 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 41049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41050 },
41051/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41052 {
41053 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 41054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41055 },
41056/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41057 {
41058 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41060 },
41061/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
41062 {
41063 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41065 },
41066/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
41067 {
41068 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41070 },
41071/* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
41072 {
41073 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41075 },
41076/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41077 {
41078 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41080 },
41081/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
41082 {
41083 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41085 },
41086/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
41087 {
41088 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41090 },
41091/* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
41092 {
41093 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 41094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41095 },
41096/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41097 {
41098 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
6772dd07 41099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41100 },
41101/* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41102 {
41103 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
6772dd07 41104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41105 },
41106/* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41107 {
41108 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
6772dd07 41109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41110 },
41111/* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41112 {
41113 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
6772dd07 41114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41115 },
41116/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41117 {
41118 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41120 },
41121/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41122 {
41123 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41125 },
41126/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41127 {
41128 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41130 },
41131/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41132 {
41133 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41135 },
41136/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41137 {
41138 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41140 },
41141/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41142 {
41143 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41145 },
41146/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41147 {
41148 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41150 },
41151/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41152 {
41153 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41155 },
41156/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41157 {
41158 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41160 },
41161/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41162 {
41163 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41165 },
41166/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41167 {
41168 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41170 },
41171/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41172 {
41173 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41175 },
41176/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41177 {
41178 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41180 },
41181/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41182 {
41183 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41185 },
41186/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41187 {
41188 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41190 },
41191/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41192 {
41193 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41195 },
41196/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41197 {
41198 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41200 },
41201/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41202 {
41203 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41205 },
41206/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41207 {
41208 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41210 },
41211/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41212 {
41213 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41215 },
41216/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41217 {
41218 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41220 },
41221/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41222 {
41223 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41225 },
41226/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41227 {
41228 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41230 },
41231/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41232 {
41233 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41235 },
41236/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41237 {
41238 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41240 },
41241/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41242 {
41243 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41245 },
41246/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41247 {
41248 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41250 },
41251/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41252 {
41253 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41255 },
41256/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41257 {
41258 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 41259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41260 },
41261/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41262 {
41263 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 41264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41265 },
41266/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41267 {
41268 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 41269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41270 },
41271/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
41272 {
41273 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 41274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41275 },
41276/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41277 {
41278 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
6772dd07 41279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41280 },
41281/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41282 {
41283 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
6772dd07 41284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41285 },
41286/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41287 {
41288 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
6772dd07 41289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41290 },
41291/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
41292 {
41293 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
6772dd07 41294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41295 },
41296/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41297 {
41298 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
6772dd07 41299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41300 },
41301/* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
41302 {
41303 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
6772dd07 41304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41305 },
41306/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41307 {
41308 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
6772dd07 41309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41310 },
41311/* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
41312 {
41313 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
6772dd07 41314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41315 },
41316/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41317 {
41318 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
6772dd07 41319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41320 },
41321/* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41322 {
41323 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
6772dd07 41324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41325 },
41326/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41327 {
41328 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41330 },
41331/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41332 {
41333 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41335 },
41336/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41337 {
41338 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41340 },
41341/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41342 {
41343 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41345 },
41346/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41347 {
41348 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
6772dd07 41349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41350 },
41351/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41352 {
41353 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
6772dd07 41354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41355 },
41356/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41357 {
41358 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41360 },
41361/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41362 {
41363 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41365 },
41366/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41367 {
41368 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41370 },
41371/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41372 {
41373 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41375 },
41376/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41377 {
41378 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41380 },
41381/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41382 {
41383 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 41384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41385 },
41386/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41387 {
41388 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41390 },
41391/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41392 {
41393 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 41394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41395 },
41396/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41397 {
41398 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
6772dd07 41399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41400 },
41401/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
41402 {
41403 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
6772dd07 41404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41405 },
41406/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41407 {
41408 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
6772dd07 41409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41410 },
41411/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
41412 {
41413 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
6772dd07 41414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41415 },
41416/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
41417 {
41418 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
6772dd07 41419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41420 },
41421/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41422 {
41423 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
6772dd07 41424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41425 },
41426/* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41427 {
41428 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
6772dd07 41429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41430 },
41431/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41432 {
41433 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
6772dd07 41434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41435 },
41436/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41437 {
41438 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
6772dd07 41439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41440 },
41441/* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41442 {
41443 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
6772dd07 41444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41445 },
41446/* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41447 {
41448 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
6772dd07 41449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41450 },
41451/* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41452 {
41453 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
6772dd07 41454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41455 },
41456/* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41457 {
41458 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
6772dd07 41459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41460 },
41461/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41462 {
41463 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41465 },
41466/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41467 {
41468 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41470 },
41471/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41472 {
41473 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41475 },
41476/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41477 {
41478 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41480 },
41481/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41482 {
41483 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41485 },
41486/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41487 {
41488 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41490 },
41491/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41492 {
41493 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41495 },
41496/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41497 {
41498 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41500 },
41501/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41502 {
41503 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 41504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41505 },
41506/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41507 {
41508 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41510 },
41511/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41512 {
41513 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41515 },
41516/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41517 {
41518 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41520 },
41521/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41522 {
41523 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41525 },
41526/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41527 {
41528 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41530 },
41531/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41532 {
41533 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41535 },
41536/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41537 {
41538 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41540 },
41541/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41542 {
41543 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41545 },
41546/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41547 {
41548 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
6772dd07 41549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41550 },
41551/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41552 {
41553 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41555 },
41556/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41557 {
41558 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41560 },
41561/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41562 {
41563 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
6772dd07 41564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41565 },
41566/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41567 {
41568 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
6772dd07 41569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41570 },
41571/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41572 {
41573 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
6772dd07 41574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41575 },
41576/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41577 {
41578 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
6772dd07 41579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41580 },
41581/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41582 {
41583 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
6772dd07 41584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41585 },
41586/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41587 {
41588 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
6772dd07 41589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41590 },
41591/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41592 {
41593 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
6772dd07 41594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41595 },
41596/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41597 {
41598 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 41599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41600 },
41601/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41602 {
41603 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 41604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41605 },
41606/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41607 {
41608 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 41609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41610 },
41611/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41612 {
41613 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 41614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41615 },
41616/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41617 {
41618 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 41619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41620 },
41621/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41622 {
41623 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 41624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41625 },
41626/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41627 {
41628 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
6772dd07 41629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41630 },
41631/* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41632 {
41633 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
6772dd07 41634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41635 },
41636/* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41637 {
41638 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
6772dd07 41639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41640 },
41641/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41642 {
41643 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41645 },
41646/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41647 {
41648 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41650 },
41651/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41652 {
41653 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41655 },
41656/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41657 {
41658 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41660 },
41661/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41662 {
41663 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41665 },
41666/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41667 {
41668 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41670 },
41671/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41672 {
41673 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41675 },
41676/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41677 {
41678 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41680 },
41681/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41682 {
41683 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41685 },
41686/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41687 {
41688 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41690 },
41691/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41692 {
41693 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41695 },
41696/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41697 {
41698 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41700 },
41701/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41702 {
41703 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41705 },
41706/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41707 {
41708 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41710 },
41711/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41712 {
41713 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41715 },
41716/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41717 {
41718 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41720 },
41721/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41722 {
41723 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41725 },
41726/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41727 {
41728 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 41729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41730 },
41731/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41732 {
41733 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41735 },
41736/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41737 {
41738 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41740 },
41741/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41742 {
41743 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41745 },
41746/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41747 {
41748 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
6772dd07 41749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41750 },
41751/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41752 {
41753 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
6772dd07 41754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41755 },
41756/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41757 {
41758 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
6772dd07 41759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41760 },
41761/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41762 {
41763 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 41764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41765 },
41766/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41767 {
41768 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 41769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41770 },
41771/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41772 {
41773 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 41774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41775 },
41776/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41777 {
41778 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41780 },
41781/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
41782 {
41783 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41785 },
41786/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
41787 {
41788 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41790 },
41791/* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
41792 {
41793 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41795 },
41796/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41797 {
41798 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41800 },
41801/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
41802 {
41803 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41805 },
41806/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
41807 {
41808 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41810 },
41811/* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
41812 {
41813 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
6772dd07 41814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41815 },
41816/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41817 {
41818 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
6772dd07 41819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41820 },
41821/* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41822 {
41823 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
6772dd07 41824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41825 },
41826/* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41827 {
41828 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
6772dd07 41829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41830 },
41831/* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41832 {
41833 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
6772dd07 41834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41835 },
41836/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41837 {
41838 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41840 },
41841/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41842 {
41843 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41845 },
41846/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41847 {
41848 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41850 },
41851/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41852 {
41853 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41855 },
41856/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41857 {
41858 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41860 },
41861/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41862 {
41863 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41865 },
41866/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41867 {
41868 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41870 },
41871/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41872 {
41873 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41875 },
41876/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41877 {
41878 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 41879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41880 },
41881/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41882 {
41883 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 41884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41885 },
41886/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41887 {
41888 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 41889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41890 },
41891/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41892 {
41893 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 41894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41895 },
41896/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41897 {
41898 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41900 },
41901/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41902 {
41903 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41905 },
41906/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41907 {
41908 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41910 },
41911/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41912 {
41913 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41915 },
41916/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41917 {
41918 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41920 },
41921/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41922 {
41923 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41925 },
41926/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41927 {
41928 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41930 },
41931/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41932 {
41933 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41935 },
41936/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41937 {
41938 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41940 },
41941/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41942 {
41943 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41945 },
41946/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41947 {
41948 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41950 },
41951/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41952 {
41953 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 41954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41955 },
41956/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41957 {
41958 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41960 },
41961/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41962 {
41963 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41965 },
41966/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41967 {
41968 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41970 },
41971/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41972 {
41973 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 41974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41975 },
41976/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41977 {
41978 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 41979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41980 },
41981/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41982 {
41983 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 41984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41985 },
41986/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41987 {
41988 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 41989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41990 },
41991/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
41992 {
41993 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 41994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 41995 },
41996/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41997 {
41998 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
6772dd07 41999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42000 },
42001/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
42002 {
42003 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
6772dd07 42004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42005 },
42006/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
42007 {
42008 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
6772dd07 42009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42010 },
42011/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
42012 {
42013 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
6772dd07 42014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42015 },
42016/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
42017 {
42018 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
6772dd07 42019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42020 },
42021/* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
42022 {
42023 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
6772dd07 42024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42025 },
42026/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
42027 {
42028 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
6772dd07 42029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42030 },
42031/* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
42032 {
42033 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
6772dd07 42034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42035 },
42036/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42037 {
42038 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
6772dd07 42039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42040 },
42041/* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
42042 {
42043 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
6772dd07 42044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42045 },
42046/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
42047 {
42048 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 42049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42050 },
42051/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
42052 {
42053 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 42054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42055 },
42056/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
42057 {
42058 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 42059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42060 },
42061/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
42062 {
42063 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 42064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42065 },
42066/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
42067 {
42068 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
6772dd07 42069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42070 },
42071/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
42072 {
42073 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
6772dd07 42074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42075 },
42076/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
42077 {
42078 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 42079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42080 },
42081/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
42082 {
42083 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 42084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42085 },
42086/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
42087 {
42088 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 42089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42090 },
42091/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
42092 {
42093 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 42094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42095 },
42096/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
42097 {
42098 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 42099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42100 },
42101/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
42102 {
42103 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 42104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42105 },
42106/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
42107 {
42108 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 42109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42110 },
42111/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
42112 {
42113 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
6772dd07 42114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42115 },
42116/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
42117 {
42118 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
6772dd07 42119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42120 },
42121/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
42122 {
42123 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
6772dd07 42124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42125 },
42126/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
42127 {
42128 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
6772dd07 42129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42130 },
42131/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
42132 {
42133 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
6772dd07 42134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42135 },
42136/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
42137 {
42138 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
6772dd07 42139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42140 },
42141/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
42142 {
42143 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
6772dd07 42144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42145 },
42146/* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
42147 {
42148 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
6772dd07 42149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42150 },
42151/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
42152 {
42153 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
6772dd07 42154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42155 },
42156/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
42157 {
42158 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
6772dd07 42159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42160 },
42161/* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
42162 {
42163 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
6772dd07 42164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42165 },
42166/* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
42167 {
42168 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
6772dd07 42169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42170 },
42171/* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
42172 {
42173 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
6772dd07 42174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42175 },
42176/* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
42177 {
42178 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
6772dd07 42179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42180 },
42181/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42182 {
42183 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42185 },
42186/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42187 {
42188 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42190 },
42191/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
42192 {
42193 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42195 },
42196/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42197 {
42198 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42200 },
42201/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42202 {
42203 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42205 },
42206/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
42207 {
42208 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42210 },
42211/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42212 {
42213 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 42214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42215 },
42216/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42217 {
42218 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 42219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42220 },
42221/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
42222 {
42223 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 42224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42225 },
42226/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
42227 {
42228 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42230 },
42231/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
42232 {
42233 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42235 },
42236/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
42237 {
42238 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42240 },
42241/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
42242 {
42243 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42245 },
42246/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
42247 {
42248 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42250 },
42251/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
42252 {
42253 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42255 },
42256/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
42257 {
42258 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42260 },
42261/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
42262 {
42263 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42265 },
42266/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
42267 {
42268 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
6772dd07 42269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42270 },
42271/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
42272 {
42273 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42275 },
42276/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
42277 {
42278 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42280 },
42281/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
42282 {
42283 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42285 },
42286/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
42287 {
42288 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
6772dd07 42289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42290 },
42291/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
42292 {
42293 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
6772dd07 42294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42295 },
42296/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
42297 {
42298 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
6772dd07 42299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42300 },
42301/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
42302 {
42303 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
6772dd07 42304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42305 },
42306/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
42307 {
42308 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
6772dd07 42309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42310 },
42311/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
42312 {
42313 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
6772dd07 42314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 42315 },
42316/* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
42317 {
42318 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 42319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42320 },
42321/* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
42322 {
42323 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
6772dd07 42324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42325 },
42326/* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
42327 {
42328 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
6772dd07 42329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42330 },
42331/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42332 {
42333 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 42334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42335 },
42336/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
42337 {
42338 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 42339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42340 },
42341/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
42342 {
42343 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
6772dd07 42344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42345 },
42346/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42347 {
42348 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 42349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42350 },
42351/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
42352 {
42353 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 42354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42355 },
42356/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
42357 {
42358 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
6772dd07 42359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42360 },
42361/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
42362 {
42363 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56,
6772dd07 42364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42365 },
42366/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42367 {
42368 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64,
6772dd07 42369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42370 },
42371/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
42372 {
42373 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64,
6772dd07 42374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42375 },
42376/* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
42377 {
42378 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 42379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42380 },
42381/* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
42382 {
42383 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
6772dd07 42384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42385 },
42386/* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
42387 {
42388 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
6772dd07 42389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42390 },
42391/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42392 {
42393 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42395 },
42396/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
42397 {
42398 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42400 },
42401/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
42402 {
42403 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
6772dd07 42404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42405 },
42406/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42407 {
42408 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 42409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42410 },
42411/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
42412 {
42413 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 42414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42415 },
42416/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
42417 {
42418 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
6772dd07 42419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42420 },
42421/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42422 {
42423 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48,
6772dd07 42424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42425 },
42426/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42427 {
42428 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56,
6772dd07 42429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42430 },
42431/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42432 {
42433 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56,
6772dd07 42434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 42435 },
42436/* divx.l $Dst32RnPrefixedSI */
42437 {
42438 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24,
6772dd07 42439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42440 },
42441/* divx.l $Dst32AnPrefixedSI */
42442 {
42443 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24,
6772dd07 42444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42445 },
42446/* divx.l [$Dst32AnPrefixed] */
42447 {
42448 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24,
6772dd07 42449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42450 },
42451/* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42452 {
42453 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32,
6772dd07 42454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42455 },
42456/* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42457 {
42458 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40,
6772dd07 42459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42460 },
42461/* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42462 {
42463 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48,
6772dd07 42464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42465 },
42466/* divx.l ${Dsp-24-u8}[sb] */
42467 {
42468 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32,
6772dd07 42469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42470 },
42471/* divx.l ${Dsp-24-u16}[sb] */
42472 {
42473 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40,
6772dd07 42474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42475 },
42476/* divx.l ${Dsp-24-s8}[fb] */
42477 {
42478 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32,
6772dd07 42479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42480 },
42481/* divx.l ${Dsp-24-s16}[fb] */
42482 {
42483 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40,
6772dd07 42484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42485 },
42486/* divx.l ${Dsp-24-u16} */
42487 {
42488 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40,
6772dd07 42489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42490 },
42491/* divx.l ${Dsp-24-u24} */
42492 {
42493 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48,
6772dd07 42494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42495 },
42496/* divu.l $Dst32RnPrefixedSI */
42497 {
42498 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24,
6772dd07 42499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42500 },
42501/* divu.l $Dst32AnPrefixedSI */
42502 {
42503 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24,
6772dd07 42504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42505 },
42506/* divu.l [$Dst32AnPrefixed] */
42507 {
42508 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24,
6772dd07 42509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42510 },
42511/* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42512 {
42513 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32,
6772dd07 42514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42515 },
42516/* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42517 {
42518 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40,
6772dd07 42519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42520 },
42521/* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42522 {
42523 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48,
6772dd07 42524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42525 },
42526/* divu.l ${Dsp-24-u8}[sb] */
42527 {
42528 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32,
6772dd07 42529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42530 },
42531/* divu.l ${Dsp-24-u16}[sb] */
42532 {
42533 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40,
6772dd07 42534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42535 },
42536/* divu.l ${Dsp-24-s8}[fb] */
42537 {
42538 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32,
6772dd07 42539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42540 },
42541/* divu.l ${Dsp-24-s16}[fb] */
42542 {
42543 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40,
6772dd07 42544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42545 },
42546/* divu.l ${Dsp-24-u16} */
42547 {
42548 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40,
6772dd07 42549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42550 },
42551/* divu.l ${Dsp-24-u24} */
42552 {
42553 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48,
6772dd07 42554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42555 },
42556/* div.l $Dst32RnPrefixedSI */
42557 {
42558 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24,
6772dd07 42559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42560 },
42561/* div.l $Dst32AnPrefixedSI */
42562 {
42563 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24,
6772dd07 42564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42565 },
42566/* div.l [$Dst32AnPrefixed] */
42567 {
42568 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24,
6772dd07 42569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42570 },
42571/* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42572 {
42573 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32,
6772dd07 42574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42575 },
42576/* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42577 {
42578 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40,
6772dd07 42579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42580 },
42581/* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42582 {
42583 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48,
6772dd07 42584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42585 },
42586/* div.l ${Dsp-24-u8}[sb] */
42587 {
42588 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32,
6772dd07 42589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42590 },
42591/* div.l ${Dsp-24-u16}[sb] */
42592 {
42593 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40,
6772dd07 42594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42595 },
42596/* div.l ${Dsp-24-s8}[fb] */
42597 {
42598 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32,
6772dd07 42599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42600 },
42601/* div.l ${Dsp-24-s16}[fb] */
42602 {
42603 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40,
6772dd07 42604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42605 },
42606/* div.l ${Dsp-24-u16} */
42607 {
42608 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40,
6772dd07 42609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42610 },
42611/* div.l ${Dsp-24-u24} */
42612 {
42613 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48,
6772dd07 42614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42615 },
42616/* divx.w $Dst32RnUnprefixedHI */
42617 {
42618 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16,
6772dd07 42619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42620 },
42621/* divx.w $Dst32AnUnprefixedHI */
42622 {
42623 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16,
6772dd07 42624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42625 },
42626/* divx.w [$Dst32AnUnprefixed] */
42627 {
42628 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16,
6772dd07 42629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42630 },
42631/* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42632 {
42633 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24,
6772dd07 42634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42635 },
42636/* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42637 {
42638 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32,
6772dd07 42639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42640 },
42641/* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42642 {
42643 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40,
6772dd07 42644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42645 },
42646/* divx.w ${Dsp-16-u8}[sb] */
42647 {
42648 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24,
6772dd07 42649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42650 },
42651/* divx.w ${Dsp-16-u16}[sb] */
42652 {
42653 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32,
6772dd07 42654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42655 },
42656/* divx.w ${Dsp-16-s8}[fb] */
42657 {
42658 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24,
6772dd07 42659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42660 },
42661/* divx.w ${Dsp-16-s16}[fb] */
42662 {
42663 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32,
6772dd07 42664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42665 },
42666/* divx.w ${Dsp-16-u16} */
42667 {
42668 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32,
6772dd07 42669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42670 },
42671/* divx.w ${Dsp-16-u24} */
42672 {
42673 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40,
6772dd07 42674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42675 },
42676/* divx.b $Dst32RnUnprefixedQI */
42677 {
42678 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16,
6772dd07 42679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42680 },
42681/* divx.b $Dst32AnUnprefixedQI */
42682 {
42683 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16,
6772dd07 42684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42685 },
42686/* divx.b [$Dst32AnUnprefixed] */
42687 {
42688 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16,
6772dd07 42689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42690 },
42691/* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42692 {
42693 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24,
6772dd07 42694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42695 },
42696/* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42697 {
42698 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32,
6772dd07 42699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42700 },
42701/* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42702 {
42703 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40,
6772dd07 42704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42705 },
42706/* divx.b ${Dsp-16-u8}[sb] */
42707 {
42708 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24,
6772dd07 42709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42710 },
42711/* divx.b ${Dsp-16-u16}[sb] */
42712 {
42713 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32,
6772dd07 42714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42715 },
42716/* divx.b ${Dsp-16-s8}[fb] */
42717 {
42718 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24,
6772dd07 42719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42720 },
42721/* divx.b ${Dsp-16-s16}[fb] */
42722 {
42723 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32,
6772dd07 42724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42725 },
42726/* divx.b ${Dsp-16-u16} */
42727 {
42728 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32,
6772dd07 42729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42730 },
42731/* divx.b ${Dsp-16-u24} */
42732 {
42733 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40,
6772dd07 42734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42735 },
42736/* divx.w $Dst16RnHI */
42737 {
42738 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16,
6772dd07 42739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42740 },
42741/* divx.w $Dst16AnHI */
42742 {
42743 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16,
6772dd07 42744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42745 },
42746/* divx.w [$Dst16An] */
42747 {
42748 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16,
6772dd07 42749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42750 },
42751/* divx.w ${Dsp-16-u8}[$Dst16An] */
42752 {
42753 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24,
6772dd07 42754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42755 },
42756/* divx.w ${Dsp-16-u16}[$Dst16An] */
42757 {
42758 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32,
6772dd07 42759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42760 },
42761/* divx.w ${Dsp-16-u8}[sb] */
42762 {
42763 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24,
6772dd07 42764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42765 },
42766/* divx.w ${Dsp-16-u16}[sb] */
42767 {
42768 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32,
6772dd07 42769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42770 },
42771/* divx.w ${Dsp-16-s8}[fb] */
42772 {
42773 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24,
6772dd07 42774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42775 },
42776/* divx.w ${Dsp-16-u16} */
42777 {
42778 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32,
6772dd07 42779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42780 },
42781/* divx.b $Dst16RnQI */
42782 {
42783 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16,
6772dd07 42784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42785 },
42786/* divx.b $Dst16AnQI */
42787 {
42788 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16,
6772dd07 42789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42790 },
42791/* divx.b [$Dst16An] */
42792 {
42793 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16,
6772dd07 42794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42795 },
42796/* divx.b ${Dsp-16-u8}[$Dst16An] */
42797 {
42798 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24,
6772dd07 42799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42800 },
42801/* divx.b ${Dsp-16-u16}[$Dst16An] */
42802 {
42803 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32,
6772dd07 42804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42805 },
42806/* divx.b ${Dsp-16-u8}[sb] */
42807 {
42808 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24,
6772dd07 42809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42810 },
42811/* divx.b ${Dsp-16-u16}[sb] */
42812 {
42813 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32,
6772dd07 42814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42815 },
42816/* divx.b ${Dsp-16-s8}[fb] */
42817 {
42818 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24,
6772dd07 42819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42820 },
42821/* divx.b ${Dsp-16-u16} */
42822 {
42823 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32,
6772dd07 42824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42825 },
42826/* divu.w $Dst32RnUnprefixedHI */
42827 {
42828 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16,
6772dd07 42829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42830 },
42831/* divu.w $Dst32AnUnprefixedHI */
42832 {
42833 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16,
6772dd07 42834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42835 },
42836/* divu.w [$Dst32AnUnprefixed] */
42837 {
42838 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16,
6772dd07 42839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42840 },
42841/* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42842 {
42843 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24,
6772dd07 42844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42845 },
42846/* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42847 {
42848 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32,
6772dd07 42849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42850 },
42851/* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42852 {
42853 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40,
6772dd07 42854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42855 },
42856/* divu.w ${Dsp-16-u8}[sb] */
42857 {
42858 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24,
6772dd07 42859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42860 },
42861/* divu.w ${Dsp-16-u16}[sb] */
42862 {
42863 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32,
6772dd07 42864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42865 },
42866/* divu.w ${Dsp-16-s8}[fb] */
42867 {
42868 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24,
6772dd07 42869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42870 },
42871/* divu.w ${Dsp-16-s16}[fb] */
42872 {
42873 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32,
6772dd07 42874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42875 },
42876/* divu.w ${Dsp-16-u16} */
42877 {
42878 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32,
6772dd07 42879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42880 },
42881/* divu.w ${Dsp-16-u24} */
42882 {
42883 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40,
6772dd07 42884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42885 },
42886/* divu.b $Dst32RnUnprefixedQI */
42887 {
42888 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16,
6772dd07 42889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42890 },
42891/* divu.b $Dst32AnUnprefixedQI */
42892 {
42893 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16,
6772dd07 42894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42895 },
42896/* divu.b [$Dst32AnUnprefixed] */
42897 {
42898 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16,
6772dd07 42899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42900 },
42901/* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42902 {
42903 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24,
6772dd07 42904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42905 },
42906/* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42907 {
42908 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32,
6772dd07 42909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42910 },
42911/* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42912 {
42913 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40,
6772dd07 42914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42915 },
42916/* divu.b ${Dsp-16-u8}[sb] */
42917 {
42918 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24,
6772dd07 42919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42920 },
42921/* divu.b ${Dsp-16-u16}[sb] */
42922 {
42923 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32,
6772dd07 42924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42925 },
42926/* divu.b ${Dsp-16-s8}[fb] */
42927 {
42928 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24,
6772dd07 42929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42930 },
42931/* divu.b ${Dsp-16-s16}[fb] */
42932 {
42933 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32,
6772dd07 42934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42935 },
42936/* divu.b ${Dsp-16-u16} */
42937 {
42938 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32,
6772dd07 42939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42940 },
42941/* divu.b ${Dsp-16-u24} */
42942 {
42943 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40,
6772dd07 42944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42945 },
42946/* divu.w $Dst16RnHI */
42947 {
42948 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16,
6772dd07 42949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42950 },
42951/* divu.w $Dst16AnHI */
42952 {
42953 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16,
6772dd07 42954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42955 },
42956/* divu.w [$Dst16An] */
42957 {
42958 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16,
6772dd07 42959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42960 },
42961/* divu.w ${Dsp-16-u8}[$Dst16An] */
42962 {
42963 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24,
6772dd07 42964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42965 },
42966/* divu.w ${Dsp-16-u16}[$Dst16An] */
42967 {
42968 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32,
6772dd07 42969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42970 },
42971/* divu.w ${Dsp-16-u8}[sb] */
42972 {
42973 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24,
6772dd07 42974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42975 },
42976/* divu.w ${Dsp-16-u16}[sb] */
42977 {
42978 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32,
6772dd07 42979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42980 },
42981/* divu.w ${Dsp-16-s8}[fb] */
42982 {
42983 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24,
6772dd07 42984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42985 },
42986/* divu.w ${Dsp-16-u16} */
42987 {
42988 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32,
6772dd07 42989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42990 },
42991/* divu.b $Dst16RnQI */
42992 {
42993 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16,
6772dd07 42994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 42995 },
42996/* divu.b $Dst16AnQI */
42997 {
42998 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16,
6772dd07 42999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43000 },
43001/* divu.b [$Dst16An] */
43002 {
43003 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16,
6772dd07 43004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43005 },
43006/* divu.b ${Dsp-16-u8}[$Dst16An] */
43007 {
43008 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24,
6772dd07 43009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43010 },
43011/* divu.b ${Dsp-16-u16}[$Dst16An] */
43012 {
43013 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32,
6772dd07 43014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43015 },
43016/* divu.b ${Dsp-16-u8}[sb] */
43017 {
43018 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24,
6772dd07 43019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43020 },
43021/* divu.b ${Dsp-16-u16}[sb] */
43022 {
43023 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32,
6772dd07 43024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43025 },
43026/* divu.b ${Dsp-16-s8}[fb] */
43027 {
43028 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24,
6772dd07 43029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43030 },
43031/* divu.b ${Dsp-16-u16} */
43032 {
43033 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32,
6772dd07 43034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43035 },
43036/* div.w $Dst32RnUnprefixedHI */
43037 {
43038 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16,
6772dd07 43039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43040 },
43041/* div.w $Dst32AnUnprefixedHI */
43042 {
43043 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16,
6772dd07 43044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43045 },
43046/* div.w [$Dst32AnUnprefixed] */
43047 {
43048 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16,
6772dd07 43049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43050 },
43051/* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43052 {
43053 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24,
6772dd07 43054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43055 },
43056/* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43057 {
43058 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32,
6772dd07 43059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43060 },
43061/* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43062 {
43063 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40,
6772dd07 43064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43065 },
43066/* div.w ${Dsp-16-u8}[sb] */
43067 {
43068 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24,
6772dd07 43069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43070 },
43071/* div.w ${Dsp-16-u16}[sb] */
43072 {
43073 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32,
6772dd07 43074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43075 },
43076/* div.w ${Dsp-16-s8}[fb] */
43077 {
43078 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24,
6772dd07 43079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43080 },
43081/* div.w ${Dsp-16-s16}[fb] */
43082 {
43083 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32,
6772dd07 43084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43085 },
43086/* div.w ${Dsp-16-u16} */
43087 {
43088 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32,
6772dd07 43089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43090 },
43091/* div.w ${Dsp-16-u24} */
43092 {
43093 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40,
6772dd07 43094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43095 },
43096/* div.b $Dst32RnUnprefixedQI */
43097 {
43098 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16,
6772dd07 43099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43100 },
43101/* div.b $Dst32AnUnprefixedQI */
43102 {
43103 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16,
6772dd07 43104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43105 },
43106/* div.b [$Dst32AnUnprefixed] */
43107 {
43108 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16,
6772dd07 43109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43110 },
43111/* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43112 {
43113 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24,
6772dd07 43114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43115 },
43116/* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43117 {
43118 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32,
6772dd07 43119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43120 },
43121/* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43122 {
43123 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40,
6772dd07 43124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43125 },
43126/* div.b ${Dsp-16-u8}[sb] */
43127 {
43128 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24,
6772dd07 43129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43130 },
43131/* div.b ${Dsp-16-u16}[sb] */
43132 {
43133 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32,
6772dd07 43134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43135 },
43136/* div.b ${Dsp-16-s8}[fb] */
43137 {
43138 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24,
6772dd07 43139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43140 },
43141/* div.b ${Dsp-16-s16}[fb] */
43142 {
43143 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32,
6772dd07 43144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43145 },
43146/* div.b ${Dsp-16-u16} */
43147 {
43148 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32,
6772dd07 43149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43150 },
43151/* div.b ${Dsp-16-u24} */
43152 {
43153 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40,
6772dd07 43154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43155 },
43156/* div.w $Dst16RnHI */
43157 {
43158 M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16,
6772dd07 43159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43160 },
43161/* div.w $Dst16AnHI */
43162 {
43163 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16,
6772dd07 43164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43165 },
43166/* div.w [$Dst16An] */
43167 {
43168 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16,
6772dd07 43169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43170 },
43171/* div.w ${Dsp-16-u8}[$Dst16An] */
43172 {
43173 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24,
6772dd07 43174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43175 },
43176/* div.w ${Dsp-16-u16}[$Dst16An] */
43177 {
43178 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32,
6772dd07 43179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43180 },
43181/* div.w ${Dsp-16-u8}[sb] */
43182 {
43183 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24,
6772dd07 43184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43185 },
43186/* div.w ${Dsp-16-u16}[sb] */
43187 {
43188 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32,
6772dd07 43189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43190 },
43191/* div.w ${Dsp-16-s8}[fb] */
43192 {
43193 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24,
6772dd07 43194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43195 },
43196/* div.w ${Dsp-16-u16} */
43197 {
43198 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32,
6772dd07 43199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43200 },
43201/* div.b $Dst16RnQI */
43202 {
43203 M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16,
6772dd07 43204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43205 },
43206/* div.b $Dst16AnQI */
43207 {
43208 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16,
6772dd07 43209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43210 },
43211/* div.b [$Dst16An] */
43212 {
43213 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16,
6772dd07 43214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43215 },
43216/* div.b ${Dsp-16-u8}[$Dst16An] */
43217 {
43218 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24,
6772dd07 43219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43220 },
43221/* div.b ${Dsp-16-u16}[$Dst16An] */
43222 {
43223 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32,
6772dd07 43224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43225 },
43226/* div.b ${Dsp-16-u8}[sb] */
43227 {
43228 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24,
6772dd07 43229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43230 },
43231/* div.b ${Dsp-16-u16}[sb] */
43232 {
43233 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32,
6772dd07 43234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43235 },
43236/* div.b ${Dsp-16-s8}[fb] */
43237 {
43238 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24,
6772dd07 43239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43240 },
43241/* div.b ${Dsp-16-u16} */
43242 {
43243 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32,
6772dd07 43244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43245 },
43246/* dec.w $Dst32RnUnprefixedHI */
43247 {
43248 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16,
6772dd07 43249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43250 },
43251/* dec.w $Dst32AnUnprefixedHI */
43252 {
43253 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16,
6772dd07 43254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43255 },
43256/* dec.w [$Dst32AnUnprefixed] */
43257 {
43258 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16,
6772dd07 43259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43260 },
43261/* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43262 {
43263 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24,
6772dd07 43264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43265 },
43266/* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43267 {
43268 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32,
6772dd07 43269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43270 },
43271/* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43272 {
43273 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40,
6772dd07 43274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43275 },
43276/* dec.w ${Dsp-16-u8}[sb] */
43277 {
43278 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24,
6772dd07 43279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43280 },
43281/* dec.w ${Dsp-16-u16}[sb] */
43282 {
43283 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32,
6772dd07 43284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43285 },
43286/* dec.w ${Dsp-16-s8}[fb] */
43287 {
43288 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24,
6772dd07 43289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43290 },
43291/* dec.w ${Dsp-16-s16}[fb] */
43292 {
43293 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32,
6772dd07 43294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43295 },
43296/* dec.w ${Dsp-16-u16} */
43297 {
43298 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32,
6772dd07 43299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43300 },
43301/* dec.w ${Dsp-16-u24} */
43302 {
43303 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40,
6772dd07 43304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43305 },
43306/* dec.b $Dst32RnUnprefixedQI */
43307 {
43308 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16,
6772dd07 43309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43310 },
43311/* dec.b $Dst32AnUnprefixedQI */
43312 {
43313 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16,
6772dd07 43314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43315 },
43316/* dec.b [$Dst32AnUnprefixed] */
43317 {
43318 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16,
6772dd07 43319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43320 },
43321/* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43322 {
43323 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24,
6772dd07 43324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43325 },
43326/* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43327 {
43328 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32,
6772dd07 43329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43330 },
43331/* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43332 {
43333 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40,
6772dd07 43334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43335 },
43336/* dec.b ${Dsp-16-u8}[sb] */
43337 {
43338 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24,
6772dd07 43339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43340 },
43341/* dec.b ${Dsp-16-u16}[sb] */
43342 {
43343 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32,
6772dd07 43344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43345 },
43346/* dec.b ${Dsp-16-s8}[fb] */
43347 {
43348 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24,
6772dd07 43349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43350 },
43351/* dec.b ${Dsp-16-s16}[fb] */
43352 {
43353 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32,
6772dd07 43354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43355 },
43356/* dec.b ${Dsp-16-u16} */
43357 {
43358 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32,
6772dd07 43359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43360 },
43361/* dec.b ${Dsp-16-u24} */
43362 {
43363 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40,
6772dd07 43364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43365 },
43366/* dec.b r0l */
43367 {
43368 M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8,
6772dd07 43369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43370 },
43371/* dec.b r0h */
43372 {
43373 M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8,
6772dd07 43374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43375 },
43376/* dec.b ${Dsp-8-u8}[sb] */
43377 {
43378 M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16,
6772dd07 43379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43380 },
43381/* dec.b ${Dsp-8-s8}[fb] */
43382 {
43383 M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16,
6772dd07 43384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43385 },
43386/* dec.b ${Dsp-8-u16} */
43387 {
43388 M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24,
6772dd07 43389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43390 },
43391/* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
43392 {
43393 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24,
6772dd07 43394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43395 },
43396/* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
43397 {
43398 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24,
6772dd07 43399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43400 },
43401/* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
43402 {
43403 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24,
6772dd07 43404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43405 },
43406/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
43407 {
43408 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32,
6772dd07 43409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43410 },
43411/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
43412 {
43413 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32,
6772dd07 43414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43415 },
43416/* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
43417 {
43418 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32,
6772dd07 43419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43420 },
43421/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
43422 {
43423 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40,
6772dd07 43424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43425 },
43426/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
43427 {
43428 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40,
6772dd07 43429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43430 },
43431/* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
43432 {
43433 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40,
6772dd07 43434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43435 },
43436/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
43437 {
43438 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40,
6772dd07 43439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43440 },
43441/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
43442 {
43443 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48,
6772dd07 43444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43445 },
43446/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
43447 {
43448 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48,
6772dd07 43449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 43450 },
43451/* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
43452 {
43453 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16,
6772dd07 43454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43455 },
43456/* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
43457 {
43458 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16,
6772dd07 43459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43460 },
43461/* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
43462 {
43463 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24,
6772dd07 43464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43465 },
43466/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
43467 {
43468 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16,
6772dd07 43469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43470 },
43471/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
43472 {
43473 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16,
6772dd07 43474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43475 },
43476/* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
43477 {
43478 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24,
6772dd07 43479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43480 },
43481/* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
43482 {
43483 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32,
6772dd07 43484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43485 },
43486/* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
43487 {
43488 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32,
6772dd07 43489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43490 },
43491/* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
43492 {
43493 M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40,
6772dd07 43494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43495 },
43496/* cmp.w${S} #${Imm-8-HI},r0 */
43497 {
43498 M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24,
6772dd07 43499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43500 },
43501/* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
43502 {
43503 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24,
6772dd07 43504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43505 },
43506/* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
43507 {
43508 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24,
6772dd07 43509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43510 },
43511/* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
43512 {
43513 M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32,
6772dd07 43514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43515 },
43516/* cmp.b${S} #${Imm-8-QI},r0l */
43517 {
43518 M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16,
6772dd07 43519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 43520 },
43521/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43522 {
43523 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
6772dd07 43524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43525 },
43526/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
43527 {
43528 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
6772dd07 43529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43530 },
43531/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
43532 {
43533 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
6772dd07 43534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43535 },
43536/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43537 {
43538 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
6772dd07 43539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43540 },
43541/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
43542 {
43543 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
6772dd07 43544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43545 },
43546/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
43547 {
43548 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
6772dd07 43549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43550 },
43551/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43552 {
43553 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
6772dd07 43554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43555 },
43556/* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
43557 {
43558 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
6772dd07 43559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43560 },
43561/* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
43562 {
43563 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
6772dd07 43564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43565 },
43566/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43567 {
43568 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43570 },
43571/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43572 {
43573 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43575 },
43576/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43577 {
43578 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43580 },
43581/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43582 {
43583 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43585 },
43586/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43587 {
43588 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43590 },
43591/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43592 {
43593 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43595 },
43596/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43597 {
43598 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43600 },
43601/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43602 {
43603 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43605 },
43606/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43607 {
43608 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43610 },
43611/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
43612 {
43613 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43615 },
43616/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
43617 {
43618 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43620 },
43621/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
43622 {
43623 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43625 },
43626/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
43627 {
43628 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43630 },
43631/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
43632 {
43633 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43635 },
43636/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
43637 {
43638 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43640 },
43641/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
43642 {
43643 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43645 },
43646/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
43647 {
43648 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43650 },
43651/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
43652 {
43653 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 43654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43655 },
43656/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
43657 {
43658 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43660 },
43661/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
43662 {
43663 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43665 },
43666/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
43667 {
43668 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43670 },
43671/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
43672 {
43673 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
6772dd07 43674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43675 },
43676/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
43677 {
43678 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
6772dd07 43679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43680 },
43681/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
43682 {
43683 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
6772dd07 43684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43685 },
43686/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
43687 {
43688 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
6772dd07 43689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43690 },
43691/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
43692 {
43693 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
6772dd07 43694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43695 },
43696/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
43697 {
43698 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
6772dd07 43699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43700 },
43701/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43702 {
43703 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43705 },
43706/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
43707 {
43708 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43710 },
43711/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
43712 {
43713 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43715 },
43716/* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
43717 {
43718 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43720 },
43721/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43722 {
43723 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43725 },
43726/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
43727 {
43728 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43730 },
43731/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
43732 {
43733 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43735 },
43736/* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
43737 {
43738 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
6772dd07 43739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43740 },
43741/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43742 {
43743 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
6772dd07 43744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43745 },
43746/* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
43747 {
43748 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
6772dd07 43749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43750 },
43751/* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
43752 {
43753 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
6772dd07 43754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43755 },
43756/* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
43757 {
43758 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
6772dd07 43759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43760 },
43761/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43762 {
43763 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43765 },
43766/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43767 {
43768 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43770 },
43771/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43772 {
43773 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43775 },
43776/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
43777 {
43778 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43780 },
43781/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43782 {
43783 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43785 },
43786/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43787 {
43788 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43790 },
43791/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43792 {
43793 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43795 },
43796/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
43797 {
43798 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43800 },
43801/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43802 {
43803 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 43804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43805 },
43806/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43807 {
43808 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 43809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43810 },
43811/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43812 {
43813 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 43814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43815 },
43816/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
43817 {
43818 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 43819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43820 },
43821/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
43822 {
43823 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43825 },
43826/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
43827 {
43828 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43830 },
43831/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
43832 {
43833 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43835 },
43836/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
43837 {
43838 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43840 },
43841/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
43842 {
43843 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43845 },
43846/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
43847 {
43848 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43850 },
43851/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
43852 {
43853 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43855 },
43856/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
43857 {
43858 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43860 },
43861/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
43862 {
43863 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43865 },
43866/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
43867 {
43868 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43870 },
43871/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
43872 {
43873 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43875 },
43876/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
43877 {
43878 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 43879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43880 },
43881/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
43882 {
43883 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43885 },
43886/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
43887 {
43888 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43890 },
43891/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
43892 {
43893 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43895 },
43896/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
43897 {
43898 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43900 },
43901/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
43902 {
43903 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
6772dd07 43904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43905 },
43906/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
43907 {
43908 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
6772dd07 43909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43910 },
43911/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
43912 {
43913 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
6772dd07 43914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43915 },
43916/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
43917 {
43918 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
6772dd07 43919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43920 },
43921/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
43922 {
43923 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
6772dd07 43924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43925 },
43926/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
43927 {
43928 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
6772dd07 43929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43930 },
43931/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
43932 {
43933 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
6772dd07 43934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43935 },
43936/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
43937 {
43938 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
6772dd07 43939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43940 },
43941/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43942 {
43943 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
6772dd07 43944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43945 },
43946/* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
43947 {
43948 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
6772dd07 43949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43950 },
43951/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43952 {
43953 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
6772dd07 43954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43955 },
43956/* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
43957 {
43958 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
6772dd07 43959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43960 },
43961/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43962 {
43963 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
6772dd07 43964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43965 },
43966/* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
43967 {
43968 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
6772dd07 43969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43970 },
43971/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
43972 {
43973 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43975 },
43976/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
43977 {
43978 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 43979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43980 },
43981/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
43982 {
43983 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 43984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43985 },
43986/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
43987 {
43988 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 43989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43990 },
43991/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
43992 {
43993 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
6772dd07 43994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 43995 },
43996/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
43997 {
43998 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
6772dd07 43999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44000 },
44001/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
44002 {
44003 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 44004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44005 },
44006/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
44007 {
44008 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 44009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44010 },
44011/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
44012 {
44013 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 44014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44015 },
44016/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
44017 {
44018 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 44019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44020 },
44021/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
44022 {
44023 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 44024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44025 },
44026/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
44027 {
44028 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
6772dd07 44029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44030 },
44031/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44032 {
44033 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 44034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44035 },
44036/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44037 {
44038 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 44039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44040 },
44041/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44042 {
44043 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
6772dd07 44044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44045 },
44046/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
44047 {
44048 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
6772dd07 44049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44050 },
44051/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44052 {
44053 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
6772dd07 44054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44055 },
44056/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
44057 {
44058 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
6772dd07 44059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44060 },
44061/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
44062 {
44063 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
6772dd07 44064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44065 },
44066/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
44067 {
44068 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
6772dd07 44069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44070 },
44071/* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
44072 {
44073 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
6772dd07 44074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44075 },
44076/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
44077 {
44078 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
6772dd07 44079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44080 },
44081/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
44082 {
44083 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
6772dd07 44084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44085 },
44086/* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
44087 {
44088 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
6772dd07 44089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44090 },
44091/* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
44092 {
44093 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
6772dd07 44094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44095 },
44096/* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
44097 {
44098 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
6772dd07 44099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44100 },
44101/* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44102 {
44103 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
6772dd07 44104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44105 },
44106/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44107 {
44108 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44110 },
44111/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44112 {
44113 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44115 },
44116/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44117 {
44118 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44120 },
44121/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44122 {
44123 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44125 },
44126/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44127 {
44128 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44130 },
44131/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44132 {
44133 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44135 },
44136/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44137 {
44138 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 44139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44140 },
44141/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44142 {
44143 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 44144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44145 },
44146/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44147 {
44148 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
6772dd07 44149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44150 },
44151/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
44152 {
44153 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44155 },
44156/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
44157 {
44158 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44160 },
44161/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44162 {
44163 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44165 },
44166/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
44167 {
44168 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44170 },
44171/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
44172 {
44173 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44175 },
44176/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44177 {
44178 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44180 },
44181/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
44182 {
44183 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44185 },
44186/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
44187 {
44188 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44190 },
44191/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44192 {
44193 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
6772dd07 44194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44195 },
44196/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
44197 {
44198 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44200 },
44201/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
44202 {
44203 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44205 },
44206/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44207 {
44208 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
6772dd07 44209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44210 },
44211/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
44212 {
44213 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
6772dd07 44214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44215 },
44216/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
44217 {
44218 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
6772dd07 44219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44220 },
44221/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44222 {
44223 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
6772dd07 44224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44225 },
44226/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
44227 {
44228 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
6772dd07 44229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44230 },
44231/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
44232 {
44233 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
6772dd07 44234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44235 },
44236/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44237 {
44238 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
6772dd07 44239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44240 },
44241/* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
44242 {
44243 M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8,
6772dd07 44244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 44245 },
44246/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
44247 {
44248 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16,
6772dd07 44249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 44250 },
44251/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
44252 {
44253 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16,
6772dd07 44254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 44255 },
44256/* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
44257 {
44258 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24,
6772dd07 44259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 44260 },
44261/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44262 {
44263 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
6772dd07 44264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44265 },
44266/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
44267 {
44268 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
6772dd07 44269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44270 },
44271/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
44272 {
44273 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
6772dd07 44274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44275 },
44276/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44277 {
44278 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
6772dd07 44279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44280 },
44281/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
44282 {
44283 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
6772dd07 44284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44285 },
44286/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
44287 {
44288 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
6772dd07 44289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44290 },
44291/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44292 {
44293 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
6772dd07 44294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44295 },
44296/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
44297 {
44298 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
6772dd07 44299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44300 },
44301/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
44302 {
44303 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
6772dd07 44304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44305 },
44306/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44307 {
44308 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44310 },
44311/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44312 {
44313 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44315 },
44316/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44317 {
44318 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44320 },
44321/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44322 {
44323 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44325 },
44326/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44327 {
44328 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44330 },
44331/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44332 {
44333 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44335 },
44336/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44337 {
44338 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44340 },
44341/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44342 {
44343 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44345 },
44346/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44347 {
44348 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44350 },
44351/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
44352 {
44353 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44355 },
44356/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
44357 {
44358 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44360 },
44361/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
44362 {
44363 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44365 },
44366/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
44367 {
44368 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44370 },
44371/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
44372 {
44373 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44375 },
44376/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
44377 {
44378 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44380 },
44381/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
44382 {
44383 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44385 },
44386/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
44387 {
44388 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44390 },
44391/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
44392 {
44393 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44395 },
44396/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
44397 {
44398 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44400 },
44401/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
44402 {
44403 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44405 },
44406/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
44407 {
44408 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44410 },
44411/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
44412 {
44413 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
6772dd07 44414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44415 },
44416/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
44417 {
44418 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
6772dd07 44419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44420 },
44421/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
44422 {
44423 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
6772dd07 44424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44425 },
44426/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
44427 {
44428 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 44429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44430 },
44431/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
44432 {
44433 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 44434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44435 },
44436/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
44437 {
44438 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 44439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44440 },
44441/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44442 {
44443 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44445 },
44446/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
44447 {
44448 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44450 },
44451/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
44452 {
44453 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44455 },
44456/* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
44457 {
44458 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44460 },
44461/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44462 {
44463 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44465 },
44466/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
44467 {
44468 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44470 },
44471/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
44472 {
44473 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44475 },
44476/* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
44477 {
44478 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 44479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44480 },
44481/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44482 {
44483 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
6772dd07 44484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44485 },
44486/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
44487 {
44488 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
6772dd07 44489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44490 },
44491/* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
44492 {
44493 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
6772dd07 44494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44495 },
44496/* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
44497 {
44498 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
6772dd07 44499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44500 },
44501/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44502 {
44503 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44505 },
44506/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44507 {
44508 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44510 },
44511/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44512 {
44513 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44515 },
44516/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
44517 {
44518 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44520 },
44521/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44522 {
44523 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44525 },
44526/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44527 {
44528 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44530 },
44531/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44532 {
44533 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44535 },
44536/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
44537 {
44538 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44540 },
44541/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44542 {
44543 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44545 },
44546/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44547 {
44548 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44550 },
44551/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44552 {
44553 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44555 },
44556/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
44557 {
44558 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44560 },
44561/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
44562 {
44563 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44565 },
44566/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
44567 {
44568 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44570 },
44571/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
44572 {
44573 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44575 },
44576/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
44577 {
44578 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44580 },
44581/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
44582 {
44583 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44585 },
44586/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
44587 {
44588 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44590 },
44591/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
44592 {
44593 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44595 },
44596/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
44597 {
44598 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44600 },
44601/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
44602 {
44603 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44605 },
44606/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
44607 {
44608 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44610 },
44611/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
44612 {
44613 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44615 },
44616/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
44617 {
44618 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44620 },
44621/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
44622 {
44623 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44625 },
44626/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
44627 {
44628 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44630 },
44631/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
44632 {
44633 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44635 },
44636/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
44637 {
44638 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44640 },
44641/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
44642 {
44643 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 44644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44645 },
44646/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
44647 {
44648 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 44649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44650 },
44651/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
44652 {
44653 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 44654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44655 },
44656/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
44657 {
44658 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 44659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44660 },
44661/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
44662 {
44663 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
6772dd07 44664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44665 },
44666/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
44667 {
44668 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
6772dd07 44669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44670 },
44671/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
44672 {
44673 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
6772dd07 44674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44675 },
44676/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
44677 {
44678 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
6772dd07 44679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44680 },
44681/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44682 {
44683 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
6772dd07 44684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44685 },
44686/* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
44687 {
44688 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
6772dd07 44689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44690 },
44691/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44692 {
44693 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
6772dd07 44694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44695 },
44696/* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
44697 {
44698 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
6772dd07 44699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44700 },
44701/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44702 {
44703 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
6772dd07 44704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44705 },
44706/* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
44707 {
44708 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
6772dd07 44709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44710 },
44711/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
44712 {
44713 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44715 },
44716/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
44717 {
44718 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44720 },
44721/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
44722 {
44723 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44725 },
44726/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
44727 {
44728 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44730 },
44731/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
44732 {
44733 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
6772dd07 44734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44735 },
44736/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
44737 {
44738 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
6772dd07 44739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44740 },
44741/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
44742 {
44743 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44745 },
44746/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
44747 {
44748 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44750 },
44751/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
44752 {
44753 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44755 },
44756/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
44757 {
44758 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44760 },
44761/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
44762 {
44763 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44765 },
44766/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
44767 {
44768 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 44769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44770 },
44771/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44772 {
44773 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44775 },
44776/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44777 {
44778 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 44779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44780 },
44781/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44782 {
44783 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
6772dd07 44784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44785 },
44786/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
44787 {
44788 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
6772dd07 44789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44790 },
44791/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44792 {
44793 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
6772dd07 44794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44795 },
44796/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
44797 {
44798 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
6772dd07 44799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44800 },
44801/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
44802 {
44803 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 44804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44805 },
44806/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
44807 {
44808 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 44809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44810 },
44811/* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44812 {
44813 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 44814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44815 },
44816/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
44817 {
44818 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 44819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44820 },
44821/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
44822 {
44823 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 44824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44825 },
44826/* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44827 {
44828 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 44829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44830 },
44831/* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
44832 {
44833 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
6772dd07 44834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44835 },
44836/* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
44837 {
44838 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
6772dd07 44839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44840 },
44841/* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44842 {
44843 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
6772dd07 44844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44845 },
44846/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44847 {
44848 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44850 },
44851/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44852 {
44853 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44855 },
44856/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44857 {
44858 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44860 },
44861/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44862 {
44863 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44865 },
44866/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44867 {
44868 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44870 },
44871/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44872 {
44873 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44875 },
44876/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44877 {
44878 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44880 },
44881/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44882 {
44883 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44885 },
44886/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44887 {
44888 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 44889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44890 },
44891/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
44892 {
44893 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44895 },
44896/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
44897 {
44898 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44900 },
44901/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44902 {
44903 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44905 },
44906/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
44907 {
44908 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44910 },
44911/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
44912 {
44913 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44915 },
44916/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44917 {
44918 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44920 },
44921/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
44922 {
44923 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44925 },
44926/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
44927 {
44928 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44930 },
44931/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44932 {
44933 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 44934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44935 },
44936/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
44937 {
44938 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44940 },
44941/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
44942 {
44943 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44945 },
44946/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44947 {
44948 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 44949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44950 },
44951/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
44952 {
44953 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
6772dd07 44954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44955 },
44956/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
44957 {
44958 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
6772dd07 44959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44960 },
44961/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44962 {
44963 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
6772dd07 44964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44965 },
44966/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
44967 {
44968 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
6772dd07 44969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44970 },
44971/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
44972 {
44973 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
6772dd07 44974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44975 },
44976/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44977 {
44978 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
6772dd07 44979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44980 },
44981/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
44982 {
44983 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 44984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44985 },
44986/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
44987 {
44988 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 44989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44990 },
44991/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
44992 {
44993 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 44994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 44995 },
44996/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
44997 {
44998 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 44999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45000 },
45001/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
45002 {
45003 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 45004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45005 },
45006/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
45007 {
45008 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 45009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45010 },
45011/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45012 {
45013 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
6772dd07 45014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45015 },
45016/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
45017 {
45018 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
6772dd07 45019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45020 },
45021/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
45022 {
45023 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
6772dd07 45024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45025 },
45026/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45027 {
45028 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45030 },
45031/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45032 {
45033 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45035 },
45036/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45037 {
45038 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45040 },
45041/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45042 {
45043 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45045 },
45046/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45047 {
45048 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45050 },
45051/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45052 {
45053 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45055 },
45056/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45057 {
45058 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45060 },
45061/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45062 {
45063 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45065 },
45066/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45067 {
45068 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45070 },
45071/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
45072 {
45073 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45075 },
45076/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45077 {
45078 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45080 },
45081/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45082 {
45083 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45085 },
45086/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
45087 {
45088 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45090 },
45091/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45092 {
45093 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45095 },
45096/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45097 {
45098 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45100 },
45101/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
45102 {
45103 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45105 },
45106/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45107 {
45108 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45110 },
45111/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45112 {
45113 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45115 },
45116/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
45117 {
45118 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45120 },
45121/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
45122 {
45123 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45125 },
45126/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
45127 {
45128 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45130 },
45131/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
45132 {
45133 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 45134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45135 },
45136/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45137 {
45138 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 45139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45140 },
45141/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45142 {
45143 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 45144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45145 },
45146/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
45147 {
45148 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 45149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45150 },
45151/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
45152 {
45153 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 45154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45155 },
45156/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
45157 {
45158 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 45159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45160 },
45161/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45162 {
45163 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45165 },
45166/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
45167 {
45168 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45170 },
45171/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
45172 {
45173 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45175 },
45176/* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
45177 {
45178 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45180 },
45181/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45182 {
45183 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45185 },
45186/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
45187 {
45188 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45190 },
45191/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
45192 {
45193 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45195 },
45196/* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
45197 {
45198 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
6772dd07 45199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45200 },
45201/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45202 {
45203 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
6772dd07 45204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45205 },
45206/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
45207 {
45208 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
6772dd07 45209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45210 },
45211/* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
45212 {
45213 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
6772dd07 45214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45215 },
45216/* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
45217 {
45218 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
6772dd07 45219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45220 },
45221/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45222 {
45223 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45225 },
45226/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45227 {
45228 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45230 },
45231/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45232 {
45233 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45235 },
45236/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
45237 {
45238 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45240 },
45241/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45242 {
45243 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45245 },
45246/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45247 {
45248 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45250 },
45251/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45252 {
45253 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45255 },
45256/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
45257 {
45258 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45260 },
45261/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45262 {
45263 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45265 },
45266/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45267 {
45268 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45270 },
45271/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45272 {
45273 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45275 },
45276/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
45277 {
45278 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45280 },
45281/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
45282 {
45283 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45285 },
45286/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45287 {
45288 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45290 },
45291/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
45292 {
45293 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45295 },
45296/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45297 {
45298 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45300 },
45301/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
45302 {
45303 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45305 },
45306/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45307 {
45308 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45310 },
45311/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
45312 {
45313 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45315 },
45316/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45317 {
45318 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45320 },
45321/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
45322 {
45323 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45325 },
45326/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45327 {
45328 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45330 },
45331/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
45332 {
45333 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45335 },
45336/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45337 {
45338 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45340 },
45341/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
45342 {
45343 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45345 },
45346/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
45347 {
45348 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45350 },
45351/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
45352 {
45353 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45355 },
45356/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
45357 {
45358 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45360 },
45361/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
45362 {
45363 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 45364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45365 },
45366/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45367 {
45368 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 45369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45370 },
45371/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
45372 {
45373 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 45374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45375 },
45376/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
45377 {
45378 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 45379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45380 },
45381/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
45382 {
45383 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
6772dd07 45384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45385 },
45386/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
45387 {
45388 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
6772dd07 45389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45390 },
45391/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
45392 {
45393 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
6772dd07 45394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45395 },
45396/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
45397 {
45398 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
6772dd07 45399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45400 },
45401/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45402 {
45403 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
6772dd07 45404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45405 },
45406/* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
45407 {
45408 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
6772dd07 45409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45410 },
45411/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45412 {
45413 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
6772dd07 45414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45415 },
45416/* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
45417 {
45418 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
6772dd07 45419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45420 },
45421/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45422 {
45423 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
6772dd07 45424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45425 },
45426/* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
45427 {
45428 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
6772dd07 45429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45430 },
45431/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
45432 {
45433 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45435 },
45436/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
45437 {
45438 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45440 },
45441/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
45442 {
45443 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45445 },
45446/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
45447 {
45448 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45450 },
45451/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
45452 {
45453 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
6772dd07 45454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45455 },
45456/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
45457 {
45458 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
6772dd07 45459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45460 },
45461/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
45462 {
45463 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45465 },
45466/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
45467 {
45468 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45470 },
45471/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
45472 {
45473 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45475 },
45476/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
45477 {
45478 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45480 },
45481/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
45482 {
45483 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45485 },
45486/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
45487 {
45488 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 45489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45490 },
45491/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
45492 {
45493 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45495 },
45496/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
45497 {
45498 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
6772dd07 45499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45500 },
45501/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
45502 {
45503 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
6772dd07 45504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45505 },
45506/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
45507 {
45508 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
6772dd07 45509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45510 },
45511/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
45512 {
45513 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
6772dd07 45514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45515 },
45516/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
45517 {
45518 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
6772dd07 45519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45520 },
45521/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
45522 {
45523 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 45524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45525 },
45526/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
45527 {
45528 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 45529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45530 },
45531/* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45532 {
45533 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 45534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45535 },
45536/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
45537 {
45538 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 45539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45540 },
45541/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
45542 {
45543 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 45544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45545 },
45546/* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45547 {
45548 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 45549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45550 },
45551/* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
45552 {
45553 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
6772dd07 45554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45555 },
45556/* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
45557 {
45558 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
6772dd07 45559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45560 },
45561/* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45562 {
45563 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
6772dd07 45564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45565 },
45566/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45567 {
45568 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45570 },
45571/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45572 {
45573 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45575 },
45576/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
45577 {
45578 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45580 },
45581/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45582 {
45583 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45585 },
45586/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45587 {
45588 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45590 },
45591/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
45592 {
45593 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45595 },
45596/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45597 {
45598 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45600 },
45601/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45602 {
45603 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45605 },
45606/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
45607 {
45608 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 45609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45610 },
45611/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
45612 {
45613 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45615 },
45616/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
45617 {
45618 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45620 },
45621/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
45622 {
45623 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45625 },
45626/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
45627 {
45628 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45630 },
45631/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
45632 {
45633 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45635 },
45636/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
45637 {
45638 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45640 },
45641/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
45642 {
45643 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45645 },
45646/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
45647 {
45648 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45650 },
45651/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
45652 {
45653 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 45654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45655 },
45656/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
45657 {
45658 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45660 },
45661/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
45662 {
45663 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45665 },
45666/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
45667 {
45668 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 45669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45670 },
45671/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
45672 {
45673 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
6772dd07 45674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45675 },
45676/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
45677 {
45678 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
6772dd07 45679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45680 },
45681/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
45682 {
45683 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
6772dd07 45684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45685 },
45686/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
45687 {
45688 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 45689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45690 },
45691/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
45692 {
45693 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 45694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45695 },
45696/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
45697 {
45698 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 45699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45700 },
45701/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
45702 {
45703 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
6772dd07 45704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45705 },
45706/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
45707 {
45708 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
6772dd07 45709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45710 },
45711/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
45712 {
45713 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
6772dd07 45714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45715 },
45716/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
45717 {
45718 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
6772dd07 45719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45720 },
45721/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
45722 {
45723 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
6772dd07 45724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45725 },
45726/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
45727 {
45728 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
6772dd07 45729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45730 },
45731/* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
45732 {
45733 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
6772dd07 45734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45735 },
45736/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
45737 {
45738 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
6772dd07 45739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45740 },
45741/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
45742 {
45743 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
6772dd07 45744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45745 },
45746/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
45747 {
45748 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
6772dd07 45749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45750 },
45751/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
45752 {
45753 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
6772dd07 45754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45755 },
45756/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
45757 {
45758 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
6772dd07 45759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45760 },
45761/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
45762 {
45763 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
6772dd07 45764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45765 },
45766/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
45767 {
45768 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
6772dd07 45769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45770 },
45771/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
45772 {
45773 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
6772dd07 45774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45775 },
45776/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
45777 {
45778 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
6772dd07 45779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45780 },
45781/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45782 {
45783 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
6772dd07 45784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45785 },
45786/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45787 {
45788 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
6772dd07 45789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45790 },
45791/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
45792 {
45793 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
6772dd07 45794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45795 },
45796/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45797 {
45798 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
6772dd07 45799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45800 },
45801/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45802 {
45803 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
6772dd07 45804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45805 },
45806/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
45807 {
45808 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
6772dd07 45809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45810 },
45811/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45812 {
45813 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
6772dd07 45814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45815 },
45816/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45817 {
45818 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
6772dd07 45819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45820 },
45821/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
45822 {
45823 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
6772dd07 45824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45825 },
45826/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45827 {
45828 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
6772dd07 45829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45830 },
45831/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45832 {
45833 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
6772dd07 45834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45835 },
45836/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
45837 {
45838 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
6772dd07 45839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45840 },
45841/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
45842 {
45843 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
6772dd07 45844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45845 },
45846/* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
45847 {
45848 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32,
6772dd07 45849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45850 },
45851/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
45852 {
45853 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
6772dd07 45854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45855 },
45856/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
45857 {
45858 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
6772dd07 45859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45860 },
45861/* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
45862 {
45863 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32,
6772dd07 45864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45865 },
45866/* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
45867 {
45868 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
6772dd07 45869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45870 },
45871/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
45872 {
45873 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
6772dd07 45874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45875 },
45876/* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
45877 {
45878 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32,
6772dd07 45879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45880 },
45881/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
45882 {
45883 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
6772dd07 45884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45885 },
45886/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
45887 {
45888 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
6772dd07 45889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45890 },
45891/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
45892 {
45893 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
6772dd07 45894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45895 },
45896/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
45897 {
45898 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
6772dd07 45899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45900 },
45901/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
45902 {
45903 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
6772dd07 45904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45905 },
45906/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
45907 {
45908 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
6772dd07 45909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45910 },
45911/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
45912 {
45913 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
6772dd07 45914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45915 },
45916/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45917 {
45918 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
6772dd07 45919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45920 },
45921/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45922 {
45923 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
6772dd07 45924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45925 },
45926/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
45927 {
45928 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
6772dd07 45929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45930 },
45931/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45932 {
45933 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
6772dd07 45934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45935 },
45936/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45937 {
45938 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
6772dd07 45939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45940 },
45941/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
45942 {
45943 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
6772dd07 45944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45945 },
45946/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45947 {
45948 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
6772dd07 45949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45950 },
45951/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45952 {
45953 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
6772dd07 45954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45955 },
45956/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
45957 {
45958 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
6772dd07 45959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45960 },
45961/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45962 {
45963 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
6772dd07 45964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45965 },
45966/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
45967 {
45968 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
6772dd07 45969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45970 },
45971/* cmp.w${G} $Src16RnHI,$Dst16RnHI */
45972 {
45973 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
6772dd07 45974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45975 },
45976/* cmp.w${G} $Src16AnHI,$Dst16RnHI */
45977 {
45978 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
6772dd07 45979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45980 },
45981/* cmp.w${G} [$Src16An],$Dst16RnHI */
45982 {
45983 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16,
6772dd07 45984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45985 },
45986/* cmp.w${G} $Src16RnHI,$Dst16AnHI */
45987 {
45988 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
6772dd07 45989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45990 },
45991/* cmp.w${G} $Src16AnHI,$Dst16AnHI */
45992 {
45993 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
6772dd07 45994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 45995 },
45996/* cmp.w${G} [$Src16An],$Dst16AnHI */
45997 {
45998 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16,
6772dd07 45999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46000 },
46001/* cmp.w${G} $Src16RnHI,[$Dst16An] */
46002 {
46003 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
6772dd07 46004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46005 },
46006/* cmp.w${G} $Src16AnHI,[$Dst16An] */
46007 {
46008 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
6772dd07 46009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46010 },
46011/* cmp.w${G} [$Src16An],[$Dst16An] */
46012 {
46013 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16,
6772dd07 46014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46015 },
46016/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
46017 {
46018 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
6772dd07 46019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46020 },
46021/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
46022 {
46023 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
6772dd07 46024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46025 },
46026/* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
46027 {
46028 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
6772dd07 46029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46030 },
46031/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
46032 {
46033 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
6772dd07 46034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46035 },
46036/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
46037 {
46038 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
6772dd07 46039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46040 },
46041/* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46042 {
46043 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
6772dd07 46044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46045 },
46046/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
46047 {
46048 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
6772dd07 46049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46050 },
46051/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
46052 {
46053 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
6772dd07 46054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46055 },
46056/* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
46057 {
46058 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
6772dd07 46059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46060 },
46061/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
46062 {
46063 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
6772dd07 46064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46065 },
46066/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
46067 {
46068 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
6772dd07 46069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46070 },
46071/* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
46072 {
46073 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
6772dd07 46074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46075 },
46076/* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
46077 {
46078 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
6772dd07 46079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46080 },
46081/* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
46082 {
46083 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
6772dd07 46084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46085 },
46086/* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
46087 {
46088 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
6772dd07 46089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46090 },
46091/* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
46092 {
46093 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
6772dd07 46094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46095 },
46096/* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
46097 {
46098 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
6772dd07 46099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46100 },
46101/* cmp.w${G} [$Src16An],${Dsp-16-u16} */
46102 {
46103 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
6772dd07 46104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46105 },
46106/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
46107 {
46108 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
6772dd07 46109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46110 },
46111/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
46112 {
46113 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
6772dd07 46114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46115 },
46116/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
46117 {
46118 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
6772dd07 46119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46120 },
46121/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
46122 {
46123 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
6772dd07 46124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46125 },
46126/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
46127 {
46128 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
6772dd07 46129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46130 },
46131/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
46132 {
46133 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
6772dd07 46134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46135 },
46136/* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
46137 {
46138 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
6772dd07 46139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46140 },
46141/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
46142 {
46143 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
6772dd07 46144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46145 },
46146/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
46147 {
46148 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
6772dd07 46149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46150 },
46151/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
46152 {
46153 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
6772dd07 46154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46155 },
46156/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
46157 {
46158 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
6772dd07 46159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46160 },
46161/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
46162 {
46163 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
6772dd07 46164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46165 },
46166/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
46167 {
46168 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
6772dd07 46169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46170 },
46171/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
46172 {
46173 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
6772dd07 46174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46175 },
46176/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
46177 {
46178 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
6772dd07 46179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46180 },
46181/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
46182 {
46183 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
6772dd07 46184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46185 },
46186/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
46187 {
46188 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
6772dd07 46189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46190 },
46191/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
46192 {
46193 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
6772dd07 46194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46195 },
46196/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
46197 {
46198 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
6772dd07 46199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46200 },
46201/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
46202 {
46203 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
6772dd07 46204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46205 },
46206/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
46207 {
46208 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
6772dd07 46209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46210 },
46211/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
46212 {
46213 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
6772dd07 46214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46215 },
46216/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
46217 {
46218 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
6772dd07 46219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46220 },
46221/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
46222 {
46223 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
6772dd07 46224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46225 },
46226/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
46227 {
46228 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
6772dd07 46229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46230 },
46231/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
46232 {
46233 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
6772dd07 46234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46235 },
46236/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
46237 {
46238 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
6772dd07 46239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46240 },
46241/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
46242 {
46243 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
6772dd07 46244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46245 },
46246/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
46247 {
46248 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
6772dd07 46249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46250 },
46251/* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
46252 {
46253 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32,
6772dd07 46254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46255 },
46256/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
46257 {
46258 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
6772dd07 46259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46260 },
46261/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
46262 {
46263 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
6772dd07 46264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46265 },
46266/* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
46267 {
46268 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32,
6772dd07 46269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46270 },
46271/* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
46272 {
46273 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
6772dd07 46274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46275 },
46276/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
46277 {
46278 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
6772dd07 46279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46280 },
46281/* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
46282 {
46283 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32,
6772dd07 46284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46285 },
46286/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
46287 {
46288 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
6772dd07 46289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46290 },
46291/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
46292 {
46293 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
6772dd07 46294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46295 },
46296/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
46297 {
46298 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
6772dd07 46299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46300 },
46301/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
46302 {
46303 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
6772dd07 46304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46305 },
46306/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
46307 {
46308 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
6772dd07 46309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46310 },
46311/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
46312 {
46313 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
6772dd07 46314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46315 },
46316/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
46317 {
46318 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
6772dd07 46319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46320 },
46321/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
46322 {
46323 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
6772dd07 46324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46325 },
46326/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
46327 {
46328 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
6772dd07 46329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46330 },
46331/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
46332 {
46333 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
6772dd07 46334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46335 },
46336/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
46337 {
46338 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
6772dd07 46339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46340 },
46341/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
46342 {
46343 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
6772dd07 46344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46345 },
46346/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
46347 {
46348 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
6772dd07 46349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46350 },
46351/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
46352 {
46353 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
6772dd07 46354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46355 },
46356/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
46357 {
46358 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
6772dd07 46359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46360 },
46361/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
46362 {
46363 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
6772dd07 46364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46365 },
46366/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
46367 {
46368 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
6772dd07 46369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46370 },
46371/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
46372 {
46373 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
6772dd07 46374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46375 },
46376/* cmp.b${G} $Src16RnQI,$Dst16RnQI */
46377 {
46378 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
6772dd07 46379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46380 },
46381/* cmp.b${G} $Src16AnQI,$Dst16RnQI */
46382 {
46383 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
6772dd07 46384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46385 },
46386/* cmp.b${G} [$Src16An],$Dst16RnQI */
46387 {
46388 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16,
6772dd07 46389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46390 },
46391/* cmp.b${G} $Src16RnQI,$Dst16AnQI */
46392 {
46393 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
6772dd07 46394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46395 },
46396/* cmp.b${G} $Src16AnQI,$Dst16AnQI */
46397 {
46398 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
6772dd07 46399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46400 },
46401/* cmp.b${G} [$Src16An],$Dst16AnQI */
46402 {
46403 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16,
6772dd07 46404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46405 },
46406/* cmp.b${G} $Src16RnQI,[$Dst16An] */
46407 {
46408 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
6772dd07 46409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46410 },
46411/* cmp.b${G} $Src16AnQI,[$Dst16An] */
46412 {
46413 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
6772dd07 46414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46415 },
46416/* cmp.b${G} [$Src16An],[$Dst16An] */
46417 {
46418 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16,
6772dd07 46419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46420 },
46421/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
46422 {
46423 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
6772dd07 46424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46425 },
46426/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
46427 {
46428 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
6772dd07 46429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46430 },
46431/* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
46432 {
46433 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
6772dd07 46434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46435 },
46436/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
46437 {
46438 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
6772dd07 46439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46440 },
46441/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
46442 {
46443 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
6772dd07 46444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46445 },
46446/* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46447 {
46448 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
6772dd07 46449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46450 },
46451/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
46452 {
46453 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
6772dd07 46454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46455 },
46456/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
46457 {
46458 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
6772dd07 46459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46460 },
46461/* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
46462 {
46463 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
6772dd07 46464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46465 },
46466/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
46467 {
46468 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
6772dd07 46469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46470 },
46471/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
46472 {
46473 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
6772dd07 46474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46475 },
46476/* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
46477 {
46478 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
6772dd07 46479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46480 },
46481/* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
46482 {
46483 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
6772dd07 46484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46485 },
46486/* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
46487 {
46488 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
6772dd07 46489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46490 },
46491/* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
46492 {
46493 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
6772dd07 46494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46495 },
46496/* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
46497 {
46498 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
6772dd07 46499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46500 },
46501/* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
46502 {
46503 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
6772dd07 46504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46505 },
46506/* cmp.b${G} [$Src16An],${Dsp-16-u16} */
46507 {
46508 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
6772dd07 46509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 46510 },
46511/* cmp.b${S} #${Imm-8-QI},r0l */
46512 {
46513 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16,
6772dd07 46514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 46515 },
46516/* cmp.b${S} #${Imm-8-QI},r0h */
46517 {
46518 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16,
6772dd07 46519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 46520 },
46521/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
46522 {
46523 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24,
6772dd07 46524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 46525 },
46526/* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
46527 {
46528 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24,
6772dd07 46529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 46530 },
46531/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
46532 {
46533 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32,
6772dd07 46534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 46535 },
46536/* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
46537 {
46538 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 46539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46540 },
46541/* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
46542 {
46543 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
6772dd07 46544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46545 },
46546/* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46547 {
46548 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
6772dd07 46549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46550 },
46551/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46552 {
46553 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 46554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46555 },
46556/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46557 {
46558 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 46559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46560 },
46561/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46562 {
46563 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 46564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46565 },
46566/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46567 {
46568 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 46569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46570 },
46571/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46572 {
46573 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 46574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46575 },
46576/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46577 {
46578 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
6772dd07 46579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46580 },
46581/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46582 {
46583 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
6772dd07 46584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46585 },
46586/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
46587 {
46588 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
6772dd07 46589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46590 },
46591/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
46592 {
46593 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
6772dd07 46594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46595 },
46596/* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
46597 {
46598 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 46599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46600 },
46601/* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
46602 {
46603 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
6772dd07 46604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46605 },
46606/* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46607 {
46608 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
6772dd07 46609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46610 },
46611/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46612 {
46613 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 46614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46615 },
46616/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46617 {
46618 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 46619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46620 },
46621/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46622 {
46623 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 46624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46625 },
46626/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46627 {
46628 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 46629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46630 },
46631/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46632 {
46633 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 46634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46635 },
46636/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46637 {
46638 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
6772dd07 46639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46640 },
46641/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46642 {
46643 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 46644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46645 },
46646/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
46647 {
46648 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
6772dd07 46649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46650 },
46651/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
46652 {
46653 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 46654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46655 },
46656/* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
46657 {
46658 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16,
6772dd07 46659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46660 },
46661/* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
46662 {
46663 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16,
6772dd07 46664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46665 },
46666/* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
46667 {
46668 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16,
6772dd07 46669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46670 },
46671/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46672 {
46673 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24,
6772dd07 46674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46675 },
46676/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46677 {
46678 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32,
6772dd07 46679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46680 },
46681/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46682 {
46683 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24,
6772dd07 46684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46685 },
46686/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46687 {
46688 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32,
6772dd07 46689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46690 },
46691/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46692 {
46693 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24,
6772dd07 46694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46695 },
46696/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
46697 {
46698 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32,
6772dd07 46699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46700 },
46701/* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
46702 {
46703 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16,
6772dd07 46704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46705 },
46706/* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
46707 {
46708 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16,
6772dd07 46709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46710 },
46711/* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
46712 {
46713 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16,
6772dd07 46714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46715 },
46716/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46717 {
46718 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24,
6772dd07 46719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46720 },
46721/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46722 {
46723 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32,
6772dd07 46724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46725 },
46726/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46727 {
46728 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24,
6772dd07 46729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46730 },
46731/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46732 {
46733 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32,
6772dd07 46734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46735 },
46736/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46737 {
46738 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24,
6772dd07 46739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46740 },
46741/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
46742 {
46743 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32,
6772dd07 46744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46745 },
46746/* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
46747 {
46748 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 46749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46750 },
46751/* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
46752 {
46753 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
6772dd07 46754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46755 },
46756/* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
46757 {
46758 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
6772dd07 46759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46760 },
46761/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46762 {
46763 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 46764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46765 },
46766/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46767 {
46768 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 46769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46770 },
46771/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46772 {
46773 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
6772dd07 46774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46775 },
46776/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46777 {
46778 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 46779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46780 },
46781/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46782 {
46783 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 46784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46785 },
46786/* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
46787 {
46788 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
6772dd07 46789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46790 },
46791/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46792 {
46793 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48,
6772dd07 46794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46795 },
46796/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46797 {
46798 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56,
6772dd07 46799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46800 },
46801/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
46802 {
46803 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56,
6772dd07 46804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46805 },
46806/* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
46807 {
46808 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 46809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46810 },
46811/* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
46812 {
46813 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
6772dd07 46814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46815 },
46816/* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
46817 {
46818 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
6772dd07 46819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46820 },
46821/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46822 {
46823 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 46824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46825 },
46826/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46827 {
46828 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 46829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46830 },
46831/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46832 {
46833 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
6772dd07 46834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46835 },
46836/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46837 {
46838 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 46839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46840 },
46841/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46842 {
46843 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 46844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46845 },
46846/* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
46847 {
46848 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
6772dd07 46849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46850 },
46851/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46852 {
46853 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40,
6772dd07 46854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46855 },
46856/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46857 {
46858 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48,
6772dd07 46859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46860 },
46861/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
46862 {
46863 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48,
6772dd07 46864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46865 },
46866/* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
46867 {
46868 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32,
6772dd07 46869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46870 },
46871/* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
46872 {
46873 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32,
6772dd07 46874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46875 },
46876/* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
46877 {
46878 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32,
6772dd07 46879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46880 },
46881/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
46882 {
46883 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40,
6772dd07 46884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46885 },
46886/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46887 {
46888 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40,
6772dd07 46889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46890 },
46891/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46892 {
46893 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40,
6772dd07 46894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46895 },
46896/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
46897 {
46898 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48,
6772dd07 46899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46900 },
46901/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46902 {
46903 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48,
6772dd07 46904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46905 },
46906/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46907 {
46908 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48,
6772dd07 46909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46910 },
46911/* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
46912 {
46913 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24,
6772dd07 46914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46915 },
46916/* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
46917 {
46918 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24,
6772dd07 46919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46920 },
46921/* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
46922 {
46923 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24,
6772dd07 46924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46925 },
46926/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
46927 {
46928 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32,
6772dd07 46929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46930 },
46931/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46932 {
46933 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32,
6772dd07 46934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46935 },
46936/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46937 {
46938 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32,
6772dd07 46939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46940 },
46941/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
46942 {
46943 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40,
6772dd07 46944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46945 },
46946/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46947 {
46948 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40,
6772dd07 46949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46950 },
46951/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46952 {
46953 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40,
6772dd07 46954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46955 },
46956/* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
46957 {
46958 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48,
6772dd07 46959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46960 },
46961/* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
46962 {
46963 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48,
6772dd07 46964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46965 },
46966/* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
46967 {
46968 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48,
6772dd07 46969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46970 },
46971/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46972 {
46973 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 46974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46975 },
46976/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
46977 {
46978 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 46979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46980 },
46981/* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
46982 {
46983 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56,
6772dd07 46984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46985 },
46986/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46987 {
46988 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64,
6772dd07 46989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46990 },
46991/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
46992 {
46993 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64,
6772dd07 46994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 46995 },
46996/* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
46997 {
46998 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64,
6772dd07 46999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 47000 },
47001/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
47002 {
47003 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64,
6772dd07 47004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 47005 },
47006/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
47007 {
47008 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72,
6772dd07 47009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 47010 },
47011/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
47012 {
47013 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72,
6772dd07 47014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 47015 },
47016/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
47017 {
47018 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56,
6772dd07 47019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47020 },
47021/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
47022 {
47023 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56,
6772dd07 47024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47025 },
47026/* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
47027 {
47028 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56,
6772dd07 47029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47030 },
47031/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
47032 {
47033 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64,
6772dd07 47034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47035 },
47036/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
47037 {
47038 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64,
6772dd07 47039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47040 },
47041/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
47042 {
47043 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64,
6772dd07 47044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47045 },
47046/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47047 {
47048 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72,
6772dd07 47049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47050 },
47051/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
47052 {
47053 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72,
6772dd07 47054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47055 },
47056/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
47057 {
47058 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72,
6772dd07 47059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47060 },
47061/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
47062 {
47063 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72,
6772dd07 47064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47065 },
47066/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47067 {
47068 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80,
6772dd07 47069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47070 },
47071/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
47072 {
47073 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80,
6772dd07 47074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47075 },
47076/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
47077 {
47078 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40,
6772dd07 47079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47080 },
47081/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
47082 {
47083 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40,
6772dd07 47084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47085 },
47086/* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
47087 {
47088 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40,
6772dd07 47089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47090 },
47091/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
47092 {
47093 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48,
6772dd07 47094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47095 },
47096/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
47097 {
47098 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48,
6772dd07 47099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47100 },
47101/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
47102 {
47103 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48,
6772dd07 47104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47105 },
47106/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47107 {
47108 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56,
6772dd07 47109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47110 },
47111/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
47112 {
47113 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56,
6772dd07 47114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47115 },
47116/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
47117 {
47118 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56,
6772dd07 47119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47120 },
47121/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
47122 {
47123 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56,
6772dd07 47124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47125 },
47126/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47127 {
47128 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64,
6772dd07 47129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47130 },
47131/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
47132 {
47133 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64,
6772dd07 47134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47135 },
47136/* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47137 {
47138 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24,
6772dd07 47139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47140 },
47141/* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47142 {
47143 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24,
6772dd07 47144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47145 },
47146/* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47147 {
47148 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24,
6772dd07 47149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47150 },
47151/* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47152 {
47153 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32,
6772dd07 47154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47155 },
47156/* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47157 {
47158 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40,
6772dd07 47159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47160 },
47161/* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47162 {
47163 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48,
6772dd07 47164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47165 },
47166/* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47167 {
47168 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32,
6772dd07 47169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47170 },
47171/* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47172 {
47173 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40,
6772dd07 47174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47175 },
47176/* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47177 {
47178 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32,
6772dd07 47179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47180 },
47181/* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47182 {
47183 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40,
6772dd07 47184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47185 },
47186/* bxor${X} ${BitBase32-24-u19-Prefixed} */
47187 {
47188 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40,
6772dd07 47189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47190 },
47191/* bxor${X} ${BitBase32-24-u27-Prefixed} */
47192 {
47193 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48,
6772dd07 47194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47195 },
47196/* bxor${X} $Bitno16R,$Bit16Rn */
47197 {
47198 M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24,
6772dd07 47199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47200 },
47201/* bxor${X} $Bitno16R,$Bit16An */
47202 {
47203 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24,
6772dd07 47204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47205 },
47206/* bxor${X} [$Bit16An] */
47207 {
47208 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16,
6772dd07 47209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47210 },
47211/* bxor${X} ${Dsp-16-u8}[$Bit16An] */
47212 {
47213 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24,
6772dd07 47214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47215 },
47216/* bxor${X} ${Dsp-16-u16}[$Bit16An] */
47217 {
47218 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32,
6772dd07 47219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47220 },
47221/* bxor${X} ${BitBase16-16-u8}[sb] */
47222 {
47223 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24,
6772dd07 47224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47225 },
47226/* bxor${X} ${BitBase16-16-u16}[sb] */
47227 {
47228 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32,
6772dd07 47229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47230 },
47231/* bxor${X} ${BitBase16-16-s8}[fb] */
47232 {
47233 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24,
6772dd07 47234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47235 },
47236/* bxor${X} ${BitBase16-16-u16} */
47237 {
47238 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32,
6772dd07 47239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47240 },
47241/* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47242 {
47243 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16,
6772dd07 47244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47245 },
47246/* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47247 {
47248 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16,
6772dd07 47249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47250 },
47251/* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47252 {
47253 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16,
6772dd07 47254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47255 },
47256/* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47257 {
47258 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24,
6772dd07 47259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47260 },
47261/* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47262 {
47263 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32,
6772dd07 47264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47265 },
47266/* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47267 {
47268 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40,
6772dd07 47269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47270 },
47271/* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47272 {
47273 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24,
6772dd07 47274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47275 },
47276/* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47277 {
47278 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32,
6772dd07 47279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47280 },
47281/* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47282 {
47283 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24,
6772dd07 47284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47285 },
47286/* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47287 {
47288 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32,
6772dd07 47289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47290 },
47291/* btsts${X} ${BitBase32-16-u19-Unprefixed} */
47292 {
47293 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32,
6772dd07 47294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47295 },
47296/* btsts${X} ${BitBase32-16-u27-Unprefixed} */
47297 {
47298 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40,
6772dd07 47299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47300 },
47301/* btsts${X} $Bitno16R,$Bit16Rn */
47302 {
47303 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24,
6772dd07 47304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47305 },
47306/* btsts${X} $Bitno16R,$Bit16An */
47307 {
47308 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24,
6772dd07 47309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47310 },
47311/* btsts${X} [$Bit16An] */
47312 {
47313 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16,
6772dd07 47314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47315 },
47316/* btsts${X} ${Dsp-16-u8}[$Bit16An] */
47317 {
47318 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24,
6772dd07 47319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47320 },
47321/* btsts${X} ${Dsp-16-u16}[$Bit16An] */
47322 {
47323 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32,
6772dd07 47324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47325 },
47326/* btsts${X} ${BitBase16-16-u8}[sb] */
47327 {
47328 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24,
6772dd07 47329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47330 },
47331/* btsts${X} ${BitBase16-16-u16}[sb] */
47332 {
47333 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32,
6772dd07 47334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47335 },
47336/* btsts${X} ${BitBase16-16-s8}[fb] */
47337 {
47338 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24,
6772dd07 47339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47340 },
47341/* btsts${X} ${BitBase16-16-u16} */
47342 {
47343 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32,
6772dd07 47344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47345 },
47346/* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47347 {
47348 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16,
6772dd07 47349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47350 },
47351/* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47352 {
47353 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16,
6772dd07 47354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47355 },
47356/* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47357 {
47358 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16,
6772dd07 47359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47360 },
47361/* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47362 {
47363 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24,
6772dd07 47364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47365 },
47366/* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47367 {
47368 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32,
6772dd07 47369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47370 },
47371/* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47372 {
47373 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40,
6772dd07 47374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47375 },
47376/* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47377 {
47378 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24,
6772dd07 47379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47380 },
47381/* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47382 {
47383 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32,
6772dd07 47384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47385 },
47386/* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47387 {
47388 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24,
6772dd07 47389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47390 },
47391/* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47392 {
47393 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32,
6772dd07 47394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47395 },
47396/* btstc${X} ${BitBase32-16-u19-Unprefixed} */
47397 {
47398 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32,
6772dd07 47399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47400 },
47401/* btstc${X} ${BitBase32-16-u27-Unprefixed} */
47402 {
47403 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40,
6772dd07 47404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47405 },
47406/* btstc${X} $Bitno16R,$Bit16Rn */
47407 {
47408 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24,
6772dd07 47409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47410 },
47411/* btstc${X} $Bitno16R,$Bit16An */
47412 {
47413 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24,
6772dd07 47414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47415 },
47416/* btstc${X} [$Bit16An] */
47417 {
47418 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16,
6772dd07 47419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47420 },
47421/* btstc${X} ${Dsp-16-u8}[$Bit16An] */
47422 {
47423 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24,
6772dd07 47424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47425 },
47426/* btstc${X} ${Dsp-16-u16}[$Bit16An] */
47427 {
47428 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32,
6772dd07 47429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47430 },
47431/* btstc${X} ${BitBase16-16-u8}[sb] */
47432 {
47433 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24,
6772dd07 47434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47435 },
47436/* btstc${X} ${BitBase16-16-u16}[sb] */
47437 {
47438 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32,
6772dd07 47439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47440 },
47441/* btstc${X} ${BitBase16-16-s8}[fb] */
47442 {
47443 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24,
6772dd07 47444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47445 },
47446/* btstc${X} ${BitBase16-16-u16} */
47447 {
47448 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32,
6772dd07 47449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47450 },
47451/* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47452 {
47453 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16,
6772dd07 47454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47455 },
47456/* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47457 {
47458 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16,
6772dd07 47459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47460 },
47461/* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47462 {
47463 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16,
6772dd07 47464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47465 },
47466/* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47467 {
47468 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24,
6772dd07 47469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47470 },
47471/* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47472 {
47473 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32,
6772dd07 47474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47475 },
47476/* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47477 {
47478 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40,
6772dd07 47479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47480 },
47481/* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47482 {
47483 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24,
6772dd07 47484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47485 },
47486/* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47487 {
47488 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32,
6772dd07 47489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47490 },
47491/* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47492 {
47493 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24,
6772dd07 47494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47495 },
47496/* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47497 {
47498 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32,
6772dd07 47499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47500 },
47501/* btst${X} ${BitBase32-16-u19-Unprefixed} */
47502 {
47503 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32,
6772dd07 47504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47505 },
47506/* btst${X} ${BitBase32-16-u27-Unprefixed} */
47507 {
47508 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40,
6772dd07 47509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47510 },
47511/* btst${G} $Bitno16R,$Bit16Rn */
47512 {
47513 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24,
6772dd07 47514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47515 },
47516/* btst${G} $Bitno16R,$Bit16An */
47517 {
47518 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24,
6772dd07 47519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47520 },
47521/* btst${G} ${Dsp-16-u8}[$Bit16An] */
47522 {
47523 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24,
6772dd07 47524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47525 },
47526/* btst${G} ${BitBase16-16-u8}[sb] */
47527 {
47528 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24,
6772dd07 47529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47530 },
47531/* btst${G} ${BitBase16-16-s8}[fb] */
47532 {
47533 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24,
6772dd07 47534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47535 },
47536/* btst${S} ${BitBase16-8-u11-S}[sb] */
47537 {
47538 M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16,
6772dd07 47539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47540 },
47541/* btst${G} ${Dsp-16-u16}[$Bit16An] */
47542 {
47543 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32,
6772dd07 47544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47545 },
47546/* btst${G} ${BitBase16-16-u16}[sb] */
47547 {
47548 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32,
6772dd07 47549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47550 },
47551/* btst${G} ${BitBase16-16-u16} */
47552 {
47553 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32,
6772dd07 47554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47555 },
47556/* btst${G} [$Bit16An] */
47557 {
47558 M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16,
6772dd07 47559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47560 },
47561/* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47562 {
47563 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16,
6772dd07 47564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47565 },
47566/* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47567 {
47568 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16,
6772dd07 47569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47570 },
47571/* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47572 {
47573 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16,
6772dd07 47574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47575 },
47576/* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47577 {
47578 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24,
6772dd07 47579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47580 },
47581/* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47582 {
47583 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32,
6772dd07 47584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47585 },
47586/* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47587 {
47588 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40,
6772dd07 47589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47590 },
47591/* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47592 {
47593 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24,
6772dd07 47594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47595 },
47596/* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47597 {
47598 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32,
6772dd07 47599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47600 },
47601/* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47602 {
47603 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24,
6772dd07 47604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47605 },
47606/* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47607 {
47608 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32,
6772dd07 47609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47610 },
47611/* bset${X} ${BitBase32-16-u19-Unprefixed} */
47612 {
47613 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32,
6772dd07 47614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47615 },
47616/* bset${X} ${BitBase32-16-u27-Unprefixed} */
47617 {
47618 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40,
6772dd07 47619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47620 },
47621/* bset${G} $Bitno16R,$Bit16Rn */
47622 {
47623 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24,
6772dd07 47624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47625 },
47626/* bset${G} $Bitno16R,$Bit16An */
47627 {
47628 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24,
6772dd07 47629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47630 },
47631/* bset${G} ${Dsp-16-u8}[$Bit16An] */
47632 {
47633 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24,
6772dd07 47634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47635 },
47636/* bset${G} ${BitBase16-16-u8}[sb] */
47637 {
47638 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24,
6772dd07 47639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47640 },
47641/* bset${G} ${BitBase16-16-s8}[fb] */
47642 {
47643 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24,
6772dd07 47644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47645 },
47646/* bset${S} ${BitBase16-8-u11-S}[sb] */
47647 {
47648 M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16,
6772dd07 47649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47650 },
47651/* bset${G} ${Dsp-16-u16}[$Bit16An] */
47652 {
47653 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32,
6772dd07 47654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47655 },
47656/* bset${G} ${BitBase16-16-u16}[sb] */
47657 {
47658 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32,
6772dd07 47659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47660 },
47661/* bset${G} ${BitBase16-16-u16} */
47662 {
47663 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32,
6772dd07 47664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47665 },
47666/* bset${G} [$Bit16An] */
47667 {
47668 M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16,
6772dd07 47669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47670 },
47671/* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47672 {
47673 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24,
6772dd07 47674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47675 },
47676/* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47677 {
47678 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24,
6772dd07 47679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47680 },
47681/* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47682 {
47683 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24,
6772dd07 47684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47685 },
47686/* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47687 {
47688 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32,
6772dd07 47689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47690 },
47691/* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47692 {
47693 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40,
6772dd07 47694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47695 },
47696/* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47697 {
47698 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48,
6772dd07 47699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47700 },
47701/* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47702 {
47703 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32,
6772dd07 47704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47705 },
47706/* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47707 {
47708 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40,
6772dd07 47709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47710 },
47711/* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47712 {
47713 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32,
6772dd07 47714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47715 },
47716/* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47717 {
47718 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40,
6772dd07 47719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47720 },
47721/* bor${X} ${BitBase32-24-u19-Prefixed} */
47722 {
47723 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40,
6772dd07 47724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47725 },
47726/* bor${X} ${BitBase32-24-u27-Prefixed} */
47727 {
47728 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48,
6772dd07 47729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47730 },
47731/* bor${X} $Bitno16R,$Bit16Rn */
47732 {
47733 M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24,
6772dd07 47734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47735 },
47736/* bor${X} $Bitno16R,$Bit16An */
47737 {
47738 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24,
6772dd07 47739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47740 },
47741/* bor${X} [$Bit16An] */
47742 {
47743 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16,
6772dd07 47744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47745 },
47746/* bor${X} ${Dsp-16-u8}[$Bit16An] */
47747 {
47748 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24,
6772dd07 47749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47750 },
47751/* bor${X} ${Dsp-16-u16}[$Bit16An] */
47752 {
47753 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32,
6772dd07 47754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47755 },
47756/* bor${X} ${BitBase16-16-u8}[sb] */
47757 {
47758 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24,
6772dd07 47759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47760 },
47761/* bor${X} ${BitBase16-16-u16}[sb] */
47762 {
47763 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32,
6772dd07 47764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47765 },
47766/* bor${X} ${BitBase16-16-s8}[fb] */
47767 {
47768 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24,
6772dd07 47769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47770 },
47771/* bor${X} ${BitBase16-16-u16} */
47772 {
47773 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32,
6772dd07 47774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47775 },
47776/* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47777 {
47778 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24,
6772dd07 47779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47780 },
47781/* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47782 {
47783 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24,
6772dd07 47784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47785 },
47786/* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47787 {
47788 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24,
6772dd07 47789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47790 },
47791/* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47792 {
47793 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32,
6772dd07 47794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47795 },
47796/* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47797 {
47798 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40,
6772dd07 47799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47800 },
47801/* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47802 {
47803 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48,
6772dd07 47804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47805 },
47806/* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47807 {
47808 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32,
6772dd07 47809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47810 },
47811/* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47812 {
47813 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40,
6772dd07 47814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47815 },
47816/* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47817 {
47818 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32,
6772dd07 47819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47820 },
47821/* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47822 {
47823 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40,
6772dd07 47824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47825 },
47826/* bnxor${X} ${BitBase32-24-u19-Prefixed} */
47827 {
47828 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40,
6772dd07 47829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47830 },
47831/* bnxor${X} ${BitBase32-24-u27-Prefixed} */
47832 {
47833 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48,
6772dd07 47834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47835 },
47836/* bnxor${X} $Bitno16R,$Bit16Rn */
47837 {
47838 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24,
6772dd07 47839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47840 },
47841/* bnxor${X} $Bitno16R,$Bit16An */
47842 {
47843 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24,
6772dd07 47844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47845 },
47846/* bnxor${X} [$Bit16An] */
47847 {
47848 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16,
6772dd07 47849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47850 },
47851/* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
47852 {
47853 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24,
6772dd07 47854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47855 },
47856/* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
47857 {
47858 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32,
6772dd07 47859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47860 },
47861/* bnxor${X} ${BitBase16-16-u8}[sb] */
47862 {
47863 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24,
6772dd07 47864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47865 },
47866/* bnxor${X} ${BitBase16-16-u16}[sb] */
47867 {
47868 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32,
6772dd07 47869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47870 },
47871/* bnxor${X} ${BitBase16-16-s8}[fb] */
47872 {
47873 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24,
6772dd07 47874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47875 },
47876/* bnxor${X} ${BitBase16-16-u16} */
47877 {
47878 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32,
6772dd07 47879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47880 },
47881/* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47882 {
47883 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24,
6772dd07 47884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47885 },
47886/* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47887 {
47888 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24,
6772dd07 47889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47890 },
47891/* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47892 {
47893 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24,
6772dd07 47894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47895 },
47896/* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47897 {
47898 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32,
6772dd07 47899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47900 },
47901/* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47902 {
47903 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40,
6772dd07 47904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47905 },
47906/* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47907 {
47908 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48,
6772dd07 47909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47910 },
47911/* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
47912 {
47913 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32,
6772dd07 47914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47915 },
47916/* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
47917 {
47918 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40,
6772dd07 47919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47920 },
47921/* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
47922 {
47923 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32,
6772dd07 47924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47925 },
47926/* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
47927 {
47928 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40,
6772dd07 47929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47930 },
47931/* bntst${X} ${BitBase32-24-u19-Prefixed} */
47932 {
47933 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40,
6772dd07 47934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47935 },
47936/* bntst${X} ${BitBase32-24-u27-Prefixed} */
47937 {
47938 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48,
6772dd07 47939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47940 },
47941/* bntst${X} $Bitno16R,$Bit16Rn */
47942 {
47943 M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24,
6772dd07 47944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47945 },
47946/* bntst${X} $Bitno16R,$Bit16An */
47947 {
47948 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24,
6772dd07 47949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47950 },
47951/* bntst${X} [$Bit16An] */
47952 {
47953 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16,
6772dd07 47954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47955 },
47956/* bntst${X} ${Dsp-16-u8}[$Bit16An] */
47957 {
47958 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24,
6772dd07 47959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47960 },
47961/* bntst${X} ${Dsp-16-u16}[$Bit16An] */
47962 {
47963 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32,
6772dd07 47964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47965 },
47966/* bntst${X} ${BitBase16-16-u8}[sb] */
47967 {
47968 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24,
6772dd07 47969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47970 },
47971/* bntst${X} ${BitBase16-16-u16}[sb] */
47972 {
47973 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32,
6772dd07 47974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47975 },
47976/* bntst${X} ${BitBase16-16-s8}[fb] */
47977 {
47978 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24,
6772dd07 47979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47980 },
47981/* bntst${X} ${BitBase16-16-u16} */
47982 {
47983 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32,
6772dd07 47984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47985 },
47986/* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47987 {
47988 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16,
6772dd07 47989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47990 },
47991/* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47992 {
47993 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16,
6772dd07 47994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 47995 },
47996/* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47997 {
47998 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16,
6772dd07 47999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48000 },
48001/* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48002 {
48003 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24,
6772dd07 48004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48005 },
48006/* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48007 {
48008 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32,
6772dd07 48009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48010 },
48011/* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48012 {
48013 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40,
6772dd07 48014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48015 },
48016/* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
48017 {
48018 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24,
6772dd07 48019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48020 },
48021/* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
48022 {
48023 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32,
6772dd07 48024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48025 },
48026/* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
48027 {
48028 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24,
6772dd07 48029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48030 },
48031/* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48032 {
48033 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32,
6772dd07 48034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48035 },
48036/* bnot${X} ${BitBase32-16-u19-Unprefixed} */
48037 {
48038 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32,
6772dd07 48039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48040 },
48041/* bnot${X} ${BitBase32-16-u27-Unprefixed} */
48042 {
48043 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40,
6772dd07 48044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48045 },
48046/* bnot${G} $Bitno16R,$Bit16Rn */
48047 {
48048 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24,
6772dd07 48049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48050 },
48051/* bnot${G} $Bitno16R,$Bit16An */
48052 {
48053 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24,
6772dd07 48054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48055 },
48056/* bnot${G} ${Dsp-16-u8}[$Bit16An] */
48057 {
48058 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24,
6772dd07 48059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48060 },
48061/* bnot${G} ${BitBase16-16-u8}[sb] */
48062 {
48063 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24,
6772dd07 48064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48065 },
48066/* bnot${G} ${BitBase16-16-s8}[fb] */
48067 {
48068 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24,
6772dd07 48069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48070 },
48071/* bnot${S} ${BitBase16-8-u11-S}[sb] */
48072 {
48073 M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16,
6772dd07 48074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48075 },
48076/* bnot${G} ${Dsp-16-u16}[$Bit16An] */
48077 {
48078 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32,
6772dd07 48079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48080 },
48081/* bnot${G} ${BitBase16-16-u16}[sb] */
48082 {
48083 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32,
6772dd07 48084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48085 },
48086/* bnot${G} ${BitBase16-16-u16} */
48087 {
48088 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32,
6772dd07 48089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48090 },
48091/* bnot${G} [$Bit16An] */
48092 {
48093 M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16,
6772dd07 48094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48095 },
48096/* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48097 {
48098 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24,
6772dd07 48099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48100 },
48101/* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48102 {
48103 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24,
6772dd07 48104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48105 },
48106/* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48107 {
48108 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24,
6772dd07 48109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48110 },
48111/* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48112 {
48113 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32,
6772dd07 48114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48115 },
48116/* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48117 {
48118 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40,
6772dd07 48119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48120 },
48121/* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48122 {
48123 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48,
6772dd07 48124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48125 },
48126/* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
48127 {
48128 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32,
6772dd07 48129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48130 },
48131/* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
48132 {
48133 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40,
6772dd07 48134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48135 },
48136/* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
48137 {
48138 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32,
6772dd07 48139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48140 },
48141/* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
48142 {
48143 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40,
6772dd07 48144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48145 },
48146/* bnor${X} ${BitBase32-24-u19-Prefixed} */
48147 {
48148 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40,
6772dd07 48149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48150 },
48151/* bnor${X} ${BitBase32-24-u27-Prefixed} */
48152 {
48153 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48,
6772dd07 48154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48155 },
48156/* bnor${X} $Bitno16R,$Bit16Rn */
48157 {
48158 M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24,
6772dd07 48159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48160 },
48161/* bnor${X} $Bitno16R,$Bit16An */
48162 {
48163 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24,
6772dd07 48164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48165 },
48166/* bnor${X} [$Bit16An] */
48167 {
48168 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16,
6772dd07 48169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48170 },
48171/* bnor${X} ${Dsp-16-u8}[$Bit16An] */
48172 {
48173 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24,
6772dd07 48174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48175 },
48176/* bnor${X} ${Dsp-16-u16}[$Bit16An] */
48177 {
48178 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32,
6772dd07 48179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48180 },
48181/* bnor${X} ${BitBase16-16-u8}[sb] */
48182 {
48183 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24,
6772dd07 48184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48185 },
48186/* bnor${X} ${BitBase16-16-u16}[sb] */
48187 {
48188 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32,
6772dd07 48189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48190 },
48191/* bnor${X} ${BitBase16-16-s8}[fb] */
48192 {
48193 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24,
6772dd07 48194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48195 },
48196/* bnor${X} ${BitBase16-16-u16} */
48197 {
48198 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32,
6772dd07 48199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48200 },
48201/* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48202 {
48203 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24,
6772dd07 48204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48205 },
48206/* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48207 {
48208 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24,
6772dd07 48209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48210 },
48211/* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48212 {
48213 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24,
6772dd07 48214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48215 },
48216/* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48217 {
48218 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32,
6772dd07 48219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48220 },
48221/* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48222 {
48223 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40,
6772dd07 48224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48225 },
48226/* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48227 {
48228 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48,
6772dd07 48229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48230 },
48231/* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
48232 {
48233 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32,
6772dd07 48234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48235 },
48236/* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
48237 {
48238 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40,
6772dd07 48239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48240 },
48241/* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
48242 {
48243 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32,
6772dd07 48244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48245 },
48246/* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
48247 {
48248 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40,
6772dd07 48249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48250 },
48251/* bnand${X} ${BitBase32-24-u19-Prefixed} */
48252 {
48253 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40,
6772dd07 48254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48255 },
48256/* bnand${X} ${BitBase32-24-u27-Prefixed} */
48257 {
48258 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48,
6772dd07 48259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48260 },
48261/* bnand${X} $Bitno16R,$Bit16Rn */
48262 {
48263 M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24,
6772dd07 48264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48265 },
48266/* bnand${X} $Bitno16R,$Bit16An */
48267 {
48268 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24,
6772dd07 48269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48270 },
48271/* bnand${X} [$Bit16An] */
48272 {
48273 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16,
6772dd07 48274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48275 },
48276/* bnand${X} ${Dsp-16-u8}[$Bit16An] */
48277 {
48278 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24,
6772dd07 48279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48280 },
48281/* bnand${X} ${Dsp-16-u16}[$Bit16An] */
48282 {
48283 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32,
6772dd07 48284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48285 },
48286/* bnand${X} ${BitBase16-16-u8}[sb] */
48287 {
48288 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24,
6772dd07 48289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48290 },
48291/* bnand${X} ${BitBase16-16-u16}[sb] */
48292 {
48293 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32,
6772dd07 48294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48295 },
48296/* bnand${X} ${BitBase16-16-s8}[fb] */
48297 {
48298 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24,
6772dd07 48299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48300 },
48301/* bnand${X} ${BitBase16-16-u16} */
48302 {
48303 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32,
6772dd07 48304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48305 },
48306/* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48307 {
48308 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24,
6772dd07 48309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48310 },
48311/* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48312 {
48313 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24,
6772dd07 48314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48315 },
48316/* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48317 {
48318 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24,
6772dd07 48319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48320 },
48321/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48322 {
48323 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32,
6772dd07 48324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48325 },
48326/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
48327 {
48328 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32,
6772dd07 48329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48330 },
48331/* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
48332 {
48333 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32,
6772dd07 48334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48335 },
48336/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48337 {
48338 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40,
6772dd07 48339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48340 },
48341/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
48342 {
48343 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40,
6772dd07 48344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48345 },
48346/* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
48347 {
48348 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40,
6772dd07 48349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48350 },
48351/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
48352 {
48353 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40,
6772dd07 48354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48355 },
48356/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48357 {
48358 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48,
6772dd07 48359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48360 },
48361/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
48362 {
48363 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48,
6772dd07 48364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48365 },
48366/* bm${cond16-24} $Bitno16R,$Bit16Rn */
48367 {
48368 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32,
6772dd07 48369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48370 },
48371/* bm${cond16-24} $Bitno16R,$Bit16An */
48372 {
48373 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32,
6772dd07 48374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48375 },
48376/* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
48377 {
48378 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32,
6772dd07 48379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48380 },
48381/* bm${cond16-24} ${BitBase16-16-u8}[sb] */
48382 {
48383 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32,
6772dd07 48384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48385 },
48386/* bm${cond16-24} ${BitBase16-16-s8}[fb] */
48387 {
48388 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32,
6772dd07 48389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48390 },
48391/* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
48392 {
48393 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40,
6772dd07 48394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48395 },
48396/* bm${cond16-32} ${BitBase16-16-u16}[sb] */
48397 {
48398 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40,
6772dd07 48399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48400 },
48401/* bm${cond16-32} ${BitBase16-16-u16} */
48402 {
48403 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40,
6772dd07 48404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48405 },
48406/* bm${cond16-16} [$Bit16An] */
48407 {
48408 M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24,
6772dd07 48409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48410 },
48411/* bitindex.w $Dst32RnUnprefixedHI */
48412 {
48413 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16,
6772dd07 48414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48415 },
48416/* bitindex.w $Dst32AnUnprefixedHI */
48417 {
48418 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16,
6772dd07 48419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48420 },
48421/* bitindex.w [$Dst32AnUnprefixed] */
48422 {
48423 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16,
6772dd07 48424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48425 },
48426/* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48427 {
48428 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24,
6772dd07 48429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48430 },
48431/* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48432 {
48433 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32,
6772dd07 48434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48435 },
48436/* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48437 {
48438 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40,
6772dd07 48439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48440 },
48441/* bitindex.w ${Dsp-16-u8}[sb] */
48442 {
48443 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24,
6772dd07 48444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48445 },
48446/* bitindex.w ${Dsp-16-u16}[sb] */
48447 {
48448 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32,
6772dd07 48449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48450 },
48451/* bitindex.w ${Dsp-16-s8}[fb] */
48452 {
48453 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24,
6772dd07 48454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48455 },
48456/* bitindex.w ${Dsp-16-s16}[fb] */
48457 {
48458 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32,
6772dd07 48459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48460 },
48461/* bitindex.w ${Dsp-16-u16} */
48462 {
48463 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32,
6772dd07 48464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48465 },
48466/* bitindex.w ${Dsp-16-u24} */
48467 {
48468 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40,
6772dd07 48469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48470 },
48471/* bitindex.b $Dst32RnUnprefixedQI */
48472 {
48473 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16,
6772dd07 48474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48475 },
48476/* bitindex.b $Dst32AnUnprefixedQI */
48477 {
48478 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16,
6772dd07 48479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48480 },
48481/* bitindex.b [$Dst32AnUnprefixed] */
48482 {
48483 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16,
6772dd07 48484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48485 },
48486/* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48487 {
48488 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24,
6772dd07 48489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48490 },
48491/* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48492 {
48493 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32,
6772dd07 48494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48495 },
48496/* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48497 {
48498 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40,
6772dd07 48499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48500 },
48501/* bitindex.b ${Dsp-16-u8}[sb] */
48502 {
48503 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24,
6772dd07 48504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48505 },
48506/* bitindex.b ${Dsp-16-u16}[sb] */
48507 {
48508 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32,
6772dd07 48509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48510 },
48511/* bitindex.b ${Dsp-16-s8}[fb] */
48512 {
48513 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24,
6772dd07 48514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48515 },
48516/* bitindex.b ${Dsp-16-s16}[fb] */
48517 {
48518 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32,
6772dd07 48519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48520 },
48521/* bitindex.b ${Dsp-16-u16} */
48522 {
48523 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32,
6772dd07 48524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48525 },
48526/* bitindex.b ${Dsp-16-u24} */
48527 {
48528 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40,
6772dd07 48529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 48530 },
48531/* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48532 {
48533 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16,
6772dd07 48534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48535 },
48536/* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48537 {
48538 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16,
6772dd07 48539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48540 },
48541/* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48542 {
48543 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16,
6772dd07 48544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48545 },
48546/* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48547 {
48548 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24,
6772dd07 48549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48550 },
48551/* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48552 {
48553 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32,
6772dd07 48554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48555 },
48556/* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48557 {
48558 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40,
6772dd07 48559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48560 },
48561/* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
48562 {
48563 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24,
6772dd07 48564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48565 },
48566/* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
48567 {
48568 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32,
6772dd07 48569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48570 },
48571/* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
48572 {
48573 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24,
6772dd07 48574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48575 },
48576/* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48577 {
48578 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32,
6772dd07 48579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48580 },
48581/* bclr${X} ${BitBase32-16-u19-Unprefixed} */
48582 {
48583 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32,
6772dd07 48584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48585 },
48586/* bclr${X} ${BitBase32-16-u27-Unprefixed} */
48587 {
48588 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40,
6772dd07 48589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48590 },
48591/* bclr${G} $Bitno16R,$Bit16Rn */
48592 {
48593 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24,
6772dd07 48594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48595 },
48596/* bclr${G} $Bitno16R,$Bit16An */
48597 {
48598 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24,
6772dd07 48599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48600 },
48601/* bclr${G} ${Dsp-16-u8}[$Bit16An] */
48602 {
48603 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24,
6772dd07 48604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48605 },
48606/* bclr${G} ${BitBase16-16-u8}[sb] */
48607 {
48608 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24,
6772dd07 48609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48610 },
48611/* bclr${G} ${BitBase16-16-s8}[fb] */
48612 {
48613 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24,
6772dd07 48614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48615 },
48616/* bclr${S} ${BitBase16-8-u11-S}[sb] */
48617 {
48618 M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16,
6772dd07 48619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48620 },
48621/* bclr${G} ${Dsp-16-u16}[$Bit16An] */
48622 {
48623 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32,
6772dd07 48624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48625 },
48626/* bclr${G} ${BitBase16-16-u16}[sb] */
48627 {
48628 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32,
6772dd07 48629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48630 },
48631/* bclr${G} ${BitBase16-16-u16} */
48632 {
48633 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32,
6772dd07 48634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48635 },
48636/* bclr${G} [$Bit16An] */
48637 {
48638 M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16,
6772dd07 48639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48640 },
48641/* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48642 {
48643 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24,
6772dd07 48644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48645 },
48646/* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48647 {
48648 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24,
6772dd07 48649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48650 },
48651/* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48652 {
48653 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24,
6772dd07 48654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48655 },
48656/* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48657 {
48658 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32,
6772dd07 48659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48660 },
48661/* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48662 {
48663 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40,
6772dd07 48664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48665 },
48666/* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48667 {
48668 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48,
6772dd07 48669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48670 },
48671/* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
48672 {
48673 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32,
6772dd07 48674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48675 },
48676/* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
48677 {
48678 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40,
6772dd07 48679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48680 },
48681/* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
48682 {
48683 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32,
6772dd07 48684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48685 },
48686/* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
48687 {
48688 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40,
6772dd07 48689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48690 },
48691/* band${X} ${BitBase32-24-u19-Prefixed} */
48692 {
48693 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40,
6772dd07 48694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48695 },
48696/* band${X} ${BitBase32-24-u27-Prefixed} */
48697 {
48698 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48,
6772dd07 48699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48700 },
48701/* band${X} $Bitno16R,$Bit16Rn */
48702 {
48703 M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24,
6772dd07 48704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48705 },
48706/* band${X} $Bitno16R,$Bit16An */
48707 {
48708 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24,
6772dd07 48709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48710 },
48711/* band${X} [$Bit16An] */
48712 {
48713 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16,
6772dd07 48714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48715 },
48716/* band${X} ${Dsp-16-u8}[$Bit16An] */
48717 {
48718 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24,
6772dd07 48719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48720 },
48721/* band${X} ${Dsp-16-u16}[$Bit16An] */
48722 {
48723 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32,
6772dd07 48724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48725 },
48726/* band${X} ${BitBase16-16-u8}[sb] */
48727 {
48728 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24,
6772dd07 48729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48730 },
48731/* band${X} ${BitBase16-16-u16}[sb] */
48732 {
48733 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32,
6772dd07 48734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48735 },
48736/* band${X} ${BitBase16-16-s8}[fb] */
48737 {
48738 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24,
6772dd07 48739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48740 },
48741/* band${X} ${BitBase16-16-u16} */
48742 {
48743 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32,
6772dd07 48744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48745 },
48746/* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48747 {
48748 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32,
6772dd07 48749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48750 },
48751/* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48752 {
48753 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32,
6772dd07 48754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48755 },
48756/* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48757 {
48758 M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40,
6772dd07 48759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48760 },
48761/* and.w${S} #${Imm-8-HI},r0 */
48762 {
48763 M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24,
6772dd07 48764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48765 },
48766/* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48767 {
48768 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24,
6772dd07 48769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48770 },
48771/* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48772 {
48773 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24,
6772dd07 48774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48775 },
48776/* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48777 {
48778 M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32,
6772dd07 48779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48780 },
48781/* and.b${S} #${Imm-8-QI},r0l */
48782 {
48783 M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16,
6772dd07 48784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48785 },
48786/* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
48787 {
48788 M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8,
6772dd07 48789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48790 },
48791/* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
48792 {
48793 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16,
6772dd07 48794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48795 },
48796/* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
48797 {
48798 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16,
6772dd07 48799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48800 },
48801/* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
48802 {
48803 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24,
6772dd07 48804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 48805 },
48806/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48807 {
48808 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
6772dd07 48809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48810 },
48811/* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
48812 {
48813 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
6772dd07 48814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48815 },
48816/* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
48817 {
48818 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
6772dd07 48819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48820 },
48821/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48822 {
48823 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
6772dd07 48824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48825 },
48826/* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
48827 {
48828 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
6772dd07 48829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48830 },
48831/* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
48832 {
48833 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
6772dd07 48834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48835 },
48836/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48837 {
48838 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
6772dd07 48839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48840 },
48841/* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48842 {
48843 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
6772dd07 48844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48845 },
48846/* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48847 {
48848 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
6772dd07 48849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48850 },
48851/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48852 {
48853 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48855 },
48856/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48857 {
48858 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48860 },
48861/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48862 {
48863 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48865 },
48866/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48867 {
48868 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48870 },
48871/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48872 {
48873 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48875 },
48876/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48877 {
48878 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48880 },
48881/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48882 {
48883 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 48884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48885 },
48886/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48887 {
48888 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 48889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48890 },
48891/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48892 {
48893 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 48894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48895 },
48896/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48897 {
48898 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48900 },
48901/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48902 {
48903 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48905 },
48906/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48907 {
48908 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48910 },
48911/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48912 {
48913 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48915 },
48916/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48917 {
48918 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48920 },
48921/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48922 {
48923 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48925 },
48926/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48927 {
48928 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48930 },
48931/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48932 {
48933 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48935 },
48936/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48937 {
48938 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 48939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48940 },
48941/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48942 {
48943 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48945 },
48946/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48947 {
48948 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48950 },
48951/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48952 {
48953 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 48954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48955 },
48956/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48957 {
48958 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
6772dd07 48959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48960 },
48961/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48962 {
48963 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
6772dd07 48964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48965 },
48966/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48967 {
48968 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
6772dd07 48969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48970 },
48971/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48972 {
48973 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 48974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48975 },
48976/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48977 {
48978 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 48979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48980 },
48981/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48982 {
48983 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 48984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48985 },
48986/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48987 {
48988 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
6772dd07 48989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48990 },
48991/* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
48992 {
48993 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
6772dd07 48994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 48995 },
48996/* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
48997 {
48998 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
6772dd07 48999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49000 },
49001/* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
49002 {
49003 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
6772dd07 49004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49005 },
49006/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49007 {
49008 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
6772dd07 49009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49010 },
49011/* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
49012 {
49013 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
6772dd07 49014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49015 },
49016/* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
49017 {
49018 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
6772dd07 49019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49020 },
49021/* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
49022 {
49023 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
6772dd07 49024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49025 },
49026/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49027 {
49028 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
6772dd07 49029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49030 },
49031/* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49032 {
49033 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
6772dd07 49034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49035 },
49036/* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49037 {
49038 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
6772dd07 49039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49040 },
49041/* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49042 {
49043 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
6772dd07 49044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49045 },
49046/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49047 {
49048 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49050 },
49051/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49052 {
49053 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49055 },
49056/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49057 {
49058 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49060 },
49061/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49062 {
49063 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49065 },
49066/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49067 {
49068 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49070 },
49071/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49072 {
49073 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49075 },
49076/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49077 {
49078 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49080 },
49081/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49082 {
49083 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49085 },
49086/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49087 {
49088 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49090 },
49091/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49092 {
49093 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49095 },
49096/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49097 {
49098 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49100 },
49101/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49102 {
49103 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49105 },
49106/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49107 {
49108 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49110 },
49111/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49112 {
49113 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49115 },
49116/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49117 {
49118 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49120 },
49121/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49122 {
49123 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49125 },
49126/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49127 {
49128 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49130 },
49131/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49132 {
49133 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49135 },
49136/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49137 {
49138 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49140 },
49141/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49142 {
49143 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49145 },
49146/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49147 {
49148 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49150 },
49151/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49152 {
49153 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49155 },
49156/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49157 {
49158 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49160 },
49161/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49162 {
49163 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49165 },
49166/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49167 {
49168 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49170 },
49171/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49172 {
49173 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49175 },
49176/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49177 {
49178 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49180 },
49181/* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49182 {
49183 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49185 },
49186/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49187 {
49188 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 49189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49190 },
49191/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49192 {
49193 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 49194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49195 },
49196/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49197 {
49198 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 49199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49200 },
49201/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
49202 {
49203 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 49204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49205 },
49206/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49207 {
49208 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
6772dd07 49209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49210 },
49211/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49212 {
49213 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
6772dd07 49214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49215 },
49216/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49217 {
49218 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
6772dd07 49219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49220 },
49221/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
49222 {
49223 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
6772dd07 49224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49225 },
49226/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49227 {
49228 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
6772dd07 49229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49230 },
49231/* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
49232 {
49233 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
6772dd07 49234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49235 },
49236/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49237 {
49238 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
6772dd07 49239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49240 },
49241/* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
49242 {
49243 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
6772dd07 49244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49245 },
49246/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49247 {
49248 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
6772dd07 49249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49250 },
49251/* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49252 {
49253 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
6772dd07 49254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49255 },
49256/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49257 {
49258 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49260 },
49261/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49262 {
49263 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49265 },
49266/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49267 {
49268 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49270 },
49271/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49272 {
49273 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49275 },
49276/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49277 {
49278 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
6772dd07 49279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49280 },
49281/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49282 {
49283 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
6772dd07 49284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49285 },
49286/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49287 {
49288 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49290 },
49291/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49292 {
49293 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49295 },
49296/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49297 {
49298 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49300 },
49301/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49302 {
49303 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49305 },
49306/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49307 {
49308 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49310 },
49311/* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49312 {
49313 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 49314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49315 },
49316/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49317 {
49318 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49320 },
49321/* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49322 {
49323 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
6772dd07 49324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49325 },
49326/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49327 {
49328 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
6772dd07 49329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49330 },
49331/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
49332 {
49333 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
6772dd07 49334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49335 },
49336/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49337 {
49338 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
6772dd07 49339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49340 },
49341/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
49342 {
49343 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
6772dd07 49344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49345 },
49346/* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
49347 {
49348 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
6772dd07 49349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49350 },
49351/* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
49352 {
49353 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
6772dd07 49354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49355 },
49356/* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49357 {
49358 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
6772dd07 49359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49360 },
49361/* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
49362 {
49363 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
6772dd07 49364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49365 },
49366/* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
49367 {
49368 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
6772dd07 49369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49370 },
49371/* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49372 {
49373 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
6772dd07 49374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49375 },
49376/* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
49377 {
49378 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
6772dd07 49379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49380 },
49381/* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
49382 {
49383 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
6772dd07 49384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49385 },
49386/* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49387 {
49388 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
6772dd07 49389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49390 },
49391/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49392 {
49393 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49395 },
49396/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49397 {
49398 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49400 },
49401/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49402 {
49403 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49405 },
49406/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49407 {
49408 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49410 },
49411/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49412 {
49413 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49415 },
49416/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49417 {
49418 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49420 },
49421/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49422 {
49423 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49425 },
49426/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49427 {
49428 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49430 },
49431/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49432 {
49433 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 49434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49435 },
49436/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49437 {
49438 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49440 },
49441/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49442 {
49443 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49445 },
49446/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49447 {
49448 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49450 },
49451/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49452 {
49453 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49455 },
49456/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49457 {
49458 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49460 },
49461/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49462 {
49463 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49465 },
49466/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49467 {
49468 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49470 },
49471/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49472 {
49473 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49475 },
49476/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49477 {
49478 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
6772dd07 49479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49480 },
49481/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49482 {
49483 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49485 },
49486/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49487 {
49488 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49490 },
49491/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49492 {
49493 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
6772dd07 49494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49495 },
49496/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49497 {
49498 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
6772dd07 49499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49500 },
49501/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49502 {
49503 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
6772dd07 49504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49505 },
49506/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49507 {
49508 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
6772dd07 49509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49510 },
49511/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49512 {
49513 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
6772dd07 49514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49515 },
49516/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49517 {
49518 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
6772dd07 49519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49520 },
49521/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49522 {
49523 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
6772dd07 49524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49525 },
49526/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49527 {
49528 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
6772dd07 49529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49530 },
49531/* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49532 {
49533 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
6772dd07 49534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49535 },
49536/* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49537 {
49538 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
6772dd07 49539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49540 },
49541/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49542 {
49543 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
6772dd07 49544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49545 },
49546/* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49547 {
49548 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
6772dd07 49549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49550 },
49551/* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49552 {
49553 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
6772dd07 49554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49555 },
49556/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49557 {
49558 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
6772dd07 49559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49560 },
49561/* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49562 {
49563 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
6772dd07 49564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49565 },
49566/* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49567 {
49568 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
6772dd07 49569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49570 },
49571/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49572 {
49573 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49575 },
49576/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49577 {
49578 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49580 },
49581/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49582 {
49583 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49585 },
49586/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49587 {
49588 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49590 },
49591/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49592 {
49593 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49595 },
49596/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49597 {
49598 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49600 },
49601/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49602 {
49603 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49605 },
49606/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49607 {
49608 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49610 },
49611/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49612 {
49613 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49615 },
49616/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49617 {
49618 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49620 },
49621/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49622 {
49623 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49625 },
49626/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49627 {
49628 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49630 },
49631/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49632 {
49633 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49635 },
49636/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49637 {
49638 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49640 },
49641/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49642 {
49643 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49645 },
49646/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49647 {
49648 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49650 },
49651/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49652 {
49653 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49655 },
49656/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49657 {
49658 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 49659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49660 },
49661/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49662 {
49663 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49665 },
49666/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49667 {
49668 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49670 },
49671/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49672 {
49673 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49675 },
49676/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49677 {
49678 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
6772dd07 49679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49680 },
49681/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49682 {
49683 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
6772dd07 49684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49685 },
49686/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49687 {
49688 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
6772dd07 49689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49690 },
49691/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49692 {
49693 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 49694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49695 },
49696/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49697 {
49698 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 49699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49700 },
49701/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49702 {
49703 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 49704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49705 },
49706/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49707 {
49708 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49710 },
49711/* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
49712 {
49713 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49715 },
49716/* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
49717 {
49718 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49720 },
49721/* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
49722 {
49723 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49725 },
49726/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49727 {
49728 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49730 },
49731/* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
49732 {
49733 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49735 },
49736/* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
49737 {
49738 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49740 },
49741/* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
49742 {
49743 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
6772dd07 49744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49745 },
49746/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49747 {
49748 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
6772dd07 49749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49750 },
49751/* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49752 {
49753 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
6772dd07 49754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49755 },
49756/* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49757 {
49758 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
6772dd07 49759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49760 },
49761/* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49762 {
49763 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
6772dd07 49764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49765 },
49766/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49767 {
49768 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49770 },
49771/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49772 {
49773 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49775 },
49776/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49777 {
49778 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49780 },
49781/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49782 {
49783 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49785 },
49786/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49787 {
49788 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49790 },
49791/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49792 {
49793 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49795 },
49796/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49797 {
49798 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49800 },
49801/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49802 {
49803 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49805 },
49806/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49807 {
49808 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
6772dd07 49809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49810 },
49811/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49812 {
49813 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
6772dd07 49814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49815 },
49816/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49817 {
49818 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
6772dd07 49819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49820 },
49821/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49822 {
49823 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
6772dd07 49824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49825 },
49826/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49827 {
49828 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49830 },
49831/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49832 {
49833 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49835 },
49836/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49837 {
49838 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49840 },
49841/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49842 {
49843 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49845 },
49846/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49847 {
49848 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49850 },
49851/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49852 {
49853 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49855 },
49856/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49857 {
49858 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49860 },
49861/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49862 {
49863 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49865 },
49866/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49867 {
49868 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49870 },
49871/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49872 {
49873 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49875 },
49876/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49877 {
49878 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49880 },
49881/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49882 {
49883 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 49884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49885 },
49886/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49887 {
49888 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49890 },
49891/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49892 {
49893 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49895 },
49896/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49897 {
49898 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49900 },
49901/* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49902 {
49903 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49905 },
49906/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49907 {
49908 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 49909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49910 },
49911/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49912 {
49913 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 49914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49915 },
49916/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49917 {
49918 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 49919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49920 },
49921/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
49922 {
49923 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 49924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49925 },
49926/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49927 {
49928 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
6772dd07 49929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49930 },
49931/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49932 {
49933 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
6772dd07 49934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49935 },
49936/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49937 {
49938 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
6772dd07 49939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49940 },
49941/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
49942 {
49943 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
6772dd07 49944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49945 },
49946/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49947 {
49948 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
6772dd07 49949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49950 },
49951/* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
49952 {
49953 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
6772dd07 49954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49955 },
49956/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49957 {
49958 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
6772dd07 49959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49960 },
49961/* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
49962 {
49963 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
6772dd07 49964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49965 },
49966/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49967 {
49968 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
6772dd07 49969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49970 },
49971/* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49972 {
49973 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
6772dd07 49974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49975 },
49976/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49977 {
49978 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49980 },
49981/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49982 {
49983 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 49984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49985 },
49986/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49987 {
49988 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
6772dd07 49989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49990 },
49991/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49992 {
49993 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
6772dd07 49994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 49995 },
49996/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49997 {
49998 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
6772dd07 49999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50000 },
50001/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
50002 {
50003 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
6772dd07 50004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50005 },
50006/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
50007 {
50008 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 50009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50010 },
50011/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
50012 {
50013 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 50014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50015 },
50016/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
50017 {
50018 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
6772dd07 50019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50020 },
50021/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
50022 {
50023 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
6772dd07 50024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50025 },
50026/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
50027 {
50028 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 50029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50030 },
50031/* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
50032 {
50033 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
6772dd07 50034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50035 },
50036/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
50037 {
50038 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
6772dd07 50039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50040 },
50041/* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
50042 {
50043 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
6772dd07 50044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50045 },
50046/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
50047 {
50048 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
6772dd07 50049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50050 },
50051/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
50052 {
50053 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
6772dd07 50054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50055 },
50056/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
50057 {
50058 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
6772dd07 50059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50060 },
50061/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
50062 {
50063 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
6772dd07 50064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50065 },
50066/* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
50067 {
50068 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
6772dd07 50069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50070 },
50071/* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
50072 {
50073 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
6772dd07 50074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50075 },
50076/* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50077 {
50078 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
6772dd07 50079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50080 },
50081/* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
50082 {
50083 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
6772dd07 50084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50085 },
50086/* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
50087 {
50088 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
6772dd07 50089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50090 },
50091/* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50092 {
50093 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
6772dd07 50094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50095 },
50096/* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
50097 {
50098 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
6772dd07 50099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50100 },
50101/* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
50102 {
50103 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
6772dd07 50104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50105 },
50106/* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50107 {
50108 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
6772dd07 50109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50110 },
50111/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50112 {
50113 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50115 },
50116/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50117 {
50118 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50120 },
50121/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
50122 {
50123 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50125 },
50126/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50127 {
50128 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50130 },
50131/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50132 {
50133 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50135 },
50136/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
50137 {
50138 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50140 },
50141/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50142 {
50143 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 50144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50145 },
50146/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50147 {
50148 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 50149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50150 },
50151/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
50152 {
50153 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 50154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50155 },
50156/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
50157 {
50158 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50160 },
50161/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
50162 {
50163 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50165 },
50166/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
50167 {
50168 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50170 },
50171/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
50172 {
50173 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50175 },
50176/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
50177 {
50178 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50180 },
50181/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
50182 {
50183 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50185 },
50186/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
50187 {
50188 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50190 },
50191/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
50192 {
50193 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50195 },
50196/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
50197 {
50198 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
6772dd07 50199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50200 },
50201/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
50202 {
50203 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50205 },
50206/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
50207 {
50208 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50210 },
50211/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
50212 {
50213 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 50214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50215 },
50216/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
50217 {
50218 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
6772dd07 50219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50220 },
50221/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
50222 {
50223 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
6772dd07 50224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50225 },
50226/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
50227 {
50228 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
6772dd07 50229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50230 },
50231/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
50232 {
50233 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
6772dd07 50234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50235 },
50236/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
50237 {
50238 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
6772dd07 50239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50240 },
50241/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
50242 {
50243 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
6772dd07 50244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50245 },
50246/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
50247 {
50248 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
6772dd07 50249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50250 },
50251/* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
50252 {
50253 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
6772dd07 50254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50255 },
50256/* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
50257 {
50258 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
6772dd07 50259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50260 },
50261/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
50262 {
50263 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24,
6772dd07 50264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50265 },
50266/* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
50267 {
50268 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24,
6772dd07 50269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50270 },
50271/* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
50272 {
50273 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24,
6772dd07 50274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50275 },
50276/* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50277 {
50278 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24,
6772dd07 50279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50280 },
50281/* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50282 {
50283 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
6772dd07 50284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50285 },
50286/* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50287 {
50288 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
6772dd07 50289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50290 },
50291/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50292 {
50293 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
6772dd07 50294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50295 },
50296/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50297 {
50298 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
6772dd07 50299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50300 },
50301/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50302 {
50303 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
6772dd07 50304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50305 },
50306/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50307 {
50308 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
6772dd07 50309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50310 },
50311/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50312 {
50313 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
6772dd07 50314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50315 },
50316/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50317 {
50318 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
6772dd07 50319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50320 },
50321/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50322 {
50323 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
6772dd07 50324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50325 },
50326/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50327 {
50328 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
6772dd07 50329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50330 },
50331/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50332 {
50333 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
6772dd07 50334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50335 },
50336/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50337 {
50338 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
6772dd07 50339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50340 },
50341/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50342 {
50343 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
6772dd07 50344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50345 },
50346/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50347 {
50348 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
6772dd07 50349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50350 },
50351/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50352 {
50353 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
6772dd07 50354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50355 },
50356/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50357 {
50358 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
6772dd07 50359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50360 },
50361/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50362 {
50363 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
6772dd07 50364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50365 },
50366/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50367 {
50368 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
6772dd07 50369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50370 },
50371/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50372 {
50373 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
6772dd07 50374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50375 },
50376/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50377 {
50378 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
6772dd07 50379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50380 },
50381/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
50382 {
50383 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
6772dd07 50384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50385 },
50386/* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
50387 {
50388 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
6772dd07 50389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50390 },
50391/* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
50392 {
50393 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32,
6772dd07 50394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50395 },
50396/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
50397 {
50398 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32,
6772dd07 50399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50400 },
50401/* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
50402 {
50403 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32,
6772dd07 50404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50405 },
50406/* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
50407 {
50408 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32,
6772dd07 50409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50410 },
50411/* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50412 {
50413 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32,
6772dd07 50414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50415 },
50416/* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50417 {
50418 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32,
6772dd07 50419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50420 },
50421/* and.w${G} ${Dsp-16-u16},[$Dst16An] */
50422 {
50423 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32,
6772dd07 50424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50425 },
50426/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50427 {
50428 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
6772dd07 50429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50430 },
50431/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50432 {
50433 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
6772dd07 50434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50435 },
50436/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50437 {
50438 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40,
6772dd07 50439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50440 },
50441/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50442 {
50443 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
6772dd07 50444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50445 },
50446/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50447 {
50448 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
6772dd07 50449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50450 },
50451/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50452 {
50453 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48,
6772dd07 50454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50455 },
50456/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50457 {
50458 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
6772dd07 50459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50460 },
50461/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50462 {
50463 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
6772dd07 50464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50465 },
50466/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50467 {
50468 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
6772dd07 50469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50470 },
50471/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50472 {
50473 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
6772dd07 50474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50475 },
50476/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50477 {
50478 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
6772dd07 50479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50480 },
50481/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50482 {
50483 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
6772dd07 50484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50485 },
50486/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50487 {
50488 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
6772dd07 50489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50490 },
50491/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50492 {
50493 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
6772dd07 50494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50495 },
50496/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50497 {
50498 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
6772dd07 50499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50500 },
50501/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50502 {
50503 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
6772dd07 50504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50505 },
50506/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50507 {
50508 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
6772dd07 50509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50510 },
50511/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
50512 {
50513 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48,
6772dd07 50514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50515 },
50516/* and.w${G} $Src16RnHI,$Dst16RnHI */
50517 {
50518 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
6772dd07 50519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50520 },
50521/* and.w${G} $Src16AnHI,$Dst16RnHI */
50522 {
50523 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
6772dd07 50524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50525 },
50526/* and.w${G} [$Src16An],$Dst16RnHI */
50527 {
50528 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16,
6772dd07 50529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50530 },
50531/* and.w${G} $Src16RnHI,$Dst16AnHI */
50532 {
50533 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16,
6772dd07 50534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50535 },
50536/* and.w${G} $Src16AnHI,$Dst16AnHI */
50537 {
50538 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16,
6772dd07 50539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50540 },
50541/* and.w${G} [$Src16An],$Dst16AnHI */
50542 {
50543 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16,
6772dd07 50544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50545 },
50546/* and.w${G} $Src16RnHI,[$Dst16An] */
50547 {
50548 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16,
6772dd07 50549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50550 },
50551/* and.w${G} $Src16AnHI,[$Dst16An] */
50552 {
50553 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16,
6772dd07 50554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50555 },
50556/* and.w${G} [$Src16An],[$Dst16An] */
50557 {
50558 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16,
6772dd07 50559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50560 },
50561/* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
50562 {
50563 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
6772dd07 50564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50565 },
50566/* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
50567 {
50568 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
6772dd07 50569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50570 },
50571/* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50572 {
50573 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24,
6772dd07 50574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50575 },
50576/* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
50577 {
50578 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
6772dd07 50579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50580 },
50581/* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
50582 {
50583 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
6772dd07 50584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50585 },
50586/* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50587 {
50588 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32,
6772dd07 50589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50590 },
50591/* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
50592 {
50593 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
6772dd07 50594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50595 },
50596/* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
50597 {
50598 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
6772dd07 50599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50600 },
50601/* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
50602 {
50603 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
6772dd07 50604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50605 },
50606/* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
50607 {
50608 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
6772dd07 50609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50610 },
50611/* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
50612 {
50613 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
6772dd07 50614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50615 },
50616/* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
50617 {
50618 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
6772dd07 50619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50620 },
50621/* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
50622 {
50623 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
6772dd07 50624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50625 },
50626/* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
50627 {
50628 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
6772dd07 50629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50630 },
50631/* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
50632 {
50633 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
6772dd07 50634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50635 },
50636/* and.w${G} $Src16RnHI,${Dsp-16-u16} */
50637 {
50638 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
6772dd07 50639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50640 },
50641/* and.w${G} $Src16AnHI,${Dsp-16-u16} */
50642 {
50643 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
6772dd07 50644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50645 },
50646/* and.w${G} [$Src16An],${Dsp-16-u16} */
50647 {
50648 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32,
6772dd07 50649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50650 },
50651/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
50652 {
50653 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
6772dd07 50654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50655 },
50656/* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
50657 {
50658 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
6772dd07 50659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50660 },
50661/* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
50662 {
50663 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
6772dd07 50664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50665 },
50666/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
50667 {
50668 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24,
6772dd07 50669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50670 },
50671/* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
50672 {
50673 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24,
6772dd07 50674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50675 },
50676/* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
50677 {
50678 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24,
6772dd07 50679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50680 },
50681/* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50682 {
50683 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24,
6772dd07 50684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50685 },
50686/* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50687 {
50688 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
6772dd07 50689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50690 },
50691/* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50692 {
50693 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
6772dd07 50694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50695 },
50696/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50697 {
50698 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
6772dd07 50699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50700 },
50701/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50702 {
50703 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
6772dd07 50704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50705 },
50706/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50707 {
50708 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
6772dd07 50709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50710 },
50711/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50712 {
50713 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
6772dd07 50714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50715 },
50716/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50717 {
50718 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
6772dd07 50719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50720 },
50721/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50722 {
50723 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
6772dd07 50724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50725 },
50726/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50727 {
50728 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
6772dd07 50729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50730 },
50731/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50732 {
50733 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
6772dd07 50734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50735 },
50736/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50737 {
50738 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
6772dd07 50739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50740 },
50741/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50742 {
50743 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
6772dd07 50744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50745 },
50746/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50747 {
50748 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
6772dd07 50749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50750 },
50751/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50752 {
50753 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
6772dd07 50754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50755 },
50756/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50757 {
50758 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
6772dd07 50759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50760 },
50761/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50762 {
50763 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
6772dd07 50764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50765 },
50766/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50767 {
50768 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
6772dd07 50769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50770 },
50771/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50772 {
50773 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
6772dd07 50774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50775 },
50776/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50777 {
50778 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
6772dd07 50779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50780 },
50781/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50782 {
50783 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
6772dd07 50784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50785 },
50786/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
50787 {
50788 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
6772dd07 50789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50790 },
50791/* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
50792 {
50793 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
6772dd07 50794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50795 },
50796/* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
50797 {
50798 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32,
6772dd07 50799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50800 },
50801/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
50802 {
50803 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32,
6772dd07 50804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50805 },
50806/* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
50807 {
50808 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32,
6772dd07 50809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50810 },
50811/* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
50812 {
50813 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32,
6772dd07 50814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50815 },
50816/* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50817 {
50818 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32,
6772dd07 50819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50820 },
50821/* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50822 {
50823 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32,
6772dd07 50824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50825 },
50826/* and.b${G} ${Dsp-16-u16},[$Dst16An] */
50827 {
50828 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32,
6772dd07 50829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50830 },
50831/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50832 {
50833 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
6772dd07 50834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50835 },
50836/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50837 {
50838 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
6772dd07 50839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50840 },
50841/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50842 {
50843 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40,
6772dd07 50844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50845 },
50846/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50847 {
50848 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
6772dd07 50849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50850 },
50851/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50852 {
50853 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
6772dd07 50854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50855 },
50856/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50857 {
50858 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48,
6772dd07 50859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50860 },
50861/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50862 {
50863 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
6772dd07 50864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50865 },
50866/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50867 {
50868 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
6772dd07 50869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50870 },
50871/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50872 {
50873 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
6772dd07 50874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50875 },
50876/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50877 {
50878 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
6772dd07 50879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50880 },
50881/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50882 {
50883 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
6772dd07 50884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50885 },
50886/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50887 {
50888 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
6772dd07 50889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50890 },
50891/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50892 {
50893 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
6772dd07 50894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50895 },
50896/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50897 {
50898 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
6772dd07 50899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50900 },
50901/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50902 {
50903 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
6772dd07 50904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50905 },
50906/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50907 {
50908 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
6772dd07 50909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50910 },
50911/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50912 {
50913 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
6772dd07 50914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50915 },
50916/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
50917 {
50918 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48,
6772dd07 50919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50920 },
50921/* and.b${G} $Src16RnQI,$Dst16RnQI */
50922 {
50923 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
6772dd07 50924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50925 },
50926/* and.b${G} $Src16AnQI,$Dst16RnQI */
50927 {
50928 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
6772dd07 50929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50930 },
50931/* and.b${G} [$Src16An],$Dst16RnQI */
50932 {
50933 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16,
6772dd07 50934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50935 },
50936/* and.b${G} $Src16RnQI,$Dst16AnQI */
50937 {
50938 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16,
6772dd07 50939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50940 },
50941/* and.b${G} $Src16AnQI,$Dst16AnQI */
50942 {
50943 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16,
6772dd07 50944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50945 },
50946/* and.b${G} [$Src16An],$Dst16AnQI */
50947 {
50948 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16,
6772dd07 50949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50950 },
50951/* and.b${G} $Src16RnQI,[$Dst16An] */
50952 {
50953 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16,
6772dd07 50954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50955 },
50956/* and.b${G} $Src16AnQI,[$Dst16An] */
50957 {
50958 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16,
6772dd07 50959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50960 },
50961/* and.b${G} [$Src16An],[$Dst16An] */
50962 {
50963 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16,
6772dd07 50964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50965 },
50966/* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
50967 {
50968 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
6772dd07 50969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50970 },
50971/* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
50972 {
50973 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
6772dd07 50974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50975 },
50976/* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50977 {
50978 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24,
6772dd07 50979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50980 },
50981/* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
50982 {
50983 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
6772dd07 50984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50985 },
50986/* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
50987 {
50988 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
6772dd07 50989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50990 },
50991/* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50992 {
50993 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32,
6772dd07 50994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 50995 },
50996/* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
50997 {
50998 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
6772dd07 50999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51000 },
51001/* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
51002 {
51003 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
6772dd07 51004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51005 },
51006/* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
51007 {
51008 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
6772dd07 51009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51010 },
51011/* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
51012 {
51013 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
6772dd07 51014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51015 },
51016/* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
51017 {
51018 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
6772dd07 51019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51020 },
51021/* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
51022 {
51023 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
6772dd07 51024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51025 },
51026/* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
51027 {
51028 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
6772dd07 51029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51030 },
51031/* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
51032 {
51033 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
6772dd07 51034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51035 },
51036/* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
51037 {
51038 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
6772dd07 51039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51040 },
51041/* and.b${G} $Src16RnQI,${Dsp-16-u16} */
51042 {
51043 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
6772dd07 51044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51045 },
51046/* and.b${G} $Src16AnQI,${Dsp-16-u16} */
51047 {
51048 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
6772dd07 51049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51050 },
51051/* and.b${G} [$Src16An],${Dsp-16-u16} */
51052 {
51053 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32,
6772dd07 51054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51055 },
51056/* and.b${S} #${Imm-8-QI},r0l */
51057 {
51058 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16,
6772dd07 51059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51060 },
51061/* and.b${S} #${Imm-8-QI},r0h */
51062 {
51063 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16,
6772dd07 51064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51065 },
51066/* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
51067 {
51068 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24,
6772dd07 51069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51070 },
51071/* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
51072 {
51073 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24,
6772dd07 51074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51075 },
51076/* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
51077 {
51078 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32,
6772dd07 51079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51080 },
51081/* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
51082 {
51083 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
6772dd07 51084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51085 },
51086/* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
51087 {
51088 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32,
6772dd07 51089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51090 },
51091/* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
51092 {
51093 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
6772dd07 51094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51095 },
51096/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51097 {
51098 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40,
6772dd07 51099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51100 },
51101/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51102 {
51103 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 51104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51105 },
51106/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51107 {
51108 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40,
6772dd07 51109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51110 },
51111/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51112 {
51113 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48,
6772dd07 51114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51115 },
51116/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51117 {
51118 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 51119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51120 },
51121/* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
51122 {
51123 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48,
6772dd07 51124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51125 },
51126/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51127 {
51128 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48,
6772dd07 51129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51130 },
51131/* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51132 {
51133 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56,
6772dd07 51134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51135 },
51136/* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
51137 {
51138 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56,
6772dd07 51139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51140 },
51141/* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
51142 {
51143 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
6772dd07 51144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51145 },
51146/* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
51147 {
51148 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24,
6772dd07 51149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51150 },
51151/* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51152 {
51153 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
6772dd07 51154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51155 },
51156/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51157 {
51158 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32,
6772dd07 51159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51160 },
51161/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51162 {
51163 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 51164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51165 },
51166/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51167 {
51168 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32,
6772dd07 51169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51170 },
51171/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51172 {
51173 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40,
6772dd07 51174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51175 },
51176/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51177 {
51178 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 51179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51180 },
51181/* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51182 {
51183 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40,
6772dd07 51184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51185 },
51186/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51187 {
51188 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40,
6772dd07 51189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51190 },
51191/* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51192 {
51193 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48,
6772dd07 51194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51195 },
51196/* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
51197 {
51198 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48,
6772dd07 51199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51200 },
51201/* and.w${G} #${Imm-16-HI},$Dst16RnHI */
51202 {
51203 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32,
6772dd07 51204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51205 },
51206/* and.w${G} #${Imm-16-HI},$Dst16AnHI */
51207 {
51208 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32,
6772dd07 51209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51210 },
51211/* and.w${G} #${Imm-16-HI},[$Dst16An] */
51212 {
51213 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32,
6772dd07 51214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51215 },
51216/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
51217 {
51218 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40,
6772dd07 51219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51220 },
51221/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51222 {
51223 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40,
6772dd07 51224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51225 },
51226/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51227 {
51228 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40,
6772dd07 51229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51230 },
51231/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
51232 {
51233 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48,
6772dd07 51234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51235 },
51236/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51237 {
51238 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48,
6772dd07 51239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51240 },
51241/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51242 {
51243 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48,
6772dd07 51244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51245 },
51246/* and.b${G} #${Imm-16-QI},$Dst16RnQI */
51247 {
51248 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24,
6772dd07 51249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51250 },
51251/* and.b${G} #${Imm-16-QI},$Dst16AnQI */
51252 {
51253 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24,
6772dd07 51254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51255 },
51256/* and.b${G} #${Imm-16-QI},[$Dst16An] */
51257 {
51258 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24,
6772dd07 51259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51260 },
51261/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
51262 {
51263 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32,
6772dd07 51264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51265 },
51266/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51267 {
51268 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32,
6772dd07 51269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51270 },
51271/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51272 {
51273 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32,
6772dd07 51274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51275 },
51276/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
51277 {
51278 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40,
6772dd07 51279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51280 },
51281/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51282 {
51283 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40,
6772dd07 51284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51285 },
51286/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51287 {
51288 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40,
6772dd07 51289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 51290 },
51291/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51292 {
51293 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32,
6772dd07 51294 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51295 },
51296/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51297 {
51298 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32,
6772dd07 51299 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51300 },
51301/* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51302 {
51303 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32,
6772dd07 51304 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51305 },
51306/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51307 {
51308 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40,
6772dd07 51309 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51310 },
51311/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51312 {
51313 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40,
6772dd07 51314 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51315 },
51316/* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51317 {
51318 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40,
6772dd07 51319 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51320 },
51321/* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51322 {
51323 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40,
6772dd07 51324 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51325 },
51326/* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51327 {
51328 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48,
6772dd07 51329 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51330 },
51331/* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51332 {
51333 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48,
6772dd07 51334 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51335 },
51336/* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
51337 {
51338 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24,
6772dd07 51339 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51340 },
51341/* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
51342 {
51343 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24,
6772dd07 51344 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51345 },
51346/* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51347 {
51348 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24,
6772dd07 51349 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51350 },
51351/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51352 {
51353 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32,
6772dd07 51354 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51355 },
51356/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51357 {
51358 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32,
6772dd07 51359 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51360 },
51361/* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51362 {
51363 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32,
6772dd07 51364 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51365 },
51366/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51367 {
51368 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40,
6772dd07 51369 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51370 },
51371/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51372 {
51373 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40,
6772dd07 51374 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51375 },
51376/* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51377 {
51378 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40,
6772dd07 51379 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51380 },
51381/* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51382 {
51383 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40,
6772dd07 51384 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51385 },
51386/* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51387 {
51388 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48,
6772dd07 51389 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51390 },
51391/* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51392 {
51393 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48,
6772dd07 51394 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51395 },
51396/* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
51397 {
51398 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24,
6772dd07 51399 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51400 },
51401/* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
51402 {
51403 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24,
6772dd07 51404 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51405 },
51406/* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51407 {
51408 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24,
6772dd07 51409 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51410 },
51411/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51412 {
51413 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32,
6772dd07 51414 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51415 },
51416/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51417 {
51418 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32,
6772dd07 51419 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51420 },
51421/* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51422 {
51423 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32,
6772dd07 51424 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51425 },
51426/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51427 {
51428 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40,
6772dd07 51429 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51430 },
51431/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51432 {
51433 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40,
6772dd07 51434 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51435 },
51436/* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51437 {
51438 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40,
6772dd07 51439 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51440 },
51441/* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
51442 {
51443 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24,
6772dd07 51444 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51445 },
51446/* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
51447 {
51448 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24,
6772dd07 51449 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51450 },
51451/* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51452 {
51453 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24,
6772dd07 51454 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51455 },
51456/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51457 {
51458 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32,
6772dd07 51459 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51460 },
51461/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51462 {
51463 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32,
6772dd07 51464 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51465 },
51466/* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51467 {
51468 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32,
6772dd07 51469 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51470 },
51471/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51472 {
51473 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40,
6772dd07 51474 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51475 },
51476/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51477 {
51478 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40,
6772dd07 51479 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51480 },
51481/* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51482 {
51483 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40,
6772dd07 51484 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51485 },
51486/* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
51487 {
51488 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24,
6772dd07 51489 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51490 },
51491/* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
51492 {
51493 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24,
6772dd07 51494 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51495 },
51496/* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51497 {
51498 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24,
6772dd07 51499 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 51500 },
51501/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51502 {
51503 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
6772dd07 51504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51505 },
51506/* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
51507 {
51508 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
6772dd07 51509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51510 },
51511/* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
51512 {
51513 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
6772dd07 51514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51515 },
51516/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51517 {
51518 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
6772dd07 51519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51520 },
51521/* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
51522 {
51523 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
6772dd07 51524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51525 },
51526/* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
51527 {
51528 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
6772dd07 51529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51530 },
51531/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51532 {
51533 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
6772dd07 51534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51535 },
51536/* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
51537 {
51538 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
6772dd07 51539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51540 },
51541/* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
51542 {
51543 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
6772dd07 51544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51545 },
51546/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51547 {
51548 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
6772dd07 51549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51550 },
51551/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51552 {
51553 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
6772dd07 51554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51555 },
51556/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51557 {
51558 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
6772dd07 51559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51560 },
51561/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51562 {
51563 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 51564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51565 },
51566/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51567 {
51568 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 51569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51570 },
51571/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51572 {
51573 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 51574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51575 },
51576/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51577 {
51578 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51580 },
51581/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51582 {
51583 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51585 },
51586/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51587 {
51588 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51590 },
51591/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
51592 {
51593 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
6772dd07 51594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51595 },
51596/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
51597 {
51598 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
6772dd07 51599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51600 },
51601/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
51602 {
51603 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
6772dd07 51604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51605 },
51606/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
51607 {
51608 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51610 },
51611/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
51612 {
51613 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51615 },
51616/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
51617 {
51618 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51620 },
51621/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
51622 {
51623 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
6772dd07 51624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51625 },
51626/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
51627 {
51628 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
6772dd07 51629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51630 },
51631/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51632 {
51633 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
6772dd07 51634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51635 },
51636/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
51637 {
51638 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51640 },
51641/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
51642 {
51643 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51645 },
51646/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
51647 {
51648 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51650 },
51651/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
51652 {
51653 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
6772dd07 51654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51655 },
51656/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51657 {
51658 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
6772dd07 51659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51660 },
51661/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51662 {
51663 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
6772dd07 51664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51665 },
51666/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
51667 {
51668 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
6772dd07 51669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51670 },
51671/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
51672 {
51673 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
6772dd07 51674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51675 },
51676/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
51677 {
51678 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
6772dd07 51679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51680 },
51681/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51682 {
51683 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
6772dd07 51684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51685 },
51686/* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
51687 {
51688 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
6772dd07 51689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51690 },
51691/* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
51692 {
51693 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
6772dd07 51694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51695 },
51696/* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
51697 {
51698 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
6772dd07 51699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51700 },
51701/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51702 {
51703 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
6772dd07 51704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51705 },
51706/* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
51707 {
51708 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
6772dd07 51709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51710 },
51711/* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
51712 {
51713 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
6772dd07 51714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51715 },
51716/* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
51717 {
51718 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
6772dd07 51719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51720 },
51721/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51722 {
51723 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
6772dd07 51724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51725 },
51726/* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
51727 {
51728 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
6772dd07 51729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51730 },
51731/* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
51732 {
51733 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
6772dd07 51734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51735 },
51736/* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
51737 {
51738 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
6772dd07 51739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51740 },
51741/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51742 {
51743 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 51744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51745 },
51746/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51747 {
51748 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 51749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51750 },
51751/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51752 {
51753 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 51754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51755 },
51756/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
51757 {
51758 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 51759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51760 },
51761/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51762 {
51763 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51765 },
51766/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51767 {
51768 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51770 },
51771/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51772 {
51773 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51775 },
51776/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
51777 {
51778 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51780 },
51781/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51782 {
51783 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
6772dd07 51784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51785 },
51786/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51787 {
51788 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
6772dd07 51789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51790 },
51791/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51792 {
51793 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
6772dd07 51794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51795 },
51796/* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
51797 {
51798 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
6772dd07 51799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51800 },
51801/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
51802 {
51803 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51805 },
51806/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51807 {
51808 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51810 },
51811/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
51812 {
51813 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51815 },
51816/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51817 {
51818 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51820 },
51821/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
51822 {
51823 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51825 },
51826/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51827 {
51828 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51830 },
51831/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
51832 {
51833 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51835 },
51836/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51837 {
51838 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51840 },
51841/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
51842 {
51843 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51845 },
51846/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51847 {
51848 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51850 },
51851/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
51852 {
51853 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51855 },
51856/* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51857 {
51858 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 51859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51860 },
51861/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
51862 {
51863 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51865 },
51866/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
51867 {
51868 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51870 },
51871/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
51872 {
51873 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51875 },
51876/* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
51877 {
51878 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51880 },
51881/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
51882 {
51883 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
6772dd07 51884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51885 },
51886/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51887 {
51888 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
6772dd07 51889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51890 },
51891/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
51892 {
51893 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
6772dd07 51894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51895 },
51896/* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
51897 {
51898 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
6772dd07 51899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51900 },
51901/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
51902 {
51903 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
6772dd07 51904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51905 },
51906/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
51907 {
51908 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
6772dd07 51909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51910 },
51911/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
51912 {
51913 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
6772dd07 51914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51915 },
51916/* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
51917 {
51918 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
6772dd07 51919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51920 },
51921/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51922 {
51923 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
6772dd07 51924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51925 },
51926/* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
51927 {
51928 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
6772dd07 51929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51930 },
51931/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51932 {
51933 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
6772dd07 51934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51935 },
51936/* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
51937 {
51938 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
6772dd07 51939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51940 },
51941/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51942 {
51943 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
6772dd07 51944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51945 },
51946/* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
51947 {
51948 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
6772dd07 51949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51950 },
51951/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
51952 {
51953 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51955 },
51956/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
51957 {
51958 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 51959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51960 },
51961/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
51962 {
51963 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
6772dd07 51964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51965 },
51966/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
51967 {
51968 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
6772dd07 51969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51970 },
51971/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
51972 {
51973 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
6772dd07 51974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51975 },
51976/* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
51977 {
51978 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
6772dd07 51979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51980 },
51981/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
51982 {
51983 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51985 },
51986/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
51987 {
51988 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
6772dd07 51989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51990 },
51991/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
51992 {
51993 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
6772dd07 51994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 51995 },
51996/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
51997 {
51998 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
6772dd07 51999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52000 },
52001/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
52002 {
52003 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
6772dd07 52004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52005 },
52006/* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
52007 {
52008 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
6772dd07 52009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52010 },
52011/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
52012 {
52013 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
6772dd07 52014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52015 },
52016/* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
52017 {
52018 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
6772dd07 52019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52020 },
52021/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
52022 {
52023 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
6772dd07 52024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52025 },
52026/* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
52027 {
52028 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
6772dd07 52029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52030 },
52031/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
52032 {
52033 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
6772dd07 52034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52035 },
52036/* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
52037 {
52038 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
6772dd07 52039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52040 },
52041/* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
52042 {
52043 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
6772dd07 52044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52045 },
52046/* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
52047 {
52048 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
6772dd07 52049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52050 },
52051/* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
52052 {
52053 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
6772dd07 52054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52055 },
52056/* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
52057 {
52058 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
6772dd07 52059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52060 },
52061/* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
52062 {
52063 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
6772dd07 52064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52065 },
52066/* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
52067 {
52068 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
6772dd07 52069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52070 },
52071/* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
52072 {
52073 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
6772dd07 52074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52075 },
52076/* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
52077 {
52078 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
6772dd07 52079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52080 },
52081/* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
52082 {
52083 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
6772dd07 52084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52085 },
52086/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52087 {
52088 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
6772dd07 52089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52090 },
52091/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52092 {
52093 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
6772dd07 52094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52095 },
52096/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
52097 {
52098 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
6772dd07 52099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52100 },
52101/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52102 {
52103 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
6772dd07 52104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52105 },
52106/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52107 {
52108 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
6772dd07 52109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52110 },
52111/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
52112 {
52113 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
6772dd07 52114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52115 },
52116/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52117 {
52118 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 52119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52120 },
52121/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52122 {
52123 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 52124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52125 },
52126/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
52127 {
52128 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 52129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52130 },
52131/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
52132 {
52133 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
6772dd07 52134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52135 },
52136/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
52137 {
52138 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
6772dd07 52139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52140 },
52141/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
52142 {
52143 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
6772dd07 52144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52145 },
52146/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
52147 {
52148 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52150 },
52151/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
52152 {
52153 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52155 },
52156/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
52157 {
52158 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52160 },
52161/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
52162 {
52163 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
6772dd07 52164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52165 },
52166/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
52167 {
52168 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
6772dd07 52169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52170 },
52171/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
52172 {
52173 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
6772dd07 52174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52175 },
52176/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
52177 {
52178 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52180 },
52181/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
52182 {
52183 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52185 },
52186/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
52187 {
52188 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52190 },
52191/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
52192 {
52193 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
6772dd07 52194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52195 },
52196/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
52197 {
52198 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
6772dd07 52199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52200 },
52201/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
52202 {
52203 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
6772dd07 52204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52205 },
52206/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
52207 {
52208 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
6772dd07 52209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52210 },
52211/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
52212 {
52213 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
6772dd07 52214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52215 },
52216/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
52217 {
52218 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
6772dd07 52219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52220 },
52221/* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
52222 {
52223 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
6772dd07 52224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52225 },
52226/* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
52227 {
52228 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24,
6772dd07 52229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52230 },
52231/* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
52232 {
52233 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24,
6772dd07 52234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52235 },
52236/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
52237 {
52238 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32,
6772dd07 52239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52240 },
52241/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
52242 {
52243 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52245 },
52246/* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
52247 {
52248 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32,
6772dd07 52249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52250 },
52251/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
52252 {
52253 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40,
6772dd07 52254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52255 },
52256/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
52257 {
52258 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40,
6772dd07 52259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52260 },
52261/* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
52262 {
52263 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40,
6772dd07 52264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52265 },
52266/* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
52267 {
52268 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40,
6772dd07 52269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52270 },
52271/* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
52272 {
52273 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48,
6772dd07 52274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52275 },
52276/* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
52277 {
52278 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48,
6772dd07 52279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 52280 },
52281/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52282 {
52283 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
6772dd07 52284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52285 },
52286/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
52287 {
52288 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
6772dd07 52289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52290 },
52291/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
52292 {
52293 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
6772dd07 52294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52295 },
52296/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52297 {
52298 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
6772dd07 52299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52300 },
52301/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
52302 {
52303 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
6772dd07 52304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52305 },
52306/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
52307 {
52308 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
6772dd07 52309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52310 },
52311/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52312 {
52313 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
6772dd07 52314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52315 },
52316/* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52317 {
52318 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
6772dd07 52319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52320 },
52321/* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52322 {
52323 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
6772dd07 52324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52325 },
52326/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52327 {
52328 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52330 },
52331/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52332 {
52333 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52335 },
52336/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52337 {
52338 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52340 },
52341/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52342 {
52343 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52345 },
52346/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52347 {
52348 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52350 },
52351/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52352 {
52353 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52355 },
52356/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52357 {
52358 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52360 },
52361/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52362 {
52363 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52365 },
52366/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52367 {
52368 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52370 },
52371/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52372 {
52373 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52375 },
52376/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52377 {
52378 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52380 },
52381/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52382 {
52383 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52385 },
52386/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52387 {
52388 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52390 },
52391/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52392 {
52393 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52395 },
52396/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52397 {
52398 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52400 },
52401/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52402 {
52403 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52405 },
52406/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52407 {
52408 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52410 },
52411/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52412 {
52413 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52415 },
52416/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52417 {
52418 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52420 },
52421/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52422 {
52423 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52425 },
52426/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52427 {
52428 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52430 },
52431/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52432 {
52433 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
6772dd07 52434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52435 },
52436/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52437 {
52438 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
6772dd07 52439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52440 },
52441/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52442 {
52443 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
6772dd07 52444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52445 },
52446/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52447 {
52448 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 52449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52450 },
52451/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52452 {
52453 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 52454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52455 },
52456/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52457 {
52458 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 52459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52460 },
52461/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52462 {
52463 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52465 },
52466/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
52467 {
52468 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52470 },
52471/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
52472 {
52473 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52475 },
52476/* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
52477 {
52478 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52480 },
52481/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52482 {
52483 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52485 },
52486/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
52487 {
52488 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52490 },
52491/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
52492 {
52493 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52495 },
52496/* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
52497 {
52498 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 52499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52500 },
52501/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52502 {
52503 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
6772dd07 52504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52505 },
52506/* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52507 {
52508 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
6772dd07 52509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52510 },
52511/* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52512 {
52513 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
6772dd07 52514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52515 },
52516/* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52517 {
52518 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
6772dd07 52519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52520 },
52521/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52522 {
52523 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52525 },
52526/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52527 {
52528 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52530 },
52531/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52532 {
52533 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52535 },
52536/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52537 {
52538 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52540 },
52541/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52542 {
52543 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52545 },
52546/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52547 {
52548 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52550 },
52551/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52552 {
52553 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52555 },
52556/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52557 {
52558 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52560 },
52561/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52562 {
52563 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52565 },
52566/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52567 {
52568 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52570 },
52571/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52572 {
52573 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52575 },
52576/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52577 {
52578 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52580 },
52581/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52582 {
52583 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52585 },
52586/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52587 {
52588 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52590 },
52591/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52592 {
52593 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52595 },
52596/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52597 {
52598 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52600 },
52601/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52602 {
52603 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52605 },
52606/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52607 {
52608 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52610 },
52611/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52612 {
52613 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52615 },
52616/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52617 {
52618 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52620 },
52621/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52622 {
52623 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52625 },
52626/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52627 {
52628 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52630 },
52631/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52632 {
52633 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52635 },
52636/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52637 {
52638 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52640 },
52641/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52642 {
52643 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52645 },
52646/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52647 {
52648 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52650 },
52651/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52652 {
52653 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52655 },
52656/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52657 {
52658 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52660 },
52661/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52662 {
52663 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 52664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52665 },
52666/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52667 {
52668 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 52669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52670 },
52671/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52672 {
52673 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 52674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52675 },
52676/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52677 {
52678 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 52679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52680 },
52681/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52682 {
52683 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
6772dd07 52684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52685 },
52686/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52687 {
52688 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
6772dd07 52689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52690 },
52691/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52692 {
52693 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
6772dd07 52694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52695 },
52696/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52697 {
52698 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
6772dd07 52699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52700 },
52701/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52702 {
52703 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
6772dd07 52704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52705 },
52706/* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52707 {
52708 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
6772dd07 52709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52710 },
52711/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52712 {
52713 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
6772dd07 52714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52715 },
52716/* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52717 {
52718 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
6772dd07 52719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52720 },
52721/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52722 {
52723 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
6772dd07 52724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52725 },
52726/* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52727 {
52728 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
6772dd07 52729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52730 },
52731/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52732 {
52733 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52735 },
52736/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52737 {
52738 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52740 },
52741/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52742 {
52743 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52745 },
52746/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52747 {
52748 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52750 },
52751/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52752 {
52753 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
6772dd07 52754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52755 },
52756/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52757 {
52758 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
6772dd07 52759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52760 },
52761/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52762 {
52763 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52765 },
52766/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52767 {
52768 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52770 },
52771/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52772 {
52773 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52775 },
52776/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52777 {
52778 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52780 },
52781/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52782 {
52783 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52785 },
52786/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52787 {
52788 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 52789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52790 },
52791/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52792 {
52793 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52795 },
52796/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52797 {
52798 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 52799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52800 },
52801/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52802 {
52803 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
6772dd07 52804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52805 },
52806/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52807 {
52808 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
6772dd07 52809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52810 },
52811/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52812 {
52813 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
6772dd07 52814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52815 },
52816/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52817 {
52818 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
6772dd07 52819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52820 },
52821/* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52822 {
52823 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
6772dd07 52824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52825 },
52826/* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52827 {
52828 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
6772dd07 52829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52830 },
52831/* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52832 {
52833 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
6772dd07 52834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52835 },
52836/* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52837 {
52838 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
6772dd07 52839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52840 },
52841/* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52842 {
52843 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
6772dd07 52844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52845 },
52846/* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52847 {
52848 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
6772dd07 52849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52850 },
52851/* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52852 {
52853 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
6772dd07 52854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52855 },
52856/* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52857 {
52858 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
6772dd07 52859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52860 },
52861/* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52862 {
52863 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
6772dd07 52864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52865 },
52866/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52867 {
52868 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52870 },
52871/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52872 {
52873 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52875 },
52876/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52877 {
52878 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52880 },
52881/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52882 {
52883 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52885 },
52886/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52887 {
52888 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52890 },
52891/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52892 {
52893 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52895 },
52896/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52897 {
52898 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52900 },
52901/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52902 {
52903 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52905 },
52906/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52907 {
52908 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 52909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52910 },
52911/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52912 {
52913 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52915 },
52916/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52917 {
52918 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52920 },
52921/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52922 {
52923 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52925 },
52926/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52927 {
52928 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52930 },
52931/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52932 {
52933 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52935 },
52936/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52937 {
52938 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52940 },
52941/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52942 {
52943 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52945 },
52946/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52947 {
52948 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52950 },
52951/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52952 {
52953 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
6772dd07 52954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52955 },
52956/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52957 {
52958 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52960 },
52961/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52962 {
52963 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52965 },
52966/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52967 {
52968 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
6772dd07 52969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52970 },
52971/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52972 {
52973 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
6772dd07 52974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52975 },
52976/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52977 {
52978 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
6772dd07 52979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52980 },
52981/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52982 {
52983 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
6772dd07 52984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52985 },
52986/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52987 {
52988 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
6772dd07 52989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52990 },
52991/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52992 {
52993 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
6772dd07 52994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 52995 },
52996/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52997 {
52998 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
6772dd07 52999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53000 },
53001/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53002 {
53003 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53005 },
53006/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
53007 {
53008 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53010 },
53011/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
53012 {
53013 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53015 },
53016/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53017 {
53018 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53020 },
53021/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
53022 {
53023 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53025 },
53026/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
53027 {
53028 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53030 },
53031/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53032 {
53033 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
6772dd07 53034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53035 },
53036/* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53037 {
53038 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
6772dd07 53039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53040 },
53041/* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53042 {
53043 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
6772dd07 53044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53045 },
53046/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53047 {
53048 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53050 },
53051/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53052 {
53053 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53055 },
53056/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53057 {
53058 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53060 },
53061/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53062 {
53063 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53065 },
53066/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53067 {
53068 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53070 },
53071/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53072 {
53073 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53075 },
53076/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53077 {
53078 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53080 },
53081/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53082 {
53083 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53085 },
53086/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53087 {
53088 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53090 },
53091/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53092 {
53093 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53095 },
53096/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53097 {
53098 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53100 },
53101/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53102 {
53103 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53105 },
53106/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53107 {
53108 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53110 },
53111/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53112 {
53113 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53115 },
53116/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53117 {
53118 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53120 },
53121/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53122 {
53123 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53125 },
53126/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53127 {
53128 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53130 },
53131/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53132 {
53133 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53135 },
53136/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53137 {
53138 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53140 },
53141/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53142 {
53143 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53145 },
53146/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53147 {
53148 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53150 },
53151/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53152 {
53153 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
6772dd07 53154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53155 },
53156/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53157 {
53158 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
6772dd07 53159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53160 },
53161/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53162 {
53163 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
6772dd07 53164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53165 },
53166/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53167 {
53168 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53170 },
53171/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53172 {
53173 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53175 },
53176/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53177 {
53178 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53180 },
53181/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53182 {
53183 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53185 },
53186/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
53187 {
53188 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53190 },
53191/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
53192 {
53193 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53195 },
53196/* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
53197 {
53198 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53200 },
53201/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53202 {
53203 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53205 },
53206/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
53207 {
53208 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53210 },
53211/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
53212 {
53213 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53215 },
53216/* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
53217 {
53218 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
6772dd07 53219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53220 },
53221/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53222 {
53223 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
6772dd07 53224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53225 },
53226/* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53227 {
53228 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
6772dd07 53229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53230 },
53231/* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53232 {
53233 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
6772dd07 53234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53235 },
53236/* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53237 {
53238 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
6772dd07 53239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53240 },
53241/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53242 {
53243 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53245 },
53246/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53247 {
53248 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53250 },
53251/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53252 {
53253 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53255 },
53256/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53257 {
53258 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53260 },
53261/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53262 {
53263 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53265 },
53266/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53267 {
53268 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53270 },
53271/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53272 {
53273 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53275 },
53276/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53277 {
53278 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53280 },
53281/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53282 {
53283 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53285 },
53286/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53287 {
53288 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53290 },
53291/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53292 {
53293 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53295 },
53296/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53297 {
53298 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53300 },
53301/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53302 {
53303 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53305 },
53306/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53307 {
53308 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53310 },
53311/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53312 {
53313 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53315 },
53316/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53317 {
53318 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53320 },
53321/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53322 {
53323 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53325 },
53326/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53327 {
53328 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53330 },
53331/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53332 {
53333 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53335 },
53336/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53337 {
53338 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53340 },
53341/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53342 {
53343 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53345 },
53346/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53347 {
53348 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53350 },
53351/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53352 {
53353 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53355 },
53356/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53357 {
53358 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53360 },
53361/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53362 {
53363 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53365 },
53366/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53367 {
53368 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53370 },
53371/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53372 {
53373 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53375 },
53376/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53377 {
53378 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53380 },
53381/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53382 {
53383 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53385 },
53386/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53387 {
53388 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53390 },
53391/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53392 {
53393 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53395 },
53396/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
53397 {
53398 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53400 },
53401/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53402 {
53403 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
6772dd07 53404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53405 },
53406/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53407 {
53408 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
6772dd07 53409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53410 },
53411/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53412 {
53413 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
6772dd07 53414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53415 },
53416/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
53417 {
53418 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
6772dd07 53419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53420 },
53421/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53422 {
53423 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
6772dd07 53424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53425 },
53426/* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53427 {
53428 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
6772dd07 53429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53430 },
53431/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53432 {
53433 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
6772dd07 53434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53435 },
53436/* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53437 {
53438 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
6772dd07 53439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53440 },
53441/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53442 {
53443 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
6772dd07 53444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53445 },
53446/* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53447 {
53448 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
6772dd07 53449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53450 },
53451/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53452 {
53453 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53455 },
53456/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53457 {
53458 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53460 },
53461/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53462 {
53463 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53465 },
53466/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53467 {
53468 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53470 },
53471/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53472 {
53473 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
6772dd07 53474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53475 },
53476/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53477 {
53478 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
6772dd07 53479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53480 },
53481/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53482 {
53483 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53485 },
53486/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53487 {
53488 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53490 },
53491/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53492 {
53493 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53495 },
53496/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53497 {
53498 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53500 },
53501/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53502 {
53503 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53505 },
53506/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53507 {
53508 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53510 },
53511/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53512 {
53513 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53515 },
53516/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53517 {
53518 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
6772dd07 53519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53520 },
53521/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53522 {
53523 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
6772dd07 53524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53525 },
53526/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53527 {
53528 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
6772dd07 53529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53530 },
53531/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53532 {
53533 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
6772dd07 53534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53535 },
53536/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53537 {
53538 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
6772dd07 53539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53540 },
53541/* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53542 {
53543 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
6772dd07 53544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53545 },
53546/* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53547 {
53548 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
6772dd07 53549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53550 },
53551/* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53552 {
53553 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
6772dd07 53554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53555 },
53556/* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53557 {
53558 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
6772dd07 53559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53560 },
53561/* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53562 {
53563 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
6772dd07 53564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53565 },
53566/* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53567 {
53568 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
6772dd07 53569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53570 },
53571/* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53572 {
53573 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
6772dd07 53574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53575 },
53576/* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53577 {
53578 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
6772dd07 53579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53580 },
53581/* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53582 {
53583 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
6772dd07 53584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53585 },
53586/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53587 {
53588 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53590 },
53591/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53592 {
53593 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53595 },
53596/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53597 {
53598 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53600 },
53601/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53602 {
53603 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53605 },
53606/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53607 {
53608 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53610 },
53611/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53612 {
53613 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53615 },
53616/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53617 {
53618 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53620 },
53621/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53622 {
53623 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53625 },
53626/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53627 {
53628 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53630 },
53631/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53632 {
53633 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53635 },
53636/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53637 {
53638 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53640 },
53641/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53642 {
53643 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53645 },
53646/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53647 {
53648 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53650 },
53651/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53652 {
53653 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53655 },
53656/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53657 {
53658 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53660 },
53661/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53662 {
53663 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53665 },
53666/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53667 {
53668 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53670 },
53671/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53672 {
53673 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
6772dd07 53674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53675 },
53676/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53677 {
53678 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53680 },
53681/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53682 {
53683 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53685 },
53686/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53687 {
53688 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53690 },
53691/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53692 {
53693 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
6772dd07 53694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53695 },
53696/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53697 {
53698 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
6772dd07 53699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53700 },
53701/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53702 {
53703 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
6772dd07 53704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53705 },
53706/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53707 {
53708 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
6772dd07 53709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53710 },
53711/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53712 {
53713 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
6772dd07 53714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53715 },
53716/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53717 {
53718 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
6772dd07 53719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53720 },
53721/* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53722 {
53723 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 53724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53725 },
53726/* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53727 {
53728 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
6772dd07 53729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53730 },
53731/* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53732 {
53733 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
6772dd07 53734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53735 },
53736/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53737 {
53738 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 53739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53740 },
53741/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53742 {
53743 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 53744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53745 },
53746/* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53747 {
53748 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48,
6772dd07 53749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53750 },
53751/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53752 {
53753 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 53754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53755 },
53756/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53757 {
53758 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 53759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53760 },
53761/* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53762 {
53763 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56,
6772dd07 53764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53765 },
53766/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53767 {
53768 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56,
6772dd07 53769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53770 },
53771/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53772 {
53773 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64,
6772dd07 53774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53775 },
53776/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53777 {
53778 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64,
6772dd07 53779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53780 },
53781/* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53782 {
53783 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53785 },
53786/* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53787 {
53788 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
6772dd07 53789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53790 },
53791/* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53792 {
53793 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
6772dd07 53794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53795 },
53796/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53797 {
53798 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53800 },
53801/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53802 {
53803 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53805 },
53806/* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53807 {
53808 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40,
6772dd07 53809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53810 },
53811/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53812 {
53813 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53815 },
53816/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53817 {
53818 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53820 },
53821/* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53822 {
53823 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48,
6772dd07 53824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53825 },
53826/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53827 {
53828 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48,
6772dd07 53829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53830 },
53831/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53832 {
53833 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56,
6772dd07 53834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53835 },
53836/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53837 {
53838 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56,
6772dd07 53839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 53840 },
53841/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53842 {
53843 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
6772dd07 53844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53845 },
53846/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53847 {
53848 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
6772dd07 53849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53850 },
53851/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53852 {
53853 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
6772dd07 53854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53855 },
53856/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53857 {
53858 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
6772dd07 53859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53860 },
53861/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53862 {
53863 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
6772dd07 53864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53865 },
53866/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53867 {
53868 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
6772dd07 53869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53870 },
53871/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53872 {
53873 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
6772dd07 53874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53875 },
53876/* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53877 {
53878 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
6772dd07 53879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53880 },
53881/* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53882 {
53883 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
6772dd07 53884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53885 },
53886/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53887 {
53888 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53890 },
53891/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53892 {
53893 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53895 },
53896/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53897 {
53898 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53900 },
53901/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53902 {
53903 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53905 },
53906/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53907 {
53908 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53910 },
53911/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53912 {
53913 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53915 },
53916/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53917 {
53918 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 53919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53920 },
53921/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53922 {
53923 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 53924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53925 },
53926/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53927 {
53928 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 53929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53930 },
53931/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53932 {
53933 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53935 },
53936/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53937 {
53938 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53940 },
53941/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53942 {
53943 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53945 },
53946/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53947 {
53948 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53950 },
53951/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53952 {
53953 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53955 },
53956/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53957 {
53958 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53960 },
53961/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53962 {
53963 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53965 },
53966/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53967 {
53968 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53970 },
53971/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53972 {
53973 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 53974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53975 },
53976/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53977 {
53978 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53980 },
53981/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53982 {
53983 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53985 },
53986/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53987 {
53988 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 53989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53990 },
53991/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53992 {
53993 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
6772dd07 53994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 53995 },
53996/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53997 {
53998 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
6772dd07 53999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54000 },
54001/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54002 {
54003 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
6772dd07 54004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54005 },
54006/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54007 {
54008 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 54009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54010 },
54011/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54012 {
54013 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 54014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54015 },
54016/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54017 {
54018 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 54019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54020 },
54021/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54022 {
54023 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54025 },
54026/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
54027 {
54028 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54030 },
54031/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
54032 {
54033 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54035 },
54036/* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
54037 {
54038 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54040 },
54041/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54042 {
54043 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54045 },
54046/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
54047 {
54048 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54050 },
54051/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
54052 {
54053 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54055 },
54056/* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
54057 {
54058 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 54059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54060 },
54061/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54062 {
54063 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
6772dd07 54064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54065 },
54066/* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54067 {
54068 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
6772dd07 54069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54070 },
54071/* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54072 {
54073 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
6772dd07 54074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54075 },
54076/* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54077 {
54078 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
6772dd07 54079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54080 },
54081/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54082 {
54083 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54085 },
54086/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54087 {
54088 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54090 },
54091/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54092 {
54093 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54095 },
54096/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54097 {
54098 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54100 },
54101/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54102 {
54103 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54105 },
54106/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54107 {
54108 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54110 },
54111/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54112 {
54113 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54115 },
54116/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54117 {
54118 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54120 },
54121/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54122 {
54123 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54125 },
54126/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54127 {
54128 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54130 },
54131/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54132 {
54133 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54135 },
54136/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54137 {
54138 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54140 },
54141/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54142 {
54143 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54145 },
54146/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54147 {
54148 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54150 },
54151/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54152 {
54153 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54155 },
54156/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54157 {
54158 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54160 },
54161/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54162 {
54163 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54165 },
54166/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54167 {
54168 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54170 },
54171/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54172 {
54173 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54175 },
54176/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54177 {
54178 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54180 },
54181/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54182 {
54183 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54185 },
54186/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54187 {
54188 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54190 },
54191/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54192 {
54193 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54195 },
54196/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54197 {
54198 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54200 },
54201/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54202 {
54203 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54205 },
54206/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54207 {
54208 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54210 },
54211/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54212 {
54213 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54215 },
54216/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54217 {
54218 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54220 },
54221/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54222 {
54223 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 54224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54225 },
54226/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54227 {
54228 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 54229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54230 },
54231/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54232 {
54233 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 54234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54235 },
54236/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
54237 {
54238 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 54239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54240 },
54241/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54242 {
54243 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
6772dd07 54244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54245 },
54246/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54247 {
54248 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
6772dd07 54249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54250 },
54251/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54252 {
54253 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
6772dd07 54254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54255 },
54256/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
54257 {
54258 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
6772dd07 54259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54260 },
54261/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54262 {
54263 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
6772dd07 54264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54265 },
54266/* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
54267 {
54268 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
6772dd07 54269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54270 },
54271/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54272 {
54273 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
6772dd07 54274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54275 },
54276/* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
54277 {
54278 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
6772dd07 54279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54280 },
54281/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54282 {
54283 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
6772dd07 54284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54285 },
54286/* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54287 {
54288 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
6772dd07 54289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54290 },
54291/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54292 {
54293 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54295 },
54296/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54297 {
54298 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54300 },
54301/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54302 {
54303 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54305 },
54306/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54307 {
54308 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54310 },
54311/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54312 {
54313 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
6772dd07 54314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54315 },
54316/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54317 {
54318 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
6772dd07 54319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54320 },
54321/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54322 {
54323 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54325 },
54326/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54327 {
54328 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54330 },
54331/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54332 {
54333 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54335 },
54336/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54337 {
54338 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54340 },
54341/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54342 {
54343 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54345 },
54346/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54347 {
54348 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 54349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54350 },
54351/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54352 {
54353 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54355 },
54356/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54357 {
54358 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 54359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54360 },
54361/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54362 {
54363 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
6772dd07 54364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54365 },
54366/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
54367 {
54368 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
6772dd07 54369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54370 },
54371/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54372 {
54373 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
6772dd07 54374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54375 },
54376/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
54377 {
54378 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
6772dd07 54379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54380 },
54381/* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
54382 {
54383 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
6772dd07 54384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54385 },
54386/* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
54387 {
54388 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
6772dd07 54389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54390 },
54391/* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
54392 {
54393 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
6772dd07 54394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54395 },
54396/* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
54397 {
54398 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
6772dd07 54399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54400 },
54401/* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
54402 {
54403 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
6772dd07 54404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54405 },
54406/* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
54407 {
54408 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
6772dd07 54409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54410 },
54411/* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
54412 {
54413 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
6772dd07 54414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54415 },
54416/* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
54417 {
54418 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
6772dd07 54419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54420 },
54421/* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54422 {
54423 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
6772dd07 54424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54425 },
54426/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54427 {
54428 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54430 },
54431/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54432 {
54433 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54435 },
54436/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54437 {
54438 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54440 },
54441/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54442 {
54443 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54445 },
54446/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54447 {
54448 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54450 },
54451/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54452 {
54453 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54455 },
54456/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54457 {
54458 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54460 },
54461/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54462 {
54463 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54465 },
54466/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54467 {
54468 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 54469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54470 },
54471/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54472 {
54473 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54475 },
54476/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54477 {
54478 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54480 },
54481/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54482 {
54483 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54485 },
54486/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54487 {
54488 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54490 },
54491/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54492 {
54493 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54495 },
54496/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54497 {
54498 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54500 },
54501/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54502 {
54503 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54505 },
54506/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54507 {
54508 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54510 },
54511/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54512 {
54513 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
6772dd07 54514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54515 },
54516/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54517 {
54518 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54520 },
54521/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54522 {
54523 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54525 },
54526/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54527 {
54528 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
6772dd07 54529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54530 },
54531/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54532 {
54533 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
6772dd07 54534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54535 },
54536/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54537 {
54538 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
6772dd07 54539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54540 },
54541/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54542 {
54543 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
6772dd07 54544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54545 },
54546/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54547 {
54548 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
6772dd07 54549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54550 },
54551/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54552 {
54553 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
6772dd07 54554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54555 },
54556/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54557 {
54558 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
6772dd07 54559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54560 },
54561/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54562 {
54563 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 54564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54565 },
54566/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54567 {
54568 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 54569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54570 },
54571/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54572 {
54573 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 54574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54575 },
54576/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54577 {
54578 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 54579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54580 },
54581/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54582 {
54583 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 54584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54585 },
54586/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54587 {
54588 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 54589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54590 },
54591/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54592 {
54593 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
6772dd07 54594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54595 },
54596/* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54597 {
54598 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
6772dd07 54599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54600 },
54601/* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54602 {
54603 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
6772dd07 54604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54605 },
54606/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54607 {
54608 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54610 },
54611/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54612 {
54613 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54615 },
54616/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54617 {
54618 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54620 },
54621/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54622 {
54623 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54625 },
54626/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54627 {
54628 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54630 },
54631/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54632 {
54633 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54635 },
54636/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54637 {
54638 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54640 },
54641/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54642 {
54643 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54645 },
54646/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54647 {
54648 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54650 },
54651/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54652 {
54653 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54655 },
54656/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54657 {
54658 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54660 },
54661/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54662 {
54663 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54665 },
54666/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54667 {
54668 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54670 },
54671/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54672 {
54673 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54675 },
54676/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54677 {
54678 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54680 },
54681/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54682 {
54683 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54685 },
54686/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54687 {
54688 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54690 },
54691/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54692 {
54693 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 54694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54695 },
54696/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54697 {
54698 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54700 },
54701/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54702 {
54703 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54705 },
54706/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54707 {
54708 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54710 },
54711/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54712 {
54713 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
6772dd07 54714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54715 },
54716/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54717 {
54718 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
6772dd07 54719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54720 },
54721/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54722 {
54723 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
6772dd07 54724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54725 },
54726/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54727 {
54728 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 54729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54730 },
54731/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54732 {
54733 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 54734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54735 },
54736/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54737 {
54738 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 54739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54740 },
54741/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54742 {
54743 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54745 },
54746/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54747 {
54748 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54750 },
54751/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54752 {
54753 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54755 },
54756/* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54757 {
54758 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54760 },
54761/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54762 {
54763 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54765 },
54766/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
54767 {
54768 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54770 },
54771/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
54772 {
54773 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54775 },
54776/* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
54777 {
54778 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
6772dd07 54779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54780 },
54781/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54782 {
54783 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
6772dd07 54784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54785 },
54786/* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54787 {
54788 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
6772dd07 54789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54790 },
54791/* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54792 {
54793 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
6772dd07 54794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54795 },
54796/* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54797 {
54798 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
6772dd07 54799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54800 },
54801/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54802 {
54803 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54805 },
54806/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54807 {
54808 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54810 },
54811/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54812 {
54813 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54815 },
54816/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54817 {
54818 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54820 },
54821/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54822 {
54823 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54825 },
54826/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54827 {
54828 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54830 },
54831/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54832 {
54833 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54835 },
54836/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54837 {
54838 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54840 },
54841/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54842 {
54843 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 54844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54845 },
54846/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54847 {
54848 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 54849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54850 },
54851/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54852 {
54853 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 54854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54855 },
54856/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54857 {
54858 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 54859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54860 },
54861/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54862 {
54863 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54865 },
54866/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54867 {
54868 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54870 },
54871/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54872 {
54873 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54875 },
54876/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54877 {
54878 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54880 },
54881/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54882 {
54883 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54885 },
54886/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54887 {
54888 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54890 },
54891/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54892 {
54893 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54895 },
54896/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54897 {
54898 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54900 },
54901/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54902 {
54903 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54905 },
54906/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54907 {
54908 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54910 },
54911/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54912 {
54913 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54915 },
54916/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54917 {
54918 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 54919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54920 },
54921/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54922 {
54923 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54925 },
54926/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54927 {
54928 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54930 },
54931/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54932 {
54933 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54935 },
54936/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54937 {
54938 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 54939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54940 },
54941/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54942 {
54943 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 54944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54945 },
54946/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54947 {
54948 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 54949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54950 },
54951/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54952 {
54953 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 54954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54955 },
54956/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
54957 {
54958 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 54959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54960 },
54961/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54962 {
54963 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
6772dd07 54964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54965 },
54966/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54967 {
54968 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
6772dd07 54969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54970 },
54971/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54972 {
54973 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
6772dd07 54974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54975 },
54976/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
54977 {
54978 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
6772dd07 54979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54980 },
54981/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54982 {
54983 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
6772dd07 54984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54985 },
54986/* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
54987 {
54988 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
6772dd07 54989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54990 },
54991/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54992 {
54993 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
6772dd07 54994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 54995 },
54996/* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
54997 {
54998 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
6772dd07 54999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55000 },
55001/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55002 {
55003 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
6772dd07 55004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55005 },
55006/* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55007 {
55008 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
6772dd07 55009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55010 },
55011/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55012 {
55013 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 55014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55015 },
55016/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55017 {
55018 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 55019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55020 },
55021/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55022 {
55023 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 55024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55025 },
55026/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55027 {
55028 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 55029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55030 },
55031/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55032 {
55033 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
6772dd07 55034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55035 },
55036/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55037 {
55038 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
6772dd07 55039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55040 },
55041/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55042 {
55043 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 55044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55045 },
55046/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55047 {
55048 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 55049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55050 },
55051/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55052 {
55053 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 55054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55055 },
55056/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55057 {
55058 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 55059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55060 },
55061/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55062 {
55063 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 55064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55065 },
55066/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55067 {
55068 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 55069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55070 },
55071/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55072 {
55073 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 55074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55075 },
55076/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55077 {
55078 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
6772dd07 55079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55080 },
55081/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55082 {
55083 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
6772dd07 55084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55085 },
55086/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
55087 {
55088 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
6772dd07 55089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55090 },
55091/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55092 {
55093 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
6772dd07 55094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55095 },
55096/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
55097 {
55098 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
6772dd07 55099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55100 },
55101/* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
55102 {
55103 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
6772dd07 55104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55105 },
55106/* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
55107 {
55108 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
6772dd07 55109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55110 },
55111/* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
55112 {
55113 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
6772dd07 55114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55115 },
55116/* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
55117 {
55118 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
6772dd07 55119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55120 },
55121/* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
55122 {
55123 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
6772dd07 55124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55125 },
55126/* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
55127 {
55128 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
6772dd07 55129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55130 },
55131/* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
55132 {
55133 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
6772dd07 55134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55135 },
55136/* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
55137 {
55138 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
6772dd07 55139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55140 },
55141/* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55142 {
55143 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
6772dd07 55144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55145 },
55146/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55147 {
55148 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55150 },
55151/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55152 {
55153 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55155 },
55156/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55157 {
55158 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55160 },
55161/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55162 {
55163 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55165 },
55166/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55167 {
55168 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55170 },
55171/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55172 {
55173 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55175 },
55176/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55177 {
55178 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 55179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55180 },
55181/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55182 {
55183 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 55184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55185 },
55186/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55187 {
55188 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 55189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55190 },
55191/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
55192 {
55193 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55195 },
55196/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
55197 {
55198 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55200 },
55201/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55202 {
55203 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55205 },
55206/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
55207 {
55208 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55210 },
55211/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
55212 {
55213 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55215 },
55216/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55217 {
55218 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55220 },
55221/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
55222 {
55223 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55225 },
55226/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
55227 {
55228 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55230 },
55231/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55232 {
55233 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
6772dd07 55234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55235 },
55236/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
55237 {
55238 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55240 },
55241/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
55242 {
55243 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55245 },
55246/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55247 {
55248 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55250 },
55251/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
55252 {
55253 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
6772dd07 55254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55255 },
55256/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
55257 {
55258 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
6772dd07 55259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55260 },
55261/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55262 {
55263 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
6772dd07 55264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55265 },
55266/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
55267 {
55268 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
6772dd07 55269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55270 },
55271/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
55272 {
55273 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
6772dd07 55274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55275 },
55276/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55277 {
55278 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
6772dd07 55279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55280 },
55281/* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
55282 {
55283 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 55284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55285 },
55286/* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
55287 {
55288 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
6772dd07 55289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55290 },
55291/* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
55292 {
55293 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
6772dd07 55294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55295 },
55296/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55297 {
55298 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 55299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55300 },
55301/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
55302 {
55303 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 55304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55305 },
55306/* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
55307 {
55308 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48,
6772dd07 55309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55310 },
55311/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55312 {
55313 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 55314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55315 },
55316/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
55317 {
55318 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 55319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55320 },
55321/* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
55322 {
55323 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56,
6772dd07 55324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55325 },
55326/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
55327 {
55328 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56,
6772dd07 55329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55330 },
55331/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55332 {
55333 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64,
6772dd07 55334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55335 },
55336/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
55337 {
55338 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64,
6772dd07 55339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55340 },
55341/* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
55342 {
55343 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 55344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55345 },
55346/* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
55347 {
55348 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
6772dd07 55349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55350 },
55351/* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
55352 {
55353 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
6772dd07 55354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55355 },
55356/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55357 {
55358 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55360 },
55361/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
55362 {
55363 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55365 },
55366/* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
55367 {
55368 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40,
6772dd07 55369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55370 },
55371/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55372 {
55373 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 55374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55375 },
55376/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
55377 {
55378 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 55379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55380 },
55381/* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
55382 {
55383 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48,
6772dd07 55384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55385 },
55386/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
55387 {
55388 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48,
6772dd07 55389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55390 },
55391/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55392 {
55393 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56,
6772dd07 55394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55395 },
55396/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
55397 {
55398 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56,
6772dd07 55399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 55400 },
55401/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55402 {
55403 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
6772dd07 55404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55405 },
55406/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
55407 {
55408 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
6772dd07 55409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55410 },
55411/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
55412 {
55413 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
6772dd07 55414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55415 },
55416/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55417 {
55418 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
6772dd07 55419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55420 },
55421/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
55422 {
55423 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
6772dd07 55424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55425 },
55426/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
55427 {
55428 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
6772dd07 55429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55430 },
55431/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55432 {
55433 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
6772dd07 55434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55435 },
55436/* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
55437 {
55438 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
6772dd07 55439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55440 },
55441/* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
55442 {
55443 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
6772dd07 55444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55445 },
55446/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
55447 {
55448 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55450 },
55451/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55452 {
55453 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55455 },
55456/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55457 {
55458 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55460 },
55461/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
55462 {
55463 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55465 },
55466/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55467 {
55468 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55470 },
55471/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55472 {
55473 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55475 },
55476/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
55477 {
55478 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55480 },
55481/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55482 {
55483 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55485 },
55486/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55487 {
55488 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55490 },
55491/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
55492 {
55493 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55495 },
55496/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
55497 {
55498 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55500 },
55501/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
55502 {
55503 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55505 },
55506/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
55507 {
55508 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55510 },
55511/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
55512 {
55513 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55515 },
55516/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
55517 {
55518 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55520 },
55521/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
55522 {
55523 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55525 },
55526/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
55527 {
55528 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55530 },
55531/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
55532 {
55533 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 55534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55535 },
55536/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
55537 {
55538 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55540 },
55541/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
55542 {
55543 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55545 },
55546/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
55547 {
55548 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55550 },
55551/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
55552 {
55553 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
6772dd07 55554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55555 },
55556/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
55557 {
55558 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
6772dd07 55559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55560 },
55561/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
55562 {
55563 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
6772dd07 55564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55565 },
55566/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
55567 {
55568 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 55569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55570 },
55571/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
55572 {
55573 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 55574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55575 },
55576/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
55577 {
55578 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 55579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55580 },
55581/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55582 {
55583 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55585 },
55586/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
55587 {
55588 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55590 },
55591/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
55592 {
55593 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55595 },
55596/* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
55597 {
55598 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55600 },
55601/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55602 {
55603 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55605 },
55606/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
55607 {
55608 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55610 },
55611/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
55612 {
55613 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55615 },
55616/* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
55617 {
55618 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
6772dd07 55619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55620 },
55621/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55622 {
55623 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
6772dd07 55624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55625 },
55626/* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55627 {
55628 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
6772dd07 55629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55630 },
55631/* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55632 {
55633 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
6772dd07 55634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55635 },
55636/* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55637 {
55638 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
6772dd07 55639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55640 },
55641/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55642 {
55643 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55645 },
55646/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55647 {
55648 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55650 },
55651/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55652 {
55653 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55655 },
55656/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55657 {
55658 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55660 },
55661/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55662 {
55663 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55665 },
55666/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55667 {
55668 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55670 },
55671/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55672 {
55673 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55675 },
55676/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55677 {
55678 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55680 },
55681/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55682 {
55683 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55685 },
55686/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55687 {
55688 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55690 },
55691/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55692 {
55693 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55695 },
55696/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55697 {
55698 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55700 },
55701/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
55702 {
55703 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55705 },
55706/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
55707 {
55708 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55710 },
55711/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
55712 {
55713 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55715 },
55716/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
55717 {
55718 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55720 },
55721/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
55722 {
55723 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55725 },
55726/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
55727 {
55728 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55730 },
55731/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
55732 {
55733 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55735 },
55736/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
55737 {
55738 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55740 },
55741/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
55742 {
55743 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55745 },
55746/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
55747 {
55748 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55750 },
55751/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
55752 {
55753 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55755 },
55756/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
55757 {
55758 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 55759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55760 },
55761/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
55762 {
55763 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55765 },
55766/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
55767 {
55768 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55770 },
55771/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
55772 {
55773 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55775 },
55776/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
55777 {
55778 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55780 },
55781/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
55782 {
55783 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 55784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55785 },
55786/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
55787 {
55788 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 55789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55790 },
55791/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
55792 {
55793 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 55794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55795 },
55796/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
55797 {
55798 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 55799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55800 },
55801/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
55802 {
55803 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
6772dd07 55804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55805 },
55806/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
55807 {
55808 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
6772dd07 55809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55810 },
55811/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
55812 {
55813 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
6772dd07 55814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55815 },
55816/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
55817 {
55818 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
6772dd07 55819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55820 },
55821/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55822 {
55823 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
6772dd07 55824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55825 },
55826/* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
55827 {
55828 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
6772dd07 55829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55830 },
55831/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55832 {
55833 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
6772dd07 55834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55835 },
55836/* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
55837 {
55838 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
6772dd07 55839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55840 },
55841/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55842 {
55843 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
6772dd07 55844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55845 },
55846/* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55847 {
55848 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
6772dd07 55849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55850 },
55851/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55852 {
55853 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55855 },
55856/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55857 {
55858 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55860 },
55861/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55862 {
55863 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55865 },
55866/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55867 {
55868 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55870 },
55871/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55872 {
55873 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
6772dd07 55874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55875 },
55876/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55877 {
55878 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
6772dd07 55879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55880 },
55881/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55882 {
55883 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55885 },
55886/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55887 {
55888 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55890 },
55891/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55892 {
55893 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55895 },
55896/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55897 {
55898 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55900 },
55901/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55902 {
55903 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55905 },
55906/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55907 {
55908 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 55909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55910 },
55911/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55912 {
55913 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55915 },
55916/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55917 {
55918 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
6772dd07 55919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55920 },
55921/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55922 {
55923 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
6772dd07 55924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55925 },
55926/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
55927 {
55928 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
6772dd07 55929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55930 },
55931/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55932 {
55933 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
6772dd07 55934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55935 },
55936/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
55937 {
55938 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
6772dd07 55939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55940 },
55941/* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
55942 {
55943 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
6772dd07 55944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55945 },
55946/* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
55947 {
55948 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
6772dd07 55949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55950 },
55951/* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
55952 {
55953 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
6772dd07 55954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55955 },
55956/* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
55957 {
55958 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
6772dd07 55959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55960 },
55961/* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
55962 {
55963 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
6772dd07 55964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55965 },
55966/* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
55967 {
55968 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
6772dd07 55969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55970 },
55971/* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
55972 {
55973 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
6772dd07 55974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55975 },
55976/* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
55977 {
55978 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
6772dd07 55979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55980 },
55981/* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55982 {
55983 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
6772dd07 55984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55985 },
55986/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55987 {
55988 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
6772dd07 55989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55990 },
55991/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55992 {
55993 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
6772dd07 55994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 55995 },
55996/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55997 {
55998 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
6772dd07 55999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56000 },
56001/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56002 {
56003 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56005 },
56006/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56007 {
56008 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56010 },
56011/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
56012 {
56013 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56015 },
56016/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56017 {
56018 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 56019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56020 },
56021/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56022 {
56023 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 56024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56025 },
56026/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
56027 {
56028 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 56029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56030 },
56031/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
56032 {
56033 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
6772dd07 56034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56035 },
56036/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
56037 {
56038 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
6772dd07 56039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56040 },
56041/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56042 {
56043 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
6772dd07 56044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56045 },
56046/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
56047 {
56048 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56050 },
56051/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
56052 {
56053 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56055 },
56056/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56057 {
56058 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56060 },
56061/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
56062 {
56063 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
6772dd07 56064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56065 },
56066/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
56067 {
56068 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
6772dd07 56069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56070 },
56071/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56072 {
56073 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
6772dd07 56074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56075 },
56076/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
56077 {
56078 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56080 },
56081/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
56082 {
56083 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56085 },
56086/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56087 {
56088 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
6772dd07 56089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56090 },
56091/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
56092 {
56093 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
6772dd07 56094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56095 },
56096/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
56097 {
56098 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
6772dd07 56099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56100 },
56101/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56102 {
56103 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
6772dd07 56104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56105 },
56106/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
56107 {
56108 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
6772dd07 56109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56110 },
56111/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
56112 {
56113 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
6772dd07 56114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56115 },
56116/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56117 {
56118 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
6772dd07 56119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56120 },
56121/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56122 {
56123 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
6772dd07 56124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56125 },
56126/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
56127 {
56128 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
6772dd07 56129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56130 },
56131/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
56132 {
56133 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
6772dd07 56134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56135 },
56136/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56137 {
56138 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
6772dd07 56139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56140 },
56141/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
56142 {
56143 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
6772dd07 56144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56145 },
56146/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
56147 {
56148 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
6772dd07 56149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56150 },
56151/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56152 {
56153 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
6772dd07 56154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56155 },
56156/* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
56157 {
56158 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
6772dd07 56159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56160 },
56161/* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
56162 {
56163 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
6772dd07 56164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56165 },
56166/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
56167 {
56168 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56170 },
56171/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56172 {
56173 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56175 },
56176/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56177 {
56178 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56180 },
56181/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
56182 {
56183 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56185 },
56186/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56187 {
56188 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56190 },
56191/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56192 {
56193 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56195 },
56196/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
56197 {
56198 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56200 },
56201/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56202 {
56203 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56205 },
56206/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56207 {
56208 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56210 },
56211/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
56212 {
56213 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56215 },
56216/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
56217 {
56218 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56220 },
56221/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
56222 {
56223 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56225 },
56226/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
56227 {
56228 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56230 },
56231/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
56232 {
56233 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56235 },
56236/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
56237 {
56238 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56240 },
56241/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
56242 {
56243 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56245 },
56246/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
56247 {
56248 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56250 },
56251/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
56252 {
56253 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56255 },
56256/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
56257 {
56258 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56260 },
56261/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
56262 {
56263 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56265 },
56266/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
56267 {
56268 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56270 },
56271/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
56272 {
56273 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
6772dd07 56274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56275 },
56276/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
56277 {
56278 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
6772dd07 56279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56280 },
56281/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
56282 {
56283 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
6772dd07 56284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56285 },
56286/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
56287 {
56288 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 56289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56290 },
56291/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
56292 {
56293 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 56294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56295 },
56296/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
56297 {
56298 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 56299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56300 },
56301/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56302 {
56303 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56305 },
56306/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
56307 {
56308 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56310 },
56311/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
56312 {
56313 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56315 },
56316/* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
56317 {
56318 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56320 },
56321/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56322 {
56323 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56325 },
56326/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
56327 {
56328 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56330 },
56331/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
56332 {
56333 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56335 },
56336/* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
56337 {
56338 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
6772dd07 56339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56340 },
56341/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56342 {
56343 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
6772dd07 56344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56345 },
56346/* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
56347 {
56348 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
6772dd07 56349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56350 },
56351/* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
56352 {
56353 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
6772dd07 56354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56355 },
56356/* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
56357 {
56358 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
6772dd07 56359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56360 },
56361/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
56362 {
56363 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56365 },
56366/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56367 {
56368 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56370 },
56371/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56372 {
56373 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56375 },
56376/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
56377 {
56378 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56380 },
56381/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
56382 {
56383 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56385 },
56386/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56387 {
56388 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56390 },
56391/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56392 {
56393 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56395 },
56396/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
56397 {
56398 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56400 },
56401/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
56402 {
56403 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56405 },
56406/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56407 {
56408 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56410 },
56411/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56412 {
56413 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56415 },
56416/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
56417 {
56418 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56420 },
56421/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
56422 {
56423 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56425 },
56426/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
56427 {
56428 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56430 },
56431/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
56432 {
56433 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56435 },
56436/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
56437 {
56438 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56440 },
56441/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
56442 {
56443 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56445 },
56446/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
56447 {
56448 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56450 },
56451/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
56452 {
56453 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56455 },
56456/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
56457 {
56458 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56460 },
56461/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
56462 {
56463 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56465 },
56466/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
56467 {
56468 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56470 },
56471/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
56472 {
56473 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56475 },
56476/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
56477 {
56478 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56480 },
56481/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
56482 {
56483 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56485 },
56486/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
56487 {
56488 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56490 },
56491/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
56492 {
56493 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56495 },
56496/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
56497 {
56498 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56500 },
56501/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
56502 {
56503 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 56504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56505 },
56506/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
56507 {
56508 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 56509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56510 },
56511/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
56512 {
56513 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 56514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56515 },
56516/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
56517 {
56518 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 56519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56520 },
56521/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
56522 {
56523 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
6772dd07 56524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56525 },
56526/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
56527 {
56528 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
6772dd07 56529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56530 },
56531/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
56532 {
56533 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
6772dd07 56534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56535 },
56536/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
56537 {
56538 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
6772dd07 56539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56540 },
56541/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56542 {
56543 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
6772dd07 56544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56545 },
56546/* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
56547 {
56548 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
6772dd07 56549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56550 },
56551/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56552 {
56553 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
6772dd07 56554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56555 },
56556/* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
56557 {
56558 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
6772dd07 56559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56560 },
56561/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56562 {
56563 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
6772dd07 56564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56565 },
56566/* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
56567 {
56568 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
6772dd07 56569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56570 },
56571/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
56572 {
56573 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56575 },
56576/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
56577 {
56578 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56580 },
56581/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
56582 {
56583 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56585 },
56586/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
56587 {
56588 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56590 },
56591/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
56592 {
56593 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
6772dd07 56594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56595 },
56596/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
56597 {
56598 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
6772dd07 56599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56600 },
56601/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
56602 {
56603 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56605 },
56606/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
56607 {
56608 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56610 },
56611/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
56612 {
56613 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56615 },
56616/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
56617 {
56618 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56620 },
56621/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
56622 {
56623 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56625 },
56626/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
56627 {
56628 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
6772dd07 56629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56630 },
56631/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
56632 {
56633 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56635 },
56636/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
56637 {
56638 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
6772dd07 56639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56640 },
56641/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
56642 {
56643 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
6772dd07 56644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56645 },
56646/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
56647 {
56648 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
6772dd07 56649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56650 },
56651/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
56652 {
56653 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
6772dd07 56654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56655 },
56656/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
56657 {
56658 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
6772dd07 56659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56660 },
56661/* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
56662 {
56663 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
6772dd07 56664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56665 },
56666/* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
56667 {
56668 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
6772dd07 56669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56670 },
56671/* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
56672 {
56673 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
6772dd07 56674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56675 },
56676/* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
56677 {
56678 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
6772dd07 56679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56680 },
56681/* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
56682 {
56683 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
6772dd07 56684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56685 },
56686/* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
56687 {
56688 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
6772dd07 56689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56690 },
56691/* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
56692 {
56693 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
6772dd07 56694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56695 },
56696/* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
56697 {
56698 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
6772dd07 56699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56700 },
56701/* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
56702 {
56703 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
6772dd07 56704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56705 },
56706/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56707 {
56708 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56710 },
56711/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56712 {
56713 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56715 },
56716/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
56717 {
56718 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56720 },
56721/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56722 {
56723 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56725 },
56726/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56727 {
56728 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56730 },
56731/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
56732 {
56733 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56735 },
56736/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56737 {
56738 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56740 },
56741/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56742 {
56743 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56745 },
56746/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
56747 {
56748 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 56749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56750 },
56751/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
56752 {
56753 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56755 },
56756/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
56757 {
56758 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56760 },
56761/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56762 {
56763 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56765 },
56766/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
56767 {
56768 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56770 },
56771/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
56772 {
56773 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56775 },
56776/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56777 {
56778 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56780 },
56781/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
56782 {
56783 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56785 },
56786/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
56787 {
56788 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56790 },
56791/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56792 {
56793 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
6772dd07 56794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56795 },
56796/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
56797 {
56798 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56800 },
56801/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
56802 {
56803 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56805 },
56806/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56807 {
56808 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 56809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56810 },
56811/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
56812 {
56813 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
6772dd07 56814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56815 },
56816/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
56817 {
56818 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
6772dd07 56819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56820 },
56821/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56822 {
56823 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
6772dd07 56824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56825 },
56826/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
56827 {
56828 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
6772dd07 56829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56830 },
56831/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
56832 {
56833 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
6772dd07 56834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56835 },
56836/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56837 {
56838 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
6772dd07 56839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56840 },
56841/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
56842 {
56843 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
6772dd07 56844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56845 },
56846/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
56847 {
56848 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
6772dd07 56849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56850 },
56851/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
56852 {
56853 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
6772dd07 56854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56855 },
56856/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
56857 {
56858 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24,
6772dd07 56859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56860 },
56861/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
56862 {
56863 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
6772dd07 56864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56865 },
56866/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
56867 {
56868 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
6772dd07 56869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56870 },
56871/* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
56872 {
56873 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
6772dd07 56874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56875 },
56876/* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
56877 {
56878 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
6772dd07 56879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56880 },
56881/* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
56882 {
56883 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
6772dd07 56884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56885 },
56886/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
56887 {
56888 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
6772dd07 56889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56890 },
56891/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
56892 {
56893 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
6772dd07 56894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56895 },
56896/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
56897 {
56898 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
6772dd07 56899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56900 },
56901/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
56902 {
56903 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
6772dd07 56904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56905 },
56906/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
56907 {
56908 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
6772dd07 56909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56910 },
56911/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
56912 {
56913 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
6772dd07 56914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56915 },
56916/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
56917 {
56918 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
6772dd07 56919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56920 },
56921/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
56922 {
56923 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
6772dd07 56924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56925 },
56926/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
56927 {
56928 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
6772dd07 56929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56930 },
56931/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
56932 {
56933 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
6772dd07 56934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56935 },
56936/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
56937 {
56938 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
6772dd07 56939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56940 },
56941/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
56942 {
56943 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
6772dd07 56944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56945 },
56946/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
56947 {
56948 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
6772dd07 56949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56950 },
56951/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
56952 {
56953 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
6772dd07 56954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56955 },
56956/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
56957 {
56958 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
6772dd07 56959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56960 },
56961/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
56962 {
56963 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
6772dd07 56964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56965 },
56966/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
56967 {
56968 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
6772dd07 56969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56970 },
56971/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
56972 {
56973 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
6772dd07 56974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56975 },
56976/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
56977 {
56978 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
6772dd07 56979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56980 },
56981/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
56982 {
56983 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
6772dd07 56984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56985 },
56986/* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
56987 {
56988 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32,
6772dd07 56989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56990 },
56991/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
56992 {
56993 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32,
6772dd07 56994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 56995 },
56996/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
56997 {
56998 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32,
6772dd07 56999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57000 },
57001/* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
57002 {
57003 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32,
6772dd07 57004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57005 },
57006/* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
57007 {
57008 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
6772dd07 57009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57010 },
57011/* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
57012 {
57013 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
6772dd07 57014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57015 },
57016/* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
57017 {
57018 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32,
6772dd07 57019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57020 },
57021/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
57022 {
57023 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
6772dd07 57024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57025 },
57026/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
57027 {
57028 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
6772dd07 57029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57030 },
57031/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57032 {
57033 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
6772dd07 57034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57035 },
57036/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57037 {
57038 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
6772dd07 57039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57040 },
57041/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57042 {
57043 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
6772dd07 57044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57045 },
57046/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57047 {
57048 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
6772dd07 57049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57050 },
57051/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57052 {
57053 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
6772dd07 57054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57055 },
57056/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57057 {
57058 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
6772dd07 57059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57060 },
57061/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57062 {
57063 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
6772dd07 57064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57065 },
57066/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57067 {
57068 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
6772dd07 57069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57070 },
57071/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57072 {
57073 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
6772dd07 57074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57075 },
57076/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57077 {
57078 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
6772dd07 57079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57080 },
57081/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57082 {
57083 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
6772dd07 57084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57085 },
57086/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57087 {
57088 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
6772dd07 57089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57090 },
57091/* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57092 {
57093 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
6772dd07 57094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57095 },
57096/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57097 {
57098 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
6772dd07 57099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57100 },
57101/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57102 {
57103 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
6772dd07 57104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57105 },
57106/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
57107 {
57108 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48,
6772dd07 57109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57110 },
57111/* adc.w${X} $Src16RnHI,$Dst16RnHI */
57112 {
57113 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
6772dd07 57114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57115 },
57116/* adc.w${X} $Src16AnHI,$Dst16RnHI */
57117 {
57118 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
6772dd07 57119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57120 },
57121/* adc.w${X} [$Src16An],$Dst16RnHI */
57122 {
57123 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16,
6772dd07 57124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57125 },
57126/* adc.w${X} $Src16RnHI,$Dst16AnHI */
57127 {
57128 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16,
6772dd07 57129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57130 },
57131/* adc.w${X} $Src16AnHI,$Dst16AnHI */
57132 {
57133 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16,
6772dd07 57134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57135 },
57136/* adc.w${X} [$Src16An],$Dst16AnHI */
57137 {
57138 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16,
6772dd07 57139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57140 },
57141/* adc.w${X} $Src16RnHI,[$Dst16An] */
57142 {
57143 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
6772dd07 57144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57145 },
57146/* adc.w${X} $Src16AnHI,[$Dst16An] */
57147 {
57148 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
6772dd07 57149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57150 },
57151/* adc.w${X} [$Src16An],[$Dst16An] */
57152 {
57153 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16,
6772dd07 57154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57155 },
57156/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
57157 {
57158 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
6772dd07 57159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57160 },
57161/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
57162 {
57163 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
6772dd07 57164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57165 },
57166/* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57167 {
57168 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
6772dd07 57169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57170 },
57171/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
57172 {
57173 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
6772dd07 57174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57175 },
57176/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
57177 {
57178 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
6772dd07 57179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57180 },
57181/* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57182 {
57183 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
6772dd07 57184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57185 },
57186/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
57187 {
57188 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
6772dd07 57189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57190 },
57191/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
57192 {
57193 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
6772dd07 57194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57195 },
57196/* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
57197 {
57198 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
6772dd07 57199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57200 },
57201/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
57202 {
57203 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
6772dd07 57204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57205 },
57206/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
57207 {
57208 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
6772dd07 57209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57210 },
57211/* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
57212 {
57213 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
6772dd07 57214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57215 },
57216/* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
57217 {
57218 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
6772dd07 57219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57220 },
57221/* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
57222 {
57223 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
6772dd07 57224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57225 },
57226/* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
57227 {
57228 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
6772dd07 57229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57230 },
57231/* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
57232 {
57233 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
6772dd07 57234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57235 },
57236/* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
57237 {
57238 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
6772dd07 57239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57240 },
57241/* adc.w${X} [$Src16An],${Dsp-16-u16} */
57242 {
57243 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32,
6772dd07 57244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57245 },
57246/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
57247 {
57248 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
6772dd07 57249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57250 },
57251/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
57252 {
57253 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
6772dd07 57254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57255 },
57256/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
57257 {
57258 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
6772dd07 57259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57260 },
57261/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
57262 {
57263 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24,
6772dd07 57264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57265 },
57266/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
57267 {
57268 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
6772dd07 57269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57270 },
57271/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
57272 {
57273 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
6772dd07 57274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57275 },
57276/* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
57277 {
57278 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
6772dd07 57279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57280 },
57281/* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
57282 {
57283 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
6772dd07 57284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57285 },
57286/* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
57287 {
57288 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
6772dd07 57289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57290 },
57291/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
57292 {
57293 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
6772dd07 57294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57295 },
57296/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
57297 {
57298 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
6772dd07 57299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57300 },
57301/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
57302 {
57303 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
6772dd07 57304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57305 },
57306/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
57307 {
57308 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
6772dd07 57309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57310 },
57311/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
57312 {
57313 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
6772dd07 57314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57315 },
57316/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
57317 {
57318 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
6772dd07 57319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57320 },
57321/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
57322 {
57323 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
6772dd07 57324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57325 },
57326/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57327 {
57328 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
6772dd07 57329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57330 },
57331/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57332 {
57333 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
6772dd07 57334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57335 },
57336/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
57337 {
57338 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
6772dd07 57339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57340 },
57341/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57342 {
57343 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
6772dd07 57344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57345 },
57346/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57347 {
57348 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
6772dd07 57349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57350 },
57351/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
57352 {
57353 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
6772dd07 57354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57355 },
57356/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57357 {
57358 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
6772dd07 57359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57360 },
57361/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57362 {
57363 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
6772dd07 57364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57365 },
57366/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
57367 {
57368 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
6772dd07 57369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57370 },
57371/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57372 {
57373 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
6772dd07 57374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57375 },
57376/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57377 {
57378 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
6772dd07 57379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57380 },
57381/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
57382 {
57383 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
6772dd07 57384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57385 },
57386/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
57387 {
57388 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
6772dd07 57389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57390 },
57391/* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
57392 {
57393 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32,
6772dd07 57394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57395 },
57396/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
57397 {
57398 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32,
6772dd07 57399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57400 },
57401/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
57402 {
57403 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32,
6772dd07 57404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57405 },
57406/* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
57407 {
57408 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32,
6772dd07 57409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57410 },
57411/* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
57412 {
57413 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
6772dd07 57414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57415 },
57416/* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
57417 {
57418 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
6772dd07 57419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57420 },
57421/* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
57422 {
57423 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32,
6772dd07 57424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57425 },
57426/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
57427 {
57428 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
6772dd07 57429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57430 },
57431/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
57432 {
57433 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
6772dd07 57434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57435 },
57436/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57437 {
57438 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
6772dd07 57439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57440 },
57441/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57442 {
57443 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
6772dd07 57444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57445 },
57446/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57447 {
57448 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
6772dd07 57449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57450 },
57451/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57452 {
57453 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
6772dd07 57454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57455 },
57456/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57457 {
57458 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
6772dd07 57459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57460 },
57461/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57462 {
57463 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
6772dd07 57464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57465 },
57466/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57467 {
57468 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
6772dd07 57469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57470 },
57471/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57472 {
57473 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
6772dd07 57474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57475 },
57476/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57477 {
57478 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
6772dd07 57479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57480 },
57481/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57482 {
57483 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
6772dd07 57484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57485 },
57486/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57487 {
57488 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
6772dd07 57489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57490 },
57491/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57492 {
57493 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
6772dd07 57494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57495 },
57496/* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57497 {
57498 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
6772dd07 57499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57500 },
57501/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57502 {
57503 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
6772dd07 57504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57505 },
57506/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57507 {
57508 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
6772dd07 57509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57510 },
57511/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
57512 {
57513 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48,
6772dd07 57514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57515 },
57516/* adc.b${X} $Src16RnQI,$Dst16RnQI */
57517 {
57518 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
6772dd07 57519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57520 },
57521/* adc.b${X} $Src16AnQI,$Dst16RnQI */
57522 {
57523 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
6772dd07 57524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57525 },
57526/* adc.b${X} [$Src16An],$Dst16RnQI */
57527 {
57528 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16,
6772dd07 57529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57530 },
57531/* adc.b${X} $Src16RnQI,$Dst16AnQI */
57532 {
57533 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16,
6772dd07 57534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57535 },
57536/* adc.b${X} $Src16AnQI,$Dst16AnQI */
57537 {
57538 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16,
6772dd07 57539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57540 },
57541/* adc.b${X} [$Src16An],$Dst16AnQI */
57542 {
57543 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16,
6772dd07 57544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57545 },
57546/* adc.b${X} $Src16RnQI,[$Dst16An] */
57547 {
57548 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
6772dd07 57549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57550 },
57551/* adc.b${X} $Src16AnQI,[$Dst16An] */
57552 {
57553 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
6772dd07 57554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57555 },
57556/* adc.b${X} [$Src16An],[$Dst16An] */
57557 {
57558 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16,
6772dd07 57559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57560 },
57561/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
57562 {
57563 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
6772dd07 57564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57565 },
57566/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
57567 {
57568 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
6772dd07 57569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57570 },
57571/* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57572 {
57573 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
6772dd07 57574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57575 },
57576/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
57577 {
57578 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
6772dd07 57579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57580 },
57581/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
57582 {
57583 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
6772dd07 57584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57585 },
57586/* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57587 {
57588 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
6772dd07 57589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57590 },
57591/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
57592 {
57593 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
6772dd07 57594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57595 },
57596/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
57597 {
57598 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
6772dd07 57599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57600 },
57601/* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
57602 {
57603 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
6772dd07 57604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57605 },
57606/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
57607 {
57608 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
6772dd07 57609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57610 },
57611/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
57612 {
57613 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
6772dd07 57614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57615 },
57616/* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
57617 {
57618 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
6772dd07 57619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57620 },
57621/* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
57622 {
57623 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
6772dd07 57624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57625 },
57626/* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
57627 {
57628 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
6772dd07 57629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57630 },
57631/* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
57632 {
57633 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
6772dd07 57634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57635 },
57636/* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
57637 {
57638 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
6772dd07 57639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57640 },
57641/* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
57642 {
57643 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
6772dd07 57644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57645 },
57646/* adc.b${X} [$Src16An],${Dsp-16-u16} */
57647 {
57648 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32,
6772dd07 57649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57650 },
57651/* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
57652 {
57653 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
6772dd07 57654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57655 },
57656/* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
57657 {
57658 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40,
6772dd07 57659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57660 },
57661/* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
57662 {
57663 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
6772dd07 57664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57665 },
57666/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57667 {
57668 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48,
6772dd07 57669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57670 },
57671/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
57672 {
57673 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 57674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57675 },
57676/* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
57677 {
57678 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48,
6772dd07 57679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57680 },
57681/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57682 {
57683 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56,
6772dd07 57684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57685 },
57686/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
57687 {
57688 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 57689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57690 },
57691/* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
57692 {
57693 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56,
6772dd07 57694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57695 },
57696/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
57697 {
57698 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56,
6772dd07 57699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57700 },
57701/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57702 {
57703 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64,
6772dd07 57704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57705 },
57706/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
57707 {
57708 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64,
6772dd07 57709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57710 },
57711/* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
57712 {
57713 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
6772dd07 57714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57715 },
57716/* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
57717 {
57718 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32,
6772dd07 57719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57720 },
57721/* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
57722 {
57723 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
6772dd07 57724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57725 },
57726/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57727 {
57728 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40,
6772dd07 57729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57730 },
57731/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
57732 {
57733 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 57734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57735 },
57736/* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
57737 {
57738 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40,
6772dd07 57739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57740 },
57741/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57742 {
57743 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48,
6772dd07 57744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57745 },
57746/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
57747 {
57748 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 57749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57750 },
57751/* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
57752 {
57753 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48,
6772dd07 57754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57755 },
57756/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
57757 {
57758 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48,
6772dd07 57759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57760 },
57761/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57762 {
57763 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56,
6772dd07 57764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57765 },
57766/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
57767 {
57768 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56,
6772dd07 57769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57770 },
57771/* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
57772 {
57773 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32,
6772dd07 57774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57775 },
57776/* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
57777 {
57778 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32,
6772dd07 57779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57780 },
57781/* adc.w${X} #${Imm-16-HI},[$Dst16An] */
57782 {
57783 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32,
6772dd07 57784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57785 },
57786/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
57787 {
57788 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40,
6772dd07 57789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57790 },
57791/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
57792 {
57793 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40,
6772dd07 57794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57795 },
57796/* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
57797 {
57798 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40,
6772dd07 57799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57800 },
57801/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
57802 {
57803 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48,
6772dd07 57804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57805 },
57806/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
57807 {
57808 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48,
6772dd07 57809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57810 },
57811/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
57812 {
57813 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48,
6772dd07 57814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57815 },
57816/* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
57817 {
57818 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24,
6772dd07 57819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57820 },
57821/* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
57822 {
57823 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24,
6772dd07 57824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57825 },
57826/* adc.b${X} #${Imm-16-QI},[$Dst16An] */
57827 {
57828 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24,
6772dd07 57829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57830 },
57831/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
57832 {
57833 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32,
6772dd07 57834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57835 },
57836/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
57837 {
57838 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32,
6772dd07 57839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57840 },
57841/* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
57842 {
57843 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32,
6772dd07 57844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57845 },
57846/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
57847 {
57848 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40,
6772dd07 57849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57850 },
57851/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
57852 {
57853 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40,
6772dd07 57854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57855 },
57856/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
57857 {
57858 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40,
6772dd07 57859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 57860 },
57861/* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
57862 {
57863 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32,
6772dd07 57864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57865 },
57866/* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
57867 {
57868 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32,
6772dd07 57869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57870 },
57871/* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
57872 {
57873 M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40,
6772dd07 57874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57875 },
57876/* add.w${S} #${Imm-8-HI},r0 */
57877 {
57878 M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24,
6772dd07 57879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57880 },
57881/* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
57882 {
57883 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24,
6772dd07 57884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57885 },
57886/* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
57887 {
57888 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24,
6772dd07 57889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57890 },
57891/* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
57892 {
57893 M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32,
6772dd07 57894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57895 },
57896/* add.b${S} #${Imm-8-QI},r0l */
57897 {
57898 M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16,
6772dd07 57899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57900 },
57901/* add.l${S} #${Imm1-S},a0 */
57902 {
57903 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8,
6772dd07 57904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57905 },
57906/* add.l${S} #${Imm1-S},a1 */
57907 {
57908 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8,
6772dd07 57909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 57910 },
57911/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57912 {
57913 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
6772dd07 57914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57915 },
57916/* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
57917 {
57918 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
6772dd07 57919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57920 },
57921/* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
57922 {
57923 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
6772dd07 57924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57925 },
57926/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57927 {
57928 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
6772dd07 57929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57930 },
57931/* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
57932 {
57933 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
6772dd07 57934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57935 },
57936/* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
57937 {
57938 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
6772dd07 57939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57940 },
57941/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57942 {
57943 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
6772dd07 57944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57945 },
57946/* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57947 {
57948 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
6772dd07 57949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57950 },
57951/* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57952 {
57953 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
6772dd07 57954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57955 },
57956/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57957 {
57958 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
6772dd07 57959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57960 },
57961/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57962 {
57963 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
6772dd07 57964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57965 },
57966/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57967 {
57968 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
6772dd07 57969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57970 },
57971/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57972 {
57973 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 57974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57975 },
57976/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57977 {
57978 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 57979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57980 },
57981/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57982 {
57983 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 57984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57985 },
57986/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57987 {
57988 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 57989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57990 },
57991/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57992 {
57993 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 57994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 57995 },
57996/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57997 {
57998 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 57999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58000 },
58001/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58002 {
58003 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58005 },
58006/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58007 {
58008 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58010 },
58011/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58012 {
58013 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58015 },
58016/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58017 {
58018 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58020 },
58021/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58022 {
58023 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58025 },
58026/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58027 {
58028 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58030 },
58031/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58032 {
58033 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58035 },
58036/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58037 {
58038 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58040 },
58041/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58042 {
58043 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58045 },
58046/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58047 {
58048 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58050 },
58051/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58052 {
58053 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58055 },
58056/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58057 {
58058 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58060 },
58061/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58062 {
58063 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
6772dd07 58064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58065 },
58066/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58067 {
58068 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
6772dd07 58069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58070 },
58071/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58072 {
58073 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
6772dd07 58074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58075 },
58076/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58077 {
58078 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
6772dd07 58079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58080 },
58081/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58082 {
58083 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
6772dd07 58084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58085 },
58086/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58087 {
58088 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
6772dd07 58089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58090 },
58091/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58092 {
58093 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58095 },
58096/* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
58097 {
58098 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58100 },
58101/* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
58102 {
58103 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58105 },
58106/* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
58107 {
58108 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58110 },
58111/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58112 {
58113 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58115 },
58116/* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
58117 {
58118 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58120 },
58121/* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
58122 {
58123 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58125 },
58126/* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
58127 {
58128 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
6772dd07 58129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58130 },
58131/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58132 {
58133 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
6772dd07 58134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58135 },
58136/* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58137 {
58138 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
6772dd07 58139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58140 },
58141/* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58142 {
58143 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
6772dd07 58144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58145 },
58146/* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58147 {
58148 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
6772dd07 58149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58150 },
58151/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58152 {
58153 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58155 },
58156/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58157 {
58158 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58160 },
58161/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58162 {
58163 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58165 },
58166/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58167 {
58168 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58170 },
58171/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58172 {
58173 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58175 },
58176/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58177 {
58178 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58180 },
58181/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58182 {
58183 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58185 },
58186/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58187 {
58188 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58190 },
58191/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58192 {
58193 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58195 },
58196/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58197 {
58198 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58200 },
58201/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58202 {
58203 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58205 },
58206/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58207 {
58208 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58210 },
58211/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58212 {
58213 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58215 },
58216/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58217 {
58218 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58220 },
58221/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58222 {
58223 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58225 },
58226/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58227 {
58228 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58230 },
58231/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58232 {
58233 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58235 },
58236/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58237 {
58238 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58240 },
58241/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58242 {
58243 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58245 },
58246/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58247 {
58248 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58250 },
58251/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58252 {
58253 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58255 },
58256/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58257 {
58258 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58260 },
58261/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58262 {
58263 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58265 },
58266/* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58267 {
58268 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58270 },
58271/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58272 {
58273 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58275 },
58276/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58277 {
58278 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58280 },
58281/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58282 {
58283 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58285 },
58286/* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58287 {
58288 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58290 },
58291/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58292 {
58293 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
6772dd07 58294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58295 },
58296/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58297 {
58298 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
6772dd07 58299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58300 },
58301/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58302 {
58303 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
6772dd07 58304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58305 },
58306/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
58307 {
58308 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
6772dd07 58309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58310 },
58311/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58312 {
58313 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
6772dd07 58314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58315 },
58316/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58317 {
58318 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
6772dd07 58319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58320 },
58321/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58322 {
58323 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
6772dd07 58324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58325 },
58326/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
58327 {
58328 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
6772dd07 58329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58330 },
58331/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58332 {
58333 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
6772dd07 58334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58335 },
58336/* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
58337 {
58338 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
6772dd07 58339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58340 },
58341/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58342 {
58343 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
6772dd07 58344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58345 },
58346/* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
58347 {
58348 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
6772dd07 58349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58350 },
58351/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58352 {
58353 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
6772dd07 58354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58355 },
58356/* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58357 {
58358 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
6772dd07 58359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58360 },
58361/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58362 {
58363 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58365 },
58366/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58367 {
58368 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58370 },
58371/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58372 {
58373 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58375 },
58376/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58377 {
58378 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58380 },
58381/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58382 {
58383 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
6772dd07 58384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58385 },
58386/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58387 {
58388 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
6772dd07 58389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58390 },
58391/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58392 {
58393 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58395 },
58396/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58397 {
58398 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58400 },
58401/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58402 {
58403 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58405 },
58406/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58407 {
58408 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58410 },
58411/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58412 {
58413 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58415 },
58416/* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58417 {
58418 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
6772dd07 58419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58420 },
58421/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58422 {
58423 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58425 },
58426/* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58427 {
58428 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
6772dd07 58429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58430 },
58431/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58432 {
58433 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
6772dd07 58434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58435 },
58436/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
58437 {
58438 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
6772dd07 58439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58440 },
58441/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58442 {
58443 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
6772dd07 58444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58445 },
58446/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
58447 {
58448 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
6772dd07 58449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58450 },
58451/* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
58452 {
58453 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
6772dd07 58454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58455 },
58456/* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
58457 {
58458 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
6772dd07 58459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58460 },
58461/* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58462 {
58463 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
6772dd07 58464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58465 },
58466/* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
58467 {
58468 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
6772dd07 58469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58470 },
58471/* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
58472 {
58473 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
6772dd07 58474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58475 },
58476/* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58477 {
58478 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
6772dd07 58479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58480 },
58481/* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
58482 {
58483 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
6772dd07 58484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58485 },
58486/* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
58487 {
58488 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
6772dd07 58489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58490 },
58491/* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58492 {
58493 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
6772dd07 58494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58495 },
58496/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58497 {
58498 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58500 },
58501/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58502 {
58503 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58505 },
58506/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58507 {
58508 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58510 },
58511/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58512 {
58513 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58515 },
58516/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58517 {
58518 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58520 },
58521/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58522 {
58523 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58525 },
58526/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58527 {
58528 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58530 },
58531/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58532 {
58533 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58535 },
58536/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58537 {
58538 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 58539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58540 },
58541/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
58542 {
58543 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58545 },
58546/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
58547 {
58548 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58550 },
58551/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58552 {
58553 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58555 },
58556/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
58557 {
58558 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58560 },
58561/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
58562 {
58563 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58565 },
58566/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58567 {
58568 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58570 },
58571/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
58572 {
58573 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58575 },
58576/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
58577 {
58578 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58580 },
58581/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58582 {
58583 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 58584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58585 },
58586/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
58587 {
58588 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58590 },
58591/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
58592 {
58593 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58595 },
58596/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58597 {
58598 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 58599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58600 },
58601/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
58602 {
58603 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
6772dd07 58604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58605 },
58606/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
58607 {
58608 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
6772dd07 58609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58610 },
58611/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58612 {
58613 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
6772dd07 58614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58615 },
58616/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
58617 {
58618 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
6772dd07 58619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58620 },
58621/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
58622 {
58623 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
6772dd07 58624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58625 },
58626/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58627 {
58628 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
6772dd07 58629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58630 },
58631/* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
58632 {
58633 M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8,
6772dd07 58634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 58635 },
58636/* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
58637 {
58638 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16,
6772dd07 58639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 58640 },
58641/* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
58642 {
58643 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16,
6772dd07 58644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 58645 },
58646/* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
58647 {
58648 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24,
6772dd07 58649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 58650 },
58651/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58652 {
58653 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
6772dd07 58654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58655 },
58656/* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
58657 {
58658 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
6772dd07 58659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58660 },
58661/* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
58662 {
58663 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
6772dd07 58664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58665 },
58666/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58667 {
58668 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
6772dd07 58669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58670 },
58671/* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
58672 {
58673 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
6772dd07 58674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58675 },
58676/* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
58677 {
58678 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
6772dd07 58679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58680 },
58681/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58682 {
58683 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
6772dd07 58684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58685 },
58686/* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58687 {
58688 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
6772dd07 58689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58690 },
58691/* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58692 {
58693 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
6772dd07 58694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58695 },
58696/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58697 {
58698 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58700 },
58701/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58702 {
58703 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58705 },
58706/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58707 {
58708 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58710 },
58711/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58712 {
58713 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58715 },
58716/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58717 {
58718 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58720 },
58721/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58722 {
58723 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58725 },
58726/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58727 {
58728 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58730 },
58731/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58732 {
58733 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58735 },
58736/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58737 {
58738 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58740 },
58741/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58742 {
58743 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58745 },
58746/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58747 {
58748 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58750 },
58751/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58752 {
58753 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58755 },
58756/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58757 {
58758 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58760 },
58761/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58762 {
58763 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58765 },
58766/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58767 {
58768 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58770 },
58771/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58772 {
58773 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58775 },
58776/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58777 {
58778 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58780 },
58781/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58782 {
58783 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 58784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58785 },
58786/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58787 {
58788 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58790 },
58791/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58792 {
58793 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58795 },
58796/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58797 {
58798 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58800 },
58801/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58802 {
58803 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
6772dd07 58804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58805 },
58806/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58807 {
58808 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
6772dd07 58809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58810 },
58811/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58812 {
58813 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
6772dd07 58814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58815 },
58816/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58817 {
58818 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 58819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58820 },
58821/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58822 {
58823 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 58824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58825 },
58826/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58827 {
58828 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 58829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58830 },
58831/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58832 {
58833 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58835 },
58836/* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
58837 {
58838 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58840 },
58841/* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
58842 {
58843 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58845 },
58846/* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
58847 {
58848 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58850 },
58851/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58852 {
58853 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58855 },
58856/* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
58857 {
58858 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58860 },
58861/* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
58862 {
58863 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58865 },
58866/* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
58867 {
58868 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
6772dd07 58869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58870 },
58871/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58872 {
58873 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
6772dd07 58874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58875 },
58876/* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58877 {
58878 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
6772dd07 58879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58880 },
58881/* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58882 {
58883 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
6772dd07 58884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58885 },
58886/* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58887 {
58888 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
6772dd07 58889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58890 },
58891/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58892 {
58893 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58895 },
58896/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58897 {
58898 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58900 },
58901/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58902 {
58903 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58905 },
58906/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58907 {
58908 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58910 },
58911/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58912 {
58913 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58915 },
58916/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58917 {
58918 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58920 },
58921/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58922 {
58923 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58925 },
58926/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58927 {
58928 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58930 },
58931/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58932 {
58933 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
6772dd07 58934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58935 },
58936/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58937 {
58938 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
6772dd07 58939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58940 },
58941/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58942 {
58943 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
6772dd07 58944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58945 },
58946/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58947 {
58948 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
6772dd07 58949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58950 },
58951/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58952 {
58953 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58955 },
58956/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58957 {
58958 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58960 },
58961/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58962 {
58963 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58965 },
58966/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58967 {
58968 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58970 },
58971/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58972 {
58973 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58975 },
58976/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58977 {
58978 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58980 },
58981/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58982 {
58983 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58985 },
58986/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58987 {
58988 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 58989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58990 },
58991/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58992 {
58993 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 58995 },
58996/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58997 {
58998 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 58999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59000 },
59001/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59002 {
59003 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 59004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59005 },
59006/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59007 {
59008 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 59009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59010 },
59011/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59012 {
59013 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59015 },
59016/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59017 {
59018 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59020 },
59021/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59022 {
59023 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59025 },
59026/* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59027 {
59028 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59030 },
59031/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59032 {
59033 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 59034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59035 },
59036/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59037 {
59038 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 59039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59040 },
59041/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59042 {
59043 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 59044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59045 },
59046/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
59047 {
59048 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 59049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59050 },
59051/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59052 {
59053 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
6772dd07 59054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59055 },
59056/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59057 {
59058 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
6772dd07 59059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59060 },
59061/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59062 {
59063 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
6772dd07 59064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59065 },
59066/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
59067 {
59068 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
6772dd07 59069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59070 },
59071/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59072 {
59073 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
6772dd07 59074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59075 },
59076/* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
59077 {
59078 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
6772dd07 59079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59080 },
59081/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59082 {
59083 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
6772dd07 59084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59085 },
59086/* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
59087 {
59088 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
6772dd07 59089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59090 },
59091/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59092 {
59093 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
6772dd07 59094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59095 },
59096/* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59097 {
59098 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
6772dd07 59099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59100 },
59101/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59102 {
59103 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59105 },
59106/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59107 {
59108 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59110 },
59111/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59112 {
59113 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
6772dd07 59114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59115 },
59116/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59117 {
59118 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
6772dd07 59119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59120 },
59121/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59122 {
59123 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
6772dd07 59124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59125 },
59126/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59127 {
59128 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
6772dd07 59129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59130 },
59131/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59132 {
59133 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59135 },
59136/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59137 {
59138 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59140 },
59141/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59142 {
59143 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
6772dd07 59144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59145 },
59146/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59147 {
59148 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
6772dd07 59149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59150 },
59151/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59152 {
59153 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59155 },
59156/* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59157 {
59158 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 59159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59160 },
59161/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59162 {
59163 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
6772dd07 59164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59165 },
59166/* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59167 {
59168 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
6772dd07 59169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59170 },
59171/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59172 {
59173 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
6772dd07 59174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59175 },
59176/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
59177 {
59178 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
6772dd07 59179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59180 },
59181/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59182 {
59183 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
6772dd07 59184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59185 },
59186/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
59187 {
59188 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
6772dd07 59189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59190 },
59191/* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
59192 {
59193 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
6772dd07 59194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59195 },
59196/* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
59197 {
59198 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
6772dd07 59199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59200 },
59201/* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59202 {
59203 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
6772dd07 59204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59205 },
59206/* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
59207 {
59208 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
6772dd07 59209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59210 },
59211/* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
59212 {
59213 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
6772dd07 59214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59215 },
59216/* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59217 {
59218 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
6772dd07 59219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59220 },
59221/* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
59222 {
59223 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
6772dd07 59224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59225 },
59226/* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
59227 {
59228 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
6772dd07 59229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59230 },
59231/* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59232 {
59233 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
6772dd07 59234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59235 },
59236/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59237 {
59238 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59240 },
59241/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59242 {
59243 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59245 },
59246/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59247 {
59248 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59250 },
59251/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59252 {
59253 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59255 },
59256/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59257 {
59258 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59260 },
59261/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59262 {
59263 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59265 },
59266/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59267 {
59268 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 59269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59270 },
59271/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59272 {
59273 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 59274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59275 },
59276/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59277 {
59278 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 59279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59280 },
59281/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
59282 {
59283 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59285 },
59286/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
59287 {
59288 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59290 },
59291/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59292 {
59293 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59295 },
59296/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
59297 {
59298 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59300 },
59301/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
59302 {
59303 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59305 },
59306/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59307 {
59308 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59310 },
59311/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
59312 {
59313 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59315 },
59316/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
59317 {
59318 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59320 },
59321/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59322 {
59323 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 59324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59325 },
59326/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
59327 {
59328 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59330 },
59331/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
59332 {
59333 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59335 },
59336/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59337 {
59338 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 59339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59340 },
59341/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
59342 {
59343 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
6772dd07 59344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59345 },
59346/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
59347 {
59348 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
6772dd07 59349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59350 },
59351/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59352 {
59353 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
6772dd07 59354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59355 },
59356/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
59357 {
59358 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
6772dd07 59359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59360 },
59361/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
59362 {
59363 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
6772dd07 59364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59365 },
59366/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59367 {
59368 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
6772dd07 59369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59370 },
59371/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59372 {
59373 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
6772dd07 59374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59375 },
59376/* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
59377 {
59378 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
6772dd07 59379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59380 },
59381/* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
59382 {
59383 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
6772dd07 59384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59385 },
59386/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59387 {
59388 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
6772dd07 59389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59390 },
59391/* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
59392 {
59393 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
6772dd07 59394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59395 },
59396/* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
59397 {
59398 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
6772dd07 59399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59400 },
59401/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59402 {
59403 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
6772dd07 59404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59405 },
59406/* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
59407 {
59408 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
6772dd07 59409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59410 },
59411/* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
59412 {
59413 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
6772dd07 59414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59415 },
59416/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59417 {
59418 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59420 },
59421/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59422 {
59423 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59425 },
59426/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59427 {
59428 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59430 },
59431/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59432 {
59433 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59435 },
59436/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59437 {
59438 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59440 },
59441/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59442 {
59443 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59445 },
59446/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59447 {
59448 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59450 },
59451/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59452 {
59453 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59455 },
59456/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59457 {
59458 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59460 },
59461/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
59462 {
59463 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59465 },
59466/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59467 {
59468 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59470 },
59471/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59472 {
59473 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59475 },
59476/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
59477 {
59478 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59480 },
59481/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59482 {
59483 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59485 },
59486/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59487 {
59488 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59490 },
59491/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
59492 {
59493 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59495 },
59496/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59497 {
59498 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59500 },
59501/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59502 {
59503 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59505 },
59506/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
59507 {
59508 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59510 },
59511/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
59512 {
59513 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59515 },
59516/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
59517 {
59518 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59520 },
59521/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
59522 {
59523 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 59524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59525 },
59526/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59527 {
59528 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 59529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59530 },
59531/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59532 {
59533 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 59534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59535 },
59536/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
59537 {
59538 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 59539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59540 },
59541/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
59542 {
59543 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 59544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59545 },
59546/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
59547 {
59548 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 59549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59550 },
59551/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59552 {
59553 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59555 },
59556/* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
59557 {
59558 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59560 },
59561/* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
59562 {
59563 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59565 },
59566/* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
59567 {
59568 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59570 },
59571/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59572 {
59573 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59575 },
59576/* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
59577 {
59578 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59580 },
59581/* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
59582 {
59583 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59585 },
59586/* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
59587 {
59588 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
6772dd07 59589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59590 },
59591/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59592 {
59593 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
6772dd07 59594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59595 },
59596/* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
59597 {
59598 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
6772dd07 59599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59600 },
59601/* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
59602 {
59603 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
6772dd07 59604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59605 },
59606/* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
59607 {
59608 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
6772dd07 59609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59610 },
59611/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59612 {
59613 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59615 },
59616/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59617 {
59618 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59620 },
59621/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59622 {
59623 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59625 },
59626/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
59627 {
59628 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59630 },
59631/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59632 {
59633 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59635 },
59636/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59637 {
59638 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59640 },
59641/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59642 {
59643 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59645 },
59646/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
59647 {
59648 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59650 },
59651/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59652 {
59653 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59655 },
59656/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59657 {
59658 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59660 },
59661/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59662 {
59663 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59665 },
59666/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
59667 {
59668 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59670 },
59671/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
59672 {
59673 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59675 },
59676/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59677 {
59678 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59680 },
59681/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
59682 {
59683 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59685 },
59686/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59687 {
59688 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59690 },
59691/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
59692 {
59693 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59695 },
59696/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59697 {
59698 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59700 },
59701/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
59702 {
59703 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59705 },
59706/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59707 {
59708 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59710 },
59711/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
59712 {
59713 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59715 },
59716/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59717 {
59718 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59720 },
59721/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59722 {
59723 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59725 },
59726/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59727 {
59728 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59730 },
59731/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59732 {
59733 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59735 },
59736/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59737 {
59738 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59740 },
59741/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59742 {
59743 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59745 },
59746/* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59747 {
59748 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59750 },
59751/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59752 {
59753 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 59754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59755 },
59756/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59757 {
59758 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 59759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59760 },
59761/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59762 {
59763 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 59764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59765 },
59766/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
59767 {
59768 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 59769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59770 },
59771/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59772 {
59773 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
6772dd07 59774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59775 },
59776/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59777 {
59778 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
6772dd07 59779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59780 },
59781/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59782 {
59783 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
6772dd07 59784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59785 },
59786/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
59787 {
59788 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
6772dd07 59789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59790 },
59791/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59792 {
59793 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
6772dd07 59794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59795 },
59796/* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
59797 {
59798 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
6772dd07 59799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59800 },
59801/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59802 {
59803 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
6772dd07 59804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59805 },
59806/* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
59807 {
59808 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
6772dd07 59809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59810 },
59811/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59812 {
59813 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
6772dd07 59814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59815 },
59816/* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59817 {
59818 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
6772dd07 59819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59820 },
59821/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59822 {
59823 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59825 },
59826/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59827 {
59828 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59830 },
59831/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59832 {
59833 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59835 },
59836/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59837 {
59838 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59840 },
59841/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59842 {
59843 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
6772dd07 59844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59845 },
59846/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59847 {
59848 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
6772dd07 59849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59850 },
59851/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59852 {
59853 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59855 },
59856/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59857 {
59858 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59860 },
59861/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59862 {
59863 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59865 },
59866/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59867 {
59868 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59870 },
59871/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59872 {
59873 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59875 },
59876/* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59877 {
59878 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
6772dd07 59879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59880 },
59881/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59882 {
59883 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59885 },
59886/* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59887 {
59888 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
6772dd07 59889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59890 },
59891/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59892 {
59893 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
6772dd07 59894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59895 },
59896/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59897 {
59898 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
6772dd07 59899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59900 },
59901/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59902 {
59903 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
6772dd07 59904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59905 },
59906/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59907 {
59908 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
6772dd07 59909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59910 },
59911/* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59912 {
59913 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
6772dd07 59914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59915 },
59916/* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59917 {
59918 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
6772dd07 59919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59920 },
59921/* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59922 {
59923 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
6772dd07 59924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59925 },
59926/* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59927 {
59928 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
6772dd07 59929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59930 },
59931/* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59932 {
59933 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
6772dd07 59934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59935 },
59936/* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59937 {
59938 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
6772dd07 59939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59940 },
59941/* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59942 {
59943 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
6772dd07 59944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59945 },
59946/* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59947 {
59948 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
6772dd07 59949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59950 },
59951/* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59952 {
59953 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
6772dd07 59954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59955 },
59956/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59957 {
59958 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
6772dd07 59959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59960 },
59961/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59962 {
59963 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
6772dd07 59964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59965 },
59966/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59967 {
59968 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
6772dd07 59969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59970 },
59971/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59972 {
59973 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59975 },
59976/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59977 {
59978 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59980 },
59981/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59982 {
59983 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 59984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59985 },
59986/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59987 {
59988 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59990 },
59991/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59992 {
59993 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 59995 },
59996/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59997 {
59998 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 59999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60000 },
60001/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
60002 {
60003 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 60004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60005 },
60006/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
60007 {
60008 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 60009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60010 },
60011/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
60012 {
60013 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 60014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60015 },
60016/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
60017 {
60018 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 60019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60020 },
60021/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
60022 {
60023 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 60024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60025 },
60026/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
60027 {
60028 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 60029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60030 },
60031/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
60032 {
60033 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 60034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60035 },
60036/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
60037 {
60038 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 60039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60040 },
60041/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
60042 {
60043 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 60044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60045 },
60046/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
60047 {
60048 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 60049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60050 },
60051/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
60052 {
60053 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 60054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60055 },
60056/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
60057 {
60058 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 60059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60060 },
60061/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
60062 {
60063 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
6772dd07 60064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60065 },
60066/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
60067 {
60068 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
6772dd07 60069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60070 },
60071/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
60072 {
60073 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
6772dd07 60074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60075 },
60076/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
60077 {
60078 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 60079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60080 },
60081/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
60082 {
60083 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 60084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60085 },
60086/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
60087 {
60088 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 60089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60090 },
60091/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
60092 {
60093 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
6772dd07 60094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60095 },
60096/* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
60097 {
60098 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
6772dd07 60099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60100 },
60101/* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
60102 {
60103 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
6772dd07 60104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60105 },
60106/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
60107 {
60108 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24,
6772dd07 60109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60110 },
60111/* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
60112 {
60113 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24,
6772dd07 60114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60115 },
60116/* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
60117 {
60118 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24,
6772dd07 60119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60120 },
60121/* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60122 {
60123 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24,
6772dd07 60124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60125 },
60126/* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60127 {
60128 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
6772dd07 60129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60130 },
60131/* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60132 {
60133 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
6772dd07 60134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60135 },
60136/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60137 {
60138 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
6772dd07 60139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60140 },
60141/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60142 {
60143 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
6772dd07 60144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60145 },
60146/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60147 {
60148 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
6772dd07 60149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60150 },
60151/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60152 {
60153 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
6772dd07 60154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60155 },
60156/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60157 {
60158 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
6772dd07 60159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60160 },
60161/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60162 {
60163 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
6772dd07 60164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60165 },
60166/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60167 {
60168 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
6772dd07 60169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60170 },
60171/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60172 {
60173 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
6772dd07 60174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60175 },
60176/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60177 {
60178 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
6772dd07 60179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60180 },
60181/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60182 {
60183 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
6772dd07 60184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60185 },
60186/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60187 {
60188 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
6772dd07 60189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60190 },
60191/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60192 {
60193 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
6772dd07 60194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60195 },
60196/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60197 {
60198 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
6772dd07 60199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60200 },
60201/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60202 {
60203 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
6772dd07 60204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60205 },
60206/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60207 {
60208 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
6772dd07 60209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60210 },
60211/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60212 {
60213 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
6772dd07 60214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60215 },
60216/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60217 {
60218 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
6772dd07 60219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60220 },
60221/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60222 {
60223 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
6772dd07 60224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60225 },
60226/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
60227 {
60228 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
6772dd07 60229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60230 },
60231/* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
60232 {
60233 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
6772dd07 60234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60235 },
60236/* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
60237 {
60238 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32,
6772dd07 60239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60240 },
60241/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
60242 {
60243 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32,
6772dd07 60244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60245 },
60246/* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
60247 {
60248 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32,
6772dd07 60249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60250 },
60251/* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
60252 {
60253 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32,
6772dd07 60254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60255 },
60256/* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60257 {
60258 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32,
6772dd07 60259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60260 },
60261/* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60262 {
60263 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32,
6772dd07 60264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60265 },
60266/* add.w${G} ${Dsp-16-u16},[$Dst16An] */
60267 {
60268 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32,
6772dd07 60269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60270 },
60271/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60272 {
60273 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
6772dd07 60274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60275 },
60276/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60277 {
60278 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
6772dd07 60279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60280 },
60281/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60282 {
60283 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40,
6772dd07 60284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60285 },
60286/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60287 {
60288 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
6772dd07 60289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60290 },
60291/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60292 {
60293 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
6772dd07 60294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60295 },
60296/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60297 {
60298 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48,
6772dd07 60299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60300 },
60301/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60302 {
60303 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
6772dd07 60304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60305 },
60306/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60307 {
60308 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
6772dd07 60309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60310 },
60311/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60312 {
60313 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
6772dd07 60314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60315 },
60316/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60317 {
60318 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
6772dd07 60319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60320 },
60321/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60322 {
60323 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
6772dd07 60324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60325 },
60326/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60327 {
60328 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
6772dd07 60329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60330 },
60331/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60332 {
60333 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
6772dd07 60334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60335 },
60336/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60337 {
60338 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
6772dd07 60339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60340 },
60341/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60342 {
60343 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
6772dd07 60344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60345 },
60346/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60347 {
60348 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
6772dd07 60349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60350 },
60351/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60352 {
60353 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
6772dd07 60354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60355 },
60356/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
60357 {
60358 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48,
6772dd07 60359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60360 },
60361/* add.w${G} $Src16RnHI,$Dst16RnHI */
60362 {
60363 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
6772dd07 60364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60365 },
60366/* add.w${G} $Src16AnHI,$Dst16RnHI */
60367 {
60368 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
6772dd07 60369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60370 },
60371/* add.w${G} [$Src16An],$Dst16RnHI */
60372 {
60373 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16,
6772dd07 60374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60375 },
60376/* add.w${G} $Src16RnHI,$Dst16AnHI */
60377 {
60378 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16,
6772dd07 60379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60380 },
60381/* add.w${G} $Src16AnHI,$Dst16AnHI */
60382 {
60383 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16,
6772dd07 60384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60385 },
60386/* add.w${G} [$Src16An],$Dst16AnHI */
60387 {
60388 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16,
6772dd07 60389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60390 },
60391/* add.w${G} $Src16RnHI,[$Dst16An] */
60392 {
60393 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16,
6772dd07 60394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60395 },
60396/* add.w${G} $Src16AnHI,[$Dst16An] */
60397 {
60398 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16,
6772dd07 60399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60400 },
60401/* add.w${G} [$Src16An],[$Dst16An] */
60402 {
60403 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16,
6772dd07 60404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60405 },
60406/* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
60407 {
60408 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
6772dd07 60409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60410 },
60411/* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
60412 {
60413 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
6772dd07 60414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60415 },
60416/* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60417 {
60418 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24,
6772dd07 60419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60420 },
60421/* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
60422 {
60423 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
6772dd07 60424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60425 },
60426/* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
60427 {
60428 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
6772dd07 60429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60430 },
60431/* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60432 {
60433 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32,
6772dd07 60434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60435 },
60436/* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
60437 {
60438 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
6772dd07 60439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60440 },
60441/* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
60442 {
60443 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
6772dd07 60444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60445 },
60446/* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
60447 {
60448 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
6772dd07 60449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60450 },
60451/* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
60452 {
60453 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
6772dd07 60454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60455 },
60456/* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
60457 {
60458 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
6772dd07 60459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60460 },
60461/* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
60462 {
60463 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
6772dd07 60464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60465 },
60466/* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
60467 {
60468 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
6772dd07 60469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60470 },
60471/* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
60472 {
60473 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
6772dd07 60474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60475 },
60476/* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
60477 {
60478 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
6772dd07 60479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60480 },
60481/* add.w${G} $Src16RnHI,${Dsp-16-u16} */
60482 {
60483 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
6772dd07 60484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60485 },
60486/* add.w${G} $Src16AnHI,${Dsp-16-u16} */
60487 {
60488 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
6772dd07 60489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60490 },
60491/* add.w${G} [$Src16An],${Dsp-16-u16} */
60492 {
60493 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32,
6772dd07 60494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60495 },
60496/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
60497 {
60498 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
6772dd07 60499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60500 },
60501/* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
60502 {
60503 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
6772dd07 60504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60505 },
60506/* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
60507 {
60508 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
6772dd07 60509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60510 },
60511/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
60512 {
60513 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24,
6772dd07 60514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60515 },
60516/* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
60517 {
60518 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24,
6772dd07 60519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60520 },
60521/* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
60522 {
60523 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24,
6772dd07 60524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60525 },
60526/* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60527 {
60528 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24,
6772dd07 60529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60530 },
60531/* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60532 {
60533 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
6772dd07 60534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60535 },
60536/* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60537 {
60538 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
6772dd07 60539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60540 },
60541/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60542 {
60543 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
6772dd07 60544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60545 },
60546/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60547 {
60548 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
6772dd07 60549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60550 },
60551/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60552 {
60553 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
6772dd07 60554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60555 },
60556/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60557 {
60558 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
6772dd07 60559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60560 },
60561/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60562 {
60563 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
6772dd07 60564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60565 },
60566/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60567 {
60568 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
6772dd07 60569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60570 },
60571/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60572 {
60573 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
6772dd07 60574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60575 },
60576/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60577 {
60578 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
6772dd07 60579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60580 },
60581/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60582 {
60583 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
6772dd07 60584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60585 },
60586/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60587 {
60588 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
6772dd07 60589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60590 },
60591/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60592 {
60593 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
6772dd07 60594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60595 },
60596/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60597 {
60598 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
6772dd07 60599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60600 },
60601/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60602 {
60603 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
6772dd07 60604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60605 },
60606/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60607 {
60608 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
6772dd07 60609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60610 },
60611/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60612 {
60613 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
6772dd07 60614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60615 },
60616/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60617 {
60618 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
6772dd07 60619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60620 },
60621/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60622 {
60623 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
6772dd07 60624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60625 },
60626/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60627 {
60628 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
6772dd07 60629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60630 },
60631/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
60632 {
60633 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
6772dd07 60634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60635 },
60636/* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
60637 {
60638 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
6772dd07 60639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60640 },
60641/* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
60642 {
60643 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32,
6772dd07 60644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60645 },
60646/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
60647 {
60648 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32,
6772dd07 60649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60650 },
60651/* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
60652 {
60653 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32,
6772dd07 60654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60655 },
60656/* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
60657 {
60658 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32,
6772dd07 60659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60660 },
60661/* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60662 {
60663 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32,
6772dd07 60664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60665 },
60666/* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60667 {
60668 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32,
6772dd07 60669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60670 },
60671/* add.b${G} ${Dsp-16-u16},[$Dst16An] */
60672 {
60673 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32,
6772dd07 60674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60675 },
60676/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60677 {
60678 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
6772dd07 60679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60680 },
60681/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60682 {
60683 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
6772dd07 60684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60685 },
60686/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60687 {
60688 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40,
6772dd07 60689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60690 },
60691/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60692 {
60693 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
6772dd07 60694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60695 },
60696/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60697 {
60698 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
6772dd07 60699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60700 },
60701/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60702 {
60703 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48,
6772dd07 60704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60705 },
60706/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60707 {
60708 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
6772dd07 60709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60710 },
60711/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60712 {
60713 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
6772dd07 60714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60715 },
60716/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60717 {
60718 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
6772dd07 60719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60720 },
60721/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60722 {
60723 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
6772dd07 60724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60725 },
60726/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60727 {
60728 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
6772dd07 60729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60730 },
60731/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60732 {
60733 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
6772dd07 60734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60735 },
60736/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60737 {
60738 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
6772dd07 60739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60740 },
60741/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60742 {
60743 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
6772dd07 60744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60745 },
60746/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60747 {
60748 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
6772dd07 60749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60750 },
60751/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60752 {
60753 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
6772dd07 60754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60755 },
60756/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60757 {
60758 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
6772dd07 60759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60760 },
60761/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60762 {
60763 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48,
6772dd07 60764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60765 },
60766/* add.b${G} $Src16RnQI,$Dst16RnQI */
60767 {
60768 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
6772dd07 60769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60770 },
60771/* add.b${G} $Src16AnQI,$Dst16RnQI */
60772 {
60773 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
6772dd07 60774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60775 },
60776/* add.b${G} [$Src16An],$Dst16RnQI */
60777 {
60778 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16,
6772dd07 60779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60780 },
60781/* add.b${G} $Src16RnQI,$Dst16AnQI */
60782 {
60783 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16,
6772dd07 60784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60785 },
60786/* add.b${G} $Src16AnQI,$Dst16AnQI */
60787 {
60788 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16,
6772dd07 60789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60790 },
60791/* add.b${G} [$Src16An],$Dst16AnQI */
60792 {
60793 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16,
6772dd07 60794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60795 },
60796/* add.b${G} $Src16RnQI,[$Dst16An] */
60797 {
60798 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16,
6772dd07 60799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60800 },
60801/* add.b${G} $Src16AnQI,[$Dst16An] */
60802 {
60803 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16,
6772dd07 60804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60805 },
60806/* add.b${G} [$Src16An],[$Dst16An] */
60807 {
60808 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16,
6772dd07 60809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60810 },
60811/* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60812 {
60813 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
6772dd07 60814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60815 },
60816/* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60817 {
60818 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
6772dd07 60819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60820 },
60821/* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60822 {
60823 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24,
6772dd07 60824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60825 },
60826/* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60827 {
60828 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
6772dd07 60829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60830 },
60831/* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60832 {
60833 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
6772dd07 60834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60835 },
60836/* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60837 {
60838 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32,
6772dd07 60839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60840 },
60841/* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60842 {
60843 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
6772dd07 60844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60845 },
60846/* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60847 {
60848 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
6772dd07 60849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60850 },
60851/* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60852 {
60853 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
6772dd07 60854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60855 },
60856/* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60857 {
60858 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
6772dd07 60859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60860 },
60861/* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60862 {
60863 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
6772dd07 60864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60865 },
60866/* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60867 {
60868 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
6772dd07 60869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60870 },
60871/* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60872 {
60873 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
6772dd07 60874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60875 },
60876/* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60877 {
60878 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
6772dd07 60879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60880 },
60881/* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60882 {
60883 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
6772dd07 60884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60885 },
60886/* add.b${G} $Src16RnQI,${Dsp-16-u16} */
60887 {
60888 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
6772dd07 60889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60890 },
60891/* add.b${G} $Src16AnQI,${Dsp-16-u16} */
60892 {
60893 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
6772dd07 60894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60895 },
60896/* add.b${G} [$Src16An],${Dsp-16-u16} */
60897 {
60898 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32,
6772dd07 60899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
49f58d10
JB		 60900 },
60901/* add.b${S} #${Imm-8-QI},r0l */
60902 {
60903 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16,
6772dd07 60904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 60905 },
60906/* add.b${S} #${Imm-8-QI},r0h */
60907 {
60908 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16,
6772dd07 60909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 60910 },
60911/* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60912 {
60913 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24,
6772dd07 60914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 60915 },
60916/* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60917 {
60918 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24,
6772dd07 60919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 60920 },
60921/* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60922 {
60923 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32,
6772dd07 60924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 60925 },
60926/* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
60927 {
60928 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
6772dd07 60929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60930 },
60931/* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
60932 {
60933 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16,
6772dd07 60934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60935 },
60936/* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60937 {
60938 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
6772dd07 60939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60940 },
60941/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60942 {
60943 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
6772dd07 60944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60945 },
60946/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60947 {
60948 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
6772dd07 60949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60950 },
60951/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60952 {
60953 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
6772dd07 60954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60955 },
60956/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60957 {
60958 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 60959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60960 },
60961/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60962 {
60963 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 60964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60965 },
60966/* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60967 {
60968 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
6772dd07 60969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60970 },
60971/* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60972 {
60973 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
6772dd07 60974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60975 },
60976/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
60977 {
60978 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
6772dd07 60979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60980 },
60981/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
60982 {
60983 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
6772dd07 60984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60985 },
60986/* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60987 {
60988 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
6772dd07 60989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60990 },
60991/* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60992 {
60993 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16,
6772dd07 60994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 60995 },
60996/* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60997 {
60998 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
6772dd07 60999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61000 },
61001/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61002 {
61003 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
6772dd07 61004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61005 },
61006/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61007 {
61008 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
6772dd07 61009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61010 },
61011/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61012 {
61013 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 61014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61015 },
61016/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
61017 {
61018 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 61019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61020 },
61021/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
61022 {
61023 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 61024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61025 },
61026/* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
61027 {
61028 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
6772dd07 61029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61030 },
61031/* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
61032 {
61033 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
6772dd07 61034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61035 },
61036/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
61037 {
61038 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
6772dd07 61039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61040 },
61041/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
61042 {
61043 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
6772dd07 61044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61045 },
61046/* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
61047 {
61048 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
6772dd07 61049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61050 },
61051/* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
61052 {
61053 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16,
6772dd07 61054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61055 },
61056/* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
61057 {
61058 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
6772dd07 61059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61060 },
61061/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61062 {
61063 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
6772dd07 61064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61065 },
61066/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61067 {
61068 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 61069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61070 },
61071/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61072 {
61073 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 61074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61075 },
61076/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
61077 {
61078 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 61079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61080 },
61081/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
61082 {
61083 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 61084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61085 },
61086/* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
61087 {
61088 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
6772dd07 61089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61090 },
61091/* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
61092 {
61093 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 61094 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61095 },
61096/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
61097 {
61098 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
6772dd07 61099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61100 },
61101/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
61102 {
61103 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 61104 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61105 },
61106/* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
61107 {
61108 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16,
6772dd07 61109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61110 },
61111/* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
61112 {
61113 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16,
6772dd07 61114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61115 },
61116/* add.w${Q} #${Imm-8-s4},[$Dst16An] */
61117 {
61118 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16,
6772dd07 61119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61120 },
61121/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61122 {
61123 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24,
6772dd07 61124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61125 },
61126/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61127 {
61128 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32,
6772dd07 61129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61130 },
61131/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61132 {
61133 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24,
6772dd07 61134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61135 },
61136/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61137 {
61138 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32,
6772dd07 61139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61140 },
61141/* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61142 {
61143 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24,
6772dd07 61144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61145 },
61146/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
61147 {
61148 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32,
6772dd07 61149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61150 },
61151/* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
61152 {
61153 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16,
6772dd07 61154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61155 },
61156/* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
61157 {
61158 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16,
6772dd07 61159 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61160 },
61161/* add.b${Q} #${Imm-8-s4},[$Dst16An] */
61162 {
61163 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16,
6772dd07 61164 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61165 },
61166/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61167 {
61168 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24,
6772dd07 61169 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61170 },
61171/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61172 {
61173 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32,
6772dd07 61174 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61175 },
61176/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61177 {
61178 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24,
6772dd07 61179 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61180 },
61181/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61182 {
61183 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32,
6772dd07 61184 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61185 },
61186/* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61187 {
61188 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24,
6772dd07 61189 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61190 },
61191/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
61192 {
61193 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32,
6772dd07 61194 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61195 },
61196/* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
61197 {
61198 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
6772dd07 61199 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61200 },
61201/* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
61202 {
61203 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32,
6772dd07 61204 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61205 },
61206/* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
61207 {
61208 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
6772dd07 61209 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61210 },
61211/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61212 {
61213 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40,
6772dd07 61214 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61215 },
61216/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61217 {
61218 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 61219 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61220 },
61221/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61222 {
61223 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40,
6772dd07 61224 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61225 },
61226/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61227 {
61228 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48,
6772dd07 61229 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61230 },
61231/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61232 {
61233 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 61234 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61235 },
61236/* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
61237 {
61238 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48,
6772dd07 61239 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61240 },
61241/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61242 {
61243 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48,
6772dd07 61244 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61245 },
61246/* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61247 {
61248 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56,
6772dd07 61249 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61250 },
61251/* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
61252 {
61253 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56,
6772dd07 61254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61255 },
61256/* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
61257 {
61258 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
6772dd07 61259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61260 },
61261/* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
61262 {
61263 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24,
6772dd07 61264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61265 },
61266/* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
61267 {
61268 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
6772dd07 61269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61270 },
61271/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61272 {
61273 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32,
6772dd07 61274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61275 },
61276/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61277 {
61278 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 61279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61280 },
61281/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61282 {
61283 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32,
6772dd07 61284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61285 },
61286/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61287 {
61288 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40,
6772dd07 61289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61290 },
61291/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61292 {
61293 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 61294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61295 },
61296/* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
61297 {
61298 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40,
6772dd07 61299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61300 },
61301/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61302 {
61303 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40,
6772dd07 61304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61305 },
61306/* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61307 {
61308 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48,
6772dd07 61309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61310 },
61311/* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
61312 {
61313 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48,
6772dd07 61314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61315 },
61316/* add.w${G} #${Imm-16-HI},$Dst16RnHI */
61317 {
61318 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32,
6772dd07 61319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61320 },
61321/* add.w${G} #${Imm-16-HI},$Dst16AnHI */
61322 {
61323 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32,
6772dd07 61324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61325 },
61326/* add.w${G} #${Imm-16-HI},[$Dst16An] */
61327 {
61328 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32,
6772dd07 61329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61330 },
61331/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
61332 {
61333 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40,
6772dd07 61334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61335 },
61336/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61337 {
61338 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40,
6772dd07 61339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61340 },
61341/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61342 {
61343 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40,
6772dd07 61344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61345 },
61346/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
61347 {
61348 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48,
6772dd07 61349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61350 },
61351/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61352 {
61353 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48,
6772dd07 61354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61355 },
61356/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61357 {
61358 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48,
6772dd07 61359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61360 },
61361/* add.b${G} #${Imm-16-QI},$Dst16RnQI */
61362 {
61363 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24,
6772dd07 61364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61365 },
61366/* add.b${G} #${Imm-16-QI},$Dst16AnQI */
61367 {
61368 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24,
6772dd07 61369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61370 },
61371/* add.b${G} #${Imm-16-QI},[$Dst16An] */
61372 {
61373 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24,
6772dd07 61374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61375 },
61376/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
61377 {
61378 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32,
6772dd07 61379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61380 },
61381/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61382 {
61383 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32,
6772dd07 61384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61385 },
61386/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61387 {
61388 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32,
6772dd07 61389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61390 },
61391/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
61392 {
61393 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40,
6772dd07 61394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61395 },
61396/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61397 {
61398 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40,
6772dd07 61399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61400 },
61401/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61402 {
61403 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40,
6772dd07 61404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61405 },
61406/* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
61407 {
61408 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48,
6772dd07 61409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61410 },
61411/* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
61412 {
61413 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48,
6772dd07 61414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61415 },
61416/* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
61417 {
61418 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48,
6772dd07 61419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61420 },
61421/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61422 {
61423 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56,
6772dd07 61424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61425 },
61426/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
61427 {
61428 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56,
6772dd07 61429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61430 },
61431/* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
61432 {
61433 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56,
6772dd07 61434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61435 },
61436/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61437 {
61438 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64,
6772dd07 61439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61440 },
61441/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
61442 {
61443 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64,
6772dd07 61444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61445 },
61446/* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
61447 {
61448 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64,
6772dd07 61449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61450 },
61451/* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
61452 {
61453 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64,
6772dd07 61454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61455 },
61456/* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61457 {
61458 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72,
6772dd07 61459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61460 },
61461/* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
61462 {
61463 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72,
6772dd07 61464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61465 },
61466/* adcf.w $Dst32RnUnprefixedHI */
61467 {
61468 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16,
6772dd07 61469 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61470 },
61471/* adcf.w $Dst32AnUnprefixedHI */
61472 {
61473 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16,
6772dd07 61474 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61475 },
61476/* adcf.w [$Dst32AnUnprefixed] */
61477 {
61478 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16,
6772dd07 61479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61480 },
61481/* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61482 {
61483 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24,
6772dd07 61484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61485 },
61486/* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61487 {
61488 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32,
6772dd07 61489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61490 },
61491/* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61492 {
61493 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40,
6772dd07 61494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61495 },
61496/* adcf.w ${Dsp-16-u8}[sb] */
61497 {
61498 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24,
6772dd07 61499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61500 },
61501/* adcf.w ${Dsp-16-u16}[sb] */
61502 {
61503 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32,
6772dd07 61504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61505 },
61506/* adcf.w ${Dsp-16-s8}[fb] */
61507 {
61508 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24,
6772dd07 61509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61510 },
61511/* adcf.w ${Dsp-16-s16}[fb] */
61512 {
61513 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32,
6772dd07 61514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61515 },
61516/* adcf.w ${Dsp-16-u16} */
61517 {
61518 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32,
6772dd07 61519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61520 },
61521/* adcf.w ${Dsp-16-u24} */
61522 {
61523 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40,
6772dd07 61524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61525 },
61526/* adcf.b $Dst32RnUnprefixedQI */
61527 {
61528 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16,
6772dd07 61529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61530 },
61531/* adcf.b $Dst32AnUnprefixedQI */
61532 {
61533 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16,
6772dd07 61534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61535 },
61536/* adcf.b [$Dst32AnUnprefixed] */
61537 {
61538 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16,
6772dd07 61539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61540 },
61541/* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61542 {
61543 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24,
6772dd07 61544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61545 },
61546/* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61547 {
61548 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32,
6772dd07 61549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61550 },
61551/* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61552 {
61553 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40,
6772dd07 61554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61555 },
61556/* adcf.b ${Dsp-16-u8}[sb] */
61557 {
61558 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24,
6772dd07 61559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61560 },
61561/* adcf.b ${Dsp-16-u16}[sb] */
61562 {
61563 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32,
6772dd07 61564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61565 },
61566/* adcf.b ${Dsp-16-s8}[fb] */
61567 {
61568 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24,
6772dd07 61569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61570 },
61571/* adcf.b ${Dsp-16-s16}[fb] */
61572 {
61573 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32,
6772dd07 61574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61575 },
61576/* adcf.b ${Dsp-16-u16} */
61577 {
61578 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32,
6772dd07 61579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61580 },
61581/* adcf.b ${Dsp-16-u24} */
61582 {
61583 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40,
6772dd07 61584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61585 },
61586/* adcf.w $Dst16RnHI */
61587 {
61588 M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16,
6772dd07 61589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61590 },
61591/* adcf.w $Dst16AnHI */
61592 {
61593 M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16,
6772dd07 61594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61595 },
61596/* adcf.w [$Dst16An] */
61597 {
61598 M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16,
6772dd07 61599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61600 },
61601/* adcf.w ${Dsp-16-u8}[$Dst16An] */
61602 {
61603 M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24,
6772dd07 61604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61605 },
61606/* adcf.w ${Dsp-16-u16}[$Dst16An] */
61607 {
61608 M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32,
6772dd07 61609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61610 },
61611/* adcf.w ${Dsp-16-u8}[sb] */
61612 {
61613 M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24,
6772dd07 61614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61615 },
61616/* adcf.w ${Dsp-16-u16}[sb] */
61617 {
61618 M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32,
6772dd07 61619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61620 },
61621/* adcf.w ${Dsp-16-s8}[fb] */
61622 {
61623 M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24,
6772dd07 61624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61625 },
61626/* adcf.w ${Dsp-16-u16} */
61627 {
61628 M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32,
6772dd07 61629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61630 },
61631/* adcf.b $Dst16RnQI */
61632 {
61633 M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16,
6772dd07 61634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61635 },
61636/* adcf.b $Dst16AnQI */
61637 {
61638 M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16,
6772dd07 61639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61640 },
61641/* adcf.b [$Dst16An] */
61642 {
61643 M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16,
6772dd07 61644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61645 },
61646/* adcf.b ${Dsp-16-u8}[$Dst16An] */
61647 {
61648 M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24,
6772dd07 61649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61650 },
61651/* adcf.b ${Dsp-16-u16}[$Dst16An] */
61652 {
61653 M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32,
6772dd07 61654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61655 },
61656/* adcf.b ${Dsp-16-u8}[sb] */
61657 {
61658 M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24,
6772dd07 61659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61660 },
61661/* adcf.b ${Dsp-16-u16}[sb] */
61662 {
61663 M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32,
6772dd07 61664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61665 },
61666/* adcf.b ${Dsp-16-s8}[fb] */
61667 {
61668 M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24,
6772dd07 61669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61670 },
61671/* adcf.b ${Dsp-16-u16} */
61672 {
61673 M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32,
6772dd07 61674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61675 },
61676/* abs.w $Dst32RnUnprefixedHI */
61677 {
61678 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16,
6772dd07 61679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61680 },
61681/* abs.w $Dst32AnUnprefixedHI */
61682 {
61683 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16,
6772dd07 61684 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61685 },
61686/* abs.w [$Dst32AnUnprefixed] */
61687 {
61688 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16,
6772dd07 61689 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61690 },
61691/* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61692 {
61693 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24,
6772dd07 61694 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61695 },
61696/* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61697 {
61698 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32,
6772dd07 61699 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61700 },
61701/* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61702 {
61703 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40,
6772dd07 61704 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61705 },
61706/* abs.w ${Dsp-16-u8}[sb] */
61707 {
61708 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24,
6772dd07 61709 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61710 },
61711/* abs.w ${Dsp-16-u16}[sb] */
61712 {
61713 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32,
6772dd07 61714 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61715 },
61716/* abs.w ${Dsp-16-s8}[fb] */
61717 {
61718 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24,
6772dd07 61719 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61720 },
61721/* abs.w ${Dsp-16-s16}[fb] */
61722 {
61723 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32,
6772dd07 61724 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61725 },
61726/* abs.w ${Dsp-16-u16} */
61727 {
61728 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32,
6772dd07 61729 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61730 },
61731/* abs.w ${Dsp-16-u24} */
61732 {
61733 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40,
6772dd07 61734 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61735 },
61736/* abs.b $Dst32RnUnprefixedQI */
61737 {
61738 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16,
6772dd07 61739 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61740 },
61741/* abs.b $Dst32AnUnprefixedQI */
61742 {
61743 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16,
6772dd07 61744 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61745 },
61746/* abs.b [$Dst32AnUnprefixed] */
61747 {
61748 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16,
6772dd07 61749 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61750 },
61751/* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61752 {
61753 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24,
6772dd07 61754 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61755 },
61756/* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61757 {
61758 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32,
6772dd07 61759 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61760 },
61761/* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61762 {
61763 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40,
6772dd07 61764 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61765 },
61766/* abs.b ${Dsp-16-u8}[sb] */
61767 {
61768 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24,
6772dd07 61769 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61770 },
61771/* abs.b ${Dsp-16-u16}[sb] */
61772 {
61773 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32,
6772dd07 61774 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61775 },
61776/* abs.b ${Dsp-16-s8}[fb] */
61777 {
61778 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24,
6772dd07 61779 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61780 },
61781/* abs.b ${Dsp-16-s16}[fb] */
61782 {
61783 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32,
6772dd07 61784 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61785 },
61786/* abs.b ${Dsp-16-u16} */
61787 {
61788 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32,
6772dd07 61789 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61790 },
61791/* abs.b ${Dsp-16-u24} */
61792 {
61793 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40,
6772dd07 61794 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61795 },
61796/* abs.w $Dst16RnHI */
61797 {
61798 M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16,
6772dd07 61799 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61800 },
61801/* abs.w $Dst16AnHI */
61802 {
61803 M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16,
6772dd07 61804 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61805 },
61806/* abs.w [$Dst16An] */
61807 {
61808 M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16,
6772dd07 61809 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61810 },
61811/* abs.w ${Dsp-16-u8}[$Dst16An] */
61812 {
61813 M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24,
6772dd07 61814 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61815 },
61816/* abs.w ${Dsp-16-u16}[$Dst16An] */
61817 {
61818 M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32,
6772dd07 61819 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61820 },
61821/* abs.w ${Dsp-16-u8}[sb] */
61822 {
61823 M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24,
6772dd07 61824 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61825 },
61826/* abs.w ${Dsp-16-u16}[sb] */
61827 {
61828 M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32,
6772dd07 61829 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61830 },
61831/* abs.w ${Dsp-16-s8}[fb] */
61832 {
61833 M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24,
6772dd07 61834 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61835 },
61836/* abs.w ${Dsp-16-u16} */
61837 {
61838 M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32,
6772dd07 61839 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61840 },
61841/* abs.b $Dst16RnQI */
61842 {
61843 M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16,
6772dd07 61844 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61845 },
61846/* abs.b $Dst16AnQI */
61847 {
61848 M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16,
6772dd07 61849 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61850 },
61851/* abs.b [$Dst16An] */
61852 {
61853 M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16,
6772dd07 61854 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61855 },
61856/* abs.b ${Dsp-16-u8}[$Dst16An] */
61857 {
61858 M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24,
6772dd07 61859 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61860 },
61861/* abs.b ${Dsp-16-u16}[$Dst16An] */
61862 {
61863 M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32,
6772dd07 61864 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61865 },
61866/* abs.b ${Dsp-16-u8}[sb] */
61867 {
61868 M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24,
6772dd07 61869 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61870 },
61871/* abs.b ${Dsp-16-u16}[sb] */
61872 {
61873 M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32,
6772dd07 61874 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61875 },
61876/* abs.b ${Dsp-16-s8}[fb] */
61877 {
61878 M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24,
6772dd07 61879 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10
JB		 61880 },
61881/* abs.b ${Dsp-16-u16} */
61882 {
61883 M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
6772dd07 61884 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
49f58d10 61885 },
92e0a941 61886/* add.w$Q #${Imm-12-s4},sp */
49f58d10 61887 {
92e0a941 61888 M32C_INSN_ADD16_WQ_SP, "add16-wQ-sp", "add.w", 16,
6772dd07 61889 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61890 },
61891/* add.b$G #${Imm-16-QI},sp */
61892 {
61893 M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24,
6772dd07 61894 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61895 },
61896/* add.w$G #${Imm-16-HI},sp */
61897 {
61898 M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32,
6772dd07 61899 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61900 },
61901/* add.l$Q #${Imm3-S},sp */
61902 {
61903 M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8,
6772dd07 61904 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61905 },
61906/* add.l$S #${Imm-16-QI},sp */
61907 {
61908 M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24,
6772dd07 61909 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61910 },
61911/* add.l$G #${Imm-16-HI},sp */
61912 {
61913 M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32,
6772dd07 61914 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61915 },
61916/* dadc.b #${Imm-16-QI} */
61917 {
61918 M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24,
6772dd07 61919 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61920 },
61921/* dadc.w #${Imm-16-HI} */
61922 {
61923 M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32,
6772dd07 61924 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61925 },
61926/* dadc.b r0h,r0l */
61927 {
61928 M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16,
6772dd07 61929 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61930 },
61931/* dadc.w r1,r0 */
61932 {
61933 M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16,
6772dd07 61934 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61935 },
61936/* dadd.b #${Imm-16-QI} */
61937 {
61938 M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24,
6772dd07 61939 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61940 },
61941/* dadd.w #${Imm-16-HI} */
61942 {
61943 M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32,
6772dd07 61944 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61945 },
61946/* dadd.b r0h,r0l */
61947 {
61948 M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16,
6772dd07 61949 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61950 },
61951/* dadd.w r1,r0 */
61952 {
61953 M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16,
6772dd07 61954 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61955 },
61956/* bm$cond16c c */
61957 {
61958 M32C_INSN_BM16_C, "bm16-c", "bm", 16,
6772dd07 61959 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61960 },
61961/* bm$cond32 c */
61962 {
61963 M32C_INSN_BM32_C, "bm32-c", "bm", 16,
6772dd07 61964 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61965 },
61966/* brk */
61967 {
61968 M32C_INSN_BRK16, "brk16", "brk", 8,
6772dd07 61969 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61970 },
61971/* brk */
61972 {
61973 M32C_INSN_BRK32, "brk32", "brk", 8,
6772dd07 61974 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61975 },
61976/* brk2 */
61977 {
61978 M32C_INSN_BRK232, "brk232", "brk2", 8,
6772dd07 61979 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61980 },
61981/* dec.w ${Dst16An-S} */
61982 {
61983 M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8,
6772dd07 61984 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61985 },
61986/* div.b #${Imm-16-QI} */
61987 {
61988 M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24,
6772dd07 61989 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61990 },
61991/* div.w #${Imm-16-HI} */
61992 {
61993 M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32,
6772dd07 61994 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 61995 },
61996/* div.b #${Imm-16-QI} */
61997 {
61998 M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24,
6772dd07 61999 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62000 },
62001/* div.w #${Imm-16-HI} */
62002 {
62003 M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32,
6772dd07 62004 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62005 },
62006/* divu.b #${Imm-16-QI} */
62007 {
62008 M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24,
6772dd07 62009 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62010 },
62011/* divu.w #${Imm-16-HI} */
62012 {
62013 M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32,
6772dd07 62014 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62015 },
62016/* divu.b #${Imm-16-QI} */
62017 {
62018 M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24,
6772dd07 62019 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62020 },
62021/* divu.w #${Imm-16-HI} */
62022 {
62023 M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32,
6772dd07 62024 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62025 },
62026/* divx.b #${Imm-16-QI} */
62027 {
62028 M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24,
6772dd07 62029 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62030 },
62031/* divx.w #${Imm-16-HI} */
62032 {
62033 M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32,
6772dd07 62034 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62035 },
62036/* divx.b #${Imm-16-QI} */
62037 {
62038 M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24,
6772dd07 62039 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62040 },
62041/* divx.w #${Imm-16-HI} */
62042 {
62043 M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32,
6772dd07 62044 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62045 },
62046/* dsbb.b #${Imm-16-QI} */
62047 {
62048 M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24,
6772dd07 62049 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62050 },
62051/* dsbb.w #${Imm-16-HI} */
62052 {
62053 M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32,
6772dd07 62054 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62055 },
62056/* dsbb.b r0h,r0l */
62057 {
62058 M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16,
6772dd07 62059 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62060 },
62061/* dsbb.w r1,r0 */
62062 {
62063 M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16,
6772dd07 62064 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62065 },
62066/* dsub.b #${Imm-16-QI} */
62067 {
62068 M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24,
6772dd07 62069 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62070 },
62071/* dsub.w #${Imm-16-HI} */
62072 {
62073 M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32,
6772dd07 62074 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62075 },
62076/* dsub.b r0h,r0l */
62077 {
62078 M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16,
6772dd07 62079 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62080 },
62081/* dsub.w r1,r0 */
62082 {
62083 M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16,
6772dd07 62084 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62085 },
62086/* enter #${Dsp-16-u8} */
62087 {
62088 M32C_INSN_ENTER16, "enter16", "enter", 24,
6772dd07 62089 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62090 },
62091/* exitd */
62092 {
62093 M32C_INSN_EXITD16, "exitd16", "exitd", 16,
6772dd07 62094 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62095 },
62096/* enter #${Dsp-8-u8} */
62097 {
62098 M32C_INSN_ENTER32, "enter32", "enter", 16,
6772dd07 62099 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62100 },
62101/* exitd */
62102 {
62103 M32C_INSN_EXITD32, "exitd32", "exitd", 8,
6772dd07 62104 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62105 },
62106/* fclr ${flags16} */
62107 {
62108 M32C_INSN_FCLR16, "fclr16", "fclr", 16,
6772dd07 62109 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62110 },
62111/* fset ${flags16} */
62112 {
62113 M32C_INSN_FSET16, "fset16", "fset", 16,
6772dd07 62114 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62115 },
62116/* fclr ${flags32} */
62117 {
62118 M32C_INSN_FCLR, "fclr", "fclr", 16,
6772dd07 62119 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62120 },
62121/* fset ${flags32} */
62122 {
62123 M32C_INSN_FSET, "fset", "fset", 16,
6772dd07 62124 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62125 },
62126/* inc.w ${Dst16An-S} */
62127 {
62128 M32C_INSN_INC16_W, "inc16.w", "inc.w", 8,
6772dd07 62129 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62130 },
62131/* freit */
62132 {
62133 M32C_INSN_FREIT32, "freit32", "freit", 8,
6772dd07 62134 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62135 },
62136/* int #${Dsp-10-u6} */
62137 {
62138 M32C_INSN_INT16, "int16", "int", 16,
6772dd07 62139 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62140 },
62141/* into */
62142 {
62143 M32C_INSN_INTO16, "into16", "into", 8,
6772dd07 62144 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62145 },
62146/* int #${Dsp-8-u6} */
62147 {
62148 M32C_INSN_INT32, "int32", "int", 16,
6772dd07 62149 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62150 },
62151/* into */
62152 {
62153 M32C_INSN_INTO32, "into32", "into", 8,
6772dd07 62154 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62155 },
62156/* j$cond16j5 ${Lab-8-8} */
62157 {
62158 M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
6772dd07 62159 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62160 },
62161/* j$cond16j ${Lab-16-8} */
62162 {
62163 M32C_INSN_JCND16, "jcnd16", "j", 24,
6772dd07 62164 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62165 },
62166/* j$cond32j ${Lab-8-8} */
62167 {
62168 M32C_INSN_JCND32, "jcnd32", "j", 16,
6772dd07 62169 { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62170 },
62171/* jmp.s ${Lab-5-3} */
62172 {
62173 M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
6772dd07 62174 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62175 },
62176/* jmp.b ${Lab-8-8} */
62177 {
62178 M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
6772dd07 62179 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62180 },
62181/* jmp.w ${Lab-8-16} */
62182 {
62183 M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
6772dd07 62184 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62185 },
62186/* jmp.a ${Lab-8-24} */
62187 {
62188 M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32,
6772dd07 62189 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62190 },
62191/* jmps #${Imm-8-QI} */
62192 {
62193 M32C_INSN_JMPS16, "jmps16", "jmps", 16,
6772dd07 62194 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62195 },
62196/* jmp.s ${Lab32-jmp-s} */
62197 {
62198 M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
6772dd07 62199 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62200 },
62201/* jmp.b ${Lab-8-8} */
62202 {
62203 M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
6772dd07 62204 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62205 },
62206/* jmp.w ${Lab-8-16} */
62207 {
62208 M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
6772dd07 62209 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62210 },
62211/* jmp.a ${Lab-8-24} */
62212 {
62213 M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32,
6772dd07 62214 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62215 },
62216/* jmps #${Imm-8-QI} */
62217 {
62218 M32C_INSN_JMPS32, "jmps32", "jmps", 16,
6772dd07 62219 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62220 },
62221/* jsr.w ${Lab-8-16} */
62222 {
62223 M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
6772dd07 62224 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62225 },
62226/* jsr.a ${Lab-8-24} */
62227 {
62228 M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32,
6772dd07 62229 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62230 },
62231/* jsr.w ${Lab-8-16} */
62232 {
62233 M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
6772dd07 62234 { 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62235 },
62236/* jsr.a ${Lab-8-24} */
62237 {
62238 M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32,
6772dd07 62239 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
49f58d10
JB		 62240 },
62241/* jsrs #${Imm-8-QI} */
62242 {
62243 M32C_INSN_JSRS16, "jsrs16", "jsrs", 16,
6772dd07 62244 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62245 },
62246/* jsrs #${Imm-8-QI} */
62247 {
62248 M32C_INSN_JSRS, "jsrs", "jsrs", 16,
6772dd07 62249 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62250 },
62251/* ldc #${Imm-16-HI},${cr16} */
62252 {
62253 M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32,
6772dd07 62254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62255 },
62256/* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
62257 {
62258 M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32,
6772dd07 62259 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62260 },
62261/* ldc #${Dsp-16-u24},${cr2-32} */
62262 {
62263 M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40,
6772dd07 62264 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62265 },
62266/* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
62267 {
62268 M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40,
6772dd07 62269 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62270 },
62271/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62272 {
62273 M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56,
6772dd07 62274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62275 },
62276/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62277 {
62278 M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56,
6772dd07 62279 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62280 },
62281/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62282 {
62283 M32C_INSN_STCTX16, "stctx16", "stctx", 56,
6772dd07 62284 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62285 },
62286/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62287 {
62288 M32C_INSN_STCTX32, "stctx32", "stctx", 56,
6772dd07 62289 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62290 },
62291/* ldipl #${Imm-13-u3} */
62292 {
62293 M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16,
6772dd07 62294 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62295 },
62296/* ldipl #${Imm-13-u3} */
62297 {
62298 M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16,
6772dd07 62299 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62300 },
62301/* mov.b$S #${Imm-8-QI},a0 */
62302 {
62303 M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16,
6772dd07 62304 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62305 },
62306/* mov.b$S #${Imm-8-QI},a1 */
62307 {
62308 M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16,
6772dd07 62309 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62310 },
62311/* mov.w$S #${Imm-8-HI},a0 */
62312 {
62313 M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24,
6772dd07 62314 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62315 },
62316/* mov.w$S #${Imm-8-HI},a1 */
62317 {
62318 M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24,
6772dd07 62319 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62320 },
62321/* mov.w$S #${Imm-8-HI},a0 */
62322 {
62323 M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24,
6772dd07 62324 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62325 },
62326/* mov.w$S #${Imm-8-HI},a1 */
62327 {
62328 M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
6772dd07 62329 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 62330 },
f75eb1c0 62331/* mov.l$S #${Dsp-8-s24},a0 */
49f58d10
JB		 62332 {
62333 M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
6772dd07 62334 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 62335 },
f75eb1c0 62336/* mov.l$S #${Dsp-8-s24},a1 */
49f58d10
JB		 62337 {
62338 M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
6772dd07 62339 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62340 },
62341/* mov.b$S r0l,a1 */
62342 {
62343 M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8,
6772dd07 62344 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62345 },
62346/* mov.b$S r0h,a0 */
62347 {
62348 M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8,
6772dd07 62349 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62350 },
62351/* nop */
62352 {
62353 M32C_INSN_NOP16, "nop16", "nop", 8,
6772dd07 62354 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62355 },
62356/* nop */
62357 {
62358 M32C_INSN_NOP32, "nop32", "nop", 8,
6772dd07 62359 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62360 },
62361/* popc ${cr16} */
62362 {
62363 M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16,
6772dd07 62364 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62365 },
62366/* popc ${cr1-Unprefixed-32} */
62367 {
62368 M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16,
6772dd07 62369 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62370 },
62371/* popc ${cr2-32} */
62372 {
62373 M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16,
6772dd07 62374 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62375 },
62376/* pushc ${cr16} */
62377 {
62378 M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16,
6772dd07 62379 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62380 },
62381/* pushc ${cr1-Unprefixed-32} */
62382 {
62383 M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16,
6772dd07 62384 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62385 },
62386/* pushc ${cr2-32} */
62387 {
62388 M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16,
6772dd07 62389 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62390 },
62391/* popm ${Regsetpop} */
62392 {
62393 M32C_INSN_POPM16, "popm16", "popm", 16,
6772dd07 62394 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62395 },
62396/* pushm ${Regsetpush} */
62397 {
62398 M32C_INSN_PUSHM16, "pushm16", "pushm", 16,
6772dd07 62399 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62400 },
62401/* popm ${Regsetpop} */
62402 {
62403 M32C_INSN_POPM, "popm", "popm", 16,
6772dd07 62404 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62405 },
62406/* pushm ${Regsetpush} */
62407 {
62408 M32C_INSN_PUSHM, "pushm", "pushm", 16,
6772dd07 62409 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62410 },
62411/* push.b$G #${Imm-16-QI} */
62412 {
62413 M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24,
6772dd07 62414 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62415 },
62416/* push.w$G #${Imm-16-HI} */
62417 {
62418 M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32,
6772dd07 62419 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62420 },
62421/* push.b #Imm-8-QI */
62422 {
62423 M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16,
6772dd07 62424 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62425 },
62426/* push.w #${Imm-8-HI} */
62427 {
62428 M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24,
6772dd07 62429 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62430 },
62431/* push.l #${Imm-16-SI} */
62432 {
62433 M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48,
6772dd07 62434 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62435 },
62436/* reit */
62437 {
62438 M32C_INSN_REIT16, "reit16", "reit", 8,
6772dd07 62439 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62440 },
62441/* reit */
62442 {
62443 M32C_INSN_REIT32, "reit32", "reit", 8,
6772dd07 62444 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62445 },
62446/* rmpa.b */
62447 {
62448 M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16,
6772dd07 62449 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62450 },
62451/* rmpa.w */
62452 {
62453 M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16,
6772dd07 62454 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62455 },
62456/* rmpa.b */
62457 {
62458 M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16,
6772dd07 62459 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62460 },
62461/* rmpa.w */
62462 {
62463 M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16,
6772dd07 62464 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62465 },
62466/* rts */
62467 {
62468 M32C_INSN_RTS16, "rts16", "rts", 8,
6772dd07 62469 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62470 },
62471/* rts */
62472 {
62473 M32C_INSN_RTS32, "rts32", "rts", 8,
6772dd07 62474 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62475 },
62476/* scmpu.b */
62477 {
62478 M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16,
6772dd07 62479 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62480 },
62481/* scmpu.w */
62482 {
62483 M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16,
6772dd07 62484 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62485 },
62486/* sha.l #${Imm-sh-12-s4},r2r0 */
62487 {
62488 M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16,
6772dd07 62489 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62490 },
62491/* sha.l #${Imm-sh-12-s4},r3r1 */
62492 {
62493 M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16,
6772dd07 62494 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62495 },
62496/* sha.l r1h,r2r0 */
62497 {
62498 M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16,
6772dd07 62499 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62500 },
62501/* sha.l r1h,r3r1 */
62502 {
62503 M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16,
6772dd07 62504 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62505 },
62506/* shl.l #${Imm-sh-12-s4},r2r0 */
62507 {
62508 M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16,
6772dd07 62509 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62510 },
62511/* shl.l #${Imm-sh-12-s4},r3r1 */
62512 {
62513 M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16,
6772dd07 62514 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62515 },
62516/* shl.l r1h,r2r0 */
62517 {
62518 M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16,
6772dd07 62519 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62520 },
62521/* shl.l r1h,r3r1 */
62522 {
62523 M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16,
6772dd07 62524 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62525 },
62526/* sin.b */
62527 {
62528 M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16,
6772dd07 62529 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62530 },
62531/* sin.w */
62532 {
62533 M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16,
6772dd07 62534 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62535 },
62536/* smovb.b */
62537 {
62538 M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16,
6772dd07 62539 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62540 },
62541/* smovb.w */
62542 {
62543 M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16,
6772dd07 62544 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62545 },
62546/* smovb.b */
62547 {
62548 M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16,
6772dd07 62549 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62550 },
62551/* smovb.w */
62552 {
62553 M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16,
6772dd07 62554 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62555 },
62556/* smovf.b */
62557 {
62558 M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16,
6772dd07 62559 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62560 },
62561/* smovf.w */
62562 {
62563 M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16,
6772dd07 62564 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62565 },
62566/* smovf.b */
62567 {
62568 M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16,
6772dd07 62569 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62570 },
62571/* smovf.w */
62572 {
62573 M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16,
6772dd07 62574 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62575 },
62576/* smovu.b */
62577 {
62578 M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16,
6772dd07 62579 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62580 },
62581/* smovu.w */
62582 {
62583 M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16,
6772dd07 62584 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62585 },
62586/* sout.b */
62587 {
62588 M32C_INSN_SOUT_B, "sout.b", "sout.b", 16,
6772dd07 62589 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62590 },
62591/* sout.w */
62592 {
62593 M32C_INSN_SOUT_W, "sout.w", "sout.w", 16,
6772dd07 62594 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62595 },
62596/* sstr.b */
62597 {
62598 M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16,
6772dd07 62599 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62600 },
62601/* sstr.w */
62602 {
62603 M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16,
6772dd07 62604 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62605 },
62606/* sstr.b */
62607 {
62608 M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16,
6772dd07 62609 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62610 },
62611/* sstr.w */
62612 {
62613 M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16,
6772dd07 62614 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62615 },
62616/* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
62617 {
62618 M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24,
6772dd07 62619 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62620 },
62621/* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
62622 {
62623 M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
6772dd07 62624 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 62625 },
c6552317 62626/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
49f58d10
JB		 62627 {
62628 M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
6772dd07 62629 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 62630 },
c6552317 62631/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
49f58d10
JB		 62632 {
62633 M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
6772dd07 62634 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10 62635 },
c6552317 62636/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
49f58d10
JB		 62637 {
62638 M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
6772dd07 62639 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62640 },
62641/* und */
62642 {
62643 M32C_INSN_UND16, "und16", "und", 8,
6772dd07 62644 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62645 },
62646/* und */
62647 {
62648 M32C_INSN_UND32, "und32", "und", 8,
6772dd07 62649 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62650 },
62651/* wait */
62652 {
62653 M32C_INSN_WAIT16, "wait16", "wait", 16,
6772dd07 62654 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62655 },
62656/* wait */
62657 {
62658 M32C_INSN_WAIT, "wait", "wait", 16,
6772dd07 62659 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62660 },
62661/* exts.w r0 */
62662 {
62663 M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16,
6772dd07 62664 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62665 },
62666/* src-indirect */
62667 {
62668 M32C_INSN_SRCIND, "srcind", "src-indirect", 8,
6772dd07 62669 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62670 },
62671/* dest-indirect */
62672 {
62673 M32C_INSN_DESTIND, "destind", "dest-indirect", 8,
6772dd07 62674 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62675 },
62676/* src-dest-indirect */
62677 {
62678 M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8,
6772dd07 62679 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
49f58d10
JB		 62680 },
62681};
62682
62683#undef OP
62684#undef A
62685
62686/* Initialize anything needed to be done once, before any cpu_open call. */
49f58d10
JB		 62687
62688static void
e729279b 62689init_tables (void)
49f58d10
JB		 62690{
62691}
62692
e729279b
NC		 62693static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
62694static void build_hw_table (CGEN_CPU_TABLE *);
62695static void build_ifield_table (CGEN_CPU_TABLE *);
62696static void build_operand_table (CGEN_CPU_TABLE *);
62697static void build_insn_table (CGEN_CPU_TABLE *);
62698static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *);
49f58d10
JB		 62699
62700/* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name. */
62701
62702static const CGEN_MACH *
e729279b 62703lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
49f58d10
JB		 62704{
62705 while (table->name)
62706 {
62707 if (strcmp (name, table->bfd_name) == 0)
62708 return table;
62709 ++table;
62710 }
62711 abort ();
62712}
62713
62714/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62715
62716static void
e729279b 62717build_hw_table (CGEN_CPU_TABLE *cd)
49f58d10
JB		 62718{
62719 int i;
62720 int machs = cd->machs;
62721 const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0];
62722 /* MAX_HW is only an upper bound on the number of selected entries.
62723 However each entry is indexed by it's enum so there can be holes in
62724 the table. */
62725 const CGEN_HW_ENTRY **selected =
62726 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
62727
62728 cd->hw_table.init_entries = init;
62729 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
62730 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
62731 /* ??? For now we just use machs to determine which ones we want. */
62732 for (i = 0; init[i].name != NULL; ++i)
62733 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
62734 & machs)
62735 selected[init[i].type] = &init[i];
62736 cd->hw_table.entries = selected;
62737 cd->hw_table.num_entries = MAX_HW;
62738}
62739
62740/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62741
62742static void
e729279b 62743build_ifield_table (CGEN_CPU_TABLE *cd)
49f58d10
JB		 62744{
62745 cd->ifld_table = & m32c_cgen_ifld_table[0];
62746}
62747
62748/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62749
62750static void
e729279b 62751build_operand_table (CGEN_CPU_TABLE *cd)
49f58d10
JB		 62752{
62753 int i;
62754 int machs = cd->machs;
62755 const CGEN_OPERAND *init = & m32c_cgen_operand_table[0];
62756 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
62757 However each entry is indexed by it's enum so there can be holes in
62758 the table. */
e729279b 62759 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
49f58d10
JB		 62760
62761 cd->operand_table.init_entries = init;
62762 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
62763 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
62764 /* ??? For now we just use mach to determine which ones we want. */
62765 for (i = 0; init[i].name != NULL; ++i)
62766 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
62767 & machs)
62768 selected[init[i].type] = &init[i];
62769 cd->operand_table.entries = selected;
62770 cd->operand_table.num_entries = MAX_OPERANDS;
62771}
62772
62773/* Subroutine of m32c_cgen_cpu_open to build the hardware table.
62774 ??? This could leave out insns not supported by the specified mach/isa,
62775 but that would cause errors like "foo only supported by bar" to become
62776 "unknown insn", so for now we include all insns and require the app to
62777 do the checking later.
62778 ??? On the other hand, parsing of such insns may require their hardware or
62779 operand elements to be in the table [which they mightn't be]. */
62780
62781static void
e729279b 62782build_insn_table (CGEN_CPU_TABLE *cd)
49f58d10
JB		 62783{
62784 int i;
62785 const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
e729279b 62786 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
49f58d10
JB		 62787
62788 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
62789 for (i = 0; i < MAX_INSNS; ++i)
62790 insns[i].base = &ib[i];
62791 cd->insn_table.init_entries = insns;
62792 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
62793 cd->insn_table.num_init_entries = MAX_INSNS;
62794}
62795
62796/* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */
62797
62798static void
e729279b 62799m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
49f58d10
JB		 62800{
62801 int i;
fb53f5a8 62802 CGEN_BITSET *isas = cd->isas;
49f58d10
JB		 62803 unsigned int machs = cd->machs;
62804
62805 cd->int_insn_p = CGEN_INT_INSN_P;
62806
62807 /* Data derived from the isa spec. */
62808#define UNSET (CGEN_SIZE_UNKNOWN + 1)
62809 cd->default_insn_bitsize = UNSET;
62810 cd->base_insn_bitsize = UNSET;
e729279b 62811 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
49f58d10
JB		 62812 cd->max_insn_bitsize = 0;
62813 for (i = 0; i < MAX_ISAS; ++i)
fb53f5a8 62814 if (cgen_bitset_contains (isas, i))
49f58d10
JB		 62815 {
62816 const CGEN_ISA *isa = & m32c_cgen_isa_table[i];
62817
62818 /* Default insn sizes of all selected isas must be
62819 equal or we set the result to 0, meaning "unknown". */
62820 if (cd->default_insn_bitsize == UNSET)
62821 cd->default_insn_bitsize = isa->default_insn_bitsize;
62822 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
e729279b 62823 ; /* This is ok. */
49f58d10
JB		 62824 else
62825 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
62826
62827 /* Base insn sizes of all selected isas must be equal
62828 or we set the result to 0, meaning "unknown". */
62829 if (cd->base_insn_bitsize == UNSET)
62830 cd->base_insn_bitsize = isa->base_insn_bitsize;
62831 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
e729279b 62832 ; /* This is ok. */
49f58d10
JB		 62833 else
62834 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
62835
62836 /* Set min,max insn sizes. */
62837 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
62838 cd->min_insn_bitsize = isa->min_insn_bitsize;
62839 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
62840 cd->max_insn_bitsize = isa->max_insn_bitsize;
62841 }
62842
62843 /* Data derived from the mach spec. */
62844 for (i = 0; i < MAX_MACHS; ++i)
62845 if (((1 << i) & machs) != 0)
62846 {
62847 const CGEN_MACH *mach = & m32c_cgen_mach_table[i];
62848
62849 if (mach->insn_chunk_bitsize != 0)
62850 {
62851 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
62852 {
62853 fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
62854 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
62855 abort ();
62856 }
62857
62858 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
62859 }
62860 }
62861
62862 /* Determine which hw elements are used by MACH. */
62863 build_hw_table (cd);
62864
62865 /* Build the ifield table. */
62866 build_ifield_table (cd);
62867
62868 /* Determine which operands are used by MACH/ISA. */
62869 build_operand_table (cd);
62870
62871 /* Build the instruction table. */
62872 build_insn_table (cd);
62873}
62874
62875/* Initialize a cpu table and return a descriptor.
62876 It's much like opening a file, and must be the first function called.
62877 The arguments are a set of (type/value) pairs, terminated with
62878 CGEN_CPU_OPEN_END.
62879
62880 Currently supported values:
62881 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
62882 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
62883 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
62884 CGEN_CPU_OPEN_ENDIAN: specify endian choice
62885 CGEN_CPU_OPEN_END: terminates arguments
62886
62887 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
62888 precluded.
62889
62890 ??? We only support ISO C stdargs here, not K&R.
62891 Laziness, plus experiment to see if anything requires K&R - eventually
62892 K&R will no longer be supported - e.g. GDB is currently trying this. */
62893
62894CGEN_CPU_DESC
62895m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
62896{
62897 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
62898 static int init_p;
fb53f5a8 62899 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
49f58d10
JB		 62900 unsigned int machs = 0; /* 0 = "unspecified" */
62901 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
62902 va_list ap;
62903
62904 if (! init_p)
62905 {
62906 init_tables ();
62907 init_p = 1;
62908 }
62909
62910 memset (cd, 0, sizeof (*cd));
62911
62912 va_start (ap, arg_type);
62913 while (arg_type != CGEN_CPU_OPEN_END)
62914 {
62915 switch (arg_type)
62916 {
62917 case CGEN_CPU_OPEN_ISAS :
fb53f5a8 62918 isas = va_arg (ap, CGEN_BITSET *);
49f58d10
JB		 62919 break;
62920 case CGEN_CPU_OPEN_MACHS :
62921 machs = va_arg (ap, unsigned int);
62922 break;
62923 case CGEN_CPU_OPEN_BFDMACH :
62924 {
62925 const char *name = va_arg (ap, const char *);
62926 const CGEN_MACH *mach =
62927 lookup_mach_via_bfd_name (m32c_cgen_mach_table, name);
62928
62929 machs |= 1 << mach->num;
62930 break;
62931 }
62932 case CGEN_CPU_OPEN_ENDIAN :
62933 endian = va_arg (ap, enum cgen_endian);
62934 break;
62935 default :
62936 fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n",
62937 arg_type);
62938 abort (); /* ??? return NULL? */
62939 }
62940 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
62941 }
62942 va_end (ap);
62943
e729279b 62944 /* Mach unspecified means "all". */
49f58d10
JB		 62945 if (machs == 0)
62946 machs = (1 << MAX_MACHS) - 1;
e729279b 62947 /* Base mach is always selected. */
49f58d10 62948 machs |= 1;
49f58d10
JB		 62949 if (endian == CGEN_ENDIAN_UNKNOWN)
62950 {
62951 /* ??? If target has only one, could have a default. */
62952 fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n");
62953 abort ();
62954 }
62955
fb53f5a8 62956 cd->isas = cgen_bitset_copy (isas);
49f58d10
JB		 62957 cd->machs = machs;
62958 cd->endian = endian;
62959 /* FIXME: for the sparc case we can determine insn-endianness statically.
62960 The worry here is where both data and insn endian can be independently
62961 chosen, in which case this function will need another argument.
62962 Actually, will want to allow for more arguments in the future anyway. */
62963 cd->insn_endian = endian;
62964
62965 /* Table (re)builder. */
62966 cd->rebuild_tables = m32c_cgen_rebuild_tables;
62967 m32c_cgen_rebuild_tables (cd);
62968
62969 /* Default to not allowing signed overflow. */
62970 cd->signed_overflow_ok_p = 0;
62971
62972 return (CGEN_CPU_DESC) cd;
62973}
62974
62975/* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
62976 MACH_NAME is the bfd name of the mach. */
62977
62978CGEN_CPU_DESC
e729279b 62979m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
49f58d10
JB		 62980{
62981 return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
62982 CGEN_CPU_OPEN_ENDIAN, endian,
62983 CGEN_CPU_OPEN_END);
62984}
62985
62986/* Close a cpu table.
62987 ??? This can live in a machine independent file, but there's currently
62988 no place to put this file (there's no libcgen). libopcodes is the wrong
62989 place as some simulator ports use this but they don't use libopcodes. */
62990
62991void
e729279b 62992m32c_cgen_cpu_close (CGEN_CPU_DESC cd)
49f58d10
JB		 62993{
62994 unsigned int i;
62995 const CGEN_INSN *insns;
62996
62997 if (cd->macro_insn_table.init_entries)
62998 {
62999 insns = cd->macro_insn_table.init_entries;
63000 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
e729279b
NC		 63001 if (CGEN_INSN_RX ((insns)))
63002 regfree (CGEN_INSN_RX (insns));
49f58d10
JB		 63003 }
63004
63005 if (cd->insn_table.init_entries)
63006 {
63007 insns = cd->insn_table.init_entries;
63008 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
e729279b
NC		 63009 if (CGEN_INSN_RX (insns))
63010 regfree (CGEN_INSN_RX (insns));
63011 }
49f58d10
JB		 63012
63013 if (cd->macro_insn_table.init_entries)
63014 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
63015
63016 if (cd->insn_table.init_entries)
63017 free ((CGEN_INSN *) cd->insn_table.init_entries);
63018
63019 if (cd->hw_table.entries)
63020 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
63021
63022 if (cd->operand_table.entries)
63023 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
63024
63025 free (cd);
63026}
63027
GDB Binutils - Deliverables
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